Information processing system

Abstract

The present invention provides a novel information processing system. The information processing system is for predicting the behavior of individual modules when a semiconductor device is operated, and comprises: a graph accepting means for accepting input of an adjacency matrix representing connections between the modules of the semiconductor device and a feature matrix representing design specifications of each of the modules; and a graph processing means for predicting and outputting a label matrix representing the behavior of the individual modules when the semiconductor device is operated, said prediction being based on the adjacency matrix and the feature matrix, wherein the graph processing means comprises a neural network that has been trained by machine learning in which adjacency matrices representing connections between modules of semiconductor devices designed in the past, feature matrices representing design specifications for each of said modules, and label matrices representing the behavior of each of said modules are used as supervisory data.

Description

Information Processing Systems

[0001] One aspect of the present invention relates to an information processing system.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. More specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, and driving methods thereof or manufacturing methods thereof.

[0003] In recent years, there has been an increasing demand for higher integration, multi-functionality, and higher performance of integrated circuits (ICs). Accordingly, the complexity of circuits has increased, and there is a demand for more efficient, optimized, and automated design. For example, Patent Document 1 discloses a design method for reducing the parasitic capacitance and parasitic resistance of wiring to an allowable value or less. Furthermore, for example, Patent Document 2 discloses a design method for suppressing variations in transistor characteristics.

[0004] Furthermore, utilization of artificial intelligence (AI) has been considered in various applications. In particular, the development of models using artificial neural networks (ANNs, hereinafter sometimes simply referred to as neural networks) has been actively carried out, and for example, graph neural networks (GNNs) that handle data represented in graphs have attracted attention. For example, Patent Document 3 discloses a method for extracting functions implemented in a netlist used in the logic design of an integrated circuit using a graph convolutional network (GCN), which is a type of GNN.

[0005] Furthermore, a transistor including an oxide semiconductor in a channel formation region is known to have an extremely small off-state current. For example, Patent Document 4 discloses a low-power processing device (such as a CPU) that utilizes the low off-state current characteristic of the transistor. Specifically, the document discloses a technology that enables power gating of a flip-flop mounted on an integrated circuit by incorporating a holding circuit including the transistor and a capacitor into the flip-flop.

[0006] JP 2003-50835 A JP 2009-65056 A JP 2021-89722 A JP 2016-82593 A

[0007] Generally, in the design of semiconductor devices such as integrated circuits, it is necessary to optimize the performance of the semiconductor device by repeating logic synthesis, placement and routing, simulation, etc. Furthermore, by carrying out a design that takes into consideration the behavior of each module when the semiconductor device is operated (such as the temperature of each module), it is possible to reduce power consumption and chip area.

[0008] For example, in the design of the processing device disclosed in Patent Document 4, the capacitance of the capacitance element of the holding circuit can be optimized according to the temperature of each module, thereby reducing power consumption and chip area.

[0009] Furthermore, in the design of semiconductor devices, various performance trade-offs may occur, requiring designers to have advanced skills based on knowledge and experience. Furthermore, as the complexity of semiconductor devices increases, even highly skilled designers take a long time to complete the design. Therefore, there is a need to reduce the dependency on designer skills as much as possible and shorten the design period.

[0010] An object of one embodiment of the present invention is to provide an information processing system capable of supporting design of a semiconductor device. Another object of one embodiment of the present invention is to provide an information processing system capable of improving performance of a semiconductor device. Another object of one embodiment of the present invention is to provide an information processing system capable of reducing power consumption of a semiconductor device. Another object of one embodiment of the present invention is to provide an information processing system capable of reducing the chip area of ​​a semiconductor device. Another object of one embodiment of the present invention is to provide an information processing system capable of reducing design costs of a semiconductor device. Another object of one embodiment of the present invention is to provide an information processing system capable of shortening the design period of a semiconductor device. Another object of one embodiment of the present invention is to provide an information processing system capable of improving the skills of a designer of a semiconductor device. Another object of one embodiment of the present invention is to provide a novel information processing system.

[0011] Another object of one embodiment of the present invention is to provide an information processing device that can be used in the information processing system.Another object of one embodiment of the present invention is to provide data output from the information processing device or the information processing system, or a computer-readable recording medium on which the data is recorded.Another object of one embodiment of the present invention is to provide an information processing method that can be applied to the information processing device or the information processing system.Another object of one embodiment of the present invention is to provide data created by the information processing method, or a computer-readable recording medium on which the data is recorded.Another object of one embodiment of the present invention is to provide a program for executing the information processing method on one or more computers, or a computer-readable recording medium on which the program is recorded.Another object of one embodiment of the present invention is to provide a design method for a semiconductor device using the information processing device or the information processing system, data created by the design method, or a computer-readable recording medium on which the data is recorded.

[0012] The above-mentioned problem does not preclude the existence of other problems. Problems other than the above-mentioned problem will become apparent from the description in this specification, drawings, claims, etc., and it is possible to extract other problems other than the above-mentioned problem from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problem and other problems).

[0013] (1) One aspect of the present invention is an information processing system that predicts the behavior of each module when a first semiconductor device is operated, the information processing system including: graph accepting means that accepts input of an adjacency matrix that represents the connections between modules of the first semiconductor device and a feature matrix that represents design specifications for each of the modules; and graph processing means that predicts and outputs a label matrix that represents the behavior of each module when the first semiconductor device is operated, from the adjacency matrix and the feature matrix, wherein the graph processing means includes a neural network that has been machine-trained using as training data the adjacency matrix that represents the connections between modules of a second semiconductor device that was previously designed, the feature matrix that represents the design specifications for each of the modules, and the label matrix that represents the behavior of each module.

[0014] (2) One aspect of the present invention is an information processing system that determines parameters of circuit elements included in a first semiconductor device based on a prediction of behavior of each module when the first semiconductor device is operated, the information processing system comprising: netlist receiving means that receives input of a netlist and design specifications of the first semiconductor device; graph creating means that creates, from the netlist and the design specifications, an adjacency matrix that represents connections between modules included in the netlist and a feature matrix that represents the design specifications for each module; label obtaining means that uses a classification model to predict and obtain a label matrix that represents behavior of each module when the first semiconductor device is operated from the adjacency matrix and the feature matrix; parameter determining means that determines parameters of the circuit elements based on the label matrix; and netlist updating means that updates and outputs the netlist based on the parameters determined by the parameter determining means, wherein the classification model comprises a neural network that has been machine-trained using as training data the adjacency matrix that represents connections between modules of a second semiconductor device designed in the past, the feature matrix that represents the design specifications for each module, and the label matrix that represents the behavior of each module.

[0015] (3) In addition, in the above (2), the first semiconductor device may include a holding circuit having a function of storing data by holding charge accumulated in the capacitive element, and the parameter of the circuit element may be the electrostatic capacitance of the capacitive element.

[0016] (4) In any one of (1) to (3) above, the design specifications of the first semiconductor device and the second semiconductor device may include an operating voltage of the module and an operating frequency of the module, and the behavior of the first semiconductor device and the second semiconductor device may include a temperature of the module.

[0017] (5) In any one of (1) to (3) above, the design specifications of the first semiconductor device and the second semiconductor device may include an operating voltage of the module and an operating frequency of the module, and the behavior of the first semiconductor device and the second semiconductor device may include power consumption of the module.

[0018] According to one embodiment of the present invention, an information processing system capable of supporting the design of a semiconductor device can be provided. According to another embodiment of the present invention, an information processing system capable of improving the performance of a semiconductor device can be provided. According to another embodiment of the present invention, an information processing system capable of reducing the power consumption of a semiconductor device can be provided. According to another embodiment of the present invention, an information processing system capable of reducing the chip area of ​​a semiconductor device can be provided. According to another embodiment of the present invention, an information processing system capable of reducing the design cost of a semiconductor device can be provided. According to another embodiment of the present invention, an information processing system capable of shortening the design period of a semiconductor device can be provided. According to another embodiment of the present invention, an information processing system capable of improving the skill of a designer of a semiconductor device can be provided. According to another embodiment of the present invention, a novel information processing system can be provided.

[0019] Alternatively, one aspect of the present invention can provide an information processing device that can be used in the information processing system. Alternatively, one aspect of the present invention can provide data output from the information processing device or the information processing system, or a computer-readable recording medium on which the data is recorded. Alternatively, one aspect of the present invention can provide an information processing method that can be applied to the information processing device or the information processing system. Alternatively, one aspect of the present invention can provide data created by the information processing method, or a computer-readable recording medium on which the data is recorded. Alternatively, one aspect of the present invention can provide a program for executing the information processing method on one or more computers, or a computer-readable recording medium on which the program is recorded. Alternatively, one aspect of the present invention can provide a method for designing a semiconductor device using the information processing device or the information processing system, data created by the design method, or a computer-readable recording medium on which the data is recorded.

[0020] The above-described effects do not preclude the existence of other effects. Effects other than the above-described effects will become apparent from the description in this specification, drawings, claims, etc., and other effects can be extracted from the description in this specification, drawings, claims, etc. One embodiment of the present invention does not necessarily have all of these effects (the above-described effects and other effects).

[0021] FIG. 1 is a block diagram illustrating an example of the configuration of an information processing system. FIGS. 2A to 2C are diagrams illustrating data handled by the information processing system. FIGS. 3A and 3B are diagrams illustrating data handled by the information processing system. FIGS. 4A and 4B are diagrams illustrating data handled by the information processing system. FIGS. 5A and 5B are diagrams illustrating data handled by the information processing system. FIG. 6 is a flowchart illustrating an example of a method for preparing a data set. FIG. 7 is a flowchart illustrating an example of a method for designing a semiconductor device. FIG. 8 is a schematic diagram illustrating an example of the configuration of an information processing system. FIG. 9 is a schematic diagram illustrating an example of the configuration of an information processing system. FIG. 10 is a schematic diagram illustrating an example of the configuration of an information processing system.

[0022] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor or a diode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit including a semiconductor element, a chip equipped with an integrated circuit, an electronic component in which a chip is housed in a package, or an electronic device equipped with an electronic component are examples of semiconductor devices. Furthermore, for example, a display device, a light-emitting device, a power storage device, an optical device, an imaging device, a lighting device, an arithmetic device, a control device, a memory device, an input device, an output device, an input / output device, a signal processing device, an electronic computer, or an electronic device may be a semiconductor device and may also include a semiconductor device.

[0023] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways. Therefore, it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments.

[0024] In this specification and the like, the configuration shown in each embodiment can be appropriately combined with the configuration shown in another embodiment to form one aspect of the present invention. Furthermore, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0025] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0026] In addition, in the drawings illustrating the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, thereby omitting repeated description thereof. Furthermore, when the drawings indicate similar functions, for example, the same hatching patterns may be used and no particular reference numerals may be used. Furthermore, in the drawings, for example, in perspective views or top views (also called "plan views"), the illustration of some components may be omitted for ease of understanding. Furthermore, in the drawings, for example, the illustration of some hidden lines may be omitted. Furthermore, in the drawings, for example, the illustration of hatching patterns may be omitted.

[0027] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not limited to, for example, their size or aspect ratio. Note that the drawings are schematic illustrations of ideal examples, and are not limited to, for example, the shapes or values ​​shown in the drawings.

[0028] Furthermore, in this specification and drawings, components may be classified by function and shown as independent elements. However, it may be difficult to separate components by function, and one element may be involved in multiple functions, or one function may be involved across multiple elements. Therefore, the elements shown in this specification and drawings may not be limited to the descriptions therein, and may be rephrased appropriately.

[0029] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0030] Embodiment A data processing system according to one embodiment of the present invention will be described with reference to the drawings. The data processing system according to one embodiment of the present invention can be used for designing a semiconductor device, for example.

[0031] In this specification and the like, designing a semiconductor device refers to designing a circuit including a plurality of circuit elements (semiconductor elements (transistors, diodes, etc.), resistive elements, capacitive elements, etc.). In particular, in the design of an integrated circuit, it may refer to designing related to logic synthesis, placement and wiring, and simulation.

[0032] Examples of integrated circuits include digital integrated circuits, analog integrated circuits, and mixed-signal integrated circuits. Examples of such integrated circuits also include central processing units (CPUs), graphics processing units (GPUs), static random access memories (SRAMs), and dynamic random access memories (DRAMs). Examples of such integrated circuits also include driver ICs, power supply ICs, micro controller units (MCUs), application specific integrated circuits (ASICs), and system large scale integration (LSIs).

[0033] Examples of the transistor include a Si transistor (a transistor containing silicon in a channel formation region) and an OS transistor (a transistor containing metal oxide in a channel formation region). That is, the semiconductor device may include, for example, a Si transistor. Alternatively, the semiconductor device may include, for example, an OS transistor. Alternatively, the semiconductor device may include, for example, both a Si transistor and an OS transistor. When the semiconductor device includes both a Si transistor and an OS transistor, the OS transistor may be provided over the Si transistor. For example, a part of a silicon substrate may be used as the channel formation region of the Si transistor, or polycrystalline silicon provided over an insulating substrate or an insulating layer may be used. For example, Patent Document 4 discloses a configuration in which a holding circuit including an OS transistor is provided over a flip-flop including a Si transistor.

[0034] <Configuration Example of Information Processing System> FIG. 1 is a block diagram illustrating an example of an information processing system according to one embodiment of the present invention.

[0035] 1 illustrates a component 110 and a component 120. In designing a semiconductor device, the component 110 has a function of predicting the behavior of each module when the semiconductor device is operated. The component 120 has a function of determining parameters of circuit elements included in the semiconductor device based on the predicted behavior of each module when the semiconductor device is operated. The component 110 and the component 120 can exchange information with each other.

[0036] The component 110 includes a graph accepting unit 111 and a graph processing unit 112. The graph processing unit 112 includes a classification model 130. The graph accepting unit 111 has a function of accepting input of an adjacency matrix 131 representing the connections between modules of the semiconductor device and a feature matrix 132 representing the design specifications for each module. The graph processing unit 112 has a function of predicting and outputting a label matrix 133 representing the behavior of each module when the semiconductor device is operated, based on the adjacency matrix 131 and the feature matrix 132. Here, the label matrix 133 is predicted by the classification model 130 from the adjacency matrix 131 and the feature matrix 132.

[0037] The component 120 includes a netlist receiving means 121, a graph creating means 122, a label obtaining means 123, a parameter determining means 124, and a netlist updating means 125. The netlist receiving means 121 has a function of receiving input of a netlist 134 and a design specification 135 of a semiconductor device. The graph creating means 122 has a function of creating, from the netlist 134 and the design specification 135, an adjacency matrix 131 representing the connections between modules included in the netlist 134 and a feature matrix 132 representing the design specification for each module. The label obtaining means 123 has a function of predicting and obtaining a label matrix 133 representing the behavior of each module when the semiconductor device is operated, from the adjacency matrix 131 and the feature matrix 132 using the classification model 130. The parameter determining means 124 has a function of determining parameters of circuit elements based on the label matrix 133. The netlist updating means 125 has a function of updating and outputting the netlist 134 (here, outputting an updated netlist 136) based on the parameters determined by the parameter determining means 124.

[0038] The classification model 130 comprises a neural network that has been machine-trained using as training data an adjacency matrix representing the connections between modules of semiconductor devices designed in the past, a feature matrix representing the design specifications for each module, and a label matrix representing the behavior of each module.

[0039] In this specification, a neural network generally refers to a model that mimics the neural circuit network of a living organism, determines the connection strengths between neurons through learning, and provides problem-solving capabilities. A neural network, for example, has an input layer, an intermediate layer (hidden layer), and an output layer. In a neural network, determining the connection strengths (also called weight coefficients) between neurons from existing information (also called a data set) is sometimes referred to as "learning." That is, a neural network model is created through learning. Examples of learning methods include "supervised learning," "unsupervised learning," and "reinforcement learning." Furthermore, constructing a neural network using the connection strengths obtained through learning and deriving new conclusions from it is sometimes referred to as "inference." A neural network is implemented using a circuit (hardware) or a program (software).

[0040] A GNN can be used as the neural network included in the classification model 130. In particular, a GCN, which is a type of GNN, can be used.

[0041] In other words, by using the trained classification model 130, even if the behavior of each module when the semiconductor device is operated is unknown, the behavior of each module can be inferred from the connections between the modules and the design specifications of each module.

[0042] The design specifications of a module include the operating voltage and operating frequency of the module, the number of gates included in the module, the number of flip-flops included in the module, and the process node of the module.

[0043] The behavior of a module may include the temperature of the module, the amount of heat generated by the module, the power consumption of the module, and the frequency of access to the module.

[0044] Here, in designing a semiconductor device, parameters of circuit elements included in the semiconductor device may be determined based on the behavior of each module obtained using the classification model 130 .

[0045] The parameters of the circuit elements include the on-current, off-current, threshold voltage, subthreshold coefficient, and field-effect mobility of the transistor. Other parameters include the channel length, channel width, gate insulating film thickness, dielectric constant of the gate insulating film, and type of semiconductor layer including the channel formation region of the transistor. Other parameters include the capacitance of the capacitive element. Other parameters include the area occupied by the capacitive element, dielectric film thickness, and dielectric constant of the dielectric.

[0046] In designing a semiconductor device, a simulation is generally performed after placement and wiring to know the behavior of each module when the semiconductor device is operated. In designing a semiconductor device using a data processing system of one embodiment of the present invention, the behavior of each module can be predicted without placement and wiring and simulation. Therefore, the design time can be reduced. A method for designing a semiconductor device using a data processing system of one embodiment of the present invention will be described later.

[0047] Next, a process performed by an information processing system according to an embodiment of the present invention will be described with reference to an example of data handled by the information processing system. The information processing system receives a netlist 134 and a design specification 135, and can output an updated netlist 136.

[0048] Specifically, in the component 120, an adjacency matrix 131 and a feature matrix 132 can be created from a netlist 134 and a design specification 135. In addition, in the component 110, a label matrix 133 can be output by receiving the adjacency matrix 131 and the feature matrix 132 as input. In addition, in the component 120, the netlist 134 can be updated based on the label matrix 133.

[0049] [Netlist Receiving Unit 121] First, the netlist receiving unit 121, graph creating unit 122, and label obtaining unit 123 provided in the component 120 will be described.

[0050] The netlist receiving unit 121 receives the netlist 134 and design specification 135 to be input to the component 120. The netlist 134 and design specification 135 are, for example, text files. Here, as an example, a netlist 134eg and design specification 135eg to be input to the component 120 from outside the information processing system of one aspect of the present invention are received.

[0051] 2A is a diagram illustrating a netlist 134eg, which is an example of the netlist 134. FIG. 2B is a diagram illustrating a design specification 135eg, which is an example of the design specification 135.

[0052] The netlist 134eg shown in FIG. 2A shows a hierarchical structure of 15 modules (module_01 to module_15) with the first module (module_01) at the top.

[0053] Here, for example, the first module (module_01) is a CPU, and the second to fifteenth modules (module_02 to module_15) are registers, decoders, and arithmetic units included in the CPU. Although not shown, each module includes basic circuits (logic gates (NAND gates, NOR gates, NOT gates, etc.), latches, flip-flops, etc.).

[0054] 2B shows the design specifications of the first, second, eighth, and fifteenth modules (module_01, module_02, module_08, and module_15) as representative examples. Here, the design specifications show the operating frequency, operating voltage, and number of gates for each module as an example.

[0055] [Graph Creation Means 122] The graph creation means 122 creates an adjacency matrix 131 and a feature matrix 132 from the netlist 134 and the design specification 135. The adjacency matrix 131 is created by extracting at least a part of the hierarchical structure of the netlist 134. Here, as an example, an adjacency matrix 131eg and a feature matrix 132eg are created from the netlist 134eg and the design specification 135eg accepted by the netlist acceptance means 121 described above.

[0056] Fig. 2C is a diagram illustrating an example of a graph representing a portion of the hierarchical structure of the netlist 134eg. Fig. 3A is a diagram illustrating an adjacency matrix 131eg, which is an example of a matrix representing the graph. Fig. 3B is a diagram illustrating a feature matrix 132eg, which is an example of a matrix representing the design specification 135eg.

[0057] In the graph shown in Figure 2C, the hierarchical structure of the first to fifteenth modules (module_01 to module_15) is shown by corresponding each module to node n01 to node n15, and the parent-child relationships between modules are shown by corresponding edges with arrows (here, the arrowheads indicate child modules).

[0058] In the adjacency matrix 131eg shown in Figure 3A, for the above graph, each of nodes n01 to n15 shown in each row is a parent module, and each of nodes n01 to n15 shown in each column is a child module, and when there is a parent-child relationship between modules, the corresponding component is shown as "1".

[0059] In the feature matrix 132eg shown in FIG. 3B, for each module corresponding to node n01 to node n15 shown on each row, the components in the first column (frq) are the operating frequency (frequency), the components in the second column (vlt) are the operating voltage (voltage), and the components in the third column (gate) are the number of gates (number of gates).

[0060] [Label Acquisition Means 123] The label acquisition means 123 inputs the adjacency matrix 131 and the feature matrix 132 from the component 120 to the component 110, and acquires the label matrix 133 output from the component 110. In the component 110, the classification model 130 predicts the label matrix 133 from the adjacency matrix 131 and the feature matrix 132. In other words, it can be said that the label acquisition means 123 has a function of predicting and acquiring the label matrix 133 from the adjacency matrix 131 and the feature matrix 132 using the classification model 130. Here, as an example, the adjacency matrix 131eg and the feature matrix 132eg created by the graph creation means 122 described above are input from the component 120 to the component 110, and the label matrix 133eg output from the component 110 is acquired.

[0061] [Graph Acceptance Unit 111] Here, the graph acceptance unit 111 and the graph processing unit 112 provided in the component 110 will be described.

[0062] The graph accepting unit 111 accepts the adjacency matrix 131 and the feature matrix 132 to be input to the component 110. Here, as an example, the graph accepting unit 111 accepts the adjacency matrix 131eg and the feature matrix 132eg to be input from the component 120 to the component 110.

[0063] [Graph Processing Means 112] The graph processing means 112 causes the classification model 130 to predict a label matrix 133 from the adjacency matrix 131 and the feature matrix 132, and outputs the label matrix 133 from the component 110. Here, as an example, the trained classification model 130 predicts a label matrix 133eg from the adjacency matrix 131eg and the feature matrix 132eg accepted by the graph accepting means 111, and outputs the label matrix 133eg from the component 110. The training of the classification model 130 will be described later.

[0064] FIG. 4A is a diagram illustrating a label matrix 133eg, which is an example of the label matrix 133.

[0065] The label matrix 133eg shown in FIG. 4A shows the behavior of each module corresponding to node n01 to node n15 shown in each row when it is operated. Here, as an example of the behavior, the temperature rise due to heat generation when the module is operated is shown. Specifically, whether the temperature of each module is low temperature (LT), medium temperature (MT), or high temperature (HT) is indicated by the component of the corresponding column being "1."

[0066] 4B is a diagram illustrating the relationship between the placement of each module, temperature, and label matrix 133eg. In FIG. 4B, as an example, the inside of the dashed two-dot line is designated as a high temperature region, and the outside is designated as a middle temperature region, and each module placed in each region is shown. Here, in label matrix 133eg, modules located in the high temperature region are designated as "1" in the high temperature (HT) column, and modules located in the middle temperature region are designated as "1" in the middle temperature (MT) column.

[0067] [Parameter Determining Unit 124] Next, the parameter determining unit 124 and netlist updating unit 125 provided in the component 110 will be described.

[0068] The parameter determination means 124 determines the parameters of the circuit elements included in each module based on the label matrix 133. Here, as an example, the type of flip-flop included in each module is determined based on the label matrix 133eg indicating the temperature of each module, which is acquired by the label acquisition means 123 described above.

[0069] Here, as the flip-flop, for example, a flip-flop with a holding circuit, in which a holding circuit having a transistor and a capacitance element is provided on the flip-flop, can be used, as shown in Patent Document 4. In a semiconductor device using a flip-flop with a holding circuit, power gating on a flip-flop basis becomes possible, and power consumption can be reduced.

[0070] In this case, the retention time can be extended by increasing the capacitance of the capacitive element included in the retention circuit, but on the other hand, there are trade-offs such as an increase in area overhead due to the larger area occupied by the capacitive element, and an increase in power consumption due to the larger charge stored in the capacitive element.

[0071] Therefore, it is preferable to optimize the capacitance of the capacitor included in the holding circuit according to the temperature of each module when the semiconductor device is operated. For example, in a flip-flop with a holding circuit arranged in a high-temperature region, the off-state current of the transistor may increase, so the capacitance of the capacitor may be increased to ensure a sufficient holding time. On the other hand, in a flip-flop with a holding circuit arranged in a low-temperature region, the capacitance of the capacitor may be reduced to a degree that ensures a sufficient holding time in order to reduce area overhead and power consumption.

[0072] That is, for example, it is preferable that the capacitance of the capacitance element included in a flip-flop with a holding circuit arranged in a medium temperature region is larger than the capacitance of the capacitance element included in a flip-flop with a holding circuit arranged in a low temperature region, and it is preferable that the capacitance of the capacitance element included in a flip-flop with a holding circuit arranged in a high temperature region is larger than the capacitance of the capacitance element included in a flip-flop with a holding circuit arranged in a medium temperature region.

[0073] In this way, the capacitance of the capacitive element included in the flip-flop with a holding circuit can be determined based on the label matrix 133eg indicating the temperature of each module.

[0074] The channel length of the transistor included in the holding circuit may be optimized depending on the temperature of each module when the semiconductor device is operated. For example, in a flip-flop with a holding circuit arranged in a high-temperature region, the off-state current of the transistor may increase, so the channel length of the transistor may be increased to ensure a sufficient holding time. On the other hand, in a flip-flop with a holding circuit arranged in a low-temperature region, the channel length of the transistor may be reduced to a degree that ensures a sufficient holding time in order to reduce area overhead and power consumption.

[0075] That is, for example, it is preferable that the channel length of a transistor included in a flip-flop with a holding circuit arranged in a medium temperature region is longer than the channel length of a transistor included in a flip-flop with a holding circuit arranged in a low temperature region, and it is preferable that the channel length of a transistor included in a flip-flop with a holding circuit arranged in a high temperature region is longer than the channel length of a transistor included in a flip-flop with a holding circuit arranged in a medium temperature region.

[0076] When the semiconductor device is operated, the power consumed by each module becomes heat, and this heat increases the temperature of each module. In other words, the power consumption, heat generation, and temperature of each module may be correlated with each other.

[0077] Therefore, for example, the amount of heat generated may be used as an indicator of the behavior of each module when the semiconductor device is operated. In this case, for example, the capacitance of a capacitor included in a flip-flop with a hold circuit that generates a medium amount of heat is preferably larger than the capacitance of a capacitor included in a flip-flop with a hold circuit that generates a small amount of heat, and the capacitance of a capacitor included in a flip-flop with a hold circuit that generates a large amount of heat is preferably larger than the capacitance of a capacitor included in a flip-flop with a hold circuit that generates a medium amount of heat. Furthermore, for example, the channel length of a transistor included in a flip-flop with a hold circuit that generates a medium amount of heat is preferably larger than the channel length of a transistor included in a flip-flop with a hold circuit that generates a small amount of heat, and the channel length of a transistor included in a flip-flop with a hold circuit that generates a large amount of heat is preferably larger than the channel length of a transistor included in a flip-flop with a hold circuit that generates a medium amount of heat.

[0078] Furthermore, for example, power consumption may be used as the behavior of each module when the semiconductor device is operated. In this case, for example, the capacitance of a capacitor included in a flip-flop with a hold circuit having medium power consumption is preferably larger than the capacitance of a capacitor included in a flip-flop with a hold circuit having low power consumption, and the capacitance of a capacitor included in a flip-flop with a hold circuit having high power consumption is preferably larger than the capacitance of a capacitor included in a flip-flop with a hold circuit having medium power consumption. Furthermore, for example, the channel length of a transistor included in a flip-flop with a hold circuit having medium power consumption is preferably larger than the channel length of a transistor included in a flip-flop with a hold circuit having low power consumption, and the channel length of a transistor included in a flip-flop with a hold circuit having high power consumption is preferably larger than the channel length of a transistor included in a flip-flop with a hold circuit having medium power consumption.

[0079] Furthermore, the capacitance of the capacitor included in the holding circuit and the channel length of the transistor may be optimized according to the access frequency of each module when the semiconductor device is operated. For example, in a flip-flop with a holding circuit that is accessed less frequently, the capacitance of the capacitor may be increased to ensure a sufficient holding time. The channel length of the transistor may also be increased. On the other hand, in a flip-flop with a holding circuit that is accessed more frequently, since long-term holding is not required, the capacitance of the capacitor may be reduced to a degree that ensures a sufficient holding time in order to reduce area overhead and power consumption. The channel length of the transistor may also be reduced.

[0080] That is, for example, the capacitance of a capacitive element included in a flip-flop with a hold circuit that is accessed at a medium frequency is preferably larger than the capacitance of a capacitive element included in a flip-flop with a hold circuit that is accessed at a high frequency, and the capacitance of a capacitive element included in a flip-flop with a hold circuit that is accessed at a low frequency is preferably larger than the capacitance of a capacitive element included in a flip-flop with a hold circuit that is accessed at a medium frequency.Furthermore, for example, the channel length of a transistor included in a flip-flop with a hold circuit that is accessed at a medium frequency is preferably larger than the channel length of a transistor included in a flip-flop with a hold circuit that is accessed at a high frequency, and the channel length of a transistor included in a flip-flop with a hold circuit that is accessed at a low frequency is preferably larger than the channel length of a transistor included in a flip-flop with a hold circuit that is accessed at a medium frequency.

[0081] The access frequency may be, for example, the frequency of backing up from a flip-flop to a holding circuit and the frequency of recovering from the holding circuit to a flip-flop, i.e., the frequency of power gating of a flip-flop.

[0082] [Netlist Update Means 125] The netlist update means 125 updates the netlist 134 based on the determined parameters of the circuit elements, and the updated netlist 136 is output from the component 120. Here, as an example, the netlist 134eg is updated based on the capacitance of the capacitive element included in the flip-flop with a holding circuit, determined by the parameter determination means 124, and the updated netlist 136eg is output from the component 120 to the outside of the information processing system according to one aspect of the present invention.

[0083] 5A and 5B are diagrams illustrating a netlist 134eg, which is an example of the netlist 134 before being updated, and a netlist 136eg, which is an example of the netlist 136 after being updated.

[0084] 5A shows a netlist in which a 16th module (module_FF01) is added to the netlist 134eg shown in FIG. 2A. 5B shows a netlist in which a module having a component of "1" in the medium temperature (MT) column of the label matrix 133eg is replaced with a 17th module (module_FF02), and a module having a component of "1" in the high temperature (HT) column is replaced with an 18th module (module_FF03).

[0085] Here, as an example, the 16th module (module_FF01) may include a flip-flop with a holding circuit for the low temperature range, the 17th module (module_FF02) may include a flip-flop with a holding circuit for the medium temperature range, and the 18th module (module_FF03) may include a flip-flop with a holding circuit for the high temperature range. That is, for example, the capacitances of the capacitive element included in the 16th module (module_FF01), the capacitive element included in the 17th module (module_FF02), and the capacitive element included in the 18th module (module_FF03) may increase in this order.

[0086] In this way, the netlist 134eg can be updated based on the label matrix 133eg indicating the temperature of each module, thereby obtaining a netlist 136eg optimized according to the temperature of each module.

[0087] [Classification Model 130] Next, a data set that can be used for training the classification model 130 will be described.

[0088] In an information processing system of one embodiment of the present invention, a classification model 130 can be trained using a dataset as training data, in which an adjacency matrix created from a netlist of a semiconductor device designed in the past and a feature matrix created from the design specifications of the semiconductor device are input, and a label matrix created from the behavior of the semiconductor device when it is operated is output.

[0089] In this case, for example, by training the classification model 130 using a label matrix created from the temperatures at which previously designed semiconductor devices were operated as training data, it is possible to obtain a classification model 130 that can infer the temperatures at which the semiconductor device is operated.

[0090] Furthermore, for example, by training the classification model 130 using a label matrix created from the heat generation amount when a semiconductor device designed in the past is operated as training data, it is possible to obtain a classification model 130 that can infer the heat generation amount when a semiconductor device is operated.

[0091] Furthermore, for example, by training the classification model 130 using a label matrix created from the power consumption when a semiconductor device designed in the past is operated as training data, it is possible to obtain a classification model 130 that can infer the power consumption when the semiconductor device is operated.

[0092] Furthermore, for example, by training the classification model 130 using a label matrix created from the access frequency when a semiconductor device designed in the past is operated as training data, it is possible to obtain a classification model 130 that can infer the access frequency when the semiconductor device is operated.

[0093] Here, the temperature, heat generation amount, power consumption, access frequency, etc., when a semiconductor device designed in the past is operated can be obtained by simulation, measurement, etc.

[0094] Therefore, in an information processing system of one embodiment of the present invention, by using a classification model 130 that has been trained using the behavior of a semiconductor device whose behavior when operated is known (e.g., a semiconductor device designed in the past) as training data, it is possible to infer the behavior of a semiconductor device whose behavior when operated is unknown (e.g., a semiconductor device currently being designed).

[0095] 6 is a flowchart illustrating an example of a method for preparing a data set that can be used for learning the classification model 130. Note that the flowchart illustrated in FIG. 6 also illustrates an example of a method for designing a semiconductor device without using the information processing system of one embodiment of the present invention.

[0096] Here, the description starts after the logic design and logic verification are performed.

[0097] First, in step S11, logic synthesis is performed to generate a netlist.

[0098] Next, in step S12, placement and routing is performed, in which each module included in the netlist is placed.

[0099] Next, in step S13, a simulation is performed. The behavior of each module can be obtained by the simulation. For example, the heat generation amount of each module can be confirmed by the simulation, and the temperature of each module can be obtained. Furthermore, for example, the operation of each module can be confirmed by the simulation, and the power consumption of each module can be obtained. Here, a simulation tool can be used to obtain the behavior of each module. Examples of simulation tools include "Celsius Thermal Solver," an EDA tool for electrical and thermal analysis from Cadence, and "PrimePower," an EDA tool for power consumption analysis from Synopsys.

[0100] Next, in step S14, it is determined whether or not a design review is necessary. For example, this determination is made based on whether the parameters of the circuit elements included in each module are appropriate for the temperature of each module. For example, if each module includes a flip-flop with a holding circuit, this determination is made based on whether the capacitance of the capacitive element included in the holding circuit is appropriate.

[0101] If it is determined in step S14 that a design revision is necessary, the design is revised in step S15. For example, the parameters of the circuit elements included in each module are updated. For example, if each module includes a flip-flop with a holding circuit, the capacitance of the capacitive element included in the holding circuit is updated.

[0102] Next, steps S12 and S13 are performed. That is, steps S15, S12, and S13 are performed until it is determined in step S14 that no design revision is necessary. Note that, for example, steps S15, S11, S12, and S13 may be performed.

[0103] Furthermore, in steps S13 and S14, timing verification may be performed. An EDA tool for timing verification may be used here. Examples of EDA tools for timing verification include "Encounter Timing System" and "Tempus" from Cadence, and "NanoTime" and "PrimeTime" from Synopsys.

[0104] If it is determined in step S14 that no design revision is necessary, then in step S16, a dataset is created to be used for training the classification model 130. In creating the dataset, an adjacency matrix and a feature matrix, which serve as input data, are created from the netlist obtained in step S11. In addition, a label matrix, which serves as output data, is created from the simulation results obtained in step S13.

[0105] By using the method described above, the data set required for training the classification model 130 can be prepared, and the classification model 130 can be trained using the data set.

[0106] Here, the dataset can be created from a semiconductor device designed in the past. In other words, it can be said that the classification model 130 trained using the dataset can perform inference based on the knowledge and experience of the designer who designed the semiconductor device in the past. Therefore, it is preferable to create the dataset from a semiconductor device designed by a highly skilled designer. As a result, the information processing system of one embodiment of the present invention can update the netlist by inference based on the knowledge and experience of the highly skilled designer. In other words, even a less skilled designer can perform a design comparable to that of a highly skilled designer. This can, for example, improve the performance of the semiconductor device, reduce power consumption, reduce the chip area, reduce design costs, and shorten the design period. Furthermore, the designer's skills can also be improved.

[0107] <Example of Design of Semiconductor Device> Next, an example of designing a semiconductor device using the data processing system of one embodiment of the present invention will be described. In other words, one embodiment of the present invention can also be said to be a method for designing a semiconductor device using the data processing system of one embodiment of the present invention.

[0108] FIG. 7 is a flowchart illustrating an example of a method for designing a semiconductor device using a data processing system of one embodiment of the present invention.

[0109] First, in step S21, logic synthesis is performed. Here, an EDA (Electronic Design Automation) tool for performing logic synthesis can be used. Examples of EDA tools for performing logic synthesis include "Encounter RTL Compiler" and "Genus" from Cadence, and "Design Compiler" and "Fusion Compiler" from Synopsys. A netlist 134 is created by the logic synthesis. Furthermore, a design specification 135 is created for each module included in the netlist 134. The design specification 135 may be created by the EDA tool or by a designer.

[0110] Next, in step S22, an adjacency matrix and a feature matrix are created using an information processing system according to one aspect of the present invention. Step S22 corresponds to processing performed by the netlist receiving unit 121 and the graph creating unit 122 included in the component 120. For example, an adjacency matrix 131 and a feature matrix 132 are created from the netlist 134 and the design specification 135 created in step S21.

[0111] Next, in step S23, a label matrix is ​​predicted using a classification model included in the information processing system of one aspect of the present invention. Step S23 corresponds to processing performed by the label acquisition means 123 included in the component 120 and processing performed by the graph acceptance means 111 and graph processing means 112 included in the component 110. For example, the classification model 130 predicts a label matrix 133 from the adjacency matrix 131 and the feature matrix 132.

[0112] Next, in step S24, the netlist is updated based on the label matrix using an information processing system according to one aspect of the present invention. Step S24 corresponds to processing performed by parameter determination means 124 and netlist update means 125 included in component 120. For example, parameters of circuit elements included in each module are determined based on label matrix 133, and netlist 134 is updated based on the determined parameters of the circuit elements, resulting in updated netlist 136.

[0113] Next, in step S25, placement and routing is performed. An EDA tool for performing placement and routing can be used here. Examples of EDA tools for performing placement and routing include "Encounter Digital Implementation" and "Innovus" from Cadence, and "IC Compiler" and "Fusion Compiler" from Synopsys. In the placement and routing, the netlist 136 updated in step S24 is used.

[0114] Next, in step S26, a simulation is performed. For example, the heat generation amount of each module may be confirmed by simulation, and the temperature of each module may be confirmed. Also, for example, the operation of each module may be confirmed by simulation, and the power consumption of each module may be confirmed. Here, a simulation tool may be used to confirm the behavior of each module. Examples of simulation tools include "Celsius Thermal Solver," an EDA tool for electrical and thermal analysis by Cadence, and "PrimePower," an EDA tool for power consumption analysis by Synopsys.

[0115] Although not shown, after step S26, the design may be reviewed as necessary, as in steps S14 and S15 described above.

[0116] In a method for designing a semiconductor device using an information processing system according to one embodiment of the present invention, behavior of the semiconductor device when it is operated can be predicted before placement and wiring and simulation are performed, and an optimized netlist can be obtained based on the prediction result. This can reduce the number of times placement and wiring, simulation, and design revision are performed. Therefore, the design period of the semiconductor device can be shortened.

[0117] Here, each of steps S22, S23, and S24 may be performed using an information processing system according to one aspect of the present invention. That is, one aspect of the present invention can also be said to be an information processing method having steps S22, S23, and S24. That is, one aspect of the present invention can also be said to be an information processing method applicable to the information processing system according to one aspect of the present invention.

[0118] Note that steps S21, S25, and S26 may each be performed outside the information processing system, or at least some of steps S21, S25, and S26 may be performed inside the information processing system. That is, the information processing system according to one aspect of the present invention may include, for example, at least one of an EDA tool for logic synthesis and an EDA tool for placement and wiring.

[0119] 8 is a schematic diagram illustrating an example of an information processing system of one embodiment of the present invention. The information processing system of one embodiment of the present invention includes one or more information processing devices (also referred to as computers). In other words, one embodiment of the present invention can be said to be an information processing device that can be used in the information processing system of one embodiment of the present invention.

[0120] FIG. 8 illustrates an information processing device 10, an information processing device 20, an information terminal 60, and a network 90.

[0121] The information processing device 10, for example, includes a component 110. That is, the information processing device 10 includes, for example, a classification model 130. The information processing device 20, for example, includes a component 120. The information processing device 10, the information processing device 20, and the information terminal 60 are each connected to a network 90. ​​This allows the information processing device 10, the information processing device 20, and the information terminal 60 to exchange information with each other via the network 90.

[0122] In this way, by configuring the information processing device 10, the information processing device 20, and the information terminal 60 to be connected via the network 90, the load related to information processing can be distributed.

[0123] For example, a large computer such as a server computer or a supercomputer can be used as the information processing device 10. It is preferable that the information processing device 10 has a function as a parallel computer, which enables the large-scale calculations required for processing such as AI learning and inference.

[0124] For example, a workstation, a server computer, or a supercomputer can be used as the information processing device 20. It is preferable that the information processing device 20 has a function as a parallel computer, which enables the large-scale calculations required for processing such as AI learning and inference.

[0125] Note that the information processing device 10 may perform larger-scale calculations than the information processing device 20 for processing such as learning and inference of the classification model 130. Therefore, it is preferable that the information processing device 10 has higher computing power than the information processing device 20, and in particular, higher parallel computing power.

[0126] For example, a desktop computer can be used as the information terminal 60. The information terminal 60 can also be called a client computer.

[0127] The network 90 may be, for example, a local network or a global network. It may also be, for example, an intranet or an extranet. It may also be, for example, a personal area network (PAN), a local area network (LAN), a campus area network (CAN), a metropolitan area network (MAN), a wide area network (WAN), or a global area network (GAN). It may also be, for example, the Internet, which is the foundation of the World Wide Web (WWW).

[0128] When wireless communication is performed, the communication protocol or technology that can be used may be, for example, a communication standard such as the fourth generation mobile communication system (4G), the fifth generation mobile communication system (5G), or the sixth generation mobile communication system (6G), or a specification standardized by the IEEE such as Wi-Fi (registered trademark) or Bluetooth (registered trademark).

[0129] Here, a person who provides a service using the information processing system according to one embodiment of the present invention can provide the service via a network 90, for example.

[0130] In addition, when a party providing a service using an information processing system according to an embodiment of the present invention and a party receiving the service belong to the same organization (such as a company), it is preferable to use a local network such as an intranet established within the organization as the network 90. ​​This allows for more secure information exchange than when a global network such as the Internet is used. Furthermore, it is possible to prevent confidential information within the organization from leaking to the outside.

[0131] Here, a user (e.g., a designer of a semiconductor device) can access the information processing system of one embodiment of the present invention via, for example, dedicated application software or a web browser running on the information terminal 60. In this way, the user can enjoy services using the information processing system.

[0132] The information processing system of one embodiment of the present invention is not limited to the configuration example shown in FIG.

[0133] Fig. 9 is a schematic diagram showing a modified example of the information processing system shown in Fig. 8. The information processing system shown in Fig. 9 differs from the information processing system shown in Fig. 8 in that it does not include the information processing device 20 and in that the information processing device 10 includes a component 120 in addition to the component 110.

[0134] 9 is configured with one information processing device, which makes it possible to reduce the introduction cost and operation cost of the information processing system.

[0135] Fig. 10 is a schematic diagram showing a modified example of the information processing system shown in Fig. 8. The information processing system shown in Fig. 10 differs from the information processing system shown in Fig. 8 in that the information processing device 10 is not connected to the network 90, the information processing device 20 and the information processing device 10 are each connected to the network 80, and the information processing device 21 is connected to both the network 80 and the network 91. Note that Fig. 10 also shows an information terminal 61 connected to the network 91.

[0136] The information processing device 20 and the information terminal 60 can exchange information with each other via a network 90. ​​The information processing device 20 and the information processing device 10 can exchange information with each other via a network 80. The information processing device 21 and the information terminal 61 can exchange information with each other via a network 91. The information processing device 21 and the information processing device 10 can exchange information with each other via the network 80.

[0137] The information processing device 21 is similar to the information processing device 20, and the information terminal 61 is similar to the information terminal 60, so detailed description thereof will be omitted here.

[0138] 10 is suitable for example when two different organizations receive a service using an information processing system according to one embodiment of the present invention. That is, for example, network 90 can be a local network established within one organization, network 91 can be a local network established within another organization, and network 80 can be a global network. That is, for example, when a service provider uses classification model 130 created by a service provider using the information processing system according to one embodiment of the present invention to provide the service, the provider can own information processing device 10, one organization can own information processing device 20, and the other organization can own information processing device 21.

[0139] Furthermore, for example, when a person who receives a service using an information processing system according to one embodiment of the present invention receives the service using a classification model 130 that the person has created himself / herself, it is preferable to construct an information processing system such as that shown in Fig. 8 or 9. This makes it possible to prevent confidential information held by the person who receives the service from leaking to the outside.

[0140] Note that, as an example, a case has been described here in which two different organizations enjoy a service using an information processing system of one embodiment of the present invention, but the present invention can also be applied to cases in which one organization enjoys the service, or three or more organizations enjoy the service.

[0141] The information processing system according to one embodiment of the present invention is not limited to the above-described example configuration and can have various other configurations.

[0142] 8 and the like, the information processing system according to one embodiment of the present invention may include, for example, a storage unit and a calculation unit in each of the information processing device 10, the information processing device 20, and the information terminal 60. The storage unit has, for example, a function of storing information exchanged in the information processing system. The calculation unit has, for example, a function of controlling the exchange of information in the information processing system.

[0143] The storage unit has a function of storing a program executed by the calculation unit, and may also have a function of storing data generated by the calculation unit (e.g., calculation results, analysis results, inference results, etc.).

[0144] The storage unit includes at least one of a volatile memory and a nonvolatile memory. Examples of the volatile memory include computer-readable recording media such as DRAM and SRAM. Examples of the non-volatile memory include computer-readable recording media such as ReRAM (Resistive Random Access Memory, also known as Resistive Random Access Memory), PRAM (Phase Change Random Access Memory), FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetoresistive Random Access Memory, also known as Magnetoresistive Memory), and flash memory.

[0145] The storage unit may be a computer-readable recording medium such as a hard disk drive (HDD) or a solid state drive (SSD). Note that a removable HDD or SSD may also be used. Alternatively, a HDD or SSD that can exchange information via a network may also be used. Note that the storage unit may also be a computer-readable recording medium such as a compact disc (CD), a digital versatile disc (DVD), a universal serial bus memory (USB memory), or a secure digital card (SD card). Note that an integrated circuit (IC) chip, a magnetic tape, or a medium having at least one of these (such as a card or tag) may also be considered a computer-readable recording medium. In addition, media (paper, plastic, metal, etc.) to which codes (sequences of numbers, letters, symbols, etc.), one-dimensional codes (such as barcodes), two-dimensional codes (such as QR Code (registered trademark)), etc. are added can also be considered computer-readable recording media.

[0146] The storage unit can store, for example, at least a portion of various data handled by the above-described information processing system (such as the classification model 130, the adjacency matrix 131, the feature matrix 132, the label matrix 133, the netlist 134, the design specification 135, the netlist 136, and a dataset that can be used for training the classification model 130). Also, for example, the storage unit can store a program for executing, on one or more computers (such as the information processing device 10 and the information processing device 20), at least a portion of the above-described information processing method of one aspect of the present invention.

[0147] Here, a program is, for example, a program that causes one or more computers to function as at least part of each of the means (graph acceptance means 111, graph processing means 112, netlist acceptance means 121, graph creation means 122, label acquisition means 123, parameter determination means 124, netlist update means 125, etc.) provided in an information processing system of one embodiment of the present invention.

[0148] Therefore, one aspect of the present invention can be said to be data output from the information processing system of one aspect of the present invention. Another aspect of the present invention can be said to be a computer-readable recording medium on which the data is recorded. Another aspect of the present invention can be said to be data created by the information processing method of one aspect of the present invention. Another aspect of the present invention can be said to be a computer-readable recording medium on which the data is recorded. Another aspect of the present invention can be said to be a program for executing the information processing method of one aspect of the present invention on one or more computers. Another aspect of the present invention can be said to be a computer-readable recording medium on which the program is recorded. Another aspect of the present invention can be said to be data created by the semiconductor device design method of one aspect of the present invention. Another aspect of the present invention can be said to be a computer-readable recording medium on which the data is recorded.

[0149] The storage unit may include a database. Note that the information processing device of one embodiment of the present invention may include a database separate from the storage unit. The information processing device may have a function of retrieving data from a database that exists outside the storage unit, outside the information processing device, or outside the information processing system of one embodiment of the present invention. Furthermore, the information processing device may have a function of retrieving data from both its own database and an external database.

[0150] Alternatively, one or both of a storage and a file server can be used as the storage unit, or a database that records paths of files stored in a file server can be used as the storage unit.

[0151] The storage unit may also include at least one of NOSRAM (registered trademark) and DOSRAM (registered trademark).

[0152] NOSRAM is an abbreviation for "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)." NOSRAM refers to a memory in which memory cells are two-transistor (2T) gain cells or three-transistor (3T) gain cells and the transistors are OS transistors. OS transistors have an extremely small off-current, i.e., a current flowing between the source and drain in an off-state. NOSRAM can be used as a nonvolatile memory by retaining a charge corresponding to data in the memory cell using its extremely small off-current characteristic. In particular, NOSRAM can read stored data without destroying it (non-destructive read), making it suitable for arithmetic processing in which only data read operations are repeated in large quantities. NOSRAM can increase its data capacity by stacking layers, and therefore can be used as a large-scale cache memory, main memory, or storage memory to improve the performance of semiconductor devices.

[0153] DOSRAM is an abbreviation for "Dynamic Oxide Semiconductor RAM" and refers to a RAM having 1T (transistor) 1C (capacitor) type memory cells. DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from an external device. DOSRAM is a memory that takes advantage of the low off-state current of OS transistors.

[0154] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor.

[0155] The metal oxide included in the channel formation region preferably contains indium (In). When the metal oxide included in the channel formation region contains indium, the carrier mobility (electron mobility) of the OS transistor is increased. Furthermore, the metal oxide included in the channel formation region is preferably an oxide semiconductor containing element M. The element M is preferably at least one of aluminum (Al), gallium (Ga), and tin (Sn). Other elements applicable to element M include boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), yttrium (Y), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), and tungsten (W). However, a combination of two or more of the above elements may be used as element M. The element M is, for example, an element having a high bond energy with oxygen. For example, it is an element having a higher bond energy with oxygen than indium. The metal oxide contained in the channel formation region is preferably a metal oxide containing zinc (Zn), since zinc-containing metal oxides may be easily crystallized.

[0156] The metal oxide contained in the channel formation region is not limited to a metal oxide containing indium, but may be, for example, a metal oxide containing zinc but not indium, such as zinc tin oxide or gallium tin oxide, a metal oxide containing gallium, or a metal oxide containing tin.

[0157] The calculation unit has a function of performing processes such as calculation, analysis, and inference using data supplied from the storage unit, etc. The calculation unit can supply generated data (e.g., calculation results, analysis results, and inference results) to the storage unit.

[0158] The calculation unit has a function of acquiring data from the storage unit, and may also have a function of recording or registering data in the storage unit.

[0159] The calculation unit can perform processing in each means (graph reception means 111, graph processing means 112, netlist reception means 121, graph creation means 122, label acquisition means 123, parameter determination means 124, netlist update means 125, etc.) provided in the above-mentioned information processing system, for example.

[0160] The calculation unit may include, for example, a calculation circuit, a CPU, or a GPU.

[0161] The arithmetic unit may have a microprocessor such as a DSP (Digital Signal Processor). The microprocessor may be configured to be implemented by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array). The arithmetic unit may also have a quantum processor. The arithmetic unit can perform various data processing and program control by interpreting and executing instructions from various programs using the processor. Programs that can be executed by the processor are stored in at least one of a memory area and a storage unit of the processor.

[0162] The calculation unit may have a main memory, which may include at least one of a volatile memory such as a random access memory (RAM) and a non-volatile memory such as a read only memory (ROM). The main memory may also include at least one of the above-mentioned NOSRAM and DOSRAM.

[0163] The RAM may be, for example, a DRAM or an SRAM, and a virtual memory space is allocated and used as a working space for the processing unit. The operating system, application programs, program modules, program data, lookup tables, and the like stored in the storage unit are loaded into the RAM for execution. The data, programs, and program modules loaded into the RAM are each directly accessed and operated by the processing unit.

[0164] The ROM can store a BIOS (Basic Input / Output System), firmware, etc., which do not require rewriting. Examples of ROM include mask ROM, OTPROM (One Time Programmable Read Only Memory), and EPROM (Erasable Programmable Read Only Memory). Examples of EPROMs include UV-EPROMs (Ultra-Violet Erasable Programmable Read Only Memories), which allow stored data to be erased by exposure to ultraviolet light, EEPROMs (Electrically Erasable Programmable Read Only Memories), and flash memories.

[0165] The computing unit can include either or both of an OS transistor and a Si transistor.

[0166] The processing unit preferably includes an OS transistor. Since an OS transistor has an extremely low off-state current, the OS transistor can be used as a switch for retaining charge (data) flowing into a capacitor functioning as a memory element, thereby ensuring a long data retention period. By using this characteristic in at least one of a register and a cache memory included in the processing unit, the processing unit can be operated only when necessary and can be turned off in other cases by saving information from the previous process to the memory element. In other words, normally-off computing is enabled, and the power consumption of an information processing system according to one embodiment of the present invention can be reduced.

[0167] Note that one embodiment of the present invention is not limited to the information processing system and the information processing device described in this embodiment. At least part of the information processing system, the information processing device, and the corresponding drawings and the like described in this embodiment can be combined as appropriate.

[0168] 10: Information processing device, 20: Information processing device, 21: Information processing device, 60: Information terminal, 61: Information terminal, 80: Network, 90: Network, 91: Network, 110: Component, 111: Graph accepting means, 112: Graph processing means, 120: Component, 121: Netlist accepting means, 122: Graph creating means, 123: Label obtaining means, 124: Parameter determining means, 125: Netlist updating means, 130: Classification model, 131: Adjacency matrix, 131eg: Adjacency matrix, 132: Feature matrix, 132eg: Feature matrix, 133: Label matrix, 133eg: Label matrix, 134: Netlist, 134eg: Netlist, 135: Design specification, 135eg: Design specification, 136: Netlist, 136eg: Netlist

Claims

An information processing system that predicts a behavior of each module when a first semiconductor device is operated, a graph receiving means for receiving an input of an adjacency matrix representing a connection between modules of the first semiconductor device and a feature matrix representing a design specification for each of the modules; a graph processing means for predicting and outputting a label matrix representing a behavior of each module when the first semiconductor device is operated, based on the adjacency matrix and the feature matrix; the graph processing means includes a neural network that has been machine-trained using as training data an adjacency matrix representing connections between modules of a second semiconductor device previously designed, a feature matrix representing design specifications for each of the modules, and a label matrix representing behavior of each of the modules; Information processing system.

1. An information processing system that determines parameters of circuit elements included in a first semiconductor device based on a prediction of a behavior of each module when the first semiconductor device is operated, a netlist receiving means for receiving an input of a netlist and a design specification of the first semiconductor device; a graph creation means for creating, from the netlist and the design specifications, an adjacency matrix representing connections between modules included in the netlist and a feature matrix representing the design specifications for each of the modules; a label acquisition means for predicting and acquiring a label matrix representing a behavior of each module when the first semiconductor device is operated from the adjacency matrix and the feature matrix using a classification model; a parameter determining means for determining parameters of the circuit elements based on the label matrix; a netlist update means for updating and outputting the netlist based on the parameters determined by the parameter determination means, the classification model includes a neural network that has been machine-trained using as training data an adjacency matrix representing connections between modules of a second semiconductor device previously designed, a feature matrix representing design specifications for each of the modules, and a label matrix representing behavior of each of the modules; Information processing system. 　 In claim 2, the first semiconductor device includes a holding circuit having a function of storing data by holding charges stored in a capacitance element; The parameter of the circuit element is the capacitance of the capacitive element. Information processing system. 　 In any one of claims 1 to 3, design specifications of the first semiconductor device and the second semiconductor device include an operating voltage of a module and an operating frequency of the module; The behavior of each of the first semiconductor device and the second semiconductor device includes a temperature of a module. Information processing system. 　 In any one of claims 1 to 3, design specifications of the first semiconductor device and the second semiconductor device include an operating voltage of a module and an operating frequency of the module; The behavior of each of the first semiconductor device and the second semiconductor device includes a power consumption of a module. Information processing system.

Images