Vertical device and semiconductor module

Abstract

The present invention provides a vertical device including a semiconductor substrate that has an upper surface and a lower surface, and a lower surface electrode that is provided to the entire lower surface of the semiconductor substrate, wherein the lower surface electrode contains copper. The lower surface electrode has a lowermost layer exposed on the farthest surface from the lower surface of the semiconductor substrate, the lowermost layer contains copper, the percentage of copper in the lowermost layer is 50-90 wt%, and the thickness of the lowermost layer is 0.2-0.8 μm.

Description

Vertical Devices and Semiconductor Modules

[0001] The present invention relates to a vertical device and a semiconductor module.

[0002] Conventionally, when an electronic component is bonded to a substrate using a thermal bonding material, a configuration in which an Au—Cu alloy layer is provided at the bonding portion is known (see Patent Document 1). Also, a Ti / Ni / Au laminated film is used as the back electrode of a power device (see Non-Patent Document 1). [Prior Art Literature] [Patent Document] [Patent Document 1] JP 2015-90900 A [Non-Patent Document] [Non-Patent Document 1] Kimiharu Kayagawa et al., "Interface Structure and Bondability of Power Device Back Electrode and Lead-Free Solder," Denso Technical Review, 2006, Vol. 11, No. 2, pp. 108-114 General disclosure

[0003] (Problem to be solved) To improve the reliability of the joints of semiconductor modules. (Means for solving the problem)

[0004] In order to solve the above problems, a first aspect of the present invention provides a vertical device including a semiconductor substrate having an upper surface and a lower surface. The vertical device may include a lower surface electrode provided on the entire lower surface of the semiconductor substrate. In any of the vertical devices, the lower surface electrode may include copper.

[0005] In any of the vertical devices described above, the bottom electrode may have a bottom layer exposed at a surface of the semiconductor substrate farthest from the bottom surface, and the bottom layer may include copper.

[0006] In any of the above vertical devices, the bottom layer may be an alloy containing copper and gold.

[0007] In any of the vertical devices described above, the proportion of copper in the bottom layer may be 50 wt % or more.

[0008] In any of the vertical devices described above, the proportion of copper in the bottom layer may be 90 wt % or less.

[0009] In any of the vertical devices described above, the thickness of the bottom layer may be 0.2 μm or more.

[0010] In any of the vertical devices described above, the bottom layer may have a thickness of 0.8 μm or less.

[0011] In any of the vertical devices described above, the bottom electrode may have an intermediate layer between the bottom layer and the bottom surface of the semiconductor substrate, and the intermediate layer may include nickel.

[0012] In any of the vertical devices described above, the bottom electrode may have an upper layer between the intermediate layer and the bottom surface of the semiconductor substrate. In any of the vertical devices described above, the upper layer may include titanium.

[0013] In any of the vertical devices described above, the thickness of the bottom layer may be 0.05 to 2 times the thickness of the intermediate layer.

[0014] In any of the vertical devices described above, the bottom electrode may have a gold-containing layer exposed on a surface of the semiconductor substrate farthest from the bottom surface, and the bottom electrode may have a copper-containing layer in contact with the gold-containing layer.

[0015] To solve the above problems, a second aspect of the present invention provides a semiconductor module including a vertical device and a mounting substrate on which the vertical device is mounted. In the semiconductor module, the vertical device may include a semiconductor substrate having an upper surface and a lower surface, and a lower surface electrode provided on the entire lower surface of the semiconductor substrate. In any of the semiconductor modules, the mounting substrate may include a mounting electrode soldered to the lower surface electrode of the vertical device. In any of the semiconductor modules, a bonding layer may be formed between the mounting electrode and the lower surface electrode. In any of the semiconductor modules, the bonding layer may contain copper and tin. In any of the semiconductor modules, the copper concentration in the bonding layer may decrease with increasing distance from the lower surface electrode.

[0016] In any of the above semiconductor modules, the outermost layer of the mounting electrode may not contain copper.

[0017] In any of the above semiconductor modules, a solder layer may be formed between the bonding layer and the mounting electrode. In any of the above semiconductor modules, at least a portion of the solder layer may be free of copper.

[0018] In any of the above semiconductor modules, the bonding layer may further contain nickel. In any of the above semiconductor modules, the concentration of nickel in the bonding layer may decrease with increasing distance from the lower electrode.

[0019] In any of the semiconductor modules described above, the atomic composition percentage of copper contained in the bonding layer may be greater than the atomic composition percentage of nickel contained in the bonding layer.

[0020] In any of the above semiconductor modules, the concentration of tin in the bonding layer may decrease with increasing distance from the mounting electrode.

[0021] In any of the semiconductor modules described above, a solder layer may be formed between the bonding layer and the mounting electrode, and a proportion of copper in the bonding layer by weight to a total weight of the solder layer may be 0.2% or more and 0.8% or less.

[0022] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also be inventions.

[0023] 3 is a diagram showing a vertical device 100 according to an embodiment of the present invention; FIG. 4 is a diagram showing a vertical device 200 according to a comparative example; FIG. 5 is a diagram showing a semiconductor module 300 according to an embodiment of the present invention; FIG. 6 is a diagram showing a semiconductor module 400 according to a comparative example; FIG. 7 is a diagram showing a concentration distribution in the AA' cross section of the semiconductor module 300 in FIG. 3; and FIG. 8 is a diagram showing a vertical device 500 according to another embodiment.

[0024] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification, the same parts in each drawing are given the same reference numerals, and their description may be omitted. Furthermore, for the sake of convenience, some components may not be illustrated.

[0025] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0026] In this specification, technical matters may be explained using an orthogonal coordinate system of X, Y, and Z axes. The orthogonal coordinate system merely specifies the relative positions of components and does not limit a specific direction. For example, the Z-axis direction does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0027] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0028] FIG. 1 is a diagram showing a vertical device 100 according to an embodiment of the present invention. The vertical device 100 includes a semiconductor substrate 10 and a bottom electrode 24. The semiconductor substrate 10 has a top surface 21 and a bottom surface 23. The top surface 21 and the bottom surface 23 are the two main surfaces of the semiconductor substrate 10. A vertical device refers to a semiconductor device in which a main current flows between the top surface and the bottom surface. The vertical device 100 may be a semiconductor device such as a transistor, and examples thereof include a vertical MOSFET or a vertical IGBT. The main current is, for example, a drain current in a MOSFET or a collector current in an IGBT.

[0029] An element structure such as a transistor is formed on the semiconductor substrate 10. For example, a MOS gate structure is formed on the upper surface 21 side of the semiconductor substrate 10, and a gate pad and a gate runner for applying a gate voltage to the MOS gate are formed above the upper surface 21 of the semiconductor substrate 10. Furthermore, a source electrode of a MOSFET or an emitter electrode of an IGBT may be formed above the upper surface 21 of the semiconductor substrate 10. However, the structures of the semiconductor substrate 10 and the upper surface 21 of the semiconductor substrate 10 are omitted in FIG. 1 . As an example, the semiconductor substrate 10 is a silicon substrate or a silicon carbide substrate.

[0030] The lower electrode 24 is provided in contact with the lower surface 23 of the semiconductor substrate 10. The lower electrode 24 may be provided on the entire lower surface 23 of the semiconductor substrate 10. The lower electrode 24 corresponds to the drain electrode in a MOSFET or the collector electrode in an IGBT.

[0031] Here, the vertical device 100 refers to the state of the chip before being mounted on a module. That is, the vertical device 100 is soldered to a mounting substrate and connected to an external power supply or the like via a lead frame or the like to be used as a semiconductor device for power conversion, for example, but the vertical device 100 shown in Fig. 1 refers to the state before being soldered to the mounting substrate. For reasons that will be described later, the bottom electrode 24 of the vertical device 100 contains copper.

[0032] The lower electrode 24 may have multiple layers. In this example, the lower electrode 24 has a bottom layer 12, a middle layer 14, and an upper layer 16. However, the number of layers included in the lower electrode 24 is not limited to this. The lower electrode 24 may have two layers, or may have four or more layers.

[0033] The bottom layer 12 is exposed at a surface 53 of the bottom electrode 24 that is farthest from the bottom surface 23 of the semiconductor substrate 10. More specifically, the bottom layer 12 is the layer of the bottom electrode 24 that is formed at a position farthest from the bottom surface 23 of the semiconductor substrate 10 in the depth direction (Z-axis direction). That is, the bottom layer 12 is exposed at a surface 53 of the bottom electrode 24. For reasons described below, the bottom layer 12 may contain copper. In this example, the bottom layer 12 is an alloy containing copper and gold. The bottom layer 12 may be composed primarily of copper and gold. In this specification, the term "major component" refers to a component with a weight ratio of 50% or more. In the bottom layer 12, the sum of the weight ratio of copper and the weight ratio of gold may be 50% or more. In the bottom layer 12, the sum of the weight ratio of copper and the weight ratio of gold may be 100%. The bottom layer 12 may be an alloy containing copper and silver. The bottom layer 12 may refer to a region that is exposed on the surface 53 of the lower electrode 24 and in which copper exists continuously from the surface 53 in the depth direction.

[0034] The intermediate layer 14 is located between the bottom layer 12 and the bottom surface 23 of the semiconductor substrate 10. In this example, the intermediate layer 14 is in contact with the bottom layer 12 but not with the bottom surface 23 of the semiconductor substrate 10. The intermediate layer 14 may contain nickel or may be mainly composed of nickel. In this example, the weight ratio of nickel in the intermediate layer 14 is 100%. The nickel in the intermediate layer 14 forms an alloy layer with the solder when the vertical device 100 is soldered to a mounting substrate.

[0035] The upper layer 16 is located between the intermediate layer 14 and the lower surface 23 of the semiconductor substrate 10. In this example, the upper layer 16 is in contact with the intermediate layer 14 and the lower surface 23 of the semiconductor substrate. The upper layer 16 may contain titanium or may be primarily composed of titanium. In this example, the upper layer 16 has a titanium weight ratio of 100%. By providing the upper layer 16 containing titanium, an ohmic contact can be established between the lower electrode 24 and the semiconductor substrate 10. However, the lower electrode 24 may further have a top layer containing aluminum or the like between the upper layer 16 and the lower surface 23. The bottom layer 12, the intermediate layer 14, and the upper layer 16 are formed, for example, by sputtering. In sputtering the bottom layer 12, a copper-gold alloy may be used as a target, or copper and gold targets may be prepared separately and discharged simultaneously.

[0036] 2 is a diagram showing a vertical device 200 according to a comparative example. The vertical device 200 of this example differs from the vertical device 100 in the configuration of the bottom electrode 24. Other points are the same as those of the vertical device 100, and therefore a description thereof will be omitted.

[0037] The bottom electrode 24 of this example has a gold layer 42 exposed on the surface 53. That is, the gold layer 42 is provided in place of the bottom layer 12 in the bottom electrode 24 of the vertical device 100. The gold layer 42 is a layer made of gold.

[0038] In the vertical device 100 of the embodiment, the bottom layer 12 is made of an alloy, which reduces the amount of expensive gold used and reduces costs compared to the case where the gold layer 42 of the vertical device 200 is used. Furthermore, the bottom layer 12 containing gold can maintain solder wettability and corrosion resistance.

[0039] 3 is a diagram showing a semiconductor module 300 according to an embodiment of the present invention. The semiconductor module 300 includes a vertical device 100 and a mounting substrate 32 on which the vertical device 100 is mounted. The vertical device 100 is attached to the mounting substrate 32 by soldering the bottom electrodes 24. In other words, the semiconductor module 300 shows a state after the vertical device 100 has been soldered to the mounting substrate 32.

[0040] The vertical device 100 of this example may be similar to the vertical device 100 described in FIG. 1 . That is, the vertical device 100 of this example also includes a semiconductor substrate 10 having an upper surface 21 and a lower surface 23, and a lower electrode 24 provided on the entire lower surface 23 of the semiconductor substrate 10. However, as will be described later, the bottom layer 12 may disappear due to soldering. The bottom electrode 24 of this example does not include the bottom layer 12.

[0041] The mounting substrate 32 includes a circuit board 30 and mounting electrodes 28. The mounting substrate 32 in this example may be an insulated circuit board having metal plates on the upper and lower surfaces of a ceramic plate. In this case, the ceramic plate may correspond to the circuit board 30, and the metal plates may correspond to the mounting electrodes 28. The mounting electrodes 28 are soldered to the lower electrodes 24 of the vertical device 100. The mounting electrodes 28 are electrodes of the mounting substrate 32 that are exposed on a surface 29 that is soldered to the vertical device 100.

[0042] A bonding layer 22 is formed between the mounting electrode 28 and the lower electrode 24. The bonding layer 22 is an alloy layer formed during soldering. In this example, the bonding layer 22 is in contact with the lower electrode 24.

[0043] A solder layer 26 is formed between the bonding layer 22 and the mounting substrate 32. The solder layer 26 is a layer of solder that remains during soldering without forming the bonding layer 22. The solder layer 26 is in contact with the mounting substrate 32.

[0044] When the vertical device 100 is soldered to the mounting substrate 32, the gold in the bottom layer 12 diffuses into the solder due to its fast diffusion rate. The copper in the bottom layer 12 interdiffuses with the tin contained in the solder to form an alloy. The layer in which this alloy is formed is the bonding layer 22. Therefore, in this example, the bonding layer 22 contains copper and tin. The bonding layer 22 may be primarily composed of copper and tin. Furthermore, the nickel in the intermediate layer 14 may also interdiffuse with the solder during soldering to form an alloy layer. In this case, the bonding layer 22 contains nickel. In this example, the bonding layer 22 is an alloy in which the sum of the weight ratios of copper, tin, and nickel is 100%. All of the copper contained in the bottom layer 12 may be contained in the bonding layer 22. The bonding layer 22 may be an alloy containing at least copper, tin, and nickel, or may be primarily composed of copper, tin, and nickel.

[0045] However, since the bottom layer 12 containing copper is provided on the surface 53 of the lower electrode 24, it is easier to form an alloy with the solder than the intermediate layer 14. Furthermore, copper diffuses into the solder faster than nickel. Therefore, the atomic composition percentage of copper contained in the bonding layer 22 may be greater than the atomic composition percentage of nickel contained in the bonding layer 22. The composition ratio of the alloy of the bonding layer 22 is, for example, (Cu, Ni). ６ Sn ５ or (Cu, Ni) ３ It is Sn.

[0046] 4 is a diagram showing a semiconductor module 400 according to a comparative example. The semiconductor module 400 differs from the semiconductor module 300 in that the vertical device 200 according to the comparative example is soldered to a mounting substrate 32. The configuration of the mounting substrate 32 is similar to that of the semiconductor module 300.

[0047] The gold layer 42 of the vertical device 200 diffuses into the solder and disappears during soldering. In the semiconductor module 400, a bonding layer 34 is also formed between the mounting substrate 32 and the lower electrode 24. However, in this example, the bonding layer 34 is an alloy made of tin in the solder and nickel in the intermediate layer 14. The composition of the bonding layer 34 is, for example, Ni ３ Sn ４In the semiconductor module 400 as well, the solder layer 26 is formed between the mounting substrate 32 and the bonding layer 34 .

[0048] Generally, when a vertical device is turned on, it generates heat. Repeated on / off switching applies thermal stress to the joint between the vertical device and the mounting board, eventually causing cracks to form at the joint. When cracks occur, an air gap forms at the joint, reducing heat dissipation and leading to the destruction of the vertical device. The number of on / off cycles required to cause the destruction is called the dTjP / C tolerance. A high dTjP / C tolerance means that the joint is resistant to thermal stress. In the future, semiconductor modules will be required to become even smaller and have higher performance, and power density will tend to increase, requiring them to operate at high temperatures. For this reason, a high dTjP / C tolerance is desirable.

[0049] The bonding layer 22 formed in the semiconductor module 300 and made of an alloy of copper, tin, and nickel has lower rigidity than the bonding layer 34 formed in the semiconductor module 400 and made of an alloy of tin and nickel. Therefore, when thermal stress is applied to the bonded portion, the bonding layer 22 deforms, thereby suppressing the occurrence of cracks. As a result, the dTjP / C resistance of the semiconductor module 300 is greater than the dTjP / C resistance of the semiconductor module 400. In other words, the bonding reliability during continuous high-temperature operation of the semiconductor module 300 is improved. In particular, when the semiconductor substrate 10 is a silicon carbide substrate, the rigidity of a silicon carbide substrate is higher than that of a silicon substrate, and therefore the above-mentioned effect is more pronounced.

[0050] Furthermore, when the vertical device 200 is soldered, after the gold layer 42 disappears, the nickel in the intermediate layer 14 and the solder interdiffuse to form the bonding layer 34. On the other hand, when the vertical device 100 is soldered, the copper in the bottom layer 12 preferentially forms an alloy with the solder, making interdiffusion between the nickel in the intermediate layer 14 and the solder less likely to occur than in the vertical device 200. Therefore, the thickness t2' (see FIG. 3) of the intermediate layer 14 in the semiconductor module 300 is greater than the thickness t2'' (see FIG. 4) of the intermediate layer 14 in the semiconductor module 400. In other words, solder erosion of the intermediate layer 14 can be reduced.

[0051] Generally, the titanium constituting the upper layer 16 does not bond well to solder. Therefore, it is preferable that the upper layer 16 does not form an alloy with the solder. By reducing the solder erosion of the intermediate layer 14, it is possible to suppress the formation of an alloy between the upper layer 16 and the solder even when the soldering conditions are high temperature, thereby improving the bonding reliability of the semiconductor module 300.

[0052] The copper ratio in the bottom layer 12 (see FIG. 1 ) of the vertical device 100 may be 50 wt % or more. This allows the formation of a copper-containing bonding layer 22 in the semiconductor module 300. The copper ratio in the bottom layer 12 may be 90 wt % or less. The bottom layer 12 may contain other elements such as gold to maintain solder wettability and corrosion resistance. In this example, the copper ratio in the bottom layer 12 is 75 wt %. The copper ratio in the bottom layer 12 may be 60 wt % or more, 70 wt % or more, or 80 wt % or less.

[0053] The thickness t1 (see FIG. 1) of the bottom layer 12 in the vertical device 100 may be 0.2 μm or more. This allows the formation of a copper-containing bonding layer 22 in the semiconductor module 300. On the other hand, if the thickness t1 of the bottom layer 12 is too large, warping of the chip may occur during soldering, which may result in the formation of voids or shrinkage cavities in the solder layer. Therefore, the thickness t1 of the bottom layer 12 may be 0.8 μm or less. The thickness t1 of the bottom layer 12 may be 0.4 μm or more and 0.5 μm or less.

[0054] The thickness t1 of the bottom layer 12 may be 0.05 times or more and 2 times or less the thickness t2 of the intermediate layer 14 (see FIG. 1 ). By setting the thickness t1 of the bottom layer 12 and the thickness t2 of the intermediate layer 14 within the above-mentioned ranges, it is possible to form a bonding layer 22 containing copper while suppressing alloy formation between the bottom layer 12 and the upper layer 16 and the solder. The thickness t1 of the bottom layer 12 may be 0.1 times or more, 1 time or more, or 2 times or more the thickness t2 of the intermediate layer 14. The thickness t1 of the bottom layer 12 may be 5 times or less, 3 times or less, or 1 time or less the thickness t2 of the intermediate layer 14.

[0055] The thickness t1 of the bottom layer 12 may be 0.5 to 20 times the thickness t3 (see FIG. 1 ) of the upper layer 16. The thickness t1 of the bottom layer 12 may be 1 to 2 times the thickness t3 of the upper layer 16. The thickness t1 of the bottom layer 12 may be 5 to 3 times the thickness t3 of the upper layer 16.

[0056] In the semiconductor module 300, the outermost layer of the mounting electrode 28 does not need to contain copper. As an example, the mounting electrode 28 may have a layer containing copper, but the surface 29 of the mounting electrode 28 is covered with NiP plating (from the standpoint of corrosion resistance, etc.). Alternatively, the mounting electrode 28 may be an aluminum electrode. Since the outermost layer of the mounting electrode 28 does not contain copper, copper does not diffuse from the mounting substrate 32. As a result, the bonding layer 22 is formed by the copper contained in the bottom layer 12, making it easier to control the composition ratio and thickness t2' of the bonding layer 22.

[0057] In the semiconductor module 300, the solder layer 26 may not contain copper. In other words, soldering may be performed using a copper-free solder. This makes it easier to control the composition ratio and thickness t2′ of the bonding layer 22, as described above. Furthermore, excessive copper, nickel, and tin alloy formation in the bulk of the solder layer 26, may reduce bonding reliability. The absence of copper in the solder allows the bonding layer 22 to be selectively formed between the lower electrode 24 and the solder layer 26. Furthermore, adding excessive copper to the solder would rapidly increase the solder melting point, resulting in a high soldering temperature. The absence of copper in the solder allows the soldering temperature to be lowered. At least a portion of the solder layer 26 may be copper-free. The surface of the solder layer 26 that contacts the mounting electrode 28 may be copper-free. The portion of the solder layer 26 closer to the mounting electrode 28 than the center in the depth direction may be copper-free. The proportion of copper contained in the solder layer 26 may be 1 wt % or less, 0.5 wt % or less, 0.1 wt % or less, or 0.01 wt % or more.

[0058] The proportion of the weight of copper in the bonding layer 22 to the total weight of the solder layer 26 may be 0.2% or more and 0.8% or less, thereby allowing a sufficient amount of bonding layer 22 to be formed.

[0059] The thickness t4 of the bonding layer 22 (see FIG. 3 ) may be 0.5 μm or more and 10 μm or less. The thickness t4 of the bonding layer 22 may be 1 μm or more, or 2 μm or more. The thickness t4 of the bonding layer 22 may be 5 μm or less, 3 μm or less, 2 μm or less, or 1 μm or less. Furthermore, the thickness t4 of the bonding layer 22 may be 0.3 times or more, 1 time or more, or 2 times or more the thickness t2′ of the intermediate layer 14 in the semiconductor module 300. The thickness t4 of the bonding layer 22 may be 30 times or less, 5 times or less, or 2 times or less the thickness t2′ of the intermediate layer 14.

[0060] Fig. 5 is a diagram showing the concentration distribution in the A-A' cross section of the semiconductor module 300 in Fig. 3. The A-A' cross section is a cross section that extends from the interface between the bonding layer 22 and the intermediate layer 14 (lower electrode 24) across the bonding layer 22 in the depth direction (Z-axis direction) and reaches the inside of the solder layer 26.

[0061] As described above, during soldering, copper in the bottom layer 12 interdiffuses with the solder to form the bonding layer 22. Therefore, in the semiconductor module 300 of this example, the copper concentration in the bonding layer 22 decreases the further away from the bottom electrode 24. The copper concentration in the bonding layer 22 may decrease without ever increasing from the interface with the bottom electrode 24 to the interface with the solder layer 26. Hereinafter, a decrease without ever increasing may be referred to as a monotonic decrease. All of the copper contained in the bonding layer 22 may be the copper that was contained in the bottom layer 12.

[0062] As described above, the nickel in the intermediate layer 14 also interdiffuses with the solder during soldering to form the bonding layer 22. Therefore, in the semiconductor module 300 of this example, the nickel concentration in the bonding layer 22 decreases the further away from the bottom electrode 24. The nickel concentration in the bonding layer 22 may monotonically decrease from the interface with the bottom electrode 24 to the interface with the solder layer 26. All of the nickel contained in the bonding layer 22 may be nickel that was contained in the intermediate layer 14. The interface between the bonding layer 22 and the solder layer 26 may be the position where the nickel has diffused furthest toward the solder layer 26.

[0063] As described above, the copper-containing bottom layer 12 is provided on the surface 53 of the lower electrode 24, and therefore is more likely to form an alloy with solder than the intermediate layer 14. Furthermore, copper diffuses into solder faster than nickel. Therefore, the concentration of copper contained in the bonding layer 22 may be greater than the concentration of nickel contained in the bonding layer 22. The concentration may be a value obtained by averaging the concentration distribution over the entire region of the bonding layer 22. Furthermore, the integrated value of the copper concentration over the entire region of the bonding layer 22 may be greater than the integrated value of the nickel concentration over the entire region of the bonding layer 22.

[0064] The tin in the solder interdiffuses with the bottom layer 12 and the intermediate layer 14 to form the bonding layer 22. Therefore, in the semiconductor module 300 of this example, the tin concentration in the bonding layer 22 decreases the further away from the mounting electrode 28 (or the solder layer 26). The interface between the bonding layer 22 and the intermediate layer 14 may be the position where the tin has diffused closest to the intermediate layer 14.

[0065] 6 is a diagram showing a vertical device 500 according to another embodiment. The vertical device 500 of this example includes a semiconductor substrate 10 and a bottom electrode 24. The semiconductor substrate 10 is the same as the semiconductor substrate 10 in the vertical device 100.

[0066] The bottom electrode 24 of the vertical device 500 includes a gold-containing layer 46, a copper-containing layer 44, an intermediate layer 14, and an upper layer 16. The intermediate layer 14 and the upper layer 16 of the vertical device 500 may be similar to the intermediate layer 14 and the upper layer 16 of the vertical device 100.

[0067] The gold-containing layer 46 in this example is exposed on the surface 53 of the lower electrode 24 that is farthest from the lower surface 23 of the semiconductor substrate 10. The gold-containing layer 46 contains gold as a constituent element. The gold-containing layer 46 may be mainly composed of gold, and may be a layer with a weight ratio of gold of 100%. However, instead of the gold-containing layer 46, a silver-containing layer containing silver may be provided. The gold-containing layer 46 in this example does not contain copper.

[0068] The copper-containing layer 44 in this example is a layer that contacts the gold-containing layer 46 and contains copper. The copper-containing layer 44 may be primarily composed of copper, and may be a layer with a copper weight ratio of 100%. The copper-containing layer 44 may be the first region where copper is continuously present from the surface 53 of the lower electrode 24 toward the semiconductor substrate 10. The copper-containing layer 44 in this example is not exposed at the surface 53 of the lower electrode 24. The copper-containing layer 44 is provided between the gold-containing layer 46 and the intermediate layer 14.

[0069] The vertical device 500 having such a configuration can also provide the same effects as the vertical device 100. Furthermore, when the vertical device 500 is soldered to the mounting substrate 32 to form a semiconductor module, the gold-containing layer 46 diffuses into the solder, and the copper-containing layer 44 and the intermediate layer 14 form the bonding layer 22 shown in FIG. 3. Therefore, the semiconductor module can provide the same effects as the semiconductor module 300. That is, the semiconductor module also has the same bonding layer 22 as the semiconductor module 300, and the concentration distribution of the bonding layer 22 and the solder layer 26 may be the same as the concentration distribution shown in FIG.

[0070] The copper ratio of the copper-containing layer 44 to the gold-containing layer 46 and the copper-containing layer 44 may be 50 wt % or more and 90 wt % or less. The copper-containing layer 44 may be thicker than the gold-containing layer 46. In addition, the total thickness t5 of the gold-containing layer 46 and the copper-containing layer 44 may be substituted for the thickness t1 of the bottom layer 12 in FIG. 1 , and the relationship with the thicknesses of the other layers (e.g., t2 or t3) described above may be applied.

[0071] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0072] DESCRIPTION OF SYMBOLS 10: Semiconductor substrate, 12: Bottom layer, 14: Intermediate layer, 16: Upper layer, 22: Bonding layer, 23: Bottom surface, 24: Bottom electrode, 26: Solder layer, 28: Mounting electrode, 29: Surface, 30: Circuit board, 32: Mounting board, 34: Bonding layer, 42: Gold layer, 44: Copper-containing layer, 46: Gold-containing layer, 53: Surface, 100: Vertical device, 200: Vertical device, 300: Semiconductor module, 400: Semiconductor module, 500: Vertical device

Claims

1. A vertical device comprising: a semiconductor substrate having an upper surface and a lower surface; and a lower surface electrode provided on the entire lower surface of the semiconductor substrate, the lower surface electrode comprising copper.

2. The vertical device of claim 1, wherein the bottom electrode has a bottom layer exposed at a surface of the semiconductor substrate furthest from the bottom surface, the bottom layer comprising copper.

3. The vertical device of claim 2, wherein the bottom layer is an alloy containing copper and gold.

4. The vertical device according to claim 2, wherein the ratio of copper in said bottom layer is 50 wt % or more.

5. The vertical device according to claim 2, wherein the ratio of copper in said bottom layer is 90 wt % or less.

6. The vertical device according to claim 2, wherein the thickness of the bottom layer is 0.2 μm or more.

7. The vertical device according to claim 2, wherein the thickness of said bottom layer is 0.8 μm or less.

8. The vertical device according to claim 2, wherein the bottom electrode has an intermediate layer between the bottom layer and the bottom surface of the semiconductor substrate, the intermediate layer comprising nickel.

9. The vertical device of claim 8, wherein the bottom electrode has an upper layer between the intermediate layer and the bottom surface of the semiconductor substrate, the upper layer comprising titanium.

10. The vertical device according to claim 8, wherein the thickness of the bottom layer is 0.05 to 2 times the thickness of the intermediate layer.

11. The vertical device according to claim 1, wherein the bottom electrode comprises: a gold-containing layer that is exposed on the surface of the semiconductor substrate furthest from the bottom surface and that contains gold; and a copper-containing layer that is in contact with the gold-containing layer and that contains copper.

12. A semiconductor module comprising a vertical device and a mounting substrate on which the vertical device is mounted, wherein the vertical device comprises: a semiconductor substrate having an upper surface and a lower surface; and a lower surface electrode provided on the entire lower surface of the semiconductor substrate; the mounting substrate comprises a mounting electrode soldered to the lower surface electrode of the vertical device; and a bonding layer is formed between the mounting electrode and the lower surface electrode, the bonding layer containing copper and tin, and a copper concentration in the bonding layer decreases with increasing distance from the lower surface electrode.

13. The semiconductor module according to claim 12, wherein the outermost layer of the mounting electrode does not contain copper.

14. The semiconductor module according to claim 12, wherein a solder layer is formed between the bonding layer and the mounting electrode, and at least a portion of the solder layer does not contain copper.

15. The semiconductor module according to any one of claims 12 to 14, wherein the bonding layer further contains nickel, and the concentration of nickel in the bonding layer decreases with increasing distance from the lower electrode.

16. The semiconductor module according to claim 15, wherein the atomic composition percentage of copper contained in said bonding layer is greater than the atomic composition percentage of nickel contained in said bonding layer.

17. The semiconductor module according to claim 12, wherein the concentration of tin in the bonding layer decreases with increasing distance from the mounting electrode.

18. The semiconductor module according to claim 12, wherein a solder layer is formed between the bonding layer and the mounting electrode, and the weight of copper in the bonding layer accounts for 0.2% or more and 0.8% or less of the total weight of the solder layer.

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