Silicon carbide substrate, method for manufacturing silicon carbide epitaxial substrate, and method for manufacturing silicon carbide semiconductor device

Abstract

This silicon carbide substrate has a main surface. The main surface is inclined in the [11-20] direction with respect to a / {0001 / } plane. When the [11-20] direction is defined as an off-downstream direction, and the [-1-120] direction is defined as an off-upstream direction, the main surface is constituted by a first half-surface region, which is positioned in the off-downstream direction with respect to the center of the main surface, and a second half-surface region, which is positioned in the off-upstream direction with respect to the center thereof, in plan view observed perpendicularly to the main surface. When the surface density of a threading screw dislocation in the first half-surface region is defined as a first surface density, and the surface density of a threading screw dislocation in the second half-surface region is defined as a second surface density, a value obtained by dividing the first surface density by the second surface density is 88% or less.

Description

Silicon carbide substrate, method for manufacturing silicon carbide epitaxial substrate, and method for manufacturing silicon carbide semiconductor device

[0001] The present disclosure relates to a silicon carbide substrate, a method for manufacturing a silicon carbide epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device. This application claims priority to Japanese Patent Application No. 2023-213720, filed December 19, 2023. The entire contents of this Japanese patent application are incorporated herein by reference.

[0002] Japanese Patent Laid-Open Publication No. 2014-28757 (Patent Document 1) describes a silicon carbide single crystal substrate having a central circular region centered on the center point of the substrate and a doughnut-shaped peripheral region excluding the central circular region, in which the average screw dislocation density observed in the doughnut-shaped peripheral region is 80% or less of the average screw dislocation density observed in the central circular region.

[0003] JP 2014-28757 A

[0004] A silicon carbide substrate according to the present disclosure is a silicon carbide substrate having a main surface. The main surface is inclined in the [11-20] direction with respect to the {0001} plane. When the [11-20] direction is the off-downstream direction and the [-1-120] direction is the off-upstream direction, in a plan view perpendicular to the main surface, the main surface is composed of a first half-surface region located in the off-downstream direction with respect to the center of the main surface and a second half-surface region located in the off-upstream direction with respect to the center. When the areal density of threading screw dislocations in the first half-surface region is defined as a first areal density and the areal density of threading screw dislocations in the second half-surface region is defined as a second areal density, the value obtained by dividing the first areal density by the second areal density is 88% or less.

[0005] FIG. 1 is a cross-sectional view schematically showing the configuration of a silicon carbide single crystal according to this embodiment. FIG. 2 is a cross-sectional view schematically showing the configuration of a silicon carbide substrate according to this embodiment. FIG. 3 is a plan view schematically showing the configuration of a silicon carbide substrate according to this embodiment. FIG. 4 is a plan view schematically showing a region for measuring the areal density of stacking faults. FIG. 5 is a flow diagram generally showing a method for manufacturing a silicon carbide substrate according to this embodiment. FIG. 6 is a cross-sectional view schematically showing a step of preparing a growth apparatus. FIG. 7 is a cross-sectional view schematically showing a first growth step. FIG. 8 is a schematic view showing the relationship between the temperature of the growth surface and the flow rate of nitrogen gas and time. FIG. 9 is a schematic view showing the relationship between the growth surface and the {0001} plane. FIG. 10 is a schematic view showing the process of crystal growth in region X of FIG. 9. FIG. 11 is a schematic view showing the process of crystal growth in region XI of FIG. 9. FIG. 12 is a cross-sectional view schematically showing a second growth step. FIG. 13 is a flow diagram generally showing a method for manufacturing a silicon carbide semiconductor device according to this embodiment. FIG. 14 is a cross-sectional view schematically illustrating the configuration of a silicon carbide epitaxial substrate according to the present embodiment. FIG. 15 is a cross-sectional view schematically illustrating a step of forming a body region. FIG. 16 is a cross-sectional view schematically illustrating a step of forming a source region. FIG. 17 is a cross-sectional view schematically illustrating a step of forming a trench in a fifth main surface of a silicon carbide epitaxial layer. FIG. 18 is a cross-sectional view schematically illustrating a step of forming a gate insulating film. FIG. 19 is a cross-sectional view schematically illustrating a step of forming a gate electrode and an interlayer insulating film. FIG. 20 is a cross-sectional view schematically illustrating the configuration of a silicon carbide semiconductor device according to the present embodiment. FIG. 21 is a diagram illustrating the distribution of threading screw dislocations in a first main surface of a silicon carbide substrate according to a comparative example. FIG. 22 is a diagram illustrating the distribution of threading screw dislocations in a first main surface of a silicon carbide substrate according to an example.

[0006] [Problem to be Solved by the Present Disclosure] In the silicon carbide single crystal substrate described in Patent Document 1, the screw dislocation density is higher in the central portion of the substrate than in the peripheral portion of the substrate. Therefore, when a semiconductor device is manufactured using this substrate, defects may occur in the semiconductor device due to screw dislocations in the central portion of the substrate. This reduces the yield of the semiconductor device.

[0007] An object of the present disclosure is to provide a silicon carbide substrate, a method for manufacturing a silicon carbide epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device, which are capable of improving the yield of semiconductor devices. [Effects of the Present Disclosure] According to the present disclosure, it is possible to provide a silicon carbide substrate, a method for manufacturing a silicon carbide epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device, which are capable of improving the yield of semiconductor devices.

[0008] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. Note that in the crystallographic descriptions in this specification, individual orientations are represented by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. Furthermore, for negative indices, in crystallography, a "-" (bar) is placed above the number, but in this specification, a negative sign is placed before the number.

[0009] (1) A silicon carbide substrate according to the present disclosure is a silicon carbide substrate having a main surface. The main surface is inclined in the [11-20] direction with respect to the {0001} plane. When the [11-20] direction is the off-downstream direction and the [-1-120] direction is the off-upstream direction, in a plan view perpendicular to the main surface, the main surface is composed of a first half-surface region located in the off-downstream direction with respect to the center of the main surface and a second half-surface region located in the off-upstream direction with respect to the center. When the areal density of threading screw dislocations in the first half-surface region is defined as a first areal density and the areal density of threading screw dislocations in the second half-surface region is defined as a second areal density, the value obtained by dividing the first areal density by the second areal density is 88% or less. In this way, the areal density of threading screw dislocations is sufficiently reduced in the first half-surface region. This can improve the yield of semiconductor devices.

[0010] (2) In the silicon carbide substrate according to (1) above, a value obtained by dividing the first areal density by the second areal density may be equal to or greater than 68%.

[0011] (3) In the silicon carbide substrate according to (1) or (2), when the main surface is divided into a plurality of square regions with a side length of 2.6 mm, the value obtained by dividing the number of the square regions included in the first half region and having stacking faults by the total number of the square regions included in the first half region may be 4% or less. The value obtained by dividing the number of the square regions included in the second half region and having stacking faults by the total number of the square regions included in the second half region may be 0%.

[0012] (4) In the silicon carbide substrate according to any one of (1) to (3), when viewed in a plan view from the center, the [11-20] direction, the [1-100] direction, and the [-1100] direction are defined as 0°, 90°, and -90°, respectively, the main surface may have a first sector region located between a half line extending in a -10° direction from the center and a half line extending in a 10° direction from the center, and a second sector region located between a half line extending in a 20° direction from the center and a half line extending in a 40° direction from the center. The areal density of stacking faults in the first sector region may be smaller than the areal density of stacking faults in the second sector region.

[0013] (5) A method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure includes the following steps: A silicon carbide substrate according to any one of (1) to (4) above is prepared; A silicon carbide epitaxial layer is formed on the silicon carbide substrate; This makes it possible to suppress the formation of defects in the silicon carbide epitaxial layer due to threading screw dislocations in the silicon carbide substrate; and as a result, it is possible to improve the yield of semiconductor devices manufactured using the silicon carbide epitaxial substrate.

[0014] (6) A method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes the following steps: A silicon carbide substrate according to any one of (1) to (4) above is prepared; A silicon carbide epitaxial layer is formed on the silicon carbide substrate; An electrode is formed on the silicon carbide epitaxial layer; This makes it possible to suppress the occurrence of defects in the semiconductor device due to threading screw dislocations in the silicon carbide substrate. As a result, it is possible to improve the yield of semiconductor devices.

[0015] [Details of the Embodiments of the Present Disclosure] Next, the details of the embodiments of the present disclosure will be described with reference to the drawings. Note that the same or corresponding parts in the following drawings are designated by the same reference numerals, and the description thereof will not be repeated.

[0016] First, the configuration of silicon carbide single crystal 200 according to this embodiment will be described. Fig. 1 is a cross-sectional schematic diagram showing the configuration of silicon carbide single crystal 200 according to this embodiment. As shown in Fig. 1, silicon carbide single crystal 200 according to this embodiment mainly has third main surface 3, fourth main surface 4, and second outer peripheral surface 29.

[0017] Third main surface 3 is, for example, planar. Fourth main surface 4 is opposite third main surface 3. Second outer peripheral surface 29 is continuous with each of third main surface 3 and fourth main surface 4. Second outer peripheral surface 29 has an annular shape. The diameter of second outer peripheral surface 29 increases with increasing distance from third main surface 3. Second outer peripheral surface 29 surrounds central axis C of silicon carbide single crystal 200.

[0018] The silicon carbide single crystal 200 is made of, for example, hexagonal silicon carbide. The polytype of the hexagonal silicon carbide constituting the silicon carbide single crystal 200 is, for example, 4H. The silicon carbide single crystal 200 contains nitrogen (N) as an n-type impurity.

[0019] 1, the third main surface 3 is inclined with respect to the {0001} plane. Specifically, the third main surface 3 may be inclined with respect to the (0001) plane, or the third main surface 3 may be inclined with respect to the (000-1) plane. The inclination angle (off angle θ) of the third main surface 3 with respect to the {0001} plane is, for example, greater than 0° and equal to or less than 8°.

[0020] The tilt direction (off direction) of the third main surface 3 is the [11-20] direction. In other words, the third main surface 3 is tilted in the [11-20] direction with respect to the {0001} plane. In this specification, the [11-20] direction is also referred to as a first direction 101 or an off-downstream direction 101. The [-1-120] direction is also referred to as a second direction 102 or an off-upstream direction 102. The second direction 102 is the direction opposite to the first direction 101.

[0021] The growth direction of silicon carbide single crystal 200 is third direction 103. The thickness direction of silicon carbide single crystal 200 is third direction 103. Third direction 103 is a direction inclined by an off angle θ with respect to the <0001> direction. A central axis C of silicon carbide single crystal 200 extends along third direction 103. The cross section shown in FIG. 1 is a cross section parallel to each of first direction 101 and third direction 103.

[0022] The third main surface 3 extends along a plane perpendicular to the third direction 103. When viewed perpendicularly to the third main surface 3, the shape of the third main surface 3 is, for example, circular. As the distance from the central axis C increases along the off-downstream direction 101, the distance in the third direction 103 between the third main surface 3 and the {0001} plane increases.

[0023] The boundary between the third main surface 3 and the second outer peripheral surface 29 is defined as a first boundary 71. The diameter of the third main surface 3 is defined as a second diameter W2. The second diameter W2 is, for example, 150 mm (6 inches). The second diameter W2 may be, for example, 100 mm (4 inches) or greater and 400 mm (16 inches) or less. When viewed perpendicular to the third main surface 3, the second diameter W2 is the longest linear distance between two different points on the first boundary 71.

[0024] As used herein, 4 inches refers to 100 mm or 101.6 mm (4 inches x 25.4 mm / inch). 6 inches refers to 150 mm or 152.4 mm (6 inches x 25.4 mm / inch). 16 inches refers to 400 mm or 406.4 mm (16 inches x 25.4 mm / inch).

[0025] The fourth main surface 4 is convex in the third direction 103. For example, the distance between the third main surface 3 and the fourth main surface 4 in the third direction 103 increases toward the central axis C. The boundary between the fourth main surface 4 and the second outer peripheral surface 29 is defined as the second boundary 72. The diameter of the fourth main surface 4 is defined as the third diameter W3. When viewed in the direction opposite to the third direction 103, the third diameter W3 is the longest linear distance between two different points on the second boundary 72. The distance between the second boundary 72 and the third main surface 3 in the third direction 103 is defined as the outer peripheral thickness H3. The distance in the third direction 103 between the intersection of the central axis C and the fourth main surface 4 and the third main surface 3 is defined as the central thickness H4.

[0026] The central thickness H4 is, for example, 25 mm or more and 100 mm or less. The central thickness H4 is thicker than the outer peripheral thickness H3. The value obtained by subtracting the outer peripheral thickness H3 from the central thickness H4 and dividing the result by the third diameter W3 is determined as the convexity. The convexity is 0.5% or more and 2.0% or less.

[0027] 1 , silicon carbide single crystal 200 has a plurality of threading screw dislocations 6 and stacking faults 10. Each of the plurality of threading screw dislocations 6 extends, for example, along the <0001> direction. From another perspective, each of the plurality of threading screw dislocations 6 is inclined by an off angle θ with respect to third direction 103. The plurality of threading screw dislocations 6 includes a first threading screw dislocation 61 and a second threading screw dislocation 62.

[0028] The first threading screw dislocation 61 is exposed, for example, at each of the third major surface 3 and the fourth major surface 4. The first threading screw dislocation 61 extends, for example, continuously from the third major surface 3 to the fourth major surface 4. The first threading screw dislocation 61 may also extend continuously from the third major surface 3 to the second outer peripheral surface 29.

[0029] The second threading screw dislocation 62 is exposed at the third main surface 3. The stacking fault 10 is connected to the end of the second threading screw dislocation 62. The stacking fault 10 extends, for example, along a plane parallel to the {0001} plane. The stacking fault 10 is a defect formed, for example, by the transformation of the second threading screw dislocation 62. The stacking fault 10 is exposed, for example, at the second outer peripheral surface 29.

[0030] As shown in FIG. 1 , silicon carbide single crystal 200 has first portion 31 and second portion 32. First portion 31 constitutes third main surface 3. The electrical resistivity of first portion 31 is, for example, 5 mΩcm or more and 15 mΩcm or less. Second portion 32 is located in third direction 103 relative to first portion 31. Second portion 32 constitutes fourth main surface 4. The electrical resistivity of second portion 32 is, for example, 15 mΩcm or more and 25 mΩcm or less. The n-type impurity concentration in second portion 32 is lower than the n-type impurity concentration in first portion 31. Interface 39 between first portion 31 and second portion 32 is convex in third direction 103. The maximum thickness (second thickness H2) of first portion 31 in third direction 103 is, for example, 10 mm.

[0031] <Silicon Carbide Substrate> Next, the configuration of silicon carbide substrate 100 according to this embodiment will be described.

[0032] Fig. 2 is a cross-sectional schematic diagram showing a configuration of silicon carbide substrate 100 according to the present embodiment. As shown in Fig. 2, silicon carbide substrate 100 mainly has a first main surface 1, a second main surface 2, and a first outer peripheral surface 9. First main surface 1 is, for example, planar. Second main surface 2 is opposite first main surface 1. Second main surface 2 is, for example, planar. First outer peripheral surface 9 is continuous with each of first main surface 1 and second main surface 2. First outer peripheral surface 9 has an annular shape.

[0033] Silicon carbide substrate 100 is made of, for example, hexagonal silicon carbide. The polytype of the hexagonal silicon carbide constituting silicon carbide substrate 100 is, for example, 4H. Silicon carbide substrate 100 contains nitrogen (N) as an n-type impurity. Silicon carbide substrate 100 has an electrical resistivity of, for example, 15 mΩcm or more and 25 mΩcm or less. Silicon carbide substrate 100 has substantially the same configuration as a part of silicon carbide single crystal 200 described above (see FIG. 1 ). Specifically, silicon carbide substrate 100 has substantially the same configuration as, for example, a part of second portion 32 of silicon carbide single crystal 200 described above.

[0034] As shown in FIG. 2 , the first main surface 1 is inclined with respect to the {0001} plane. Specifically, the first main surface 1 may be inclined with respect to the (0001) plane or the (000-1) plane. The inclination angle (off angle θ) of the first main surface 1 with respect to the {0001} plane is, for example, greater than 0° and equal to or less than 8°. The inclination direction (off direction) of the first main surface 1 is the [11-20] direction. In other words, the first main surface 1 is inclined in the [11-20] direction with respect to the {0001} plane. As the distance from the center O of the first main surface 1 increases along the off-downstream direction 101, the distance in the third direction 103 between the first main surface 1 and the {0001} plane increases.

[0035] The direction from first main surface 1 toward second main surface 2 is third direction 103. First main surface 1 extends along a plane perpendicular to third direction 103. Silicon carbide substrate 100 has a thickness in third direction 103 (first thickness H1) of 2 mm or less, for example.

[0036] As shown in Fig. 2, silicon carbide substrate 100 has a plurality of threading screw dislocations 6 and stacking faults 10. Each of the plurality of threading screw dislocations 6 extends, for example, along the <0001> direction. The plurality of threading screw dislocations 6 is composed of, for example, a first threading screw dislocation 61. First threading screw dislocation 61 corresponds to first threading screw dislocation 61 in silicon carbide single crystal 200 described above (see Fig. 1).

[0037] The first threading screw dislocation 61 is exposed, for example, at each of the first main surface 1 and the second main surface 2. The first threading screw dislocation 61 extends, for example, continuously from the first main surface 1 to the second main surface 2. The first threading screw dislocation 61 may also extend continuously from the first main surface 1 to the first outer peripheral surface 9.

[0038] Stacking faults 10 are exposed, for example, on each of first main surface 1 and first outer peripheral surface 9. Stacking faults 10 may reach each of first main surface 1 and second main surface 2. Stacking faults 10 extend, for example, along a plane parallel to the {0001} plane. Stacking faults 10 correspond to stacking faults 10 in silicon carbide single crystal 200 described above (see FIG. 1 ). The cross section shown in FIG. 2 is perpendicular to first main surface 1, parallel to first direction 101, and passing through center O.

[0039] 3 is a plan view schematically illustrating the configuration of silicon carbide substrate 100 according to this embodiment. As shown in FIG. 3 , first outer peripheral surface 9 has orientation flat portion 7 and arc-shaped portion 8.

[0040] When viewed along a straight line perpendicular to the first main surface 1 (hereinafter also referred to as a plan view), the orientation flat portion 7 is linear. The direction in which the orientation flat portion 7 extends is, for example, the <11-20> direction. The arc-shaped portion 8 is continuous with the orientation flat portion 7. In a plan view, the arc-shaped portion 8 is arc-shaped. In a plan view, the center O of the first main surface 1 is the center of a circle containing an arc along the arc-shaped portion 8. In a plan view, a straight line perpendicular to the off-downstream direction 101 and passing through the center O is defined as a center line 99. The direction in which the center line 99 extends is the [1-100] direction. In this specification, the [1-100] direction is also referred to as a fourth direction 104.

[0041] As shown in FIG. 3 , the diameter of the first main surface 1 is defined as a first diameter W1. The first diameter W1 is, for example, 150 mm (6 inches). The first diameter W1 may be, for example, 100 mm (4 inches) or greater and 400 mm (16 inches) or less. In a plan view, the first diameter W1 is the longest linear distance between two different points on the outer edge of the first main surface 1.

[0042] 3 , the first main surface 1 is composed of a first half region 11 and a second half region 12. In a plan view, the first half region 11 is located in an off-downstream direction 101 relative to the center O. From another perspective, in a plan view, the first half region 11 is located in an off-downstream direction 101 relative to the center line 99. In a plan view, the second half region 12 is located in an off-upstream direction 102 relative to the center O. From another perspective, in a plan view, the second half region 12 is located in an off-upstream direction 102 relative to the center line 99.

[0043] In a plan view, the [11-20] direction (first direction 101), the [1-100] direction (fourth direction 104), and the [-1100] direction as viewed from the center O are defined as 0°, 90°, and -90°, respectively. A half-ray extending in the -10° direction from the center O is defined as a first half-ray 81. A half-ray extending in the 10° direction from the center O is defined as a second half-ray 82. A half-ray extending in the 20° direction from the center O is defined as a third half-ray 83. A half-ray extending in the 40° direction from the center O is defined as a fourth half-ray 84.

[0044] The portion of the first main surface 1 located between the first half ray 81 and the second half ray 82 is defined as a first sector region 13. The portion of the first main surface 1 located between the third half ray 83 and the fourth half ray 84 is defined as a second sector region 14. From another perspective, the first main surface 1 has the first sector region 13 and the second sector region 14. Each of the first sector region 13 and the second sector region 14 is located in the first half-surface region 11. Each of the first sector region 13 and the second sector region 14 includes a center O.

[0045] <Area Density of Threading Screw Dislocations> The areal density of the threading screw dislocations 6 in the first half surface region 11 is set to a first areal density. The areal density of the threading screw dislocations 6 in the second half surface region 12 is set to a second areal density. The first areal density is smaller than the second areal density.

[0046] The value obtained by dividing the first areal density by the second areal density is 88% or less. The value obtained by dividing the first areal density by the second areal density may be, for example, 85% or less, or 80% or less. The value obtained by dividing the first areal density by the second areal density is, for example, 68% or more. The value obtained by dividing the first areal density by the second areal density may be, for example, 70% or more, or 75% or more.

[0047] Next, a method for measuring the areal density of threading screw dislocations 6 will be described. The areal density of threading screw dislocations 6 is determined using, for example, molten potassium hydroxide (KOH). Specifically, for example, sodium peroxide (Na ２ O ２ ) is added to prepare molten KOH. First main surface 1 is etched with the molten KOH. As a result, silicon carbide regions near threading screw dislocations 6 exposed at first main surface 1 are etched, and etch pits are formed at first main surface 1. The temperature of the molten KOH is set to, for example, 500°C. The etching time is set to, for example, 1 minute.

[0048] After etching, the etch pits formed on the first main surface 1 are observed using a Nomarski differential interference microscope. The value obtained by dividing the number of etch pits formed in the first half-surface region 11 by the measured area of ​​the first half-surface region 11 corresponds to the first areal density. Similarly, the value obtained by dividing the number of etch pits formed in the second half-surface region 12 by the measured area of ​​the second half-surface region 12 corresponds to the second areal density. The observation field is, for example, 0.82 mm × 0.70 mm. The measurement interval is, for example, 5 mm.

[0049] <Area Density of Stacking Faults> Fig. 4 is a schematic plan view showing a measurement area for the area density of stacking faults 10. As shown in Fig. 4, in measuring the area density of stacking faults 10, the first main surface 1 is virtually divided into a plurality of square regions 70. In plan view, each of the plurality of square regions 70 has a substantially square shape. The length L of one side of each of the plurality of square regions 70 is 2.6 mm.

[0050] Specifically, a square is first assumed to circumscribe the first main surface 1 in a plan view. The length of one side of the square is the first diameter W1 (see FIG. 3 ). The square is divided into square regions of 2.6 mm × 2.6 mm.

[0051] In a plan view, the square regions that intersect with the outer edge of the first main surface 1 are missing portions and are not complete square regions. Therefore, the square regions that intersect with the outer edge of the first main surface 1 are not considered to be square regions 70 that constitute the first main surface 1. Note that, in a plan view, one side of each of the multiple square regions 70 is parallel to the extension direction of the orientation flat portion 7. In other words, in a plan view, one side of each of the multiple square regions 70 is parallel to the first direction 101.

[0052] To measure the areal density of stacking faults 10, for example, a photoluminescence imaging device (model number: PLI-200) manufactured by Photon Design Inc. is used. When excitation light is irradiated onto the measurement area of ​​the first principal surface 1, photoluminescence light is observed from the measurement area. For example, a mercury-xenon lamp is used as the excitation light source. The excitation light from the light source passes through a 313 nm bandpass filter and then irradiates the measurement area. The photoluminescence light passes through a light-receiving filter that transmits light with wavelengths greater than 750 nm. As a result, photoluminescence light with wavelengths greater than 750 nm reaches a light-receiving element such as a camera. In this manner, a photoluminescence image of the measurement area is captured.

[0053] The luminescence intensity of the stacking faults 10 is higher than that of the silicon carbide regions with a polytype of 4H. Therefore, the stacking faults 10 appear as bright linear regions in the photoluminescence image. For example, a photoluminescence image of the first main surface 1 is captured while moving the silicon carbide substrate 100 in a direction parallel to the first main surface 1. Specifically, a photoluminescence image of each of the plurality of square regions 70 is captured. The field of view of one photoluminescence image is set to 2.6 mm × 2.6 mm. This allows a photoluminescence image of the entire region of the first main surface 1 to be acquired. The stacking faults 10 are identified in the acquired photoluminescence image. This allows the number of stacking faults 10 in each of the plurality of square regions 70 to be identified.

[0054] The total number of stacking faults 10 in the plurality of square regions 70 included in the first sector region 13 is calculated. The total number is divided by the total area of ​​the plurality of square regions 70 included in the first sector region 13 to calculate the areal density of stacking faults 10 in the first sector region 13. Note that the square regions 70 through which the first half ray 81 and the second half ray 82 (see FIG. 3 ) pass are not considered to be the plurality of square regions 70 included in the first sector region 13. Similarly, the areal density of stacking faults 10 in the second sector region 14 is calculated. The areal density of stacking faults 10 in the first sector region 13 is smaller than the areal density of stacking faults 10 in the second sector region 14.

[0055] The presence or absence of stacking faults 10 is identified in the photoluminescence image of each of the square regions 70. The number of square regions 70 containing stacking faults 10 among the square regions 70 included in the first half region 11 is identified. A value (first value) is calculated by dividing the number of square regions 70 by the total number of square regions 70 included in the first half region 11. Note that the square regions 70 through which the center line 99 passes are not considered to be square regions 70 included in the first half region 11.

[0056] Similarly, the number of square regions 70 containing stacking faults 10 is calculated from among the square regions 70 contained in the second half region 12. A value (second value) is calculated by dividing the calculated number by the total number of square regions 70 contained in the second half region 12. Note that the square regions 70 through which the center line 99 passes are not considered to be square regions 70 contained in the second half region 12.

[0057] The first value is, for example, 4% or less. The first value may be, for example, 0% or more, greater than 0%, or 1% or more. The first value may be 3.5% or less, or 3% or less.

[0058] The second value is, for example, smaller than the first value. The second value is, for example, 0%. From another perspective, as shown in FIG. 2 , the stacking faults 10 may not be exposed in the second half region 12.

[0059] <Method for manufacturing silicon carbide substrate> Next, a method for manufacturing silicon carbide substrate 100 according to this embodiment will be described. Fig. 5 is a flow diagram schematically showing the method for manufacturing silicon carbide substrate 100 according to this embodiment. As shown in Fig. 5, the method for manufacturing silicon carbide substrate 100 according to this embodiment includes a step (S10) of preparing a growth apparatus, a first growth step (S20), a temperature increase step (S30), a second growth step (S40), and a step (S50) of cutting silicon carbide single crystal 200.

[0060] First, a step (S10) of preparing a growth apparatus is carried out. Fig. 6 is a cross-sectional schematic diagram showing the step (S10) of preparing a growth apparatus. As shown in Fig. 6, a growth apparatus 500 for silicon carbide single crystal 200 is prepared. Growth apparatus 500 for silicon carbide single crystal 200 mainly includes crucible 30, first resistive heater 21, second resistive heater 22, third resistive heater 23, and a heat insulating material (not shown).

[0061] The crucible 30 is made of graphite. The crucible 30 has a raw material storage section 36 and a lid 35. The lid 35 is disposed on the raw material storage section 36. The first resistive heater 21 is disposed above the lid 35. The second resistive heater 22 is disposed so as to surround the outer periphery of the raw material storage section 36. The third resistive heater 23 is disposed below the bottom surface of the raw material storage section 36. The outputs of the first resistive heater 21, the second resistive heater 22, and the third resistive heater 23 can be individually controlled using a control unit (not shown). A heat insulating material (not shown) is disposed, for example, so as to cover the entire crucible 30.

[0062] As shown in FIG. 6 , silicon carbide source material 59 is placed in source material storage unit 36. Silicon carbide source material 59 is, for example, polycrystalline silicon carbide powder. Seed substrate 50 is fixed to lid unit 35 using, for example, an adhesive (not shown). Seed substrate 50 is made of, for example, a hexagonal silicon carbide single crystal of polytype 4H. The diameter of seed substrate 50 is substantially the same as second diameter W2 (see FIG. 1 ) of silicon carbide single crystal 200.

[0063] The central axis C passes through, for example, the center of the seed substrate 50. The seed substrate 50 has a growth surface 51 and an attachment surface 52. The attachment surface 52 is opposite to the growth surface 51. The attachment surface 52 faces the lid portion 35. The growth surface 51 is disposed so as to face the surface of the silicon carbide raw material 59. The growth surface 51 is inclined by an off-angle θ with respect to the {0001} plane. The seed substrate 50 has a plurality of threading screw dislocations 6.

[0064] Next, the first growth step (S20) is performed. Crucible 30 is heated until the temperature of growth surface 51 reaches, for example, 2050°C or higher and 2150°C or lower. The temperature of the center of growth surface 51 is made lower than the temperature of the outer periphery of growth surface 51. Specifically, the outputs of first resistive heater 21, second resistive heater 22, and third resistive heater 23 are controlled, so that the temperature of growth surface 51 decreases with increasing distance from central axis C. While the temperature of growth surface 51 is increasing, the pressure inside crucible 30 is maintained at, for example, approximately 80 kPa.

[0065] The atmosphere gas in the crucible 30 contains an inert gas such as argon gas, helium gas, or nitrogen gas. Specifically, the atmosphere gas in the crucible 30 contains, for example, argon (Ar) gas and nitrogen (N ２ ) gas.

[0066] Next, the pressure of the atmospheric gas in crucible 30 is reduced to, for example, 1.0 kPa. As a result, silicon carbide source material 59 begins to sublimate, and the sublimated silicon carbide gas is recrystallized on growth surface 51 of seed substrate 50. Silicon carbide single crystal 200 begins to grow on growth surface 51. While silicon carbide single crystal 200 is growing, the pressure in crucible 30 is maintained at, for example, approximately 0.1 kPa or more and 3 kPa or less.

[0067] Fig. 7 is a cross-sectional view showing the first growth step (S20). For ease of explanation, the first resistive heater 21, the second resistive heater 22, and the third resistive heater 23 are not shown in Fig. 7. Fig. 8 is a schematic diagram showing the relationship between the temperature of the growth surface and the flow rate of nitrogen gas and time. In Fig. 8, the upper vertical axis represents the temperature of the growth surface, and the lower vertical axis represents the flow rate of nitrogen gas. The horizontal axis represents time.

[0068] 7 , first portion 31 of silicon carbide single crystal 200 is formed on growth surface 51 of seed substrate 50. In this specification, the surface along which growth proceeds in silicon carbide single crystal 200 is referred to as growth surface 38. Growth surface 38 is the surface facing the surface of silicon carbide raw material 59.

[0069] The temperature of the central portion of growth surface 38 is made lower than the temperature of the peripheral portion of growth surface 38. Specifically, the output of each of first resistive heater 21, second resistive heater 22, and third resistive heater 23 (see FIG. 6 ) is controlled to decrease the temperature of growth surface 38 as it approaches central axis C. This causes growth surface 38 to become convex in third direction 103. From another perspective, the degree of convexity of silicon carbide single crystal 200 can be increased.

[0070] 8 , the temperature of growth surface 38 is maintained at first temperature B1 from first time point T1 to second time point T2. First time point T1 is the time when growth of silicon carbide single crystal 200 starts. Second time point T2 is the time when first growth step (S20) ends. First temperature B1 is, for example, not less than 2050° C. and not more than 2150° C.

[0071] Between the first time point T1 and the second time point T2, the flow rate of the nitrogen gas is set to a first flow rate C1, e.g., 80 sccm, and between the first time point T1 and the second time point T2, the flow rate of the argon gas is set to 300 sccm.

[0072] As a result, first portion 31 of silicon carbide single crystal 200 is formed from first point in time T1 to second point in time T2. The maximum thickness of first portion 31 at second point in time T2 is, for example, 10 mm. The maximum thickness of first portion 31 at second point in time T2 is the longest linear distance in third direction 103 from growth surface 51 to growth surface 38. The convexity of silicon carbide single crystal 200 at second point in time T2 is greater than 2%. The convexity of silicon carbide single crystal 200 at second point in time T2 is the value obtained by subtracting the peripheral thickness from the maximum thickness and dividing the value by the diameter of growth surface 38. The peripheral thickness at second point in time T2 is the longest linear distance in third direction 103 from growth surface 51 to the boundary between growth surface 38 and second peripheral surface 29. The diameter of growth surface 38 is the longest linear distance between two different points on the boundary between growth surface 38 and second peripheral surface 29 when viewed in the direction opposite to third direction 103.

[0073] 7 , in the process of growing the first portion 31, at least some of the threading screw dislocations 6 in the seed substrate 50 are inherited by the first portion 31. In the process of growing the first portion 31, some of the threading screw dislocations 6 inherited from the seed substrate 50 are transformed into stacking faults 10.

[0074] Next, the process by which threading screw dislocations 6 are transformed into stacking faults 10 will be described. FIG. 9 is a schematic diagram showing the relationship between a growth surface 38 and the {0001} plane. As shown in FIG. 9 , when the growth surface 38 is convex in the growth direction 103, the angle between the portion of the growth surface 38 located in the off-upstream direction 102 with respect to the central axis C and the {0001} plane is relatively small. Specifically, the angle between the tangent (first tangent 91) of the growth surface 38 located in the off-upstream direction 102 with respect to the central axis C and the {0001} plane is relatively small. On the other hand, the angle between the portion of the growth surface 38 located in the off-downstream direction 101 with respect to the central axis C and the {0001} plane is relatively large. Specifically, the angle between the tangent (second tangent 92) of the portion of the growth surface 38 located in the off-downstream direction 101 with respect to the central axis C and the {0001} plane is relatively large.

[0075] Fig. 10 is a schematic diagram showing the process of crystal growth in region X in Fig. 9. Fig. 11 is a schematic diagram showing the process of crystal growth in region XI in Fig. 9. As shown in Fig. 10 and Fig. 11, during the crystal growth process, steps 95 grow along a direction parallel to the {0001} plane, thereby growing a silicon carbide crystal.

[0076] 10 , in the portion of the growth surface 38 that forms a small angle with the {0001} plane, the number of steps 95 per unit area (step density) is small. Therefore, the height T of the steps 95 in the direction perpendicular to the {0001} plane tends to be small. When the height T of the steps 95 is small, the threading screw dislocations 6 tend to propagate in the direction perpendicular to the {0001} plane.

[0077] On the other hand, as shown in FIG. 11 , the step density is high in the portion of the growth surface 38 that forms a large angle with the {0001} plane. Therefore, step bunching is likely to occur. This tends to increase the height T of the steps 95 in the direction perpendicular to the {0001} plane. When the step height T is high, the threading screw dislocations 6 are likely to be converted into stacking faults 10. Specifically, the threading screw dislocations 6 are converted into stacking faults 10 by bending along the growth direction of the steps 95.

[0078] According to the method for manufacturing silicon carbide substrate 100 of this embodiment, the convexity of silicon carbide single crystal 200 is increased during the growth of silicon carbide single crystal 200. Therefore, growth surface 38 is convex in growth direction 103. This allows the angle formed by the portion of growth surface 38 located in off-downstream direction 101 with respect to central axis C and the {0001} plane to be sufficiently large. This can promote the occurrence of step bunching. Therefore, the conversion of threading screw dislocations 6 to stacking faults 10 can be promoted on growth surface 38 located in off-downstream direction 101.

[0079] According to the method for manufacturing silicon carbide substrate 100 according to this embodiment, the temperature of growth surface 38 in first growth step (S20) is 2050°C or higher and 2150°C or lower. It is believed that growing silicon carbide single crystal 200 at a relatively low temperature in this manner inhibits crystal growth in a direction parallel to the {0001} plane (two-dimensional growth) and promotes crystal growth in a direction perpendicular to the {0001} plane (three-dimensional growth, island-like growth). This allows height T of steps 95 to be increased. As a result, the conversion of threading screw dislocations 6 to stacking faults 10 can be promoted.

[0080] According to the method for manufacturing silicon carbide substrate 100 in accordance with the present embodiment, first portion 31 has an electrical resistivity of, for example, 5 mΩcm or more and 15 mΩcm or less. From another perspective, the nitrogen concentration in first portion 31 is relatively high. Accordingly, the nitrogen concentration in growth surface 38 is relatively high. Nitrogen is thought to have the effect of changing the surface energy at growth surface 38 (surfactant effect). This is thought to inhibit crystal growth in a direction parallel to the {0001} plane and promote crystal growth in a direction perpendicular to the {0001} plane in first growth step (S20). Therefore, height T of step 95 can be increased. As a result, the conversion of threading screw dislocations 6 to stacking faults 10 can be promoted.

[0081] As described above, in the first growth step (S20), the conversion of threading screw dislocations 6 to stacking faults 10 is promoted on the growth surface 38 located in the off-downstream direction 101 with respect to the central axis C. This makes it possible to reduce the density of threading screw dislocations 6 on the growth surface 38 located in the off-downstream direction 101.

[0082] When the [11-20] direction (first direction 101), the [1-100] direction (fourth direction 104), and the [-1100] direction are defined as 0°, 90°, and -90°, respectively, as viewed from the central axis C, the {10-10} plane (m-plane) is located at a 30° angle. When steps 95 grow along a direction perpendicular to the m-plane (i.e., the <10-10> direction), step bunching is likely to occur. For this reason, stacking faults 10 converted from threading screw dislocations 6 are likely to propagate along the <10-10> direction. For this reason, in the manufactured silicon carbide substrate 100, the areal density of threading screw dislocations 6 in the second sector region 14 (see FIG. 3 ) is likely to be higher than the areal density of threading screw dislocations 6 in the first sector region 13 (see FIG. 3 ).

[0083] Next, a temperature-raising step (S30) is carried out. Specifically, the temperature of growth surface 38 is raised from first temperature B1 to second temperature B2 between second time point T2 and third time point T3. Second temperature B2 is, for example, 2150°C or higher and 2250°C or lower. By raising the temperature inside crucible 30, the growth rate of silicon carbide single crystal 200 can be improved.

[0084] From the second time point T2 to the third time point T3, the flow rate of the nitrogen gas decreases from the first flow rate C1 to the second flow rate C2, e.g., 20 sccm. From the second time point T2 to the third time point T3, the flow rate of the argon gas is, e.g., 300 sccm.

[0085] The output of each of first resistive heater 21, second resistive heater 22, and third resistive heater 23 is controlled to reduce the difference in temperature between the central portion of growth surface 38 and the peripheral portion of growth surface 38. From another perspective, the difference in temperature between the central portion of growth surface 38 and the peripheral portion of growth surface 38 at third point in time T3 is smaller than the difference in temperature between the central portion of growth surface 38 and the peripheral portion of growth surface 38 at second point in time T2. As a result, in the second growth step (S40) described below, the convexity of silicon carbide single crystal 200 decreases as silicon carbide single crystal 200 grows.

[0086] Next, a second growth step (S40) is carried out. As shown in Fig. 8, from third point in time T3 to fourth point in time T4, the temperature of growth surface 38 is maintained at second temperature B2, and the flow rate of nitrogen gas is maintained at second flow rate C2. The flow rate of argon gas is maintained at 300 sccm. Fourth point in time T4 is the time when growth of silicon carbide single crystal 200 ends. The time from first point in time T1 to second point in time T2 is, for example, 10% or more and 30% or less of the time from first point in time T1 to fourth point in time T4.

[0087] FIG. 12 is a cross-sectional schematic diagram showing the second growth step (S40). As shown in FIG. 12 , silicon carbide single crystal 200 continues to grow. This forms second portion 32 of silicon carbide single crystal 200. During the growth of second portion 32, threading screw dislocations 6 may be converted into stacking faults 10. During the growth of second portion 32, stacking faults 10 reach, for example, second outer peripheral surface 29. Stacking faults 10 that have reached second outer peripheral surface 29 no longer grow. Therefore, as growth of second portion 32 progresses, the density of stacking faults 10 in the newly grown portion of the crystal decreases. From another perspective, the areal density of stacking faults 10 in silicon carbide single crystal 200 decreases with increasing distance from third main surface 3 along growth direction 103. As described above, silicon carbide single crystal 200 is produced using a sublimation method.

[0088] Next, a step (S50) of cutting silicon carbide single crystal is carried out. For example, using a saw wire (not shown), silicon carbide single crystal 200 is sliced ​​along a plane perpendicular to central axis C of silicon carbide single crystal 200. This results in a plurality of silicon carbide substrates 100 (see FIGS. 2 and 3 ).

[0089] Although the above describes a method of controlling the temperature distribution at growth surface 38 by controlling the output of the resistance heater, the method of controlling the temperature distribution at growth surface 38 is not limited to the above method. Specifically, for example, in the step (S10) of preparing the growth apparatus, the temperature distribution at growth surface 38 may be controlled by appropriately changing the arrangement of the heat insulating material.

[0090] (Method of Manufacturing Silicon Carbide Semiconductor Device) Next, a method of manufacturing silicon carbide semiconductor device 400 according to this embodiment will be described. Fig. 13 is a flow diagram that schematically shows the method of manufacturing silicon carbide semiconductor device 400 according to this embodiment. As shown in Fig. 13, the method of manufacturing silicon carbide semiconductor device 400 according to this embodiment mainly includes a step (S1) of manufacturing a silicon carbide epitaxial substrate and a step (S2) of forming an electrode on the silicon carbide epitaxial layer.

[0091] First, a step (S1) of manufacturing a silicon carbide epitaxial substrate is performed. The step (S1) of manufacturing a silicon carbide epitaxial substrate includes a step (S60) of preparing a silicon carbide substrate and a step (S70) of forming a silicon carbide epitaxial layer on the silicon carbide substrate. First, the step (S60) of preparing a silicon carbide substrate is performed. In the step (S60) of preparing a silicon carbide substrate, silicon carbide substrate 100 (see FIGS. 2 and 3 ) is prepared using the method for manufacturing silicon carbide substrate 100 described above. Silicon carbide substrate 100 may be ground so as to remove at least a portion of second half region 12 of first main surface 1.

[0092] Next, a step (S70) of forming a silicon carbide epitaxial layer on the silicon carbide substrate is performed. Specifically, silicon carbide epitaxial layer 40 is formed by epitaxial growth on first main surface 1 of silicon carbide substrate 100. In the epitaxial growth, for example, silane (SiH4) and propane (C3H8) are used as source gases, and hydrogen (H2) is used as a carrier gas. The temperature of the epitaxial growth is, for example, about 1400°C or higher and 1700°C or lower. In the epitaxial growth, an n-type impurity such as nitrogen is introduced into silicon carbide epitaxial layer 40. In this way, silicon carbide epitaxial substrate 300 according to the present embodiment is manufactured.

[0093] Figure 14 is a cross-sectional schematic diagram showing the configuration of a silicon carbide epitaxial substrate 300 according to this embodiment. As shown in Figure 14, the silicon carbide epitaxial substrate 300 has a silicon carbide substrate 100 and a silicon carbide epitaxial layer 40. The silicon carbide epitaxial layer 40 is provided on the silicon carbide substrate 100. The silicon carbide epitaxial layer 40 has a fifth main surface 5. The fifth main surface 5 constitutes the front surface of the silicon carbide epitaxial substrate 300. The second main surface 2 constitutes the back surface of the silicon carbide epitaxial substrate 300.

[0094] Silicon carbide epitaxial layer 40 may have a buffer layer 41 and a drift layer 42. Buffer layer 41 is in contact with silicon carbide substrate 100 at first main surface 1. Drift layer 42 is provided on buffer layer 41. Buffer layer 41 and drift layer 42 each contain an n-type impurity such as nitrogen. The concentration of the n-type impurity contained in buffer layer 41 may be higher than the concentration of the n-type impurity contained in drift layer 42.

[0095] Next, a step (S2) of forming an electrode on the silicon carbide epitaxial layer is performed. Specifically, the following processing is performed on silicon carbide epitaxial substrate 300. First, ions are implanted into silicon carbide epitaxial substrate 300.

[0096] 15 is a schematic cross-sectional view showing a step of forming a body region. In the step of forming the body region, p-type impurities such as aluminum are ion-implanted into fifth main surface 5 of silicon carbide epitaxial layer 40. This forms body region 113 having p-type conductivity. Portions where body region 113 is not formed become drift layer 42 and buffer layer 41. The thickness of body region 113 is, for example, 0.9 μm. Silicon carbide epitaxial layer 40 includes buffer layer 41, drift layer 42, and body region 113.

[0097] Next, a step of forming a source region is performed. FIG. 16 is a schematic cross-sectional view showing the step of forming the source region. Specifically, n-type impurities such as phosphorus are ion-implanted into the body region 113. This forms a source region 114 having n-type conductivity. The thickness of the source region 114 is, for example, 0.4 μm. The concentration of the n-type impurity contained in the source region 114 is higher than the concentration of the p-type impurity contained in the body region 113.

[0098] Next, a p-type impurity such as aluminum is ion-implanted into the source region 114 to form a contact region 118. The contact region 118 is formed to penetrate the source region 114 and the body region 113 and to be in contact with the drift layer 42. The concentration of the p-type impurity contained in the contact region 118 is higher than the concentration of the n-type impurity contained in the source region 114.

[0099] Next, activation annealing is performed to activate the implanted impurities. The temperature of the activation annealing is, for example, 1500° C. or higher and 1900° C. or lower. The activation annealing time is, for example, about 30 minutes. The atmosphere of the activation annealing is, for example, an argon atmosphere.

[0100] Next, a step of forming trenches in fifth main surface 5 of silicon carbide epitaxial layer 40 is performed. FIG. 17 is a cross-sectional schematic view showing the step of forming trenches in fifth main surface 5 of silicon carbide epitaxial layer 40. A mask 117 having openings is formed on fifth main surface 5 configured from source region 114 and contact region 118. Using mask 117, source region 114, body region 113, and part of drift layer 42 are removed by etching. As an etching method, for example, inductively coupled plasma reactive ion etching can be used. Specifically, for example, SF is used as a reactive gas. ６ or science fiction ６ and O ２ The etching is performed by inductively coupled plasma reactive ion etching using a mixed gas of SiO 2 and SiO 2 . The etching forms a recess in the fifth main surface 5 .

[0101] Next, thermal etching is performed on the recesses. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one type of halogen atom, with the mask 117 formed on the fifth main surface 5. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere can be, for example, Cl ２ , BCl ３ , S.F. ６ or CF ４ For example, a mixed gas of chlorine gas and oxygen gas is used as the reactive gas, and thermal etching is performed at a heat treatment temperature of, for example, 700°C or higher and 1000°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. The carrier gas may be, for example, nitrogen gas, argon gas, or helium gas.

[0102] 17 , a trench 56 is formed in the fifth main surface 5 by thermal etching. The trench 56 is defined by a sidewall surface 53 and a bottom wall surface 54. The sidewall surface 53 is formed by the source region 114, the body region 113, and the drift layer 42. The bottom wall surface 54 is formed by the drift layer 42. Next, the mask 117 is removed from the fifth main surface 5.

[0103] Next, a step of forming a gate insulating film is performed. FIG. 18 is a schematic cross-sectional view showing the step of forming a gate insulating film. Specifically, silicon carbide epitaxial substrate 300 having trench 56 formed in fifth main surface 5 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. This forms gate insulating film 115 that is in contact with drift layer 42 at bottom wall surface 54, in contact with drift layer 42, body region 113, and source region 114 at sidewall surface 53, and in contact with source region 114 and contact region 118 at fifth main surface 5.

[0104] Next, a step of forming a gate electrode is performed. FIG. 19 is a cross-sectional view showing a step of forming a gate electrode and an interlayer insulating film. The gate electrode 127 is formed inside the trench 56 so as to contact the gate insulating film 115. The gate electrode 127 is disposed inside the trench 56 and is formed on the gate insulating film 115 so as to face each of the sidewall surface 53 and the bottom wall surface 54 of the trench 56. The gate electrode 127 is formed by, for example, a low pressure chemical vapor deposition (LPCVD) method.

[0105] Next, an interlayer insulating film 126 is formed. The interlayer insulating film 126 is formed so as to cover the gate electrode 127 and to be in contact with the gate insulating film 115. The interlayer insulating film 126 is formed by, for example, chemical vapor deposition. The interlayer insulating film 126 is made of, for example, a material containing silicon dioxide. Next, the interlayer insulating film 126 and part of the gate insulating film 115 are etched so as to form openings over the source region 114 and the contact region 118. As a result, the contact region 118 and the source region 114 are exposed from the gate insulating film 115.

[0106] Next, a step of forming a source electrode is performed. The source electrode 116 is formed so as to be in contact with each of the source region 114 and the contact region 118. The source electrode 116 is formed by, for example, a sputtering method. The source electrode 116 is made of, for example, a material containing Ti (titanium), Al (aluminum), and Si (silicon).

[0107] Next, alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of, for example, 900° C. or higher and 1100° C. or lower for about 5 minutes. As a result, at least a portion of the source electrode 116 is silicided. This forms the source electrode 116 in ohmic contact with the source region 114. The source electrode 116 may also form an ohmic contact with the contact region 118.

[0108] Next, the source wiring 119 is formed. The source wiring 119 is electrically connected to the source electrode 116. The source wiring 119 is formed so as to cover the source electrode 116 and the interlayer insulating film 126.

[0109] Next, a step of forming a drain electrode is carried out. First, silicon carbide substrate 100 is polished at second main surface 2. This reduces the thickness of silicon carbide substrate 100. Next, drain electrode 123 is formed. Drain electrode 123 is formed so as to be in contact with second main surface 2. In this manner, silicon carbide semiconductor device 400 according to this embodiment is manufactured.

[0110] 20 is a cross-sectional schematic diagram showing the configuration of a silicon carbide semiconductor device 400 according to this embodiment. The silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The silicon carbide semiconductor device 400 mainly includes a silicon carbide epitaxial substrate 300, a gate electrode 127, a gate insulating film 115, a source electrode 116, a drain electrode 123, a source wiring 119, and an interlayer insulating film 126. The silicon carbide epitaxial substrate 300 includes a buffer layer 41, a drift layer 42, a body region 113, a source region 114, and a contact region 118. Silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0111] Next, the effects of the silicon carbide substrate 100 according to this embodiment will be described. According to the silicon carbide substrate 100 according to this embodiment, the first main surface 1 has a first half region 11 and a second half region 12. The first half region 11 is located in an off-downstream direction 101 relative to the center O. The second half region 12 is located in an off-upstream direction 102 relative to the center O. The value obtained by dividing the areal density of threading screw dislocations 6 in the first half region 11 by the areal density of threading screw dislocations 6 in the second half region 12 is 88% or less. Thus, the areal density of threading screw dislocations 6 is sufficiently reduced in the first half region 11. Therefore, for example, by grinding the silicon carbide substrate 100 so as to remove at least a portion of the second half region 12, a substrate with few threading screw dislocations 6 can be obtained. By manufacturing a semiconductor device using this substrate, the occurrence of defects in the semiconductor device due to threading screw dislocations 6 can be suppressed. As a result, the yield of semiconductor devices can be improved.

[0112] According to the method for manufacturing silicon carbide epitaxial substrate 300 according to the present disclosure, silicon carbide epitaxial layer 40 is formed on silicon carbide substrate 100 according to the present embodiment. This makes it possible to suppress the formation of defects caused by threading screw dislocations 6 in silicon carbide substrate 100 in silicon carbide epitaxial layer 40 formed on first half surface region 11. As a result, it is possible to improve the yield of semiconductor devices manufactured using silicon carbide epitaxial substrate 300 according to the present embodiment.

[0113] According to the method for manufacturing silicon carbide semiconductor device 400 according to the present disclosure, silicon carbide epitaxial layer 40 is formed on silicon carbide substrate 100 according to the present embodiment. Gate electrode 127 is formed on silicon carbide epitaxial layer 40. Therefore, in silicon carbide semiconductor device 400 formed on first half surface region 11, it is possible to suppress the occurrence of defects caused by threading screw dislocations 6 in silicon carbide substrate 100. As a result, it is possible to improve the yield of silicon carbide semiconductor device 400.

[0114] (Sample Preparation) First, silicon carbide substrates 100 according to Samples 1 to 6 were prepared. Silicon carbide substrates 100 according to Samples 1 to 3 are comparative examples. Silicon carbide substrates 100 according to Samples 4 to 6 are examples.

[0115] Silicon carbide substrate 100 according to Samples 1 to 3 was manufactured by performing the step (S10) of preparing a growth apparatus, the second growth step (S40), and the step (S50) of cutting silicon carbide single crystal in the above-described method for manufacturing silicon carbide substrate 100. From another perspective, the first growth step (S20) and the temperature-raising step (S30) were not performed in the manufacture of silicon carbide substrate 100 according to Samples 1 to 3. Silicon carbide single crystal 200, the growth of which was stopped under the same growth conditions as Samples 1 to 3 after the same time as that of the first growth step (S20) (i.e., the time from the start of growth to second time point T2), had a convexity of 0.5% or more and 2.0% or less.

[0116] Silicon carbide substrates 100 according to Samples 4 to 6 were manufactured in accordance with the above-described method for manufacturing silicon carbide substrate 100. From another perspective, all of the steps in the above-described method for manufacturing silicon carbide substrate 100 were performed in the manufacture of silicon carbide substrates 100 according to Samples 4 to 6. Silicon carbide single crystal 200 whose growth was stopped at the end of the first growth step (S20) (second time point T2) under growth conditions equivalent to those of Samples 4 to 6 had a convexity of more than 2.0%.

[0117] Silicon carbide substrate 100 according to Samples 1 to 6 was produced by slicing a portion of silicon carbide single crystal 200 at a distance of 25 mm from third main surface 3. From another perspective, silicon carbide substrate 100 according to Samples 1 to 6 was produced by slicing a part of second portion 32 of silicon carbide single crystal 200.

[0118] (Evaluation Method) For Samples 1 to 6, the areal density (first areal density) of threading screw dislocations 6 in the first half-face region 11 and the areal density (second areal density) of threading screw dislocations 6 in the second half-face region 12 were measured. Specifically, the first areal density and the second areal density were measured according to the above-mentioned method for measuring the areal density of threading screw dislocations 6. Na ２ O ２ The first main surface 1 was etched using molten KOH to which was added. The temperature of the molten KOH was set to 500°C. The etching time was set to 1 minute. The observation field was set to 0.82 mm x 0.70 mm. The measurement interval was set to 5 mm. Based on the measured areal density, a value obtained by dividing the first areal density by the second areal density was calculated.

[0119] The areal density of stacking faults 10 was measured for Samples 1 to 6. Specifically, the number of stacking faults 10 in each of the plurality of square regions 70 was measured according to the above-described method for measuring the areal density of stacking faults 10. A photoluminescence imaging device (model number: PLI-200) manufactured by Photon Design Inc. was used to measure the number of stacking faults 10.

[0120] Based on the number of stacking faults 10 in each of the plurality of square regions 70, a value (first value) was calculated by dividing the number of the plurality of square regions 70 contained in the first half region 11 and having stacking faults 10 by the total number of the plurality of square regions 70 contained in the first half region 11. A value (second value) was calculated by dividing the number of the plurality of square regions 70 contained in the second half region 12 and having stacking faults 10 by the total number of the plurality of square regions 70 contained in the second half region 12.

[0121] The areal density (A) of the stacking faults 10 in the first sector region 13 and the areal density (B) of the stacking faults 10 in the second sector region 14 were calculated. It was confirmed which of the areal density of the stacking faults 10 in the first sector region 13 and the areal density of the stacking faults 10 in the second sector region 14 was larger.

[0122] (Evaluation results)

[0123]

[0124]

[0125] Tables 1 and 2 show the value obtained by dividing the first areal density by the second areal density, the first value, the second value, and the magnitude relationship between the areal density (A) of stacking faults 10 in first sectoral region 13 and the areal density (B) of stacking faults 10 in second sectoral region 14. As shown in Table 1, in Samples 1 to 3, the value obtained by dividing the first areal density by the second areal density was 95% or more. In Samples 4 to 6, the value obtained by dividing the first areal density by the second areal density was 68% or more and 88% or less. From this, it was confirmed that, according to the silicon carbide substrate 100 according to the example, the value obtained by dividing the first areal density by the second areal density was reduced.

[0126] 21 is a diagram showing the distribution of threading screw dislocations 6 in the first main surface 1 of the silicon carbide substrate 100 according to Sample 1. Fig. 22 is a diagram showing the distribution of threading screw dislocations 6 in the first main surface 1 of the silicon carbide substrate 100 according to Sample 4.

[0127] 21 and 22, the first region is the region where the number of measured etch pits was 5 or less. The second region is the region where the number of measured etch pits was 6 to 17. The third region is the region where the number of measured etch pits was 18 to 28. The fourth region is the region where the number of measured etch pits was 29 or more.

[0128] 21 and 22 , compared with silicon carbide substrate 100 according to the comparative example, silicon carbide substrate 100 according to the example had a reduced density of threading screw dislocations 6 in a region located in off-downstream direction 101 relative to center O. In other words, it was confirmed that silicon carbide substrate 100 according to the example had a reduced density of threading screw dislocations 6 in first half-surface region 11.

[0129] As shown in Table 2, the first value was 0% in Samples 1 to 6. The second value was 0% in Samples 1 to 4. The second value was 2% or more and 4% or less in Samples 5 and 6.

[0130] As shown in Table 2, in Samples 1 to 4, the areal density (A) of the stacking faults 10 in the first sector region 13 was equal to the areal density (B) of the stacking faults 10 in the second sector region 14. In Samples 5 and 6, the areal density (A) of the stacking faults 10 in the first sector region 13 was smaller than the areal density (B) of the stacking faults 10 in the second sector region 14.

[0131] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include meanings equivalent to the claims and all modifications within the scope thereof.

[0132] 1 First main surface, 2 Second main surface, 3 Third main surface, 4 Fourth main surface, 5 Fifth main surface, 6 Threading screw dislocation, 7 Orientation flat portion, 8 Arc-shaped portion, 9 First outer peripheral surface, 10 Stacking fault, 11 First half-surface region, 12 Second half-surface region, 13 First sector-shaped region, 14 Second sector-shaped region, 21 First resistance heater, 22 Second resistance heater, 23 Third resistance heater, 29 Second outer peripheral surface, 30 Crucible, 31 First portion, 32 Second portion, 35 Lid portion, 36 Source material container portion, 38 Growth surface, 39 Interface, 40 Silicon carbide epitaxial layer, 41 Buffer layer, 42 Drift layer, 50 Seed substrate, 51 Growth surface, 52 Mounting surface, 53 Side wall surface, 54 Bottom wall surface, 56 Trench, 59 Silicon carbide raw material, 61 first threading screw dislocation, 62 second threading screw dislocation, 70 square region, 71 first boundary, 72 second boundary, 81 first ray, 82 second ray, 83 third ray, 84 fourth ray, 91 first tangent, 92 second tangent, 95 step, 99 center line, 100 silicon carbide substrate, 101 first direction (off-downstream direction), 102 second direction (off-upstream direction), 103 third direction (growth direction), 104 fourth direction, 113 body region, 114 source region, 115 gate insulating film, 116 source electrode, 117 mask, 118 contact region, 119 source wiring, 123 drain electrode, 126 interlayer insulating film, 127 gate electrode, 200 silicon carbide single crystal, 300 silicon carbide epitaxial substrate, 400 Silicon carbide semiconductor device, 500 growth apparatus, B1 first temperature, B2 second temperature, C central axis, C1 first flow rate, C2 second flow rate, H1 first thickness, H2 second thickness, H3 peripheral thickness, H4 central thickness, L length, O center, T height, T1 first point in time, T2 second point in time, T3 third point in time, T4 fourth point in time, W1 first diameter, W2 second diameter, W3 third diameter, θ off angle.

Claims

1. A silicon carbide substrate having a main surface, the main surface being inclined in a [11-20] direction with respect to a {0001} plane, wherein when the [11-20] direction is an off-downstream direction and the [-1-120] direction is an off-upstream direction, in a plan view perpendicular to the main surface, the main surface is composed of a first half-surface region located in the off-downstream direction with respect to a center of the main surface, and a second half-surface region located in the off-upstream direction with respect to the center, and wherein when an areal density of threading screw dislocations in the first half-surface region is a first areal density and an areal density of threading screw dislocations in the second half-surface region is a second areal density, a value obtained by dividing the first areal density by the second areal density is not more than 88%.

2. The silicon carbide substrate according to claim 1, wherein a value obtained by dividing said first areal density by said second areal density is equal to or greater than 68%.

3. The silicon carbide substrate according to claim 1 or 2, wherein, when the main surface is divided into a plurality of square regions, each having a side length of 2.6 mm, a value obtained by dividing the number of the plurality of square regions included in the first half-surface region and having stacking faults by the total number of the plurality of square regions included in the first half-surface region is 4% or less, and a value obtained by dividing the number of the plurality of square regions included in the second half-surface region and having stacking faults by the total number of the plurality of square regions included in the second half-surface region is 0%.

4. The silicon carbide substrate according to any one of claims 1 to 3, wherein, in the plan view, when viewed from the center, a [11-20] direction, a [1-100] direction, and a [-1100] direction are 0°, 90°, and -90°, respectively, the main surface includes: a first sector region located between a half line extending in a -10° direction from the center and a half line extending in a 10° direction from the center, and a second sector region located between a half line extending in a 20° direction from the center and a half line extending in a 40° direction from the center, and an areal density of stacking faults in the first sector region is smaller than an areal density of stacking faults in the second sector region.

5. A method for manufacturing a silicon carbide epitaxial substrate, comprising the steps of: preparing a silicon carbide substrate according to any one of claims 1 to 4; and forming a silicon carbide epitaxial layer on the silicon carbide substrate.

6. A method for manufacturing a silicon carbide semiconductor device, comprising the steps of: preparing a silicon carbide substrate according to any one of claims 1 to 4; forming a silicon carbide epitaxial layer on the silicon carbide substrate; and forming an electrode on the silicon carbide epitaxial layer.

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