Method of manufacturing chip-on-wafer for micro LED display

Abstract

The present invention relates to a method of manufacturing a chip-on-wafer for a micro LED display, the method, using a chip-on-wafer method to manufacture a lateral chip, a flip chip, and a vertical chip for a micro LED display, etching an undoped semiconductor region (uGaN) and an n-type semiconductor region (nGaN) of a semiconductor layer without damaging the chips to allow thickness of the semiconductor layer to be significantly reduced.

Description

Method for manufacturing chip-on-wafer for micro LED display

[0001] The present invention relates to a method for manufacturing a chip-on-wafer for a micro LED display, and more particularly, to a method for manufacturing a chip-on-wafer for a micro LED display, which can significantly reduce the thickness of a semiconductor layer by etching an undoped semiconductor region (uGaN) and an n-type semiconductor region (nGaN) of a semiconductor layer without damaging the chip, in manufacturing a lateral chip, a flip chip, and a vertical chip for a micro LED display using a chip-on-wafer method.

[0002] Recently, the demand for higher-performance metaverse devices has driven the need for ever-smaller chips for the manufacture of micro-level LED displays. To meet this market demand, currently manufactured micro-LED display chips are typically between 5 and 8 ㎛ thick. However, achieving a thickness of less than 5 ㎛ is reportedly difficult due to processing difficulties and chip breakage.

[0003] Meanwhile, the chip-on-wafer method refers to a method in which the entire process, from the process of epitaxially growing a semiconductor layer on the initial growth substrate to the final fab process, is performed on the initial growth wafer.

[0004] According to this conventional chip-on-wafer method, since the stacked structure of the chip is completed using only the initial growth substrate, the thickness of the undoped semiconductor region (uGaN) or n-type semiconductor region (nGaN) cannot be controlled, making it impossible to manufacture a micro LED with a thickness of 5 μm or less. In addition, there is also a disadvantage in that the light extraction efficiency is lowered by this thick undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, uAlGaInN, uGaP, uInGaP, uAlGaP or uAlGaInP).

[0005] Meanwhile, in the conventional chip-on-wafer method, a completed chip is attached to TFT Glass, an interposer, etc., and then the initial growth substrate on the opposite side is removed to expose an undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, uAlGaInN, uGaP, uInGaP, uAlGaP, or uAlGaInP). However, even if the undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, uAlGaInN, uGaP, uInGaP, uAlGaP, or uAlGaInP) is etched, there is a problem in that the completed chip, TFT Glass, or interposer is damaged by the high temperature generated during etching and the gas injected.

[0006] Furthermore, when the first growth substrate is removed by the laser lift off (LLO) process, a large number of gallium (Ga) droplets (solid, powder) that interfere with the scattering of the generated light are generated on the surface of the semiconductor layer from which the first growth substrate was removed. Currently, the gallium droplets are removed by hydrochloric acid treatment or taping, but the method using hydrochloric acid treatment has the problem that the TFT Glass and interposer may be damaged, and when taping is used, there is the problem that the gallium droplets cannot be completely removed. However, when the first growth substrate for Si (nitride that emits blue, green, and red) and GaAs (phosphide that emits red) micro LEDs is removed by the chemical lift off (CLO) process, there is no issue with gallium droplets.

[0007] Furthermore, since conventional chip-on-wafer methods use only the initial growth substrate to complete the chip's stacked structure, ohmic contact electrodes must be formed in a later (back-end) process. In this case, heat treatment at temperatures above 300°C is essential to form these ohmic contact electrodes, posing the problem of chips already stacked with multiple layers being damaged by the high temperatures.

[0008] The purpose of the present invention is to solve the above-described conventional problems, and to provide a method for manufacturing a chip-on-wafer for a micro LED display, which can drastically reduce the thickness of a semiconductor layer by etching an undoped semiconductor region (uGaN) and an n-type semiconductor region (nGaN) of a semiconductor layer without damaging the chip, in manufacturing a lateral chip, a flip chip, and a vertical chip for a micro LED display using a chip-on-wafer method.

[0009] The above object is achieved by a method for manufacturing a chip-on-wafer for a micro LED display according to the present invention, comprising: a growth step of epitaxially growing a semiconductor layer on an initial growth substrate; an electrode formation step of forming an ohmic contact electrode on the semiconductor layer; a bonding step of bonding the ohmic contact electrode to an intermediate temporary substrate through an adhesive layer; an exposure step of removing the initial growth substrate to expose one surface of the semiconductor layer; an etching step of etching the exposed one surface of the semiconductor layer to reduce the thickness of the semiconductor layer; a bonding step of bonding the etched one surface of the semiconductor layer to a final support substrate; and a removal step of removing the intermediate temporary substrate and the adhesive layer.

[0010] In addition, in the growth step, a third semiconductor region, a second semiconductor region, an active region, and a first semiconductor region are sequentially epitaxially grown on an initial growth substrate, and in the etching step, the exposed third semiconductor region is etched to reduce the thickness of the semiconductor layer, and the third semiconductor region may be an undoped semiconductor region.

[0011] In addition, the etching step reduces the thickness of the semiconductor layer by etching the second semiconductor region, and the second semiconductor region may be an n-type semiconductor region.

[0012] The above object is achieved by a method for manufacturing a chip-on-wafer for a micro LED display according to the present invention, comprising: a growth step of epitaxially growing a semiconductor layer on an initial growth substrate; an electrode formation step of forming an ohmic contact electrode on the semiconductor layer; a bonding step of bonding the ohmic contact electrode to a final support substrate; an exposure step of removing the initial growth substrate to expose one surface of the semiconductor layer; and an etching step of etching the exposed one surface of the semiconductor layer to reduce the thickness of the semiconductor layer.

[0013] In addition, in the growth step, a third semiconductor region, a second semiconductor region, an active region, and a first semiconductor region are sequentially epitaxially grown on an initial growth substrate, and in the etching step, the exposed third semiconductor region is etched to reduce the thickness of the semiconductor layer, and the third semiconductor region may be an undoped semiconductor region.

[0014] In addition, the etching step reduces the thickness of the semiconductor layer by etching the second semiconductor region, and the second semiconductor region may be an n-type semiconductor region.

[0015] According to the present invention, the thickness of the semiconductor layer can be drastically reduced to 0.57 to 5.7 μm by etching the undoped semiconductor region (uGaN) and the n-type semiconductor region (nGaN) of the semiconductor layer without damaging the chip, thereby enabling the manufacture of a chip for a high-quality, high-brightness micro LED display.

[0016] In addition, according to the present invention, the problem of gallium (Ga) droplets remaining on the surface of the semiconductor layer can be fundamentally prevented, so that light extraction efficiency can be significantly improved.

[0017] Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within a range obvious to those skilled in the art from the contents described below.

[0018] Figures 1 and 2 illustrate the overall process of manufacturing a chip-on-wafer according to the method for manufacturing a chip-on-wafer for a micro LED display according to the first embodiment of the present invention.

[0019] FIG. 3 is a flowchart of a method for manufacturing a chip-on-wafer for a micro LED display according to the first embodiment of the present invention.

[0020] FIG. 4 illustrates chip-on-wafers of various structures manufactured according to a method for manufacturing a chip-on-wafer for a micro LED display according to the first embodiment of the present invention.

[0021] FIG. 5 is a diagram illustrating the overall process of manufacturing a chip-on-wafer according to a method for manufacturing a chip-on-wafer for a micro LED display according to a second embodiment of the present invention.

[0022] FIG. 6 is a flowchart of a method for manufacturing a chip-on-wafer for a micro LED display according to a second embodiment of the present invention.

[0023] FIG. 7 illustrates chip-on-wafers of various structures manufactured according to a method for manufacturing a chip-on-wafer for a micro LED display according to a second embodiment of the present invention.

[0024] FIG. 8 is a diagram for explaining a size error affecting performance deviation in a method for manufacturing a chip-on-wafer for a micro LED display according to the first and second embodiments of the present invention.

[0025] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components are given the same reference numerals, even if they appear in different drawings.

[0026] In addition, when describing an embodiment of the present invention, if a detailed description of a related known configuration or function is judged to hinder understanding of the embodiment of the present invention, the detailed description is omitted.

[0027] Additionally, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms.

[0028]

[0029] From now on, with reference to the attached drawings, a method (S100) for manufacturing a chip-on-wafer for a micro LED display according to the first embodiment of the present invention will be described in detail.

[0030] FIG. 1 and FIG. 2 are overall diagrams illustrating a process of manufacturing a chip-on-wafer according to a method for manufacturing a chip-on-wafer for a micro LED display (S100) according to a first embodiment of the present invention, FIG. 3 is a flowchart of a method for manufacturing a chip-on-wafer for a micro LED display (S100) according to a first embodiment of the present invention, and FIG. 4 illustrates chip-on-wafers of various structures manufactured according to a method for manufacturing a chip-on-wafer for a micro LED display (S100) according to a first embodiment of the present invention.

[0031] As illustrated in FIGS. 1 to 3, a method (S100) for manufacturing a chip-on-wafer for a micro LED display according to a first embodiment of the present invention manufactures a chip-on-wafer through a two-step wafer bonding method, and includes a growth step (S110), an electrode formation step (S120), an adhesion step (S130), an exposure step (S140), an etching step (S150), a bonding step (S160), and a removal step (S170).

[0032] The growth stage (S110) is a stage in which the first growth substrate (110) is prepared and a semiconductor layer (120) is epitaxially grown on the first growth substrate (110).

[0033] In the case where the semiconductor layer (120) emits blue or green light, when the laser lift off (LLO) process is used to remove the first growth substrate (110), the first growth substrate (110) can be made of a sapphire (α-phase Al2O3) substrate that is optically transparent and has high temperature resistance, through which a laser beam (single wavelength light) can theoretically be 100% transmitted without absorption, and when the chemical lift off (CLO) process is used to remove the first growth substrate (110), the first growth substrate (110) can be made of a Si substrate having a (111), (110), or (100) crystal plane that can be removed by wet etching.

[0034] Meanwhile, in the case where the first growth substrate (110) is prepared as a sapphire substrate, it is also desirable for the first growth substrate (110) to have a protrusion shape that is patterned regularly or irregularly in various dimensions (size and shape) in microscale or nanoscale in order to minimize crystal defects within the group III nitride semiconductor thin film grown on top (patterned sapphire substrate, PSS).

[0035] In addition, when the semiconductor layer (120) emits red light, the initial growth substrate (110) may be prepared as a GaAs substrate that can be removed by wet etching using a chemical lift off (CLO) process. Furthermore, when the semiconductor layer (120) emits red light through a high-quality InGaN active region (124) having a high In composition of 30% or more, the initial growth substrate (110) may be prepared as a sapphire or Si substrate, similarly to when the semiconductor layer (120) emits blue or green light.

[0036] The semiconductor layer (120) generates light and includes a third semiconductor region (123), a second semiconductor region (122), an active region (124), and a first semiconductor region (121).

[0037] In the present invention, the semiconductor layer (120) can emit blue, green, or red light. When the semiconductor layer (120) emits blue or green light, a binary, ternary, or quaternary compound such as InN, InGaN, GaN, AlGaN, AlN, or AlGaInN, which is a group 3 (Al, Ga, In) nitride semiconductor among group 3-5 compound semiconductors, can be epitaxially grown by arranging it in an appropriate position and order on the initial growth substrate (110).

[0038] In particular, a high-quality group III nitride semiconductor of InGaN having a high In composition to emit blue or green light should be preferentially formed on the top of a group III nitride semiconductor composed of GaN, AlGaN, AlN or AlGaInN (active region (124)), but is not limited thereto.

[0039] In addition, in the present invention, when the semiconductor layer (120) emits red light, a binary, ternary, or quaternary compound such as InP, InGaP, GaP, AlInP, AlGaP, AlP, or AlGaInP, which is a group 3 (Al, Ga, In) phosphide semiconductor among group 3-5 compound semiconductors, can be epitaxially grown by being placed in an appropriate position and order on the initial growth substrate (110).

[0040] In particular, in order to emit red light, a high-quality group III phosphide semiconductor such as InGaP having a high In composition should be preferentially formed on top of a group III phosphide semiconductor composed of GaP, AlInP, AlGaP, AlP or AlGaInP, but is not limited thereto, and for convenience of explanation, the group III nitride semiconductor will be used as a basis for the following description.

[0041] Furthermore, in order to further improve the value of display panel products and the development of equipment and process technology in recent years, in the case of emitting red light, in addition to group III phosphide semiconductors, a group III nitride semiconductor of high quality InGaN having a high In composition of 30% or more can be preferentially formed on the top of the group III nitride semiconductor (active region (124)) composed of GaN, AlGaN, AlN or AlGaInN. Specifically, the active region (124) is In x Ga 1-x When composed of N, x, that is, when the composition of indium is 16 to 20%, it emits blue light in the wavelength band of 450 nm to 470 nm, when the composition of indium is 22 to 28%, it emits green light in the wavelength band of 525 nm to 540 nm, and when the composition of indium is 30 to 35% (preferably 33%), it emits red light in the wavelength band of 625 nm to 635 nm.

[0042] In more detail, the growth step (S110) may sequentially epitaxially grow a third semiconductor region (123) (e.g., uGaN, uInGaN, uAlGaN, or uAlGaInN) which is an undoped semiconductor region, a second semiconductor region (122) (e.g., nGaN, nInGaN, nAlGaN, or nAlGaInN) which is an n-type semiconductor region, an active region (124) (MQWs) of a multi-quantum well structure, and a first semiconductor region (121) (e.g., pGaN, pInGaN, pAlGaN, or nAlGaInN) which is a p-type semiconductor region on the initial growth substrate (110), and may ultimately have an overall thickness of typically about 5.0 μm to 8.0 μm including multiple multi-layers of group III nitrides, but is not limited thereto.

[0043] The third semiconductor region (123) is an undoped semiconductor region, and specifically, the third semiconductor region (123) is a region that acts as a buffer to relieve stress and improve thin film quality of the epitaxially grown second semiconductor region (122), active region (124), and first semiconductor region (121) before epitaxially growing the second semiconductor region (122), active region (124), and first semiconductor region (121) on top of the initial growth substrate (110).

[0044] This third semiconductor region (123) may include a nucleation layer (NL) and may be formed to a thickness of typically 2.5 μm to 3 μm. In addition, when the initial growth substrate (110) is removed using a laser lift off (LLO) technique, a sacrificial layer (SL) may be provided between the nucleation layer and the third semiconductor region (123), and the nucleation layer may also function as the sacrificial layer.

[0045] The second semiconductor region (122) has n-type conductivity and is formed on the third semiconductor region (123). This second semiconductor region (122) may have a thickness of 2.0 to 2.5 μm, and its lower surface has nitrogen polarity (N-polarity).

[0046] The active region (124) has a multi-quantum well structure and generates light by utilizing the recombination of electrons and holes, and is formed on the second semiconductor region (122). This active region (124) may have a multi-layer thickness of about 50 nm.

[0047] The first semiconductor region (121) has p-type conductivity and is formed on the active region (124). This first semiconductor region (121) may have a multilayer thickness of 0.5 μm or less, and the upper surface has gallium polarity (Ga-polarity).

[0048] That is, the active region (124) is interposed between the second semiconductor region (122) and the first semiconductor region (121), and when electrons in the second semiconductor region (122), which is an n-type semiconductor region, and holes in the first semiconductor region (121), which is a p-type semiconductor region, recombine in the active region (124), light is generated.

[0049] The electrode formation step (S120) is a step of forming an ohmic contact electrode (130) on a semiconductor layer (120).

[0050] According to the conventional chip-on-wafer method, since the stacked structure of the chip (including horizontal chips, flip chips, and vertical chips) is completed using only the initial growth substrate (110), the p-type ohmic contact electrode has no choice but to be formed in the back-end process. In this case, in order to form the p-type ohmic contact electrode (130), heat treatment must be performed at a temperature of 450°C or higher, so there is a problem that the chip, on which multiple layers have already been stacked, is damaged by the high temperature.

[0051] Accordingly, in the present invention, after the semiconductor layer (120) is grown, a p-type ohmic contact electrode (130) is formed through high-temperature heat treatment in a state where other layers are not laminated (i.e., in a state where the structure of the chip is not completed), and then the remaining necessary layers, such as a reflective layer (170), are laminated on one surface of the semiconductor layer (120), so that the problem of the laminated chip being damaged by the high-temperature heat treatment for forming the p-type ohmic contact electrode (130) can be fundamentally prevented.

[0052] More specifically, in the present invention, the ohmic contact electrode (130) is formed to be in contact with the first semiconductor region (121) which is a p-type semiconductor, and is formed as a p-type ohmic contact electrode. Since the present embodiment is used in a vertical chip structure, the p-type ohmic contact electrode (130) is formed of a material having transparent conductivity so that light from the bottom can be transmitted to the top. In this case, the ohmic contact electrode (130) material may include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, or IGZO.

[0053] Meanwhile, in the present invention, the p-type ohmic contact electrode (130) may have a single-layer structure, and may have a multi-layer structure in which a thin p-type ohmic contact electrode (130) is first formed on a gallium polarity (Ga-polarity) surface, and then a p-type electrode is formed thereon with a material that is the same as or different from the p-type ohmic contact electrode (130) and is electrically connected.

[0054] The bonding step (S130) is a step of bonding the ohmic contact electrode (130) to the intermediate temporary substrate (150) through the bonding layer (140).

[0055] Here, the intermediate temporary substrate (150) preferably has a coefficient of thermal expansion (CTE) that is equal to or similar to that of the initial growth substrate (110) and the final support substrate (190). In the case where a laser lift off (LLO) process is used to remove the intermediate temporary substrate (150), the intermediate temporary substrate (150) may be formed of a sapphire (α-phase Al2O3) substrate that is optically transparent and has high temperature resistance and allows 100% (theoretically) transmission of a laser beam (single wavelength light) without absorption, glass whose coefficient of thermal expansion (CTE) is adjusted to have a difference of 2 ppm or less from that of the final support substrate (190), and in the case where a chemical lift off (CLO) process is used to remove the intermediate temporary substrate (150), the intermediate temporary substrate (150) may be formed of a Si substrate having a (111), (110), or (100) crystal plane that can be removed by wet etching.

[0056] In addition, in the present embodiment, the adhesive layer (140) may be formed of a metal or alloy, ceramic, or resin material. In particular, it is preferable to preferentially select a material that performs metallic bonding (eutectic bonding, diffusion bonding, direct bonding, etc.) as the adhesive layer (140), and the adhesive layer (140) may include a metallic bonding material that can be soldered at a temperature of 300°C or lower, such as In, Sn, Ga, Zn, Au, Ag, Cu, Pd, Ni, Ti, Cr, Al, or Si. In addition, a ceramic material that can be directly bonded at a temperature of 100°C or lower, such as SiO2, SOG (spin on glass), FOx (flowable oxides), SiN x , Al2O3, AlN, SiCN, ITO, IZO or ZnO, and may include resin materials such as epoxy, BCB (benzocyclobutene) or PI (polyimide) as organic adhesives capable of indirect bonding at a temperature of 100℃ or lower.

[0057] Meanwhile, the bonding step (S130) may form a sacrificial separation layer (S) on an intermediate temporary substrate (150), and then bond the ohmic contact electrode (130) to the sacrificial separation layer (S) through an adhesive layer (140). This sacrificial separation layer (S) is a layer that is sacrificed and separated when the intermediate temporary substrate (150) is removed, and its material may vary depending on whether a laser lift off (LLO) process or a chemical lift off (CLO) process is used. Meanwhile, this sacrificial separation layer (S) may be located on the upper or lower side of the adhesive layer (140) depending on the purpose, and if the adhesive layer (140) performs the function of the sacrificial separation layer (S), the sacrificial separation layer (S) may be omitted.

[0058] In addition, the bonding step (S130) can form a protective layer (P) on the ohmic contact electrode (130), and then bond the protective layer (P) to the intermediate temporary substrate (150) through the adhesive layer (140). This protective layer (P) serves to protect the elements below the ohmic contact electrode (130) when the adhesive layer (140) is removed in a subsequent process, and representative materials of the protective layer (P) include SiO2 and SiN. x , or AlN, but is not limited thereto, and various materials may be used depending on the method of removing the adhesive layer (140) (for example, when removing the adhesive layer (140) with hydrochloric acid, a SiO2 protective layer (P) is used). Furthermore, if the removal of the adhesive layer (140) does not affect the device, the protective layer (P) may be omitted.

[0059] Furthermore, the bonding step (S130) may form a sacrificial separation layer (S) on an intermediate temporary substrate (150), form a protective layer (P) on an ohmic contact electrode (130), and then bond the protective layer (P) to the sacrificial separation layer (S) through an adhesive layer (140).

[0060] The exposure step (S140) is a step of removing the initial growth substrate (110) to expose one side of the semiconductor layer (120).

[0061] In more detail, the exposure step (S140) can expose the third semiconductor region (123), which is an undoped semiconductor region, to the outside by removing the first growth substrate (110) using a laser lift off (LLO) process or a chemical lift off (CLO) process.

[0062] The etching step (S150) is a step of etching one surface of the exposed semiconductor layer (120) to reduce the thickness of the semiconductor layer (120).

[0063] According to the conventional chip-on-wafer method, since the stacked structure of the chip (including horizontal chips, flip chips, and vertical chips) is completed using only the initial growth substrate (110), the thickness of the undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, or uAlGaInN) or the n-type semiconductor region (e.g., nGaN, nInGaN, nAlGaN, or nAlGaInN) cannot be controlled, making it impossible to manufacture a high-quality, high-brightness micro LED having a thickness of 5 μm or less. In addition, there is also a disadvantage that the light extraction efficiency is lowered by such a thick undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, or uAlGaInN).

[0064] Meanwhile, in the conventional chip-on-wafer method, a completed chip is attached to TFT Glass, an interposer, etc., and then the initial growth substrate (110) on the opposite side is removed to expose an undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, or uAlGaInN). However, even if the undoped semiconductor region (e.g., uGaN, uInGaN, uAlGaN, or uAlGaInN) is etched, there is a problem in that the completed chip is damaged by the high temperature generated during etching and the gas injected.

[0065] Meanwhile, FIG. 8 is for explaining the size error affecting the performance deviation in the manufacturing method of a chip-on-wafer for a micro LED display according to the first and second embodiments of the present invention.

[0066] As illustrated in Fig. 8, the process of implementing an epitaxial wafer on which growth has been completed into a device includes an isolation process that determines the size and shape of the chip, and in this process, the GaN semiconductor layer (120) is etched. Here, the etching of the semiconductor layer (120) can be performed using photolithography, which creates a pattern using a photoresist of a desired size and shape and then etches the GaN semiconductor layer (120) by dry or wet etching.

[0067] At this time, during the etching process, a size error (A), which is an error in the size of the lower surface and upper surface of the semiconductor layer (120), inevitably exists, and this size error (A) is according to the following mathematical formula.

[0068]

[0069] That is, since θ and the thickness (B) of the semiconductor layer (120) and the size error (A) are in a directly proportional relationship, in order to reduce the size error (A) of the chip, θ or the thickness (B) of the semiconductor layer (120) must be reduced. In other words, when manufacturing an extremely small chip such as a micro LED chip, the closer the isolation slope is to vertical, and the smaller the thickness of the semiconductor layer (120), the more advantageous it is.

[0070] Furthermore, as chip size decreases, the surface area ratio of the side increases. Consequently, the smaller the chip, the greater the impact of surface leakage and surface recombination on the surface. To address this, it is necessary to either increase the chip size or decrease its thickness. However, since increasing the chip size is meaningless, a method of reducing the chip thickness is necessary.

[0071] More specifically, for a micro LED chip with a top surface size of 0.1 to 10 ㎛, assuming that the isolation slope is implemented to be 80° to 89°, the thickness of the semiconductor layer (120) required when the size error (A) is set to within 10% is as shown in the following table. Meanwhile, the thickness of the semiconductor layer (120) can be thicker as the isolation slope approaches 90°, but the implementation of 90° is realistically difficult.

[0072] case 1case 2case 3case 4case 5case 6top size(㎛)0.100.101.001.0010.0010.00bottom size(㎛)0.110.111.101.1011.0011.00size error(㎛)0.010.010.10.111Isolation slope(°)808980898089θ(°)101101101tanθ0.180.020.180.020.180.02Required semiconductor layer(120) thickness0.057(impossible to implement)0.570.575.75.757.3(no thickness reduction required)

[0073] As shown in the table above, assuming that the isolation slope is ideally implemented up to 89°, the thickness of the semiconductor layer (120) required to implement a size error (A) of less than 10% in a micro LED chip having an upper surface size of 0.1 to 10 ㎛ was found to be 0.57 to 5.7 ㎛. In addition, after the growth step (S110) to the exposure step (S140) of the present invention, the third semiconductor region (123), which is an undoped semiconductor region with a thickness of 2.5 μm to 3 μm, is etched and removed in the etching step (S150), and the second semiconductor region (122), which is an n-type semiconductor region with a thickness of 2.0 to 2.5 μm, is partially etched, thereby realizing a semiconductor layer (120) with a thickness of 0.57 to 5.7 μm. It was confirmed through an actual prototype that this is possible. That is, according to the present invention, the ohmic contact electrode (130) on the semiconductor layer (120) is bonded to an intermediate temporary substrate (150), and then the first growth substrate (110) is removed while other layers are not stacked (i.e., the structure of the chip is not completed), and then the undoped semiconductor region (uGaN) and the n-type semiconductor region (nGaN) of the semiconductor layer (120) are etched, thereby forming the semiconductor layer (120). Since the thickness of the semiconductor layer (120) can be drastically reduced to a thickness of 0.57 to 5.7 μm, a chip for a high-quality, high-brightness micro LED display can be manufactured. Accordingly, in the etching step (S150), the thickness of the semiconductor layer (120) can be reduced by etching and removing part or all of the third semiconductor region (123), which is an undoped semiconductor region exposed by removing the growth substrate (110), and when the third semiconductor region (123) is removed, the thickness of the semiconductor layer (120) can be reduced to a thickness of 0.57 to 5.7 μm by additionally etching part of the second semiconductor region (122) to a preset thickness.

[0074] Meanwhile, in the case where a buffer layer is provided under the third semiconductor region (123), the exposure step (S140) can expose one side of the buffer layer, and the etching step (S150) can etch the buffer layer and the third semiconductor region (123) to remove them, and then etch the second semiconductor region (122) to a preset thickness.

[0075] The bonding step (S160) is a step of bonding one surface of the semiconductor layer (120) to the final support substrate (190) through the bonding layer (180).

[0076] Here, the final support substrate (190) is a substrate that supports the structure of a chip that has gone through each step of the manufacturing method (S100) of a chip-on-wafer for a micro LED display according to the first embodiment of the present invention, and this final support substrate (190) can be prepared as a sapphire (α-phase Al2O3) substrate, glass with a controlled coefficient of thermal expansion (CTE), a Si substrate, etc., depending on the purpose.

[0077] Meanwhile, the bonding step (S160) may form a sacrificial separation layer (S) on the final support substrate (190), and then bond one surface of the semiconductor layer (120) to the sacrificial separation layer (S). This sacrificial separation layer (S) is a layer that is sacrificed and separated when the final support substrate (190) is removed, and a material according to a laser lift off (LLO) process may be used. Meanwhile, this sacrificial separation layer (S) may be located on the upper or lower side of the bonding layer (180) depending on the purpose, and if the sacrificial bonding layer (180) performs the function of the sacrificial separation layer (S), the sacrificial separation layer (S) may be omitted.

[0078] The removal step (S170) is a step of removing the intermediate temporary substrate (150) and the adhesive layer (140).

[0079] In more detail, the removal step (S170) removes the intermediate temporary substrate (150) and the adhesive layer (140) using a laser lift off (LLO) process or a chemical lift off (CLO) process, and when a sacrificial separation layer (S) and a protective layer (P) are formed, the sacrificial separation layer (S) and the protective layer (P) are also removed together.

[0080] Meanwhile, as illustrated in FIG. 4, the chip-on-wafer for a micro LED display according to the first embodiment of the present invention may have various structures.

[0081] First, as shown in (b), (d), (f), and (h) of FIG. 4, in the etching step (S150) of the present invention, a surface roughness pattern can be formed on one surface of the etched semiconductor layer (120).

[0082] In addition, as illustrated in (a), (b), (c), and (d) of FIG. 4, in the bonding step (S160) of the present invention, after a reflective layer (170) is formed on one surface of an etched semiconductor layer (120), a bonding layer (180) is formed to surround the reflective layer (170), and then one surface of the semiconductor layer (120) on which the reflective layer (170) is formed can be bonded to a support substrate (190) or a sacrificial separation layer (S) through the bonding layer (180).

[0083] At this time, the reflective layer (170) may be made of Ag, Al, Au, Pd, Pt, Ni, Mo, Cu, Cr, Ti, TiW, ITO, IZO, ZnO, TiN, DBR (distributed Bragg reflector), ODR (omni-directional reflector) or a combination thereof, and may be in ohmic contact with the semiconductor layer (120) as shown in (a) and (b) of FIG. 4, or may not be in ohmic contact with the semiconductor layer (120) as shown in (c) and (d) of FIG. 4.

[0084] In addition, as shown in (e), (f), (g) and (h) of FIG. 4, in the bonding step (S160) of the present invention, one surface of the etched semiconductor layer (120) can be bonded to the support substrate (190) or the sacrificial separation layer (S) through the bonding layer (180) without forming a separate reflective layer (170).

[0085] At this time, the bonding layer (180) may or may not be in ohmic contact with the semiconductor layer (120). As shown in (e) and (f) of FIG. 4, when the bonding layer (180) is in ohmic contact with the semiconductor layer (120), the bonding layer (180) may be formed of a metal material, and may include materials such as In, Sn, Ga, Zn, Au, Ag, Cu, Pd, Ni, Ti, Cr, Al, and Si, as a metallic bonding material that can be soldered at a temperature of 300°C or lower, and may also perform the function of a reflector.

[0086] In addition, as shown in (g) and (h) of FIG. 4, when the bonding layer (180) is not in ohmic contact with the semiconductor layer (120), the bonding layer (180) is made of SiO2, SiN so that the generated light can be transmitted. x , SiCN, AlN, Al2O3, SOG (spin on glass, liquid SiO2), HSQ (hydrogen silsesquioxane), etc., and in this case, the ohmic contact electrode (130) may be formed of a metallic material so as to reflect the generated light.

[0087]

[0088] From now on, with reference to the attached drawings, a method for manufacturing a chip-on-wafer for a micro LED display according to a second embodiment of the present invention (S200) will be described in detail.

[0089] FIG. 5 is a diagram illustrating a process of manufacturing a chip-on-wafer according to a method for manufacturing a chip-on-wafer for a micro LED display (S200) according to a second embodiment of the present invention, FIG. 6 is a flowchart of a method for manufacturing a chip-on-wafer for a micro LED display (S200) according to a second embodiment of the present invention, and FIG. 7 illustrates chip-on-wafers of various structures manufactured according to a method for manufacturing a chip-on-wafer for a micro LED display (S200) according to a second embodiment of the present invention.

[0090] As illustrated in FIGS. 5 and 6, a method (S200) for manufacturing a chip-on-wafer for a micro LED display according to a second embodiment of the present invention manufactures a chip-on-wafer through a one-time wafer bonding method, and includes a growth step (S210), an electrode formation step (S220), a bonding step (S230), an exposure step (S240), an etching step (S250), and a forming step (S260).

[0091] Here, the undescribed contents of the growth step (S210) and the electrode formation step (S220) are the same as those of the manufacturing method (S100) of a chip-on-wafer for a micro LED display according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0092] The bonding step (S230) is a step of bonding the ohmic contact electrode (230) to the final support substrate (290) through the bonding layer (280).

[0093] Here, the final support substrate (290) is a substrate that supports the structure of a chip that has gone through each step of the manufacturing method (S200) of a chip-on-wafer for a micro LED display according to the second embodiment of the present invention. This final support substrate (290) can be prepared, similarly to the initial growth substrate (210), from a sapphire (α-phase Al2O3) substrate, glass with a controlled coefficient of thermal expansion (CTE), a Si substrate, etc.

[0094] In addition, in this embodiment, the bonding layer (280) is made of SiO2, SiN so that the generated light can be transmitted. x , SiCN, AlN, Al2O3, SOG (spin on glass, liquid SiO2), HSQ (hydrogen silsesquioxane), etc. may be included.

[0095] Meanwhile, the bonding step (S230) may form a sacrificial separation layer (S) on the final support substrate (290), and then bond the ohmic contact electrode (230) to the sacrificial separation layer (S). This sacrificial separation layer (S) is a layer that is sacrificed and separated when the final support substrate (290) is removed, and a material according to the laser lift off (LLO) process may be used. Meanwhile, this sacrificial separation layer (S) may be located on the upper or lower side of the bonding layer (280) depending on the purpose, and if the bonding layer (280) performs the function of the sacrificial separation layer (S), the sacrificial separation layer (S) may be omitted.

[0096] The exposure step (S240) is a step of removing the initial growth substrate (210) to expose one side of the semiconductor layer (220).

[0097] The etching step (S250) is a step of etching one surface of the exposed semiconductor layer (220) to reduce the thickness of the semiconductor layer (220).

[0098] Here, the undescribed contents of the exposure step (S240) and the etching step (S250) are the same as those of the manufacturing method (S100) of a chip-on-wafer for a micro LED display according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0099] The forming step (S260) is a step of forming a reflective layer (270) or a transparent layer (282) on one surface of the etched semiconductor layer (220). Here, the reflective layer (270) may be formed of Ag, Al, Au, Pd, Pt, Ni, Mo, Cu, Cr, Ti, TiW, ITO, IZO, ZnO, TiN, a distributed Bragg reflector (DBR), an omni-directional reflector (ODR), or a combination thereof, and the transparent layer (282) is formed of a material having transparent conductivity so that light from below can be transmitted upward. In this case, the material of the transparent layer (282) may include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, or IGZO.

[0100] Meanwhile, as illustrated in FIG. 7, the chip-on-wafer for a micro LED display according to the second embodiment of the present invention may have various structures.

[0101] First, as shown in (b) and (d) of FIG. 7, in the etching step (S250) of the present invention, a surface roughness pattern can be formed on one surface of the etched semiconductor layer (220).

[0102] In addition, as illustrated in (a) and (b) of FIG. 7, in the forming step (S260) of the present invention, a reflective layer (270) that reflects light generated on one surface of the etched semiconductor layer (220) can be formed. At this time, the reflective layer (270) may be in ohmic contact with the semiconductor layer (220) or may not be in ohmic contact with the semiconductor layer (220).

[0103] In addition, as illustrated in (c) and (d) of FIG. 7, in the formation step (S260) of the present invention, a transmission layer (282) that transmits light generated on one surface of the etched semiconductor layer (220) can be formed. In this case, in the electrode formation step (S220), a reflection layer (270) can be additionally formed on the ohmic contact electrode (230). Meanwhile, the transmission layer (282) may or may not be in ohmic contact with the semiconductor layer (220).

[0104]

[0105] Although all components constituting the embodiments of the present invention have been described as being combined or operating in combination as one, the present invention is not necessarily limited to such embodiments. That is, within the scope of the present invention, all of the components may be selectively combined and operated in one or more combinations.

[0106] Furthermore, terms such as "include," "comprise," or "have" described above, unless specifically stated otherwise, imply that the corresponding component may be present, and therefore should be interpreted to include other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in dictionaries, should be interpreted to be consistent with the contextual meaning of the relevant technology, and shall not be interpreted in an ideal or overly formal sense, unless explicitly defined in the present invention.

[0107] The above description is merely an example of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present invention.

[0108] Accordingly, the embodiments disclosed in the present invention are intended to illustrate, rather than limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical concepts within the scope equivalent thereto should be construed as being included within the scope of the present invention.

Claims

1. A method for manufacturing a chip-on-wafer for a micro LED display, A growth stage in which a semiconductor layer is grown epitaxially on an initial growth substrate; An electrode forming step for forming an ohmic contact electrode on the semiconductor layer; A bonding step of bonding the above-mentioned ohmic contact electrode to an intermediate temporary substrate through an adhesive layer; An exposure step of removing the first growth substrate to expose one side of the semiconductor layer; An etching step for reducing the thickness of the semiconductor layer by etching one surface of the exposed semiconductor layer; A bonding step of bonding one surface of the etched semiconductor layer to a final support substrate; and A method for manufacturing a chip-on-wafer for a micro LED display, comprising a removing step of removing the intermediate temporary substrate and the adhesive layer.

2. In claim 1, The above growth stages are, On the first growth substrate, the third semiconductor region, the second semiconductor region, the active region, and the first semiconductor region are sequentially epitaxially grown. The above etching step is, Etching the exposed third semiconductor region to reduce the thickness of the semiconductor layer, The third semiconductor region is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized in that the chip-on-wafer is an un-doped semiconductor region.

3. In claim 2, The above etching step is, Etching the second semiconductor region to reduce the thickness of the semiconductor layer, The above second semiconductor region is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized by having an n-type semiconductor region.

4. A method for manufacturing a chip-on-wafer for a micro LED display, A growth stage in which a semiconductor layer is grown epitaxially on an initial growth substrate; An electrode forming step for forming an ohmic contact electrode on the semiconductor layer; A bonding step for bonding the above ohmic contact electrode to a final support substrate; An exposure step of removing the first growth substrate to expose one side of the semiconductor layer; and A method for manufacturing a chip-on-wafer for a micro LED display, comprising an etching step of etching one surface of the exposed semiconductor layer to reduce the thickness of the semiconductor layer.

5. In claim 4, The above growth stages are, On the first growth substrate, the third semiconductor region, the second semiconductor region, the active region, and the first semiconductor region are sequentially epitaxially grown. The above etching step is, Etching the exposed third semiconductor region to reduce the thickness of the semiconductor layer, The third semiconductor region is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized in that the chip-on-wafer is an un-doped semiconductor region.

6. In claim 5, The above etching step is, Etching the second semiconductor region to reduce the thickness of the semiconductor layer, The above second semiconductor region is, A method for manufacturing a chip-on-wafer for a micro LED display, characterized by having an n-type semiconductor region.

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