Data interpolation digital-to-analog converter having automatic correction function

Abstract

Disclosed is a data interpolation digital-to-analog converter having an automatic correction function. As an example, disclosed is a data interpolation digital-to-analog converter comprising: a delay time correction control unit that applies a control signal for frequency correction so that at least one of a plurality of clock signals that have passed through a delay line is close to a target delay time; and a delay time correction operation unit that is connected to the delay time correction control unit and performs frequency correction in response to the control signal. The delay time correction operation unit has an automatic correction function for correcting the delay time of the clock signal through a plurality of modes in response to the control signal of the delay time correction control unit.

Description

Data interpolation digital-to-analog converter with automatic compensation function

[0001] The present invention relates to a data interpolation digital-to-analog converter having an automatic compensation function.

[0002]

[0003] To implement a bioimpedance measurement system, a sine wave is required, and a digital-to-analog converter (DAC) can be used to generate this sine wave. The DAC is one of the most power-consuming components in a bioimpedance measurement system.

[0004] Meanwhile, achieving high measurement accuracy requires a highly linear sine wave, and generating this requires a digital-to-analog converter (DAC) capable of high resolution and operating at an oversampling ratio (OSR). Implementing this with a conventional DAC results in high power consumption and a large area. Therefore, a data interpolation DAC can be used to minimize power consumption while improving linearity.

[0005]

[0006] The present invention provides a data interpolation digital-to-analog converter having an automatic compensation function.

[0007]

[0008] A data interpolation digital-to-analog converter having an automatic correction function according to the present invention comprises: a delay time correction control unit that applies a control signal for frequency correction to at least one clock signal selected from among a plurality of clock signals that have passed through a delay line so as to bring at least one selected signal closer to a target delay time; and a delay time correction operation unit that is connected to the delay time correction control unit and performs delay time correction according to the control signal, wherein the delay time correction operation unit can correct the delay time of the clock signal through a plurality of modes according to the control signal of the delay time correction control unit.

[0009] Here, the delay time compensation control unit can primarily control compensation in an OSC mode that compares the at least one selected clock signal with a first reference clock and controls the delay time of the delay line so that the at least one selected clock signal becomes closer to the first reference clock.

[0010] And the first reference clock may be a clock signal in which the frequency of at least one selected clock signal is changed by 1 / N (where N is a natural number).

[0011] Additionally, the delay time compensation control unit can compare at least one of the plurality of clock signals selected in the OSC mode with the first reference clock and count the rising edge to determine whether it is faster than the first reference clock.

[0012] Additionally, the delay time compensation control unit may be configured to terminate at least one of the plurality of clock signals selected in the OSC mode in a fast state compared to the first reference clock.

[0013] In addition, the delay time compensation operation unit can control the delay time with the applied bias current through the bias circuit in the OSC mode.

[0014] In addition, the delay time compensation control unit can control compensation in a TDC mode in which, after the OSC mode, at least two of a plurality of clock signals are selected, compared with a second reference clock, and the rising edges of each are compared to compensate for the two selected clock signals to approximate the second reference clock.

[0015] In addition, the delay time compensation control unit can select the last clock signal among the clock signals of one cycle and the first clock signal among the clock signals of the next cycle for the plurality of clock signals, and compare them with the second reference clock to adjust the delay time.

[0016] In addition, the delay time compensation control unit can terminate the TDC mode when the last clock signal among the clock signals of one cycle is compensated to be faster than the second reference clock and the first clock signal among the clock signals of the next cycle is compensated to be slower than the second reference clock.

[0017] In addition, the delay time compensation operation unit can control the delay time of the last clock signal among the clock signals of one cycle and the first clock signal among the clock signals of the next cycle through a flip-flop or latch in the TDC mode.

[0018]

[0019] The data interpolation digital-to-analog converter having an automatic compensation function according to the present invention performs delay time compensation of clock signals generated from delay lines by first performing rapid compensation up to a target frequency in a counting manner through the OSC mode, and second performing accurate compensation up to a target delay time through fine adjustment using the TDC mode, thereby enabling fast and accurate delay time compensation.

[0020]

[0021] FIG. 1 is a timing diagram of a clock signal used in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0022] FIG. 2 is a block diagram of a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0023] FIG. 3 is a block diagram of a delay line used in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0024] FIG. 4 is a block diagram for explaining the operation of the OSC used in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0025] FIG. 5 is a timing diagram for explaining the OSC operation used in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0026] FIG. 6 is a bias circuit used in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0027] FIG. 7 is a block diagram for explaining the TDC operation used in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0028] FIGS. 8A and 8B are timing diagrams of clock signals for explaining TDC operation used in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0029] FIG. 9 illustrates a simulation result of the OSC mode in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0030] Figures 10a and 10b illustrate simulation results of TDC mode in a data interpolation digital-to-analog converter according to an embodiment.

[0031]

[0032] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0033] The embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. The following embodiments may be modified in various ways, and the scope of the present invention is not limited to the embodiments described below. Rather, these embodiments are provided to more faithfully and completely explain the present disclosure and fully convey the spirit of the present invention to those skilled in the art.

[0034] In addition, in the drawings below, the thickness and size of each layer are exaggerated for convenience and clarity of explanation, and the same reference numerals in the drawings indicate the same elements. As used herein, the term "and / or" includes any one and all combinations of one or more of the listed items. In addition, the meaning of "connected" in this specification means not only when member A and member B are directly connected, but also when member C is interposed between member A and member B, so that member A and member B are indirectly connected.

[0035] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the present invention. As used herein, the singular forms "a," "an," and "the" include plural forms unless the context clearly dictates otherwise. Furthermore, when used herein, the words "comprise" and / or "comprising" specify the presence of stated features, numbers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, elements, components, and / or groups thereof.

[0036] Although the terms first, second, etc. are used herein to describe various elements, components, regions, layers, and / or portions, it is to be understood that these elements, components, regions, layers, and / or portions are not limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another. Accordingly, a first element, component, region, layer, or portion described below may refer to a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0037] Spatial terms such as "beneath," "below," "lower," "above," and "upper" are used to facilitate understanding of one element or feature depicted in the drawings relative to another element or feature. These spatial terms are intended to facilitate understanding of the present invention in various process states or usage states and are not intended to limit the present invention. For example, if an element or feature in a drawing is flipped, an element described as "beneath" or "below" becomes "above" or "above." Therefore, "beneath" is a concept encompassing "top" or "below."

[0038]

[0039] Below, the configuration of a data interpolation digital-to-analog converter according to an embodiment of the present invention will be described in more detail.

[0040] FIG. 1 is a timing diagram of a clock signal used in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0041] First, referring to FIG. 1, in the case of a clock signal used in a data interpolation digital-to-analog converter according to an embodiment of the present invention, a process of aligning the clocks through delay time calibration is required in a unit block that divides one clock into multiple clocks. In addition, when n clocks are used, clocks 0 to (n-1) can be used, and the rising edges of clock 0 and clock n must match.

[0042] For example, as shown in Fig. 1, when using 16 clocks, the first clock is CLK <0> CLK, the 16th clock in <15> can be used as one cycle, and the 17th clock is CLK <16> The rising edge of CLK <0> It must coincide with the rising edge of .

[0043] That is, the first clock CLK <0> The rising edges of all clocks to be used must be located within one cycle. It is also possible to use the falling edge instead of the rising edge as the reference.

[0044]

[0045] FIG. 2 is a block diagram of a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0046] Referring to FIG. 2, a data interpolation digital-to-analog converter according to an embodiment of the present invention may be configured to include a delay time compensation control unit, a delay time compensation operation unit, and an interpolation digital-to-analog converter.

[0047] The delay time compensation control unit applies a control signal for delay time compensation or operation (Calibration or Operation) to the delay time compensation operation unit, thereby performing delay time compensation in the delay time compensation operation unit, and operating the interpolation digital-to-analog converter after the compensation is completed. As described later, the delay time compensation operation unit first performs delay time compensation through frequency compensation in the OSC mode, and then can further compensate the delay time in detail through the TDC mode. The detailed operations of the delay time compensation control unit and the delay time compensation operation unit will be described in more detail below.

[0048]

[0049] FIG. 3 is a block diagram of a delay line used in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0050] The delay time compensation operation unit can be configured including the delay line block diagram of Fig. 3. First, when a clock signal (CLK) is applied to the delay time compensation operation unit, an output signal (e.g., the CLK signal shown in the figure) that has passed through each of the multiple arranged delay cells <0> Mainland CLK <16> ) can be used as a clock signal. At this time, each delay cell receives a bias current from an external circuit. If the bias current is large, the delay time is reduced, and if the bias current is small, the delay time is increased. Through these delay cells, one clock can be delayed and used as multiple clocks.

[0051]

[0052] Hereinafter, the OSC operation used in the data interpolation digital-to-analog converter according to an embodiment of the present invention will be specifically described.

[0053] Fig. 4 is a block diagram illustrating the operation of the OSC used in a data interpolation digital-to-analog converter according to an embodiment of the present invention. Fig. 5 is a timing diagram illustrating the operation of the OSC used in a data interpolation digital-to-analog converter according to an embodiment of the present invention. Fig. 6 is a bias circuit used in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0054] Referring to Fig. 4, the OSC (Oscillator) operation using the delay line block diagram of Fig. 3 is mainly illustrated. In the OSC operation, the CLK is generated through a ring oscillator. <0> and clock signals (CLK) that pass through each delay cell <1> Mainland CLK <16> ) can be printed.

[0055] Meanwhile, in OSC mode, for example, CLK <14> The inverted DOUT_CAL1 signal can be compared with Fclk / 2, which is half the frequency of the applied Fclk. However, for convenience, it is illustrated and described as 1 / 2 of Fclk, but it is also possible to set the standard as 1 / N (where N is a natural number). As shown in Fig. 5, for example, the count number of DOUT_CAL1 can be compared within the set count number of fixed Fclk / 2. In Fig. 5, since DOUT_CAL1 counted 7 times while Fclk / 2 was counted 4 times, CLK <14> The frequency of can be determined to be faster than the target frequency of Fclk / 2. Therefore, the delay time compensation operation unit can be controlled to provide more delay time.

[0056] Referring to FIG. 6, a control signal (CAL_COARSE, CAL_FINE) can be applied to a variable resistor in the bias circuit of the delay time compensation operation unit. Here, the control signal CAL_COARSE can mean a control signal for a large resistance unit, and CAL_FINE can mean a control signal for a small resistance unit. For example, the CAL_COARSE code can be designed to have a structure in which, when it increases, the resistance increases, thereby reducing the bias current, and when the current decreases, the delay time increases. In addition, the CAL_FINE code can have a structure in which, when it increases, the resistance decreases, thereby increasing the bias current, and when the current increases, the delay time decreases. In other words, CAL_COARSE and CAL_FINE can be designed to adjust the delay time when the code increases or decreases. Therefore, in a situation such as FIG. 5, the delay time compensation operation unit can make the delay time larger or smaller through the control signals (CAL_COARSE, CAL_FINE).

[0057]

[0058] Hereinafter, the TDC operation used in the data interpolation digital-to-analog converter according to an embodiment of the present invention will be specifically described.

[0059] Fig. 7 is a block diagram for explaining the TDC operation used in a data interpolation digital-to-analog converter according to an embodiment of the present invention. Figs. 8a and 8b are timing diagrams of clock signals for explaining the TDC operation used in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0060] Referring to Fig. 7, the delay time compensation operation unit may be composed of a plurality of flip-flops or latch circuits. In addition, the delay time compensation operation unit may be configured as a CLK <15> Wow CLK <16> , and this signal can be compared with the inverted signal of CAL_TDC_IN, which is respectively received from the delay time compensation control unit.

[0061] Also, as shown in Fig. 8a, when compared with the rising edge of the inversion signal of CAL_TDC_IN, CLK <15> Wow CLK <16> If all the rising edges of the CLK are fast, the delay time compensation operation unit can operate with a longer delay time (make-slow). As a result, as shown in Fig. 8a, the CLK <15> has a faster rising edge than the rising edge of the inverted signal of CAL_TDC_IN, and CLK <16> can be compensated to have a slower rising edge compared to the rising edge of the inverted signal of CAL_TDC_IN.

[0062]

[0063] Meanwhile, as shown in Fig. 8b, in contrast, when compared with the rising edge of the inversion signal of CAL_TDC_IN, CLK <15> Wow CLK <16> If all the rising edges of the CLK are slow, the delay time compensation operation unit can operate with a shorter delay time (make-fast). As a result, as shown in Fig. 8b, the CLK <15> has a faster rising edge than the rising edge of the inverted signal of CAL_TDC_IN, and CLK <16> can be compensated to have a rising edge that is faster or slower than the rising edge of the inverted signal of CAL_TDC_IN.

[0064] To elaborate, the Make slow operation in Fig. 8a is CLK <15> Wow CLK <16> All of these are faster than the rising edge of the CAL_TDC_IN inverting signal CLK <16> The moment when the rising edge of the CAL_TDC_IN inversion signal becomes slower than the rising edge of the CAL_TDC_IN inversion signal may indicate that the compensation is complete. On the other hand, the Make fast operation is performed by CLK <15> Wow CLK <16> All of these are slower than the rising edge of the CAL_TDC_IN inverted signal CLK <16> The moment it becomes faster than this CAL_TDC_IN inversion signal may be when the calibration is complete.

[0065]

[0066] However, since the TDC mode is adjusted slightly faster than the target frequency through the OSC mode that is performed first in the data interpolation digital-to-analog converter according to the embodiment of the present invention, the TDC mode can mostly operate with a longer delay time (make-slow).

[0067]

[0068] Below, the simulation results of each mode in the data interpolation digital-to-analog converter according to an embodiment of the present invention will be described in more detail.

[0069] FIG. 9 illustrates a simulation result of the OSC mode in a data interpolation digital-to-analog converter according to an embodiment of the present invention.

[0070] As shown in Fig. 9, in OSC mode, the delay time compensation operation unit can perform an operation to increase the code to provide a large delay time when the frequency is large, and to decrease the code to provide a small delay time when the frequency is small.

[0071] At this time, in OSC mode, frequency correction can be performed slightly faster than the target frequency (2MHz), and when frequency correction is completed, a completion signal (CAL_COARSE_DONE) signal is output, so that OSC mode can be terminated.

[0072]

[0073] Figures 10a and 10b illustrate simulation results of TDC mode in a data interpolation digital-to-analog converter according to an embodiment.

[0074] Referring to Figure 10a, the inversion of CAL_TDC_IN is blue, CLK <16> Silver red, CLK <15> is shown in green. In Fig. 10a, compared to the rising edge of the inversion of CAL_TDC_IN, CLK <15> Wow CLK <16> You can see that everything happens faster.

[0075] Meanwhile, referring to Fig. 10 b where TDC mode is in progress, CLK <15> The rising edge of CAL_TDC_IN, the rising edge of the inversion of CLK <16> You can see that the order has changed with the rising edge of CAL_TDC_IN, and also, the rising edge of the inversion of CAL_TDC_IN, CLK <16> It can be seen that the time difference of the rising edge of the CLK is reduced. That is, through the make-slow operation as explained above, through the TDC mode. <15> Wow CLK <16> This enables precise frequency delay time compensation.

[0076]

[0077] The above description is only one embodiment for implementing the data interpolation digital-to-analog converter according to the present invention, and the present invention is not limited to the above embodiment, and as claimed in the following claims, it will be understood that the technical spirit of the present invention exists to the extent that various modifications can be implemented by anyone having ordinary skill in the art to which the present invention pertains without departing from the gist of the present invention.

Claims

1. In a data interpolation digital-to-analog converter with an automatic compensation function, A delay time compensation control unit that applies a control signal for frequency compensation to at least one clock signal selected from among a plurality of clock signals passing through a delay line to make at least one of the selected clock signals closer to a target delay time; and Includes a delay time compensation operation unit that is connected to the above delay time compensation control unit and performs frequency compensation according to a control signal, The above delay time compensation operation unit is a data interpolation digital-to-analog converter that compensates for the delay time of a clock signal through a plurality of modes according to a control signal of the above delay time compensation control unit.

2. In paragraph 1, A data interpolation digital-to-analog converter in which the above delay time compensation control unit primarily controls compensation in an OSC mode that compares the at least one selected clock signal with a first reference clock and controls the delay time of the delay line so that the clock signal of the at least one selected clock signal becomes closer to the first reference clock.

3. In paragraph 2, A data interpolation digital-to-analog converter in which the first reference clock is a clock signal whose frequency of at least one selected clock signal is changed by 1 / N (where N is a natural number).

4. In paragraph 2, A data interpolation digital-to-analog converter wherein the delay time compensation control unit compares at least one of the plurality of clock signals selected in the OSC mode with the first reference clock, counts edges, and determines whether the signal is faster than the first reference clock.

5. In paragraph 2, The above delay time compensation control unit is a data interpolation digital-to-analog converter in which at least one of the plurality of clock signals selected in the OSC mode is terminated in a fast state compared to the first reference clock.

6. In paragraph 2, The above delay time compensation operation unit is a data interpolation digital-to-analog converter that controls the delay time with the applied bias current through the bias circuit in the OSC mode.

7. In paragraph 2, The above delay time compensation control unit is a data interpolation digital-to-analog converter that controls compensation in a TDC mode, which selects at least two of a plurality of clock signals after the OSC mode, compares them with a second reference clock, and compares the rising edges of each of them to compensate the two selected clock signals to approximate the second reference clock.

8. In paragraph 7, The above delay time compensation control unit is a data interpolation digital-to-analog converter that selects the last clock signal among the clock signals of one cycle and the first clock signal among the clock signals of the next cycle for the plurality of clock signals, and compares them with the second reference clock to adjust the delay time.

9. In paragraph 8, A data interpolation digital-to-analog converter that terminates the TDC mode when the delay time compensation control unit compensates that the last clock signal among the clock signals of the one cycle is faster than the second reference clock and the first clock signal among the clock signals of the next cycle is slower than the second reference clock.

10. In paragraph 8, The above delay time compensation operation unit is a data interpolation digital-to-analog converter that controls the delay time of the last clock signal among the clock signals of one cycle and the first clock signal among the clock signals of the next cycle through a flip-flop or a latch in the TDC mode.

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