Microled array with active control

Abstract

A microarray includes: a) a plurality of individually controllable microLED elements; b) an integrated surface, and c) a CMOS driver chip. Each microLED element is paired with a corresponding activation circuit on the CMOS driver chip. The activation circuit is configured to control activation of the microLED elements. The microarray may also include a plurality of photodetector elements, where each photodetector element is paired with a corresponding microLED and its corresponding activation circuit.

Description

MICROLED ARRAY WITH ACTIVE CONTROLBACKGROUND

[0001] Complex custom polymers can be synthesized using sequential deprotection and bonding cycles. In this process, selective localized illumination of a microLED within an array enables a controllable photolabile-initiated chemical reaction. A polymer with a protective chemical group at the distal end of its polymer chain has its proximal end attached to the surface of a fluidic channel above a microLED array. The protective chemical group at the polymer’s distal end is deprotected during microLED illumination. Subsequent introduction of a reagent into the fluidic channel would bind to the deprotected polymer, but only at those microLED array locations which were previously illuminated and thus deprotected.

[0002] This cycle of selective deprotection through microLED illumination followed by reagent binding at deprotected locations is repeated, using a sequence of unique microLED array illumination patterns and reagents. Specific polymers can thus be synthesized at each microLED location in the array. However, the prior art circuitry commonly used to control microLED array illumination for commercial display applications is ill-suited to the characteristics of the photochemistry used in polymer synthesis.SUMMARYA microarray includes: a) a plurality of individually controllable microLED elements; b) an integrated surface, and c) a CMOS driver chip. Each microLED element is paired with a corresponding activation circuit on the CMOS driver chip. Theactivation circuit is configured to control activation of the microLED elements. The microarray may also include a plurality of photodetector elements, where each photodetector element is paired with a corresponding microLED and its corresponding activation circuit. Each photodetector element may also be paired with the corresponding activation circuit on the CMOS driver chip.BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A illustrates a block diagram of an example embodiment of a microLED array 101 and a memory storage array 102 in a CMOS driver chip, as described in the disclosure.

[0004] Figure 1 B illustrates a cross-section of an example embodiment of a microLED array bonded to a silicon driver chip, as described in the disclosure.

[0005] Figure 1C illustrates a cross-section of an example embodiment of a photodetector structure integrated with the microLED array of Figure 1 B, as described in the disclosure.

[0006] Figure 1 D illustrates a cross-section of an example embodiment of a photodetector structure integrated with the microLED array bonded to a silicon driver chip of Figure 1 B, as described in the disclosure.

[0007] Figure 2 illustrates one example embodiment of a bitcell in a CMOS driver chip connected to an individual microLED, as described in the disclosure.

[0008] Figure 3 illustrates an example embodiment of a timing waveform diagram for a polymer synthesis experiment, as described in the disclosure.

[0009] Figure 4A illustrates example embodiments of a CMOS logic gate driver for a microLED, as described in the disclosure.

[0010] Figure 4B illustrates an example embodiment of an intersection of a current- versus-voltage curve for a microLED and a load line of a CMOS drive circuit, as described in the disclosure.

[0011] Figure 5 illustrates an example embodiment of a CMOS array write operation to update a microLED array illumination pattern, during the chemical binding phase of a polymer synthesis cycle in a polymer synthesis experiment, as described in the disclosure.

[0012] Figure 6A illustrates an example embodiment of an architecture for permanently disabling a CMOS memory array bank, as described in the disclosure.

[0013] Figure 6B illustrates an example embodiment of an architecture for temporarily disabling a CMOS memory storage array bank, as described in the disclosure.

[0014] Figure 7 illustrates example embodiment of a circuitry connected to differential bitlines in a CMOS memory storage array to write a new illumination pattern value at a selected address, as described in the disclosure.

[0015] Figure 8 illustrates a block diagram of an example embodiment of a circuity introducing redundant fabricated elements incorporated into a microelectronic array architecture, as described in the disclosure.

[0016] Figure 9 depicts an example embodiment of a memory array BIST architecture integrated on a CMOS die, as described in the disclosure.

[0017] Figure 10 illustrates an example embodiment of a modified test compression implementation appropriate for a memory storage array with a CMOS driver, as described in the disclosure.

[0018] Figure 11 illustrates an example embodiment of a material with a fluorophore applied directly to the top of a microLED array surface to facilitate testing of the microarray, as described in the disclosure.

[0019] Figure 12 illustrates an example embodiment of the excitation and local fluorophore emission measurement timing when measuring fluorophore emission, as described in the disclosure.

[0020] Figure 13 illustrates one example embodiment of a method for measuring a target binding affinity using a time-resolved fluorophore material, as described in the disclosure.

[0021] Figure 14 illustrates an example embodiment of clearing a microLED illumination patterns from CMOS memory after the polymer synthesis portion of the experiment is completed, enabling storage of a photoemission integration result, as described in the disclosure.

[0022] Figure 15 illustrates an example embodiment of writing a threshold result into a corresponding CMOS chip memory location corresponding to the microLED, as described in the disclosure.

[0023] Figure 16 illustrates an example embodiment of an expanded memory bitcell including photocurrent measurement circuitry, as described in the disclosure.

[0024] Figure 17 depicts an example embodiment of an architecture for readout of target binding affinity values from a memory storage array, as described in the disclosure.

[0025] Figure 18 illustrates one typical commercial implementation of a passive microLED array usings a separate electronic chip to provide the microLED drive current, as described in the disclosure.

[0026] Figure 19 illustrates one example embodiment of an architecture for an active matrix microLED array, as described in the disclosure.

[0027] Figure 20 illustrates one example embodiment of a microLED array utilizing anode vias, cathode vias, and photodetector structures arranged concentrically around a microLED, as described in the disclosure.

[0028] Figure 21 illustrates an example embodiment of a fluidic channel attached to the surface of a microLED array, as described in the disclosure.

[0029] Figure 22 illustrates an example embodiment of an application of die-to-die bonding using microbumps.

[0030] Figure 23 illustrates an example embodiment of a timing diagram for the stimulus signal transitions and subsequent photocurrent measurement duration for an embodiment that provides self-testing of a microLED and integrated photodetector.DETAILED DESCRIPTION

[0031] To facilitate an understanding of the principles and features of the disclosed technology, illustrative embodiments are explained below. The components described hereinafter as making up various elements of the disclosed technology are intended to be illustrative and not restrictive. Many suitable components that would perform the same or similar functions as components described herein are intended to be embraced within the scope of the disclosed electronic devices and methods. Such othercomponents not described herein may include, but are not limited to, for example, components developed after development of the disclosed technology.

[0032] It must also be noted that, as used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise.

[0033] By “comprising” or “containing” or “including” is meant that at least the named compound, element, particle, or method step is present in the composition or article or method, but does not exclude the presence of other compounds, materials, particles, method steps, even if the other such compounds, material, particles, method steps have the same function as what is named.

[0034] It is also to be understood that the mention of one or more method steps does not preclude the presence of additional method steps or intervening method steps between those steps expressly identified. Similarly, it is also to be understood that the mention of one or more components in a device or system does not preclude the presence of additional components or intervening components between those components expressly identified.

[0035] Conventional Passive MicroLED Arrays

[0036] As noted above, the prior art circuitry commonly used to control microLED array illumination for commercial display applications is ill-suited to the characteristics of the photochemistry used in polymer synthesis. The typical commercial implementation uses a separate electronic chip to provide the microLED drive current, as shown in Figure 18. Figure 18 depicts a common system architecture for a commercial microLEDarray application, denoted as a passive matrix circuit. This chip scans through individual rows in the microLED array at a frequency sufficiently high to provide the visual appearance of a static illumination (“visual acuity”). Figure 19 depicts an alternative commercial system architecture, where additional circuitry provides dynamic capacitive storage of the microLED array value for each frame, denoted as an active matrix. However, as will be discussed, these architectures leverage repetitive scanning through the microLED drivers connected to the array at high frequency to provide visual acuity. Because of their repetitive-scanning architecture, neither of these scan-based architectures will suffice for photolabile deprotection polymer synthesis, which requires extended constant intensity for an illuminated microLED, potentially spanning milliseconds to seconds.

[0037] The intensity of each microLED array pixel is commonly controlled by additional electronic circuitry that modulates either the amplitude of the voltage applied to each microLED or the current through each microLED for the duration of the microLED array line illumination.

[0038] A passive matrix microLED array utilizes a number of microLEDs arranged in an aligned set of microLED rows and columns. Current passive matrix microLED arrays and the corresponding driver electronics used for display applications are designed to rapidly scan through individual rows of the microLED array to illuminate one frame of the display image. The scan lines are individually activated in a high frequency sequence, such that the illuminated image is viewed as a single planar frame, rather than a line scan. Crosstalk from electrical coupling between adjacent rows due to the scanning sequence results in variations in microLED intensity.

[0039] The driver electronics for a passive matrix microLED provides current to the active pixels when the scanned row is active. There is no microLED illumination data storage associated with the driver electronics for a passive matrix array, necessitating higher microLED intensity during the active row scan duration and a faster scan frequency through all rows, to provide a suitable visual image without display flicker for each frame.

[0040] The row activation scan sequence completes one or more iterations through the entire microLED array each frame. A higher number of row sequence iterations through the microLED array reduces flicker in the image. The typical frame rates for visual display applications are 30 frames per second (fps), 60 fps, or 120 fps. These frame rates are sufficient to present the human eye with a planar frame rather than a line scan.

[0041] One advantage of the passive matrix microLED array is the simplicity of the microLED drive current design. When the microLED array row is active, the corresponding image memory array row in the drive electronics is accessed, and values in the memory array define which microLEDs in the row receive drive current and are illuminated. Another advantage is the reduced number of microLED drivers and connections required between the electronics and the microLED array, equal to the number of microLEDs in the row (i.e. , the number of columns in the array). As a result of the reduced number of connections required, discrete electronics separate from the microLED array are commonly used, such as the ASIC illustrated in Figure 18.

[0042] However, these characteristics of the passive matrix microLED array are disadvantages when considering polymer synthesis applications. The microLEDillumination intensity uniformity during the entire deprotection phase of the polymer synthesis cycle is of paramount importance to ensure consistent and complete photolabile chemical reactions across the entire microLED surface. A row scan-based excitation sequence providing an average intensity for the duration of an image frame may be suitable for visual comprehension, but is unsuitable for deprotection of a photolabile polymer.

[0043] For polymer synthesis, all illuminated locations in the microLED array must be at the appropriate intensity level and duration to provide deprotection and removal of the deprotected ligand.

[0044] The reduced number of microLED drivers used with a passive matrix microLED array with row scan mode operation enables separate microLED array and drive electronics chip packages, with the number of driver connections equal to the number of microLED array columns. However, any product architecture using separate components does not scale well to a larger microLED array size.

[0045] In a traditional product - like an HDTV -- the individual microLEDs are bonded on a substrate, with connections out to external pins, where separate silicon driver chip(s) provide the current to the LEDs. Because there are many, many more LEDs in the monitor than available external pin connections, a scan-based method is used to keep the number of connections between the LEDs and the driver in check.

[0046] Each row of the microLED array in the monitor is repeatedly scanned by the silicon driver chip, at a rate sufficient to "fool" the eye into interpreting the illumination as constant for the entire visual frame. Thus, the scan driver, constant-current driver, and the timing circuitry (labeled ASIC in Figure 18) are all external to the microLED array.

[0047] Active MicroLED Arrays

[0048] In various embodiments, to achieve high throughput polymer synthesis using photolabile deprotection at each microLED, a uniform illumination intensity is provided for the entire duration of the deprotection phase. In other words, the microLED illumination requirements for visual perception are less stringent than for polymer synthesis.

[0049] As a result, in various embodiments, individual drive current connections are provided to each microLED in the array for the deprotection phase. In some such embodiments, each unique circuit providing the microLED drive current has a direct contact to the anode and cathode. The number of connections between the driver chip and the microLED array far exceeds the capability to use a discrete driver chip package, as with commercial display electronics. In certain embodiments, an integrated connection to each microLED from the drive circuitry is employed.

[0050] In this disclosure, various embodiments of a sequence of illumination patterns used to synthesize unique polymers at different microLED locations, combined with constant illumination during the deprotection phase, and an unconventional SRAM memory array on the CMOS chip are described.

[0051] In certain embodiments, a polymer synthesis application requires that all illuminated locations in the microLED array for a specific deprotection cycle in a specific synthesis experiment be active concurrently. In some such embodiments, scaling of the microLED array sizes to a large number of elements (e.g., one million) precludes the use of existing passive matrix designs with discrete components. In some suchembodiments, the polymer synthesis product architecture therefore requires directly integrated connectivity between each individual microLED and its corresponding driver.

[0052] One example architecture for an active matrix microLED array is depicted in Figure 19. In this implementation, two additional transistors are integrated into the microLED unit cell.

[0053] An active matrix display system integrates driver electronics circuitry with each individual microLED in the array. The driver electronics for an active matrix system includes transistors with each microLED to provide dynamic storage of the illumination value. When the active row is scanned, the pixel data value is written into the dynamic storage data bit for the array location. The dynamic stored value in the driver electronics for this location maintains the specific microLED illumination value after the scan row is no longer active, while the remaining rows in the microLED array are scanned in sequence.

[0054] Each microLED in the active matrix design with the dynamic storage transistors remains powered after the scan row is no longer active. Whereas each microLED in the passive matrix array design is solely powered by the drive electronics while the scan row is active, additional connections provided with the active matrix design enable illumination current to flow through a microLED when the scan row is no longer active, based on the value in the dynamic storage with each microLED.

[0055] The dynamic stored pixel illumination value for each microLED in a row is refreshed when the row is once again the active scanned row. The valid duration of the dynamic stored value must be longer than the time required to sequence through all the rows. For example, the drive electronics for an active matrix design with 192 rows inthe array with 256 microLEDs in a row may achieve 16 frames per second, where the row scan rate is 50MHz. The scan driver electronics sequences through all rows at a rate sufficient to refresh the dynamically stored illumination data value hundreds of times per frame.

[0056] MicroLEDs in an active matrix design may therefore emit light while the scan rows are being written, reducing the magnitude of the required drive current when compared to the limited duration of illumination in a passive matrix system to achieve the same overall average intensity for the image frame.

[0057] Adding to the complexity of the commercial microLED drive electronics is the requirement to support multiple intensity levels for every pixel in each frame. A specific microLED in the frame may need to support 16 or 64 different intensity levels. While a passive microLED array row is active, additional electronic circuitry is required to modulate the microLED intensity, corresponding to the data intensity value for that pixel in the image for the frame via current modulation or voltage modulation.

[0058] Like the passive LED matrix design, the active matrix relies upon frequent refresh of the illumination value. Although suitable for visual display products, the illumination intensity required for deprotection of a polymer attached above a microLED must be uniform throughout this phase of the synthesis cycle. The active matrix architecture provides continuous power to each LED and integrates additional storage circuitry with each LED, which are also characteristics of the architecture required for polymer synthesis applications.

[0059] Additionally, there is no requirement in polymer deprotection for modulating the intensity level of an illuminated microLED, unlike the shading features necessary ina visual display product. As a result, the polymer synthesis control architecture can be simplified to provide a single drive current measure.

[0060] The architecture of the microLED control circuitry described in this disclosure is uniquely optimized for polymer synthesis, in contrast to the existing passive and active LED matrix implementations.

[0061] The number of microLEDs in the commercial array and thus the number of potentially unique synthesized polymers is large, often larger than will be required for many polymer synthesis experiments. The throughput of the iterative polymer synthesis cycle could be improved and the power dissipation associated with the microLED array and driver electronics could be reduced if only a subset of the microLED array sites needs to be updated for deprotection illumination for a specific experiment. The capability to temporarily disable a subset of the microLED array sites and corresponding driver electronics for a specific experiment is a key feature of polymer synthesis system design.

[0062] Figure 2 depicts how each bitcell 107 in the CMOS driver chip connects to an individual microLED 108. The bitcell shown in Figure 2 is based on a six-transistor (6T- SRAM) CMOS circuit 109, where cross-coupled inverters offer circuit nodes with both polarities of the stored data.

[0063] Other bit storage circuit embodiments are possible, but could require more transistors to implement. A register file organization is often used for small array storage designs, due to the ease of manufacturing test. As the density of microLED arrays continues to scale with advanced fabrication technology, the corresponding datastorage density in the bonded CMOS driver chip should also be to scale. As a result, a six-transistor static memory storage cell is an exemplary embodiment.

[0064] Figure 2 also shows an additional CMOS logic circuit 110 whose output connects to a terminal of the corresponding microLED. For example, the logic driver circuit output could connect to the microLED anode, while the microLED cathode is connected to ground. This logic circuit 110 is directly integrated with the bitcell layout design. The microLED illumination pattern storage array design 102 integrates the transistor storage circuit 109 and the microLED driver circuit, within a physical dimension that matches the layout pitch of the microLED and photodetector element.

[0065] Figure 3 illustrates a timing waveform diagram 111 for a polymer synthesis experiment. An example experiment cycle includes an interval when a selected set of individual microLEDs is illuminated, followed by an interval when all microLEDs in the array are off. A fluidic channel is attached to the surface of the microLED array, as shown in Figure 21 . A photolabile probe is attached to the polymer being synthesized, which is bound to the surface of the microLED array. The deprotection phase illuminates the probe at selected microLED locations, based upon the pattern stored in the storage array 102. For example, a logical T value stored in a bitcell location corresponds to illuminating the microLED in the next deprotection phase, while a logical ‘0’ in a bitcell location results in the microLED being dark. During the subsequent chemical binding phase, all microLEDs are off, and a chemical solution containing a concentration of a selected monomer can be introduced into the fluidic channel. The monomer can then bond to the specific deprotected probes.

[0066] The microLED array illumination pattern for the next deprotection event is updated during the preceding binding phase of the polymer synthesis cycle.

[0067] Figure 4A illustrates example embodiments of the CMOS logic gate driver 110 for each microLED. The active low Enable_bar input signal is connected to all CMOS memory storage array locations, and is active during the deprotection phase of the cycle. If the data stored in a specific CMOS memory array bitcell is a T, the logic circuit integrated with the bitcell will source current from the CMOS driver chip supply to the corresponding microLED. The deprotection phase ends when the Enable_bar signal returns to its inactive value. During the chemical binding phase, the logic circuit no longer sources current to the corresponding microLED.

[0068] The first circuit implementation 112 in Figure 4A can result in a high- impedance node during the deprotection phase when the stored CMOS memory bitcell data value is 'O’. Although no significant driver current path is provided to the microLED, high impedance nodes in a CMOS circuit for any significant duration can be susceptible to capacitive coupling transients. The second embodiment 113 in Figure 4A eliminates the floating node logic condition at the expense of an additional transistor in the CMOS drive circuit. In either embodiment, the additional transistors for the CMOS drive circuit are integrated with each memory storage bitcell.

[0069] Although the logic NOR drive circuit 113 in Figure 4A shows a traditional topology of complementary nFET and pFET transistors, the physical sizing for these transistors differs from a typical CMOS logic implementation, where the circuit output loading is strictly capacitive. To source the microLED current during the deprotection phase of the cycle, a low resistance pFET path from the CMOS supply to the drivercircuit output is provided. The pFET devices can be sized accordingly, much wider than the complementary nFET devices. An example of the intersection of the current-versus- voltage curve for the microLED and the load line of the CMOS drive circuit 114 is shown in Figure 4B.

[0070] The drive circuit can be designed to source the requisite microLED current to result in the target illumination energy. Depending on the illumination needs of the active process step, the drive circuit can be designed to provide different illumination intensities. For example, different illumination intensities may be employed for each of the deprotection, fluorescence measurement, and self-test features (further described below). Because the illumination of individual microLEDs as described in this disclosure is strictly binary (on / off) based on the value stored in the bitcell, the illumination intensity is necessarily determined elsewhere in the CMOS chip. In one example embodiment, the CMOS supply voltage may be modulated based on the desired illumination intensity. In another example embodiment, the CMOS supply current to the illumination circuits may be modulated based on the desired illumination intensity. Both example embodiments may incorporate additional circuitry to balance the current delivered to each individual microLED.

[0071] For example, if the nominal supply voltage applied to the CMOS driver chip is 3.6V, when the chip is set to the self-test mode, a lower supply voltage (e.g., 3.4V, -5%) could be applied to identify “weak” bits in the combination of the array bitcell, the current driver, the microLED, and the photocurrent detection circuitry. These weak bits could be subsequently excluded from the polymer synthesis experiment. Alternatively, timing adjustments for the CMOS driver chip could be made to extend the duration of thedeprotection phase of the synthesis cycle in Figure 3, to ensure a suitable (minimum) illumination dose is applied.

[0072] Additionally, microLED illumination intensity is strongly temperaturedependent. Temperature sensors could be readily integrated on the CMOS driver chip to adjust the supply voltage and / or the duration of the Enable_bar illumination signal accordingly.

[0073] Figure 5 illustrates the CMOS array write operation to update the microLED array illumination pattern, during the chemical binding phase of the polymer synthesis cycle. The Enable_bar signal is inactive during this phase, so that all CMOS memory storage array values can be updated while all CMOS drive circuit outputs are at a logic ‘0’ and all microLEDs are dark.

[0074] The address sequence 115 illustrated in Figure 5 indicates that all memory row addresses in the array 0 to (n-1 ) will be written, and that the full array illumination pattern will be updated in preparation for the next deprotection cycle.

[0075] Figures 6A and 6B illustrate an example architectural organization of the microLED array and the corresponding CMOS memory storage array. A set of banks of each array 116 is shown in Figures 6A and 6B. For the case of a synthetic biology experiment where only a subset of the microLED array locations needs to be illuminated, the other bank(s) would be inactive.

[0076] In both Figures 6A and 6B, a sleepFET topology 117 is shown, where a set of gating pFET devices are in series between the CMOS memory storage array bank and the power supply connection. In this manner, when the sleepFET input is a logic T, the entire CMOS array bank is removed from the power supply, saving the static leakagecurrent and static power dissipation in the array. The corresponding microLED bank will likewise be nonilluminated.

[0077] Two example embodiments of a power management sleep state can be commonly employed. As shown in Figures 6A and 6B, a series pFET sleep gate disconnects the supply from the CMOS memory array bank. Alternatively, a series nFET sleep gate may be used, to disconnect the CMOS memory array bank from ground. It is hypothesized that the microLEDs in the microLED array can share a common ground connection to multiple cathodes, and the ground distribution throughout the CMOS driver chip can be robustly designed to support the total current from the possible patterns of illuminated microLEDs during the deprotection cycle. As a result, a pFET sleep gate 117 is shown in Figures 6A and 6B as an exemplary embodiment.

[0078] Figure 6A depicts the architecture support for permanently disabling a CMOS memory array bank. The logic gates 118 offer an input signal that fully disable a memory bank from an active write operation. When used in combination with the pFET sleep gate 117, the memory bank is disconnected to save power dissipation. A variety of embodiments could be used to implement the generation of the additional input signals to logic gates 118 that control the active memory banks, including writing the disable signals into an embedded non-volatile memory array integrated on the CMOS driver die or programming embedded fuses integrated on the CMOS driver die. Permanently disabling banks of the CMOS memory storage array also enables a population of manufactured parts to be released with reduced capacity, as failing bitcell locations in the CMOS memory storage array and / or individual emitters in the microLED array would be permanently inactive.

[0079] Figure 6B depicts an example embodiment where the CMOS memory storage array banks are disabled on a temporary basis, again to save static power dissipation.In this embodiment, the sleepFET control signals 119 are switched externally, corresponding to the microLED array illumination pattern for the scope of the current experiment.

[0080] In a typical microelectronics application supporting power management operation, it is useful to retain some data storage values during the disconnected sleep state. Note that in the microLED array illumination application, the next illumination pattern is fully written to the enabled CMOS memory storage array during the binding phase of the cycle. As a result, no retention storage support is required for the CMOS memory storage array in support of the array bank sleep state.

[0081] Another characteristic of the microLED array application is that the illumination pattern written into the CMOS memory storage array is never functionally read for evaluation. The stored value in each CMOS memory array location is connected to the logic gate 110 which sources the microLED drive current.

[0082] Figure 7 shows an implementation of the circuitry 120 connected to the differential bitlines in the CMOS memory storage array to write the new illumination pattern value at the selected address. Unlike a conventional microelectronics memory array, no read sense amplifier is required for the microLED array illumination application. Additionally, no bitline pre-charge operation is required, and no read cycle timing sequence is needed to enable a sense amplifier after a differential read bitline voltage is established. For the microLED array illumination application, the peripheral support circuitry around the CMOS bitcells is greatly simplified.

[0083] The addition of a photocurrent integration circuit to each microLED bitcell location extends the capability of the memory array, and will involve the addition of array read capability, as will be discussed.

[0084] Figure 1A presents a block diagram of a microLED array 101 and a memory storage array 102 in a CMOS driver chip. There is a one-to-one correspondence between each microLED in the array and each bitcell location in the CMOS driver chip memory storage array.

[0085] Figure 1 B illustrates a cross-section of a microLED array 103 bonded to a silicon driver chip 104. A through-substrate via 105 is provided to connect the individual microLED anode terminal to a corresponding electrical pad on the CMOS driver chip, while the microLED cathode 106 connects directly to a pad on the CMOS driver chip.

[0086] The semiconductor material used for microLED fabrication is typically a (complex stoichiometric) set of layers comprised of Gallium-Nitride, with small impurity concentrations of other elements (e.g., Indium-Gallium-Nitride, Aluminum-Gallium- Nitride, etc.) in a layer stack-up. The circuitry that drives the microLED array is based on traditional silicon fabrication technology, to address performance and (especially) cost targets. GaN is commonly deposited on a sapphire substrate, as GaN and sapphire are a closer crystallographic match.

[0087] However, in another example embodiment, the GaN layers are deposited on a blank silicon wafer substrate. Depositing GaN-on-Si enables the wealth of equipment and expertise with larger diameter wafers -- e.g., 4", 6", or 8" - to be used and to drive down the fabrication cost.

[0088] Technologies exist for bonding two wafers together. These methods have been widely adopted in the computer electronics industry. The common acronym is "W2W", for wafer-to-wafer bonding.

[0089] One example method is to use "through substrate vias" (TSV) in the top wafer from the circuitry to the wafer backside, with "microbumps" between the two wafer surfaces to provide the electrical connection. Microbumps are known in the art and are used for die-to-die bonding in applications like high-bandwidth memory chips, as illustrated in Figure 22.

[0090] In another example embodiment, the two wafers are directly bonded, without an intervening solder bump. This technique can facilitate a more aggressive bond pitch, allowing for many more connections between the two dies. In one example embodiment, this employs a "hybrid" process, where the dielectric and conductive surfaces at the \N2\N interface are first aligned and then suitably bonded, both for electrical connectivity and mechanical strength (to avoid delamination during subsequent processing). A "thermo-compression" technique is commonly used for the bonding, combining temperature and pressure to facilitate the surface adhesion and metal connectivity.

[0091] This example embodiment can facilitate a denser bonding pitch and integration of as many microLEDs as possible.

[0092] During fabrication, several signals must be routed from each microLED location to the corresponding CMOS circuitry:

[0093] (1) from the microLED anode (to CMOS driver in the CMOS chip)

[0094] (2) from the microLED cathode (to CMOS driver)

[0095] (3) from the integrated photodiode anode (to the photocurrent integrating circuit next to the SRAM bitcell in the CMOS chip — described in detail below)

[0096] (4) from the integrated photodiode cathode (to the photocurrent integrating circuit next to the SRAM bitcell)

[0097] In one example embodiment, the attenuation of "stray light" between microLED locations will be optimized if these connections are fully circumferential around the body of the microLED, as shown in Figure 20. In another example embodiment, these connections do not fully encompass the microLED, simplifying the routing pattern from the microLED element to the corresponding CMOS connections in the W2W bonding.

[0098] Integration of the microarray into a device for synthesizing polymers is illustrated in Figure 21 , showing packaged chip design, with fluidic channel for reagent solutions.

[0099] Figure 21 illustrates a cross-section of the packaged chip design (i.e. , the composite GaN plus silicon die), after singulation from the bonded wafer. The package illustrates a “flip-chip” configuration, where the connections from the chip to package substrate are made from the bottom of the composite die. The microLED and photodiode surface is at the top.

[0100] The encapsulation of the die is planar to the die surface. A fluidic channel consisting of 3D-printed plastic is attached to the top of the package by an adhesive. The channel has an input port and output port, with fittings to connect to tubing carrying the chemical reagents (and wash) fluids. These fluids flow across the exposed surface dielectric of the composite die and are contained on the top and side by the printedplastic channel, although other types of channel may be used. The composite die surface needs to be highly planar for optimum (laminar) fluid flow, minimizing turbulence. (A polishing step will be part of the GaN wafer process flow, after the top dielectric material is deposited.)

[0101] During polymer synthesis, one example microarray executes the following iterations of the synthesis cycle:

[0102] (1) loading an illumination pattern into the bitcell memory associated with each micro(LED;

[0103] (2) illuminating the appropriate microLEDs determined by the illumination pattern to deprotect the end of the existing polymer at each active microLED position; and

[0104] (3) introducing a reagent into the fluid channel to bind to the deprotected polymer at each active microLED site.

[0105] In one example embodiment of the microarray, an Enable_bar signal may be employed during polymer synthesis, as illustrated in Figure 4A. During the deprotection phase, the Enable_bar signal may have a value of ‘0,’ allowing the microLEDs to be active according to the current illumination pattern. During the polymer binding phase, the Enable_bar signal may have a value of ‘1 ,’ disabling all of the microLEDs while the nest polymer reagent is introduced and chemical binding occurs. During the polymer binding process, all photodetector circuitry (described in greater detail below) would be disabled by the following signals:

[0106] - lntegrator_reset: ON (‘1 ’)

[0107] - Bitcell_reset: OFF (‘0’)

[0108] - Enable ntegration: OFF (‘1’)

[0109] Active MicroLED Arrays With Photodetectors

[0110] After polymer synthesis, a target is introduced to the array of polymers attached across the microLED array surface. A fluorescent binder is attached to the target molecule. Illumination of the microLED array will provide local fluorescence at specific microLED locations where the target has bound. A photodiode integrated with each microLED in the array provides the capability to measure the magnitude of the fluorescence, and thus provide a quantitative measure of the target binding affinity.

[0111] Existing implementations of fluorescence measurement across an array of elements commonly use complex shifting of analog charge and multiplexing as input to analog-to-digital conversion circuitry, introducing additional sources of measurement error. This disclosure integrates a unique combination of fluorescence measurement and SRAM memory circuitry, to represent the target binding affinity value. The target binding affinity measurement is made after the polymer synthesis cycle is completed. This disclosure leverages the existing microLED illumination pattern memory array present in the CMOS driver chip as the storage for the affinity measurement result. The photocurrent generated during fluorescence excitation is integrated over a defined interval. The resulting voltage is compared to a threshold value, and the binary result of this comparison is stored in the corresponding memory storage bitcell location for the associated microLED. The conventional memory bitcell circuit is enhanced to incorporate the photocurrent integration circuitry and the threshold reference voltage input. The bitcell is written after the photocurrent integration interval is complete. Thisintegration interval is programmable, and multiple integration intervals may be enabled during the fluorescence measurement (further described below).

[0112] This disclosure describes the unique circuitry added to a traditional bitcell in support of storing the target affinity measurement value. This disclosure also includes the architecture for measuring and recording the photocurrent from the integrated photodiode, after excitation of the fluorophore attached to the target. Additional information regarding wafer-level techniques for fabricating the integrated photodetector can be found in PCT Patent Application PCT / US2023 / 072653, titled “MicroLED Array With Integrated Photodetectors,” and filed on August 22, 2023, which is incorporated herein by reference in its entirety.

[0113] In one example, fluorophore excitation could be provided by each microLED or from an external excitation source. Unlike the polymer synthesis cycle that precedes it, the fluorophore excitation is uniformly applied across the microLED array surface.The fluorophore excitation pulse will be controlled by timing circuitry integrated with the CMOS driver chip.

[0114] An example embodiment of the excitation and local fluorophore emission measurement timing is shown in Figure 12. The excitation pulse is typically very short in duration, with high light intensity. The duration interval t1 in Figure 12 is programmable by the timing circuitry. Timing interval t2 in Figure 12 depicts the duration between the end of the excitation pulse and the start of the photocurrent integration from the integrated photodiode receiving the fluorophore emission. Timing interval t3 in Figure 12 denotes the duration of the photocurrent integration. Figure 12 indicates that different fluorophore molecules to attach to the binding target areavailable, with various fluorescence response times. The time-resolved fluorescence materials have a much longer duration of emission, measured in hundreds of microseconds.

[0115] Figure 13 illustrates one example embodiment for target binding affinity measurement using a time-resolved fluorophore material. The long duration of the fluorescent emission enables potentially multiple photocurrent integration intervals to be measured. The notation in Figure 13 denotes the integration (I), measure (M), and reset (R) timing within each interval.

[0116] In some experiments, the entire fluorophore emission energy at a local photodetector is of interest, utilizing full integration of the photocurrent area under the emission curve. In other cases, the rate of local emission from the fluorophore is of interest at different points in the long-duration emission curve. The multiple measurement intervals will be a programmable setting within the timing circuitry. If both the full integration and rate-based integration of fluorophore response is required for a specific experiment, the excitation followed by emission sequence could be repeated with different integration duration settings. Multiple fluorophore excitations after target binding are feasible, within the same polymer synthesis and target binding experiment. For example, a strong target binding affinity will likely exceed the integration threshold over multiple interval samples. A weak binding target may drift off the corresponding polymer, and result in an integration signal result below the threshold.

[0117] The corresponding digital signals for this example embodiment would be:• External light source current drive ON for duration 't 1 ', then OFF microLED array illumination OFF: Enable_bar = T• lntegrator_reset: ON ('T) until time 't1 + t2', then OFF ('0') to start integration• Bitcell_reset: ON ('1 ') until time 't1 then OFF before 't1 + 't2' (resets the microLED array values)• Enable ntegration: OFF ('1') until 't1 + 't2', then ON ('0')

[0118] Figure 13 also depicts that the photocurrent measurement at the end of the integration interval will be compared to a programmable threshold value. The comparison of the photocurrent integration to the threshold will be represented as a binary value.

[0119] If only a single reading of photocurrent is required, the signal values above remain in effect for hundreds of microseconds. After the end of the fluorescence, the array values are read out.

[0120] If multiple readings of photocurrent are required, then there will be an intermediate cycle, beginning with the start of the "MR" phase in Figure 13:• Enablejntegration goes to OFF ('1')• Readout of the array values (i.e., which integrations exceeded the threshold)

[0121] After the readout is complete, the values are reset for the next integration ('I") phase:• Bitcell_reset: ON (T)• lntegrator_reset: ON (T)

[0122] After these short duration reset signal pulses, the next integration phase is initiated: lntegrator_reset: OFF ('0') to start integrationBitceljreset: OFF ('0')Enable ntegration: ON ('0')

[0123] This 'MR' + 'I' cycle can be repeated (over potentially hundreds of microseconds).

[0124] In another example embodiment, the array of microLEDs can be used to illuminate the synthesized polymers and bound targets with fluorophores. This example embodiment would employ a sequence similar to that described above, except the “External light source” signal is inactive, and the entire array of microLEDs is illuminated to serve as the fluorophore excitation source.

[0125] To enable this sequence, the only significant change is that Enable_bar to the array is active for duration ‘t1 ’. Conveniently, the Bitcell_reset signal sets the value to uniformly enable the microLED drive current at all locations. The Bitcell_reset signal turns off before time ‘t1 + 12’.

[0126] An alternative embodiment would be to convert the analog value of the integrated photocurrent to a digital word. A number of analog-to-digital converters would be integrated into the CMOS driver chip, and individual photocurrent integration values would be multiplexed as inputs to the A-to-D converters. Although a digital word may represent additional measurement granularity, the multiplexing of these values will introduce noise errors in the result, and will require significant time for shifting and settling of the A-to-D result. These issues will be exacerbated as the number of microLEDs and photodetectors in the array increases, as the additional CMOS driver chip area required for the A-to-D converters also increases.

[0127] To minimize the complexity and potential for errors, in certain embodiments, the integrated photocurrent compared to the threshold is captured as a single binaryvalue, for efficient storage and readout. As depicted in Figure 14, after the polymer synthesis portion of the experiment is completed, the storage array on the CMOS driver chip is no longer written with microLED illumination patterns. The same memory array on the CMOS driver chip can thus be used to store the binary photocurrent integration measurement data for each microLED and integrated photodiode location.

[0128] The threshold result will be written into the corresponding CMOS chip memory location corresponding to the microLED, as shown in Figure 15. Additional transistors will be incorporated into the bitcell architecture. The photocurrent integrator will include two additional input signals, which define the duration of the integration, as well as reset the integrator for the next measurement interval. The output of the integrator will connect to an additional write port to the bitcell.

[0129] Figure 16 depicts the expanded memory bitcell including the photocurrent measurement circuitry. (The write port to the bitcell associated with storing the microLED illumination pattern value during polymer synthesis is not shown, and will be inactive during the fluorescence measurement.) Transistors M3, M4, M5, and M6 represent the cross-coupled inverters storing the bit value.

[0130] The photodiode is represented on this schematic diagram as diode D1 , oriented in reverse bias.

[0131] Prior to the start of photocurrent integration, the voltage across capacitor C1 is discharged by transistor M10 with a reset input signal. The bitcell value is set to T at node D using the input to transistor M7, which drives the cross-coupled inverters from circuit node Dbar. The complementary side of the bitcell at node D is not externally driven, as transistor M2 is off. Transistor M7 will drive the bitcell to a known value.

[0132] The start of the photocurrent integration begins when the reset inputs to transistors M10 and M7 are no longer active, and transistor M8 is enabled. Incident light emitted by the fluorophore excitation strikes the photodiode, resulting in a photocurrent charging capacitor C1 to an increasing voltage.

[0133] The increasing input voltage to transistor M2 will approach the threshold value of the transistor. The current through transistor M2 is adjusted by the series resistance of transistor M1 . As current starts to flow through the series connection of transistors M2 and M1 , the resistance of transistor M1 will result in a voltage at the node between M2 and M1 , which will increase the required input voltage at transistor M2 to further turn on this transistor. As the photocurrent integration voltage across capacitor C1 increases, transistors M2 and M1 will eventually conduct sufficient current to discharge node D of the bitcell, and flip the stored value.

[0134] If the fluorescence emission is strong, indicative of strong target binding affinity to the synthesized polymer at the microLED location, the stored value will flip within the duration of the photocurrent integration. If the fluorescence emission is weak, indicative of poor target binding affinity, the bitcell value will not change within the integration duration. This final bitcell value at the end of the integration duration provides a binary result, directly stored in the memory array on the CMOS driver chip. The threshold level which defines the necessary photocurrent integration is established by the sizing of capacitor C1 , the sizing of the bitcell transistors M3 through M6, the sizing of transistors M1 and M2, and especially, the reference voltage applied to the input of transistor M1 .

[0135] The reference voltage input to transistor M1 provides a unique method to adjust the desired threshold for different experiments.

[0136] To the base six-transistor memory bitcell for writing microLED illumination pattern data, this architecture for storing target binding affinity data in the same array adds 5 additional transistors plus the photocurrent integrating capacitor. The reuse of the storage array for storing affinity data minimizes the additional chip area required.

[0137] The memory storage array architecture for polymer synthesis does not require reading the array values. Re-using the array to capture the target affinity binding results does require adding circuitry to read the stored data. However, unlike a conventional random-access memory where any array row may be read in any read cycle, this application requires a simple sequential readout of all stored values.

[0138] Whereas read access time is a key performance metric for a general-purpose memory array, the readout of the stored affinity values is not as time-critical. Whereas differential sensing of the bitcell D and Dbar values for a read access is commonly used, with timing-critical pre-charge, read access transistor enable, and sense amplifier clocking for high-performance, this application may employ a simpler single-ended connection from the bitcells in each column to provide the data output value (not shown in Figure 16). One embodiment would omit any sensing circuitry, if the single-ended bitline data drive transistor current provides sufficient read noise margin. Alternatively, a single-ended sense amplifier circuit with a bitline pre-charge timing phase could be incorporated at the end of the bitline, an embodiment well-known in the industry.Another alternative embodiment would be to add a dedicated read port with a separateread bitline and read wordline to each bitcell, with a pre-charge timing phase, using an eight-transistor static memory bitcell configuration well-known in the industry. .

[0139] Figure 17 depicts a simple architecture for readout of the target binding affinity values in the memory storage array. A row decoder sequences through all row addresses associated with each bank of the memory array. The additional memory bitcell port associated with photocurrent integration is disabled.

[0140] The bitcell output connected to the array column is connected to a multiplexor, which steers the array bank outputs for the selected row to the CMOS driver chip outputs, to be read by a computer system (not shown in Figure 17). Depending upon the width of the external interface to the computer system, the number of select inputs to the multiplexor could be larger than the number of array banks, sending all or a subset of the row values to external chip outputs. The multiplexor selects all the row values in all the array banks before the row sequencer increments to the next row.

[0141] As an example, assume a system with 256K microLEDs and integrated photodetectors on a single chip. The storage array could be divided into 4 banks of 64kbits each. The bank array size could be 256 rows by 256 columns. Assume the external interface to the computer system is 64 bits. The total read cycle from the binding affinity array would multiplex through 4 subsets of a 256 bit row to the 64 bit interface and through the 4 banks, while sequencing through the 256 rows in the array. This example read cycle would need to be completed in the duration denoted as MR in Figure 13, on the order of ~200 microseconds. This example requires an individual array read access cycle time of ~25 nanoseconds, which is easily achievable withmature microelectronic process nodes. (If faster MR duration performance is required, the interface width to the external system could be expanded and / or faster array read sensing circuitry could be added.)

[0142] Figure 1C expands upon Figure 1 B illustrating a photodetector structure 103A integrated with each microLED in the array. The semiconductor layers comprising the photodetector are deposited and patterned above each microLED 103. The electrical connections to the photodetector anode 103B and cathode 103C are provided by through-substrate vias to the corresponding pads on the CMOS driver chip. An optional anti-reflective coating over the surface of the microLED and photodiode array is also shown in Figure 1 C.

[0143] During analysis of the binding of a target to one or more synthesized polymers, the microarray executes the following iterations of the analysis cycle:

[0144] (1) introducing a target molecule that has a predefined fluorophore attached;

[0145] (2) exciting the fluorophore attached to the target;

[0146] (3) measuring the emissions of the fluorophore at a specific microLED location to determine the affinity of the target to the synthesized polymer;

[0147] (4) storing the affinity measurement;

[0148] (5) reading out the affinity measurement.

[0149] Active MicroLEDs Arrays With Error Self Detection

[0150] A commercial display utilizing a microLED array and driver electronics must satisfy extremely stringent manufacturing test acceptance criteria for acceptable visual quality. For example, an assembled display with more than approximately ten randomlylocated pixels which fail to meet illumination intensity measures is discarded, resulting in considerable additional manufacturing costs. This requirement applies to the successive testing of the fabricated microLED array, driver electronics, and final assembly.

[0151] For polymer synthesis applications, the adoption of the memory bank architecture for the CMOS driver chip and corresponding microLED array can enable improved manufacturing yields, as failing locations may be permanently disabled and reduced functionality parts released. For the cases where only a small number of failing locations are identified after production test, an alternative method would be to fabricate additional, redundant CMOS memory array and microLED array locations and permanently switch those locations into operation to replace the failing locations.

[0152] The incorporation of redundant fabricated elements is commonly used in microelectronic array architectures, as illustrated in Figure 8 for the case of inserting a spare row of elements 121. For the implementation of a combined CMOS driver chip and microLED array, the value in the redundancy repair register 122 in Figure 8 would reflect the requirement to bypass failing locations identified after production test in both the CMOS memory storage array and the microLED array.

[0153] The manufacturing test requirements for polymer synthesis are less stringent than those for visual displays, as failing locations in the microLED array and / or driver electronics are acceptable. These locations would be excluded from the polymer synthesis experiment definition, and would be disabled from illumination, which simply reduces the number of polymer synthesis sites available.

[0154] A fabricated microLED array may have failing illumination sites which are localized to a specific row or column of the array. A microLED array used for a visual display application is unable to effectively utilize spare microLED array rows or columns fabricated with the array to repair failing locations, due to the loss of visual quality associated with unilluminated black lines running through the image for the bypassed failing row or column.

[0155] Conversely, a microLED array used for a polymer synthesis application may readily employ a spare array row and / or column to supplant localized failing locations, so that the array does not need to be discarded.

[0156] A fabricated microLED array used for polymer synthesis with failing locations beyond the capability for repair with a spare array row or spare array column may still be employed for experiments, with a reduced number of available synthesis sites. The software controlling the sequencing of illumination patterns each deprotection cycle will bypass the known failing microLED array locations reported after manufacturing test. This configuration of employing a reduced experiment capacity microLED array improves manufacturing yield.

[0157] Current microLED array and driver electronics hardware is tested for image illumination intensity with separate test equipment, using a digitizing microscope and / or high-resolution imaging spectrophotometer.

[0158] The time to complete commercial microLED array testing is long, resulting in additional manufacturing cost. A method to improve test throughput over existing microLED array intensity measurement using external spectroscopy equipment would reduce cost.

[0159] The proposed architecture in this disclosure integrates a photodetector element with each microLED in the array. The combination of the electronic circuitry to illuminate an individual microLED and detect the corresponding photocurrent provides a self-test capability, both expediting the test time and eliminating the need for expensive external photometer test equipment.

[0160] Two self-test implementations are viable. If the photodetector is sensitive to the illumination wavelength of the microLED, the resulting photocurrent will be indicative of a pass / fail test for the combination of the microLED and photodetector. If the photodetector is not sensitive to the illumination wavelength of the microLED, introduction of a fluorescent solution on top of the fluidic channel surface of the polymer synthesis platform will provide uniform light energy to test all the photodetectors in the array.

[0161] Example embodiments to implement the redundancy signals after production test are to load the values into a writeable register as part of a system initialization sequence or, more commonly, to permanently store the redundancy values by programming e-fuses integrated into the CMOS driver chip. In this application e-fuses represent an array of very small fuses, which are electrically programmed during chip test to represent binary values, depending upon whether the fuse is intact or blown. These small e-fuses are used to permanently store information specific to an individual chip, identified during wafer-level test. Examples include: information about the fabrication lot, part number, and the insertion of redundant memory columns or rows to replace a failing set of on-chip memory locations, as described herein.

[0162] Production test of the combined CMOS driver chip and microLED implementation can be conducted into two steps. The CMOS driver chip memory storage array locations can be exercised and measured first, to identify failing parts after CMOS fabrication. The known good CMOS driver chip die can then be bonded to a microLED die and the full implementation tested.

[0163] Production test of a memory-intensive CMOS driver chip array design can utilize additional built-in self-test (BIST) sequencer logic functionality on the CMOS die, to internally exercise the array circuitry with specific pattern values and sequences to evaluate manufacturing fault mechanisms. A variety of array storage patterns and pattern transitions in successive array write cycles can be used during BIST, with a programmable sequence description written into the BIST controller, as part of the setup procedure prior to exercising the array in BIST mode. Figure 9 depicts a memory array BIST architecture 123 integrated on a CMOS die.

[0164] As the internally-generated BIST pattern write-then-read performance cycle for a typical CMOS memory array is significantly faster than the pattern application and response measure rate from external automated test equipment, the CMOS memory array implementation can integrate a logic compression register at the array outputs. This compression register provides a test signature reflecting the entire sequence of memory array outputs produced during the BIST program.

[0165] An embodiment of a modified test compression implementation appropriate for the memory storage array with CMOS driver is shown in Figure 10. The CMOS logic gate current driver integrated with each memory storage bitcell 113 can also be connected to a multiplexing circuit 124. The multiplexor output serves as an input to asignature register 125. The value stored in a row of the memory array during the BIST write-only sequence can be copied into the signature register 125 by establishing the multiplexor select input corresponding to the row position, and then clocking the register. A transition through the row address space with successive copies into the signature register 125 can provide a final signature for the memory array pattern written into the bank during the BIST cycle. The final signature may be scanned out from the signature register 125 for comparison to the expected test result for the pattern written into the bank.

[0166] This method is similar to the multi-input signature register (MISR) architecture commonly employed in microelectronics design for logic network built-in self-test (LBIST). This method adapts the implementation to provide values to the signature register 125 from sequencing through the memory array address space, with the CMOS driver circuit as the input source to the signature register.

[0167] The production test method after the microLED array and CMOS driver chip are bonded can necessitate a means to measure the microLED emission intensity after a test pattern has been written into the memory storage array. The emission intensity measurement technique can employ both a minimum threshold of illumination energy when the microLED is active, as well as a maximum illumination energy threshold for inactive locations to ensure that deprotection will not erroneously occur above nonilluminated elements.

[0168] One embodiment of product test of the bonded CMOS driver die and microLED array would be to position suitable spectroscopic instrumentation above the microLED array. This instrumentation would measure the intensity of each illuminatedmicroLED for the minimum threshold test, as well as the intensity of each nonilluminated microLED for the maximum threshold test.

[0169] As depicted in Figure 1 C, a unique embodiment would be to integrate a photodetector directly with each microLED element, with the photodetector terminals connected with through vias back to the CMOS driver die. In this embodiment, the photodetector response can be sensed by circuitry integrated into the CMOS driver die to detect minimum illumination current and maximum dark current from each microLED location during pattern test of the assembled product. This second method saves test time and equipment cost.

[0170] Figure 23 illustrates the timing sequence employed for this self-test feature using the integrated microLED and photodetector. In this case, a test pattern is written into the microLED storage array (prior to “time 0”). As explained above, the Bitcell_reset signal is not active during the writing of the test pattern, nor when the Enable_bar signal is active, from time 0 to time ‘t1.’ A solution containing a fluorophore is then introduced into the test cell. The microLEDs are then illuminated according to the test pattern during period t1 . After the microLEDs stop illuminating at the end of period t1 , the bitcell memory is reset. This is accomplished by toggling the Bitcell_reset signal ON then OFF during the period t2.

[0171] During the period t3 the fluorophore fluoresces in response to the microLED illumination. Accordingly, during period t3 this fluorescence is measured and integrated, and values are written to the bitcells if the integrated fluorescence measurement exceeds the threshold, as described above. As also described above, the threshold forthe self-test can be adjusted if needed and does not need to be the same as the threshold for any particular polymer target binding affinity analysis.

[0172] Unlike a polymer target binding affinity analysis, there is no need to have multiple “MR” + “I” sequences during self-test, as depicted in Figure 11 , as there is no target binding affinity analysis required. Although some of the initial fluorophore response may not be captured with a longer 12’ duration, the photocurrent integration during self-test could be active throughout the entire 13’ interval before the array results readout, ensuring a valid test result. In either embodiment, for testing of the photocurrent integrator circuitry using either direct microLED illumination or fluorophore excitation, the number and position of failing locations can be used to determine whether redundant CMOS memory storage array bitcells and microLED array elements are sufficient to repair the part, using the architecture presented in Figure 8. This repair method applies if failing locations are localized to microLED array rows or columns with redundant locations. Alternatively, random failing microLED array locations could be recorded, and excluded from the available pattern of polymer synthesis experiments.

[0173] There can be additional pattern sensitivities associated with the microLED array which can be incorporated into the illumination pattern provided by the BIST controller, measured by the integrated photodetector. For example, a dark microLED which is surrounded by illuminated microLEDs can be evaluated, to measure light leakage into the unilluminated area. As another example, as the illuminated microLED draws static current from the corresponding CMOS bitcell driver 113, a large local density of illuminated microLEDs would be active to evaluate the robustness of the power supply distribution from the fabricated CMOS driver chip.

[0174] The test method utilizing the microLED array source illumination and integrated photodetector in Figure 1 C assumes the photodetector would have high sensitivity to the microLED illumination wavelength. For product testing to confirm photocurrent integration at the specific wavelength of the binding target fluorophore emission, an alternative test method would be to apply a material with a fluorophore 127 directly to the top of the microLED array surface, as depicted in Figure 11. In this method, the test of the composite microLED and photodetector involves selectively illuminating the microLED, exciting the fluorophore above the microLED array surface, and measuring the photodetector current from the fluorophore emission. This test method accommodates a different wavelength sensitivity of the photodetector with a simple fixture applying the fluorescent solution to the surface, avoiding the need for external spectroscopy test equipment.

[0175] The self-test method could also be exercised periodically during system operation between experiments, for ongoing equipment functional in-field test. In this method, rather than the test fixture 127 applied to the packaged assembly in Figure 11 , a fluid reagent containing a fluorophore could be introduced into the fluidic channel above the microLED array. The test of the microLED and photodetector would be conducted as shown in Figure 11 , replacing the test fixture 127 with the emission from the reagent present in the fluidic channel.

[0176] The design and functionality described in this application is intended to be exemplary in nature and is not intended to limit the instant disclosure in any way. Those having ordinary skill in the art will appreciate that the teachings of the disclosure may be implemented in a variety of suitable forms, including those forms disclosed herein andadditional forms known to those having ordinary skill in the art. For example, one skilled in the art will recognize that executable instructions may be stored on a non-transient, computer-readable storage medium, such that when executed by one or more processors, causes the one or more processors to implement the method described above.

[0177] As used in this application, the terms “component,” “module,” “system” and the like are intended to include a computer-related entity, such as but not limited to hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and / or thread of execution and a component may be localized on one computer and / or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and / or remote processes such as in accordance with a signal having one or more data packets, such as data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems by way of the signal.

[0178] Certain embodiments of this technology are described above with reference to block and flow diagrams of computing devices and methods and / or computer program products according to example embodiments of the disclosure. It will beunderstood that one or more blocks of the block diagrams and flow diagrams, and combinations of blocks in the block diagrams and flow diagrams, respectively, can be implemented by computer-executable program instructions. Likewise, some blocks of the block diagrams and flow diagrams may not necessarily need to be performed in the order presented, or may not necessarily need to be performed at all, according to some embodiments of the disclosure.

[0179] These computer-executable program instructions may be loaded onto a general-purpose computer, a special-purpose computer, a processor, or other programmable data processing apparatus to produce a particular machine, such that the instructions that execute on the computer, processor, or other programmable data processing apparatus create means for implementing one or more functions specified in the flow diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means that implement one or more functions specified in the flow diagram block or blocks.

[0180] As an example, embodiments of this disclosure may provide for a computer program product, comprising a computer-usable medium having a computer-readable program code or program instructions embodied therein, said computer-readable program code adapted to be executed to implement one or more functions specified in the flow diagram block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause aseries of operational elements or steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions that execute on the computer or other programmable apparatus provide elements or steps for implementing the functions specified in the flow diagram block or blocks.

[0181] Accordingly, blocks of the block diagrams and flow diagrams support combinations of means for performing the specified functions, combinations of elements or steps for performing the specified functions, and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flow diagrams, and combinations of blocks in the block diagrams and flow diagrams, can be implemented by special-purpose, hardware-based computer systems that perform the specified functions, elements or steps, or combinations of special-purpose hardware and computer instructions.

[0182] While certain embodiments of this disclosure have been described in connection with what is presently considered to be the most practical and various embodiments, it is to be understood that this disclosure is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

[0183] This written description uses examples to disclose certain embodiments of the technology and also to enable any person skilled in the art to practice certainembodiments of this technology, including making and using any apparatuses or systems and performing any incorporated methods.

Claims

CLAIMSWe claim:1 . A microarray comprising: a plurality of individually controllable microLED elements; an integrated surface; and a CMOS driver chip; wherein each microLED element is paired with a corresponding activation circuit on the CMOS driver chip, wherein the activation circuit is configured to control activation of the microLED elements.

2. The microarray of claim 1 , wherein each activation circuit is physically proximate to the corresponding microLED.

3. The microarray of claim 2 wherein each activation circuit comprises a memory circuit and a drive circuit.

4. The microarray of claim 3, wherein the memory circuit stores data comprising a first value and a second value.

5. The microarray of claim 4, wherein the drive circuit is configured to illuminate the microLED if the memory circuit stores the first value and configured to not to illuminate the microLED if the memory circuit stores the second value.

6. The microarray of claim 5, wherein the memory circuit comprises a bitcell.

7. The microarray of claim 1 , further comprising a temporary disablement circuit configured to temporarily disable one or more of the activation circuits while data is written to the activation circuit.

8. The microarray of claim 1 , further comprising a permanent disablement circuit configured to permanently disable one or more of the microLEDs.

9. The microarray of claim 8, further comprising a plurality of redundant microLEDs configured to be enabled to compensate for any disabled microLEDs.

10. The microarray of claim 1 , further comprising a plurality of polymers synthesized on the integrated surface of the microarray, wherein the polymers are arranged in an array of features corresponding to the microLED elements.11 . The microarray of claim 1 , further comprising a plurality of photodetector elements, wherein each photodetector element is paired with a corresponding microLED and its corresponding activation circuit on the CMOS driver chip, wherein the activation circuit is further configured to receive signals from the photodetector element.

12. The microarray of claim 11 , wherein each activation circuit is physically proximate to the corresponding microLED.

13. The microarray of claim 12 wherein each activation circuit comprises a memory circuit and a drive circuit.

14. The microarray of claim 13, wherein the activation circuit further comprises an integration circuit.

15. The microarray of claim 14, wherein the integration circuit is configured to integrate a signal from the photodetector element.

16. The microarray of claim 15 wherein the integration circuit is configured to write a value to the memory circuit if the integrated signal from the photodetector element exceeds a threshold value.

17. The microarray of claim 16, wherein the drive circuit is configured to illuminate the microLED if the memory circuit stores the first value and configured to not to illuminate the microLED if the memory circuit stores the second value.

18. The microarray of claim 17, wherein the memory circuit comprises a bitcell.

19. The microarray of claim 18, further comprising a temporary disablement circuit configured to temporarily disable one or more of the activation circuits while data is written to the memory circuit.

20. The microarray of claim 1 , wherein each activation circuit is physically proximate to the corresponding microLED.

21. A microarray comprising: a plurality of individually controllable microLED elements; a plurality of photodetectors; an integrated surface; and a CMOS driver chip, wherein each microLED element is paired with a corresponding photodetector and with a corresponding activation circuit on the CMOS driver chip.

22. The microarray of claim 21 , wherein each activation circuit is physically proximate to the corresponding microLED and the corresponding photodetector.

23. The microarray of claim 21 , wherein each activation circuit is configured to control the corresponding photodetector.

24. The microarray of claim 23 wherein each activation circuit comprises a memory circuit and an integration circuit.

25. The microarray of claim 24, wherein the memory circuit stores data comprising a first value and a second value.

26. The microarray of claim 25, wherein the memory circuit comprises a bitcell.

27. The microarray of claim 26, wherein the integration circuit is configured to integrate a signal from the photodetector element.

28. The microarray of claim 27, wherein the integration circuit is configured to write a value to the memory circuit if the integrated signal from the photodetector element exceeds a threshold value.

29. The microarray of claim 28, wherein the activation circuit further comprises a drive circuit.

30. The microarray of claim 29, wherein the drive circuit is configured to illuminate the microLED.

31. The microarray of claim 30, wherein the drive circuit is configured to illuminate the microLED if the memory circuit stores the first value and configured to not to illuminate the microLED if the memory circuit stores the second value.

32. The microarray of claim 16, wherein the drive circuit is configured to illuminate the microLED if the memory circuit stores the first value and configured to not to illuminate the microLED if the memory circuit stores the second value.

33. The microarray of claim 21 , further comprising a temporary disablement circuit configured to temporarily disable one or more of the activation circuits while data is written to the activation circuit.

34. The microarray of claim 21 , further comprising a permanent disablement circuit configured to permanently disable one or more of the microLEDs.

35. The microarray of claim 21 , further comprising a plurality of redundant microLEDs configured to be enabled to compensate for any disabled microLEDs.

36. The microarray of claim 21 , further comprising a plurality of polymers synthesized on the integrated surface of the microarray, wherein the polymers are arranged in an array of features corresponding to the microLED elements.

37. The microarray of claim 30, further comprising a plurality of polymers synthesized on the integrated surface of the microarray, wherein the polymers are arranged in an array of features corresponding to the microLED elements.

38. A method of synthesizing polymers using a microarray, the microarray comprising a plurality of individually controllable microLED elements, an integrated surface, and a CMOS driver chip, wherein each microLED element is paired with a corresponding activation circuit on the CMOS driver chip, wherein the activation circuit is configured to control activation of the microLED elements, the method comprising: loading an illumination pattern into the activation circuit associated with each microLED; illuminating the appropriate microLEDs determined by the illumination pattern to deprotect the end of the existing polymer at each active microLED position; and introducing a reagent into the fluid channel to bind to the deprotected polymer at each active microLED site.

39. The method of claim 38 further comprising deleting the illumination pattern.

40. The method of claim 38, further comprising: introducing a target molecule that has a predefined fluorophore attached; exciting the fluorophore attached to the target; measuring the emissions of the fluorophore at each specific microLED location to determine the affinity of the target to the synthesized polymer; storing the affinity measurement; reading out the affinity measurement.41 . The method of claim 40, wherein the fluorophore is excited by illuminating the plurality of microLEDs.

42. The method of claim 40, wherein the emissions of the fluorophore at each specific microLED location are measured using a plurality of photodetectors, wherein each photodetector is associated with a corresponding microLED.

43. The method of claim 40, wherein the activation circuit comprises a memory circuit and the affinity measurement is stored in the memory circuit.

44. A method of analyzing polymers synthesized using a microarray, wherein the microarray comprises a plurality of individually controllable microLED elements, a plurality of photodetectors, an integrated surface, and a CMOS driver chip, and wherein each microLED element is paired with a corresponding photodetector and with a corresponding activation circuit on the CMOS driver chip, the method comprising: introducing a target molecule that has a predefined fluorophore attached; exciting the fluorophore attached to the target; measuring the emissions of the fluorophore at each specific microLED location to determine the affinity of the target to the synthesized polymer; storing the affinity measurement; reading out the affinity measurement.

45. The method of claim 44, wherein the fluorophore is excited by illuminating the plurality of microLEDs.

46. The method of claim 44, wherein the emissions of the fluorophore at each specific microLED location are measured using a plurality of photodetectors, wherein each photodetector is associated with a corresponding microLED.

47. The method of claim 44, wherein the activation circuit comprises a memory circuit and the affinity measurement is stored in the memory circuit.

48. The method of claim 44, the method further comprising the steps of: loading an illumination pattern into the activation circuit associated with each microLED; illuminating the appropriate microLEDs determined by the illumination pattern to deprotect the end of the existing polymer at each active microLED position; and introducing a reagent into the fluid channel to bind to the deprotected polymer at each active microLED site.

49. A method of testing a microarray, the method comprising: illuminating a plurality of microLEDs; measuring the illumination from the plurality of microLEDs via a plurality of photodetectors; and storing the illumination measurement.

50. The method of claim 49, wherein each of the plurality of photodetectors corresponds to one of the plurality of microLEDs.51 . The method of claim 50, wherein each of the plurality of photodetectors is physically proximate to its corresponding microLED.

52. The method of claim 51 , wherein the illumination is measured by integrating a signal from each of the plurality of photodetectors.

53. The method of claim 52, wherein the signal from each of the plurality of photodetectors is measured by one of a plurality of integration circuits on a CMOS driver chip, wherein each of the integration circuits is physically proximate to the photodetector whose signal is it integrating.

54. The method of claim 53, further comprising writing a value to each of a plurality of memory circuits if the integrated signal exceeds a threshold value, wherein each of the plurality of memory circuits corresponds to one of the plurality of integration circuits.

55. The method of claim 54, where each of the plurality of memory circuits resides on the CMOS driver chip and is physically proximate to the corresponding integration circuit and physically proximate to the photodetector whose signal it is integrating.

56. The method of claim 50, the method further comprising the step of disabling each of the plurality of microLEDs if the illumination value from the corresponding photodetector fails to exceed a threshold value.

57. A method of testing a microarray, the method comprising: introducing a fluorescent compound to an integrated surface of the microarray; illuminating the fluorescent compound; measuring the fluorescence of the fluorescent compound via a plurality of photodetectors residing in the microarray; and storing the fluorescence measurement.

58. The method of claim 49, wherein each of the plurality of photodetectors corresponds to one of a plurality of microLEDs.

59. The method of claim 50, wherein each of the plurality of photodetectors is physically proximate to its corresponding microLED.

60. The method of claim 51 , wherein the fluorescence is measured by integrating a signal from each of the plurality of photodetectors.61 . The method of claim 52, wherein the signal from each of the plurality of photodetectors is measured by one of a plurality of integration circuits on a CMOS driver chip, wherein each of the integration circuits is physically proximate to the photodetector whose signal it is integrating.

62. The method of claim 53, further comprising writing a value to each of a plurality of memory circuits if the integrated signal exceeds a threshold value, wherein each of the plurality of memory circuits corresponds to one of the plurality of integration circuits.

63. The method of claim 54, where each of the plurality of memory circuits resides on the CMOS driver chip and is physically proximate to the corresponding integration circuit and physically proximate to the photodetector whose signal it is integrating.

64. The method of claim 50, the method further comprising the step of disabling each of the plurality of microLEDs if the fluorescence value from the corresponding photodetector fails to exceed a threshold value.

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