Display substrate and display device

Abstract

A display substrate (100) and a display device (200). The display substrate (100) comprises: a first gate signal line (VGHO) and a second gate signal line (VGHE); a first gate driving unit (11) and a second gate driving unit (12), wherein the first gate driving unit (11) and the second gate driving unit (12) each comprise a buffer unit (111, 121), and the buffer unit (111, 121) comprises a first transistor (T1), a second transistor (T2) and an output electrode (O1) that outputs a gate control signal, a first electrode of the first transistor (T1) and a first electrode of the second transistor (T2) being connected to the output electrode (O1); and a pixel circuit (PXL) electrically connected to the output electrodes (O1) of the buffer units (111,121), wherein the pixel circuit (PXL) comprises pixel groups (PXU) in odd-numbered rows and pixel groups (PXU) in even-numbered rows. The first gate signal line (VGHO) is connected to a second electrode of the first transistor (T1) included in the first gate driving unit (11), such that the first gate driving unit (11) provides a gate control signal for the pixel groups (PXU) in the odd-numbered rows; and the second gate signal line (VGHE) is connected to a second electrode of the first transistor (T1) included in the second gate driving unit (12), such that the second gate driving unit (12) provides a gate control signal for the pixel groups (PXU) in the even-numbered rows.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a display substrate and a display device. Background Art

[0002] The gate signal lines that provide gate signals in the existing gate drive circuit are of a shared design. The output loads of adjacent rows will cause large noise in the signals on the gate signal lines. When there are pixels in a panel with a 1-drive-2 design, the noise of a 2-row cycle will cause charging differences between the pixels in the odd and even rows, resulting in brightness differences between the odd and even rows, causing uneven display effects.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, comprising: gate signal lines, including a first gate signal line and a second gate signal line, each of the first gate signal line and the second gate signal line being applied with a first voltage, the first gate signal line and the second gate signal line being spaced apart from each other; a first gate driving unit and a second gate driving unit, each of the first gate driving unit and the second gate driving unit comprising a buffer unit, the buffer unit comprising a first transistor, a second transistor, and an output electrode for outputting a gate control signal; a first electrode of the first transistor and a first electrode of the second transistor being connected to the output electrode, and a second electrode of the first transistor being connected to the gate signal line; a pixel circuit electrically connected to the output electrode of the buffer unit, the pixel circuit comprising an odd-numbered row pixel group and an even-numbered row pixel group, the pixel group comprising at least two rows of pixel circuits; the first gate signal line being connected to the second electrode of the first transistor included in the first gate driving unit, so that the first gate driving unit provides a gate control signal to the odd-numbered row pixel group, and the second gate signal line being connected to the second electrode of the first transistor included in the second gate driving unit, so that the second gate driving unit provides a gate control signal to the even-numbered row pixel group.

[0006] In some exemplary embodiments of the present disclosure, the display substrate further includes a reference gate signal line, to which a second voltage is applied, and the reference gate signal line is connected to a second electrode of a second transistor included in the buffer unit.

[0007] In some exemplary embodiments of the present disclosure, the first gate driving unit and the second gate driving unit each further include a scanning unit connected to the gate signal line.

[0008] In some exemplary embodiments of the present disclosure, the scanning unit in the first gate driving unit is electrically connected to the first gate signal line; and the scanning unit in the second gate driving unit is electrically connected to the second gate signal line.

[0009] In some exemplary embodiments of the present disclosure, the scanning unit in the first gate driving unit is electrically connected to the second gate signal line; and the scanning unit in the second gate driving unit is electrically connected to the first gate signal line.

[0010] In some exemplary embodiments of the present disclosure, the gate signal line also includes a third gate signal line, to which the first voltage is applied, and the third gate signal line is spaced apart from the first gate signal line and the second gate signal line; the third gate signal line is connected to the scanning unit in the first gate driving unit, and the third gate signal line is connected to the scanning unit in the second gate driving unit.

[0011] In some exemplary embodiments of the present disclosure, the reference gate signal line is connected to a scanning unit in the first gate driving unit, and the reference gate signal line is connected to a scanning unit in the second gate driving unit.

[0012] In some exemplary embodiments of the present disclosure, the gate signal line includes: a first connection point where the first gate signal line is connected to the first gate driving unit; a second connection point where the second gate signal line is connected to the second gate driving unit; and / or a third connection point where the third gate signal line is connected to the first gate driving unit or the second gate driving unit; and a short-circuit connection point on the gate signal line that is away from the first connection point, the second connection point and / or the third connection point so as to short-circuit the first gate signal line, the second gate signal line and / or the third gate signal line.

[0013] In some exemplary embodiments of the present disclosure, a voltage-stabilizing capacitor connected to the first gate signal line, the second gate signal line and / or the third gate signal line is provided at a position on the gate signal line away from the first connection point, the second connection point and / or the third connection point.

[0014] In some exemplary embodiments of the present disclosure, the voltage-stabilizing capacitor is disposed between the first connection point, the second connection point, and / or the third connection point and the short-circuit connection point.

[0015] In some exemplary embodiments of the present disclosure, the voltage-stabilizing capacitor includes: a first voltage-stabilizing capacitor connected to the first gate signal line; a second voltage-stabilizing capacitor connected to the second gate signal line; and / or a third voltage-stabilizing capacitor connected to the third gate signal line.

[0016] In some exemplary embodiments of the present disclosure, the short-circuit connection point is located at an edge of a display area of ​​the display substrate; or the short-circuit connection point is located in a flexible circuit board included in the display substrate; or the short-circuit connection point is located in a driver integrated circuit included in the display substrate.

[0017] In some exemplary embodiments of the present disclosure, the voltage-stabilizing capacitor is disposed in a flexible circuit board included in the display substrate.

[0018] In some exemplary embodiments of the present disclosure, the number of the first gate signal lines is at least two, and the number of the second gate signal lines is at least two.

[0019] In some exemplary embodiments of the present disclosure, each pixel group in the pixel circuit includes a first row of pixel circuits and a second row of pixel circuits arranged in parallel, and the first row of pixel circuits and the second row of pixel circuits include a common N-type gate; the first row of pixel circuits also includes a first P-type gate, and the second row of pixel circuits includes a second P-type gate.

[0020] In some exemplary embodiments of the present disclosure, the output electrode includes a first output electrode, a second output electrode and a third output electrode; the first output electrode is connected to the N-type gate to provide a first gate signal to the N-type gate; the second output electrode is connected to the first P-type gate to provide a second gate signal to the first P-type gate; the third output electrode is connected to the second P-type gate to provide a third gate signal to the second P-type gate.

[0021] In some exemplary embodiments of the present disclosure, the low voltage signal in the second gate signal and the low voltage signal in the third gate signal do not overlap in timing.

[0022] In some exemplary embodiments of the present disclosure, the display substrate further includes: a first clock signal line, a second clock signal line, an initial signal line, and a control signal line connected to the scanning unit.

[0023] In some exemplary embodiments of the present disclosure, when the first gate signal line provides gate control signals for the pixel groups in the odd rows, and when the second gate signal line provides gate control signals for the pixel groups in the even rows, the timing of the maximum pull-down potential of the first gate signal line due to the load does not overlap with the timing of the maximum pull-down potential of the second gate signal line due to the load; the timing of the low voltage signal of the second gate signal and the timing of the low voltage signal of the third gate signal do not overlap with the timing of the maximum pull-down potential of the first gate signal line due to the load and the timing of the maximum pull-down potential of the second gate signal line due to the load.

[0024] In yet another aspect of the present disclosure, a display device is provided, comprising the display substrate described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0026] FIG1A is a block diagram of a display substrate of a GOA in the prior art;

[0027] FIG1B is a schematic diagram of the gate driving unit in FIG1A ;

[0028] FIG2 is a block diagram of a display substrate according to an embodiment of the present disclosure;

[0029] 3A is a schematic diagram showing connections between a first gate signal line, a second gate signal line, and a first gate driving unit and a second gate driving unit of a display substrate according to an embodiment of the present disclosure;

[0030] 3B is a schematic diagram showing connections between a first gate signal line, a second gate signal line, and a first gate driving unit and a second gate driving unit of a display substrate according to another embodiment of the present disclosure;

[0031] 3C is a schematic diagram showing connections between the first gate signal line, the second gate signal line, the third gate signal line, and the first gate driving unit and the second gate driving unit of the display substrate according to an embodiment of the present disclosure;

[0032] 4A is a schematic diagram showing a short circuit connection between a first gate signal line and a second gate signal line according to an embodiment of the present disclosure;

[0033] 4B is a schematic diagram showing a short circuit connection between a first gate signal line and a second gate signal line according to another embodiment of the present disclosure;

[0034] 4C is a schematic diagram showing a short circuit connection between a first gate signal line and a second gate signal line according to yet another embodiment of the present disclosure;

[0035] 4D is a schematic diagram showing a short circuit connection between a first gate signal line and a second gate signal line according to yet another embodiment of the present disclosure;

[0036] 5A is a schematic diagram showing a short circuit connection between a first gate signal line, a second gate signal line, and a third gate signal line according to an embodiment shown in FIG. 3C ;

[0037] 5B is a schematic diagram showing a short circuit connection between the first gate signal line, the second gate signal line, and the third gate signal line according to another embodiment shown in FIG. 3C ;

[0038] 5C is a schematic diagram showing a short-circuit connection between the first gate signal line, the second gate signal line, and the third gate signal line according to another embodiment shown in FIG. 3C ;

[0039] 5D is a schematic diagram showing a short-circuit connection between the first gate signal line, the second gate signal line, and the third gate signal line according to yet another embodiment shown in FIG3C ;

[0040] FIG6 is a schematic structural diagram of a voltage-stabilizing capacitor according to an embodiment of the present disclosure;

[0041] 7A is a schematic diagram showing a plurality of first gate signal lines and a plurality of second gate signal lines being short-circuited according to an embodiment of the present disclosure;

[0042] 7B is a schematic diagram showing a plurality of first gate signal lines and a plurality of second gate signal lines being short-circuited according to another embodiment of the present disclosure;

[0043] 7C is a schematic diagram showing a plurality of first gate signal lines and a plurality of second gate signal lines being short-circuited according to yet another embodiment of the present disclosure;

[0044] 7D is a schematic diagram showing a plurality of first gate signal lines and a plurality of second gate signal lines being short-circuited according to yet another embodiment of the present disclosure;

[0045] 8A is a signal waveform diagram of a first gate signal line, a second gate signal line, an N-type gate, a first P-type gate, and a second P-type gate included in a display substrate according to an embodiment of the present disclosure;

[0046] 8B is a signal waveform diagram of a first gate signal line, a second gate signal line, an N-type gate, a first P-type gate, and a second P-type gate according to an embodiment of the present disclosure;

[0047] 9A is a diagram showing simulation waveforms of a gate control signal on a first gate signal line and a gate control signal on a second gate signal line without a voltage-stabilizing capacitor;

[0048] 9B is a simulation waveform diagram of a gate control signal on a first gate signal line and a gate control signal on a second gate signal line in which a voltage-stabilizing capacitor is provided according to an embodiment of the present disclosure;

[0049] FIG10A is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0050] FIG10B is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0051] FIG10C is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0052] FIG10D is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0053] FIG10E is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0054] FIG10F is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0055] FIG10G is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0056] FIG10H is a circuit structure diagram of a first gate driving unit according to an embodiment of the present disclosure;

[0057] FIG. 11 is a schematic diagram of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0059] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0060] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on the other element, directly connected to the other element, or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent," or "on..." versus "directly on...", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0061] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0062] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0063] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0064] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0065] In this document, the directional expressions "first direction" and "second direction" are used to describe different directions along a pixel region, such as the longitudinal and transverse directions of a pixel region, or the row and column directions of a sub-pixel arrangement. It should be understood that such expressions are merely exemplary descriptions and are not intended to limit the present disclosure.

[0066] The transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the thin film transistors used here are symmetrical, their source and drain can be interchanged. In the embodiments of the present disclosure, the transistor may include a gate, a first electrode and a second electrode, wherein the first electrode can represent one of the source and the drain, and the second electrode can represent the other of the source and the drain. In the following examples, the case of a P-type thin film transistor used as a driving transistor is mainly described, and other transistors have the same or different types as the driving transistor according to the circuit design. Similarly, in other embodiments, the driving transistor may also be shown as an N-type thin film transistor.

[0067] Some exemplary embodiments of the present disclosure provide a display substrate, the display substrate comprising: gate signal lines, including a first gate signal line and a second gate signal line, each of the first gate signal line and the second gate signal line being applied with a first voltage, the first gate signal line and the second gate signal line being spaced apart from each other; a first gate driving unit and a second gate driving unit, each of the first gate driving unit and the second gate driving unit comprising a buffer unit, the buffer unit comprising a first transistor, a second transistor, and an output electrode for outputting a gate control signal; a first electrode of the first transistor and a first electrode of the second transistor being connected to the output electrode, and a second electrode of the first transistor being connected to the gate signal line; a pixel circuit electrically connected to the output electrode of the buffer unit, the pixel circuit comprising an odd-numbered row of pixel groups and an even-numbered row of pixel groups, the pixel group comprising at least two rows of pixel circuits; the first gate signal line being connected to the second electrode of the first transistor included in the first gate driving unit, so that the first gate driving unit provides a gate control signal to the odd-numbered row of pixel groups, and the second gate signal line being connected to the second electrode of the first transistor included in the second gate driving unit, so that the second gate driving unit provides a gate control signal to the even-numbered row of pixel groups.

[0068] In an embodiment of the present disclosure, by setting the gate signal line to a first gate signal line connected to the first gate driving unit and a second gate signal line connected to the second gate driving unit, the first gate signal line can provide a gate control signal for the pixel group of odd rows, and the second gate signal line can provide a gate control signal for the pixel group of even rows, that is, segmented control of the gate control signal is realized, thereby effectively avoiding the problem of uneven display of two rows of pixel circuits in the pixel group caused by noise generated by the gate signal line being affected by the load, thereby effectively improving the display effect of the display substrate.

[0069] Figure 1A is a block diagram of a display substrate of a GOA in the prior art. Figure 1B is a schematic diagram of a gate driving unit in Figure 1A.

[0070] As shown in FIG1A , an existing display substrate includes a display area AA located on the display substrate. A gate signal line is provided in a non-display area NA at the edge of the display area AA to provide a signal to a gate drive circuit (GOA) that controls each row of pixels. The gate drive circuit controls the gate of the pixel circuit located in the display area AA through a signal outputted through an output terminal (out), thereby realizing control over the lighting, shutoff, and brightness of the pixels.

[0071] As shown in Figures 1A and 1B, each row of pixels in the display substrate in the existing design is provided with signals through a gate drive circuit. Within the display substrate, the gate signal lines (VGH) and reference gate signal lines (VGL) of pixels in different rows are all shared. One end of the gate signal line and the reference gate signal line are uniformly connected to a flexible printed circuit (FPC), and are finally connected to the output end of an integrated circuit (such as a display driver integrated circuit (DDIC) or a power management integrated circuit (PMIC)) through the FPC routing.

[0072] As shown in FIG1B , the gate drive circuit of each row also includes multiple clock signal lines, such as a first clock signal line CK, a second clock signal line CB, and a reference gate signal line VGL. The clock signal line CK, the gate signal line VGH, and the reference gate signal line VGL all adopt a common design, and the gate signal lines VGH of pixels in different rows are connected to the same gate signal line. When the gate line in the pixel circuit is charged through the gate signal line, the gate signal line VGH first charges the gate line through the transistor at the pull-up node. Due to the large instantaneous current, the gate signal line has a load (for example, a resistive load). At this time, the voltage of the gate signal line VGH is pulled down, generating a pull-down potential, and then returns to the set pull-up voltage again. In this process, the voltage on the gate signal line VGH presents fluctuating noise, which is eventually transmitted to the gate line in the non-pull-down state in the pixel circuit, resulting in noise on the gate line, which in turn affects the light-emitting state of the pixel unit in the pixel circuit, resulting in the problem of local brightness variation.

[0073] When a shared N-type gate is used in a pixel circuit to drive the P-type gates of two rows of pixels, when the P-type gates of the pixels in the odd and even rows are turned on, the noise states of the corresponding different N-type gate signals cause differences in the gate signals of the odd and even rows, ultimately forming uneven brightness horizontal stripes on the odd and even rows, reducing the display effect of the display substrate.

[0074] In order to solve the above problems, the present disclosure provides a display substrate. The structure of the display substrate according to an embodiment of the present disclosure will be described below with reference to FIG. 2 to FIG. 10H .

[0075] FIG. 2 is a block diagram of a display substrate according to an embodiment of the present disclosure.

[0076] 2 , a display substrate 100 according to an embodiment of the present disclosure may include a base substrate and pixel units disposed on the base substrate. The pixel units are arranged along set rows and columns to form a pixel area, for example, along a first direction X and a second direction Y.

[0077] The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where pixel units displaying an image are disposed. Each pixel unit will be described later. The non-display area NA is an area where no pixel units are disposed, that is, an area where no image is displayed. The non-display area NA corresponds to the frame of the final display device, and the width of the frame is determined based on the width of the non-display area NA.

[0078] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a closed polygon (e.g., a rectangle) with straight sides, a circle or an ellipse with curved sides, or a semicircle or a semiellipse with both straight and curved sides. In the embodiment of the present disclosure, the display area AA is provided as a quadrilateral with straight sides. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0079] The non-display area NA may be provided on at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a transverse portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0080] The pixel unit is arranged in the display area AA. The pixel unit is the smallest unit for displaying an image and can be arranged in plurality. For example, the pixel unit can include a light emitting device that emits white light and / or colored light.

[0081] The pixel units may be provided in a plurality and arranged in a matrix along rows extending in the first direction X and columns extending in the first direction Y. However, the embodiments of the present disclosure do not specifically limit the arrangement of the pixel units, and the pixel units may be arranged in various forms. For example, the pixel units may be arranged such that a direction inclined relative to the first direction X and the first direction Y becomes a column direction, and a direction intersecting the column direction becomes a row direction.

[0082] That is, the plurality of pixel units are arranged in an array along the first direction X and the second direction Y to form a plurality of rows of pixel units and a plurality of columns of pixel units.

[0083] A pixel unit may include multiple sub-pixels. For example, a pixel unit may include three sub-pixels, namely a first sub-pixel, a second sub-pixel, and a third sub-pixel. For example, the first sub-pixel may be a red sub-pixel, the second sub-pixel may be a green sub-pixel, and the third sub-pixel may be a blue sub-pixel.

[0084] It should be noted that, in the embodiment of the present disclosure, the number of sub-pixels included in a pixel unit is not particularly limited and is not limited to the above-mentioned three.

[0085] Each pixel unit is arranged along a predetermined row to form a row of pixels PXL. Each pixel unit has a pixel circuit for controlling the on / off state and brightness of each pixel. This control is achieved via the data lines described below and the gate signal lines described above. The pixel circuit includes an N-type gate and a P-type gate.

[0086] In this embodiment, two rows of pixels PXL together form a group, for example, the first row of pixels PXL and the second row of pixels PXL form a group, namely, pixel group PXU, and each pixel group includes a first row of pixel circuits corresponding to the first row of pixels PXL and a second row of pixel circuits corresponding to the second row of pixels PXL arranged in parallel.

[0087] In some embodiments of the present disclosure, the first row of pixel circuits and the second row of pixel circuits in two adjacent and parallel rows of pixels PXL include a common N-type gate. Each row of pixel circuits also includes a P-type gate, for example, the first row of pixel circuits includes a first P-type gate, and the second row of pixel circuits includes a second P-type gate.

[0088] For example, in the exemplary embodiment shown in FIG2 , scan control signal lines 110 and data lines 120 are schematically illustrated. That is, the display substrate 100 may further include: a plurality of scan control signal lines 110 and a plurality of data lines 120 disposed on the base substrate. The plurality of scan control signal lines 110 respectively supply scan control signals, i.e., gate control signals outputted by the output electrodes of the first gate driving unit and the second gate driving unit, to a plurality of rows of pixel units; and the plurality of data lines 120 respectively supply data signals to a plurality of columns of pixel units. The scan control signal lines 110 extend along a first direction X, and the plurality of scan control signal lines 110 are arranged at intervals along a second direction Y. The data lines 120 extend along the second direction Y, and the plurality of data lines 120 are arranged at intervals along the first direction X.

[0089] For example, the scan control signal line 110 may be a representative of a horizontal line, and the data line 120 may be a representative of a vertical line. It should be understood that the horizontal line may also include lines of other types or lines for supplying other signals, and the vertical line may also include lines of other types or lines for supplying other signals.

[0090] Each sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, in an OLED display substrate or display panel, the light-emitting element of a sub-pixel may include a stacked anode, a light-emitting material layer, and a cathode. The anodes of the light-emitting elements of each sub-pixel are spaced apart and arranged in a matrix along rows extending in a first direction X and columns extending in a first direction Y.

[0091] It should be noted that the transistors in the pixel circuit can be divided into N-type transistors and P-type transistors according to their different semiconductor characteristics. When the transistor is used as a switching transistor, the N-type switching transistor is turned on by a high-level switching control signal and turned off by a low-level switching control signal. The P-type switching transistor is turned on by a low-level switching control signal and turned off by a high-level switching control signal.

[0092] In the embodiments of the present disclosure, the pixel circuit can adopt an LTPO circuit, that is, an LTPO circuit is prepared using low-temperature polysilicon (LTPS) technology and oxide (IGZO). The low-temperature polysilicon thin-film transistor (LTPS) uses polysilicon deposition to form an active layer. LTPS has high electron mobility, fast response speed, and has advantages such as high brightness, high resolution and low power consumption. Oxide thin-film transistors (TFTs) use oxide semiconductors as the active layer of TFTs, such as indium gallium zinc oxide (IGZO). Oxide semiconductors have high electron mobility and good turn-off characteristics. Compared with LTPS, oxide semiconductors have a simple process and are more compatible with amorphous silicon processes. Of course, oxide thin-film transistors can also be other metal oxide semiconductors, such as indium zinc tin oxide (IZTO) or indium gallium zinc tin oxide (IGZTO). The use of oxide thin film transistors can effectively reduce the size of the transistors and prevent leakage current, thereby making the pixel circuit suitable for low-frequency driving while also increasing the resolution of the display substrate.

[0093] Figure 3A is a schematic diagram illustrating the connection between the first gate signal line, the second gate signal line, and the first gate driving unit, and the second gate driving unit of a display substrate according to one embodiment of the present disclosure. Figure 3B is a schematic diagram illustrating the connection between the first gate signal line, the second gate signal line, and the first gate driving unit, and the second gate driving unit of a display substrate according to another embodiment of the present disclosure. Figure 3C is a schematic diagram illustrating the connection between the first gate signal line, the second gate signal line, and the third gate signal line of a display substrate and the first gate driving unit, and the second gate driving unit according to one embodiment of the present disclosure.

[0094] The structure of the display substrate according to the embodiment of the present disclosure will be described below with reference to FIG. 2 and FIG. 3A to FIG. 3C .

[0095] The display substrate 100 includes a gate signal line VGH, a reference gate signal line VGL, a first clock signal line CK, and a second clock signal line CB.

[0096] The gate signal lines VGH include a first gate signal line VGHO and a second gate signal line VGHE. A first voltage V1 is applied to each of the first gate signal line VGHO and the second gate signal line VGHE. The first gate signal line VGHO and the second gate signal line VGHE are spaced apart from each other. For example, the first gate signal line VGHO and the second gate signal line VGHE extend along a second direction Y and are located on a side of the display substrate near the display area AA. A certain distance is provided between the first gate signal line VGHO and the second gate signal line VGHE, thereby separating the first gate signal line VGHO and the second gate signal line VGHE.

[0097] The reference gate signal line VGL and the gate signal line VGH are also arranged on the side of the display substrate close to the display area AA and are located in the non-display area NA. The reference gate signal line VGL is also extended along the second direction Y, and the reference gate signal line VGL and the gate signal line VGH are spaced apart to avoid mutual influence between the signals. The reference gate signal line VGL is applied with a second voltage V2.

[0098] A first gate drive unit 11 and a second gate drive unit 12 are provided on the display substrate 100. Each of the first gate drive unit 11 and the second gate drive unit 12 includes a scanning unit and a buffer unit. The structures of the first gate drive unit 11 and the second gate drive unit 12 can be identical. For example, the first gate drive unit 11 includes a scan buffer unit 111 and a scanning unit 112. The second gate drive unit 12 includes a buffer unit 121 and a scanning unit 122.

[0099] In some optional embodiments, the first gate driving unit 11 and / or the second gate driving unit 12 may include one or more gate driving circuits GOA. For example, in this embodiment, the first gate driving unit 11 and the second gate driving unit 12 have the same structure and each includes a gate driving circuit GOA.

[0100] The buffer unit 111 includes a first transistor T1, a second transistor T2, and an output electrode O1 for outputting a gate control signal. The gate of the first transistor T1 is connected to a pull-up node, and the gate of the second transistor T2 is connected to a pull-down node. The first electrode of the first transistor T1 and the first electrode of the second transistor T2 are connected to the output electrode O1, and the second electrode of the first transistor T1 is connected to the gate signal line VGH. The second electrode of the second transistor T2 of the buffer unit 111 is connected to the reference gate signal line VGL.

[0101] A pixel circuit is also provided on the display substrate, and the pixel circuit includes a third transistor and a fourth transistor. The third transistor is an N-type transistor. The third transistor is shared by the first row of pixel circuits and the second row of pixel circuits in a pixel group, for example. The gate of the third transistor is connected to the output electrode of the buffer unit.

[0102] The pixel circuits include pixel groups PXU in odd rows and pixel groups PXU in even rows. For example, the pixel groups PXU in odd rows and the pixel groups PXU in even rows each include two rows of pixel circuits PXL.

[0103] In other optional embodiments, the pixel group PXU may include more rows of pixel circuits.

[0104] The first gate signal line VGHO is connected to the second electrode of the first transistor T1 included in the first gate driving unit 11, so that the first gate driving unit 11 provides a gate control signal for the pixel group of the odd rows, and the second gate signal line VGHE is connected to the second electrode of the first transistor T1 included in the second gate driving unit 12, so that the second gate driving unit 12 provides a gate control signal for the pixel group of the even rows.

[0105] In the embodiment of the present disclosure, by separating the first gate signal line VGHO and the second gate signal line VGHE, and providing gate control signals to the pixel groups of odd rows and the pixel groups of even rows, respectively, the problem of fluctuation interference between the first gate signal line VGHO and the second gate signal line VGHE due to load between the odd rows and the even rows can be effectively avoided, and the gate control signal between the two rows of pixel circuits in one pixel group can be avoided from being interfered with by the noise on the first gate signal line or the second gate signal line.

[0106] In some embodiments, the scanning unit is connected to the gate signal line.

[0107] In one embodiment, as shown in FIG3A , the buffer unit 111 in the first gate driver unit 11 is connected to the first gate signal line VGHO. Specifically, the first gate signal line VGH is connected to the second electrode of the first transistor T1 included in the first gate driver unit 11. The scanning unit 112 in the first gate driver unit 11 is electrically connected to the first gate signal line VGHO. The buffer unit 121 in the second gate driver unit 12 is connected to the second gate signal line VGHE. Specifically, the second gate signal line VGHE is connected to the second electrode of the first transistor T2 included in the second gate driver unit 12. The scanning unit 112 in the second gate driver unit 12 is electrically connected to the second gate signal line VGHE. A reference gate signal line VGL is connected to the scanning unit 112 in the first gate driver unit 11 and to the second electrode of the second transistor T2 included in the buffer unit 111 in the first gate driver unit 11. Similarly, the reference gate signal line VGL is connected to the scanning unit 122 in the second gate driver unit 12 and to the second electrode of the second transistor T2 included in the buffer unit 121 in the second gate driver unit 12.

[0108] In another embodiment, as shown in FIG3B , the buffer unit 111 in the first gate driving unit 11 is connected to the first gate signal line VGHO. Specifically, the first gate signal line VGHO is connected to the second electrode of the first transistor T included in the first gate driving unit 11. The scanning unit 112 in the first gate driving unit 11 is electrically connected to the second gate signal line VGHE. The buffer unit 121 in the second gate driving unit 12 is connected to the second gate signal line VGHE. Specifically, the second gate signal line VGHE is connected to the second electrode of the first transistor T1 included in the second gate driving unit 12. The scanning unit 122 in the second gate driving unit 12 is electrically connected to the first gate signal line VGHO.

[0109] In another embodiment, as shown in FIG3C , the gate signal line VGH further includes a third gate signal line VGHC, the third gate signal line VGHC is applied with the first voltage V1, and the third gate signal line VGHC is spaced apart from the first gate signal line VGHO and the second gate signal line VGHE.

[0110] The first gate signal line VGHO is connected to the second electrode of the first transistor T1 included in the buffer unit 111 in the first gate driving unit 11, the second gate signal line VGHE is connected to the second electrode of the first transistor T1 included in the buffer unit 121 in the second gate driving unit 12, the third gate signal line VGHC is connected to the scanning unit 112 in the first gate driving unit 11, and the third gate signal line VGHC is connected to the scanning unit 122 in the second gate driving unit 12.

[0111] In some embodiments of the present disclosure, the gate signal line VGH includes: a first connection point D1 connecting the first gate signal line VGHO and the first gate driving unit 11; a second connection point D2 connecting the second gate signal line VGHE and the second gate driving unit 12; and / or a third connection point D3 connecting the third gate signal line VGHC and the first gate driving unit 11 or the second gate driving unit 12; and a short-circuit connection point DD on the gate signal line away from the first connection point D1, the second connection point D2 and / or the third connection point D3 to short-circuit the first gate signal line VGHO, the second gate signal line VGHE and / or the third gate signal line VGHC.

[0112] For example, the first connection point D1 is a point connecting a first gate signal line extending along the second direction Y to the second electrode of a first transistor included in a buffer unit of the first gate driving unit. The second connection point D2 is a point connecting a second gate signal line extending along the second direction Y to the second electrode of a first transistor included in a buffer unit of the second gate driving unit. The third connection point D3 is a point connecting a third gate signal line extending along the second direction Y to a scanning unit of the first gate driving unit or a scanning unit connected to the second gate driving unit.

[0113] For example, when the last row is an odd-numbered pixel group, the third connection point D3 is the point where the third gate signal line is connected to the scanning unit of the first gate driving unit; when the last row is an even-numbered pixel group, the third connection point D3 is the point where the third gate signal line is connected to the scanning unit of the second gate driving unit.

[0114] When the gate signal lines include a first gate signal line and a second gate signal line, the short-circuit connection point DD refers to a point where the first gate signal line and the second gate signal line are short-circuited. When the gate signal lines include a first gate signal line, a second gate signal line, and a third gate signal line, the short-circuit connection point refers to a point where the first gate signal line, the second gate signal line, and the third gate signal line are simultaneously short-circuited.

[0115] The first connection point, the second connection point, and the short-circuit connection point in the first gate signal line and the second gate signal line are described below with reference to FIG. 4A to FIG. 4D .

[0116] Figure 4A is a schematic diagram of a first gate signal line and a second gate signal line being short-circuited according to one embodiment of the present disclosure. Figure 4B is a schematic diagram of a first gate signal line and a second gate signal line being short-circuited according to another embodiment of the present disclosure. Figure 4C is a schematic diagram of a first gate signal line and a second gate signal line being short-circuited according to yet another embodiment of the present disclosure. Figure 4D is a schematic diagram of a first gate signal line and a second gate signal line being short-circuited according to yet another embodiment of the present disclosure.

[0117] In the embodiments shown in Figures 4A to 4D, one first gate signal line VGHO and one second gate signal line VGHE are provided. The first gate signal line VGHO is used to enable the first gate driving unit 11 to provide gate control signals to the pixel groups in the odd rows, and the second gate signal line VGHE is used to enable the second gate driving unit 12 to provide gate control signals to the pixel groups in the even rows.

[0118] In order to reduce mutual interference of voltage fluctuations caused by loads during power-on of the first gate signal line and the second gate signal line, a short-circuit connection point is provided on the gate signal line away from the first connection point and the second connection point so as to short-circuit the first gate signal line and the second gate signal line.

[0119] Because the first connection point is connected to the second electrode of the first transistor included in the buffer unit in the first gate drive unit, and the second connection point is connected to the second electrode of the first transistor included in the buffer unit in the second gate drive unit, noise interference will occur when the gate signal lines in different rows are pulled up. If the short-circuit connection point of the short-circuit connection between the first gate signal line and the second gate signal line is set at a position close to the first connection point or the second connection point, it will cause the electrical signals on the first gate signal line and the second gate signal line to interfere with each other. Therefore, setting the short-circuit connection point at a position on the gate signal line away from the first connection point and the second connection point can effectively reduce or completely avoid the problem of electrical signals on the gate signal lines interfering with each other.

[0120] A stabilizing capacitor C connected to the first gate signal line VGHO and the second gate signal line VGHE is provided at a position on the gate signal line VGH away from the first connection point D1 and the second connection point D2. The stabilizing capacitor C is provided between the first connection point D1, the second connection point D2 and the short-circuit connection point DD.

[0121] In order to further reduce the jitter problem caused by the load during the pull-up process of the electrical signals on the first gate signal line and the second gate signal line, a voltage-stabilizing capacitor is set at one end of the first gate signal line and the second gate signal line, thereby reducing the noise on the first gate signal line and the second gate signal line and suppressing the jitter.

[0122] The voltage stabilizing capacitor C includes a first voltage stabilizing capacitor C1 connected to the first gate signal line VGHO and a second voltage stabilizing capacitor C2 connected to the second gate signal line VGHE. The voltage stabilizing capacitor is disposed in a flexible circuit board 14 included in the display substrate.

[0123] In some embodiments of the present disclosure, a voltage-stabilizing capacitor is provided for each gate signal line. When the signal on different gate signal lines jitters, the voltage-stabilizing capacitor can be used to reduce the noise on the gate signal line and suppress the jitter. At the same time, since a voltage-stabilizing capacitor is provided on each gate signal line, the problem of gate signal lines interfering with each other through short-circuit connection points can be avoided, thereby further improving the signal stability of each gate signal line in the entire display substrate.

[0124] As shown in Figure 4A , the short-circuit connection point is located at the edge of the display area of ​​the display substrate, that is, the short-circuit connection point is set in the non-display area NA and at the edge of the display area AA. As shown in Figure 4B , the short-circuit connection point is located in the flexible printed circuit board 14 included in the display substrate. As shown in Figures 4C and 4D , the short-circuit connection point is located in the driver integrated circuit 13 included in the display substrate. As shown in Figure 4C , the first gate signal line VGHO and the second gate signal line VGHE are respectively connected to adjacent pins in the driver integrated circuit 13, short-circuiting the circuit within the driver integrated circuit. As shown in Figure 4D , the first gate signal line VGHO and the second gate signal line VGHE are respectively connected to different pins on either side of the driver integrated circuit 13, short-circuiting the circuit within the driver integrated circuit.

[0125] In addition, each of the first gate signal line VGHO and the second gate signal line VGHE is provided with a voltage-stabilizing capacitor, for example, a first voltage-stabilizing capacitor C1 and a second voltage-stabilizing capacitor C2. The first voltage-stabilizing capacitor C1 and the second voltage-stabilizing capacitor C2 are provided in the flexible circuit board 14, so that the signal on each gate signal line can be noise-suppressed, thereby improving the display effect of the display substrate.

[0126] In some embodiments of the present disclosure, the gate signal line VGH further includes a third gate signal line VGHC. The first connection point D1, the second connection point D2, the third connection point D3, and the short-circuit connection point DD in the first gate signal line VGHO, the second gate signal line VGHE, and the third gate signal line VGHC included in the embodiments of the present disclosure are described below with reference to FIG. 5A to FIG. 5D .

[0127] FIG5A is a schematic diagram illustrating a short-circuit connection between the first gate signal line, the second gate signal line, and the third gate signal line according to one embodiment shown in FIG3C . FIG5B is a schematic diagram illustrating a short-circuit connection between the first gate signal line, the second gate signal line, and the third gate signal line according to another embodiment shown in FIG3C . FIG5C is a schematic diagram illustrating a short-circuit connection between the first gate signal line, the second gate signal line, and the third gate signal line according to yet another embodiment shown in FIG3C . FIG5D is a schematic diagram illustrating a short-circuit connection between the first gate signal line, the second gate signal line, and the third gate signal line according to yet another embodiment shown in FIG3C .

[0128] As shown in Figures 5A and 5D, the gate signal line includes: a first connection point D1 connecting the first gate signal line VGHO and the first gate driving unit 11; a second connection point D2 connecting the second gate signal line VGHE and the second gate driving unit 12; a third connection point D3 connecting the third gate signal line VGHC and the first gate driving unit 11 or the second gate driving unit 12; and a short-circuit connection point DD on the gate signal line away from the first connection point D1, the second connection point D2 and / or the third connection point D3 to short-circuit the first gate signal line VGHO, the second gate signal line VGHE and the third gate signal line VGHC.

[0129] FIG6 is a schematic structural diagram of a voltage-stabilizing capacitor according to an embodiment of the present disclosure.

[0130] As shown in FIG6 , a stabilizing capacitor C connected to the first gate signal line VGHO, the second gate signal line VGHE and the third gate signal line VGHC is provided on the gate signal line at a position away from the first connection point D1, the second connection point D2 and the third connection point D3.

[0131] The voltage stabilizing capacitor is arranged between the first connection point, the second connection point, the third connection point and the short-circuit connection point, and the short-circuit connection point is located in the flexible circuit board 14 .

[0132] The voltage-stabilizing capacitors C include: a first voltage-stabilizing capacitor C1 connected to the first gate signal line VGHO; a second voltage-stabilizing capacitor C2 connected to the second gate signal line VGHE; and a third voltage-stabilizing capacitor C3 connected to the third gate signal line VGHC. The voltage-stabilizing capacitors C are disposed within a flexible circuit board included in the display substrate.

[0133] In some other optional embodiments of the present disclosure, the short-circuit connection point DD may also be set in the driver integrated circuit.

[0134] According to an embodiment of the present disclosure, by providing a voltage-stabilizing capacitor for each gate signal line (for example, the first gate signal line, the second gate signal line, and the third gate signal line), the influence of signal jitter on the gate signal line on the signals on other gate signal lines can be avoided, thereby improving the display effect of the display substrate.

[0135] As shown in FIG5A , the short-circuit connection point is located at the edge of the display area of ​​the display substrate. As shown in FIG5B , the short-circuit connection point is located in the flexible printed circuit board included in the display substrate. As shown in FIG5C and FIG5D , the short-circuit connection point is located in the driver integrated circuit included in the display substrate.

[0136] As shown in Figure 5C, the first gate signal line VGHO, the second gate signal line VGHE and the third gate signal line VGHC are respectively pulled to adjacent pins in the driver integrated circuit 13 and short-circuited inside the driver integrated circuit. As shown in Figure 5D, the first gate signal line VGHO, the second gate signal line VGHE and the third gate signal line VGHC are respectively pulled to different pins on both sides of the driver integrated circuit 13 and short-circuited inside the driver integrated circuit.

[0137] In some embodiments of the present disclosure, the first gate signal lines include at least two, and the second gate signal lines include at least two.

[0138] For example, there are two first gate signal lines and two second gate signal lines.

[0139] Figure 7A is a schematic diagram of a plurality of first gate signal lines and a plurality of second gate signal lines being short-circuited according to one embodiment of the present disclosure. Figure 7B is a schematic diagram of a plurality of first gate signal lines and a plurality of second gate signal lines being short-circuited according to another embodiment of the present disclosure. Figure 7C is a schematic diagram of a plurality of first gate signal lines and a plurality of second gate signal lines being short-circuited according to yet another embodiment of the present disclosure. Figure 7D is a schematic diagram of a plurality of first gate signal lines and a plurality of second gate signal lines being short-circuited according to yet another embodiment of the present disclosure.

[0140] As shown in Figures 7A to 7D, the first gate signal lines VGHO include two lines, namely, VGH01 and VGH02. VGH01 is connected to the second electrode of the first transistor included in the buffer unit of the first gate driving unit 11 in the first row, so that the first gate driving unit in the first row provides a gate control signal to the pixel group in the first row. VGH02 is connected to the second electrode of the first transistor included in the buffer unit of the first gate driving unit 11' in the third row, so that the first gate driving unit in the third row provides a gate control signal to the pixel group in the third row.

[0141] The second gate signal lines VHGE also include two, namely VGHE1 and VGHE2. VGHE1 is connected to the second electrode of the first transistor included in the buffer unit of the second gate driving unit 12 in the second row, so that the second gate driving unit in the second row provides a gate control signal to the pixel group in the second row. VGHE2 is connected to the second electrode of the first transistor included in the buffer unit of the second gate driving unit 12' in the fourth row, so that the second gate driving unit in the fourth row provides a gate control signal to the pixel group in the fourth row.

[0142] The connection manners of the pixel groups in other odd-numbered rows and the pixel groups in even-numbered rows and the first gate signal line and the second gate signal line are similar and will not be described in detail here.

[0143] According to the embodiment of the present disclosure, when two or more first gate signal lines and second gate signal lines are provided, the influence of signal fluctuation caused by indium load between gate signals can be effectively avoided, thereby improving the display effect of the display substrate.

[0144] In some embodiments of the present disclosure, the output poles in the buffer unit include a first output pole, a second output pole and a third output pole; the first output pole is connected to the N-type gate to provide a first gate signal to the N-type gate; the second output pole is connected to the first P-type gate to provide a second gate signal to the first P-type gate; the third output pole is connected to the second P-type gate to provide a third gate signal to the second P-type gate.

[0145] In some embodiments of the present disclosure, when the first gate signal line provides the gate control signal for the pixel group of the odd rows, and when the second gate signal line provides the gate control signal for the pixel group of the even rows, the timing of the maximum pull-down potential of the first gate signal line due to the load does not overlap with the timing of the maximum pull-down potential of the second gate signal line due to the load; the timing of the low voltage signal of the second gate signal and the timing of the low voltage signal of the third gate signal do not overlap with the timing of the maximum pull-down potential of the first gate signal line due to the load and the timing of the maximum pull-down potential of the second gate signal line due to the load.

[0146] Figure 8A is a signal waveform diagram of a first gate signal line, a second gate signal line, an N-type gate, a first P-type gate, and a second P-type gate included in a display substrate according to an embodiment of the present disclosure. Figure 8B is a signal waveform diagram of a first gate signal line, a second gate signal line, an N-type gate, a first P-type gate, and a second P-type gate according to an embodiment of the present disclosure.

[0147] As shown in Figures 8A and 8B, when the first gate signal line VGHO is pulled up to charge the gate wiring, that is, the first gate signal line VGHO charges the second electrode of the first transistor included in the buffer unit 111 in the first gate driving unit 11, and outputs it to the N-type gate and the first P-type gate and the second P-type gate in the pixel circuit through the output electrode of the buffer unit 111, due to the large instantaneous current, the signal of the first gate signal line VGHO is pulled down by the resistance load, thereby generating a maximum pull-down potential due to the load. Similarly, the signal of the second gate signal line VGHE is pulled down, thereby generating a maximum pull-down potential due to the load. Since the first gate signal line VGHO and the second gate signal line VGHE are respectively connected to the gate driving units corresponding to the pixel groups in different rows, the maximum pull-down potentials generated by the load do not overlap in timing.

[0148] As shown in Figures 8A and 8B, the first gate signal line VGHO provides a signal corresponding to VGHO to the second electrode of the first transistor included in the buffer unit in the first gate driving unit, the signal output by the first output pole among the output poles included in the buffer unit in the first gate driving unit is the waveform corresponding to Ngate(N), the signal output by the second output pole among the output poles is the waveform corresponding to Pgate(N), and the signal output by the third output pole among the output poles is the waveform corresponding to Pgate(N+1).

[0149] The second gate signal line VGHE provides a signal corresponding to VGHE to the second electrode of the first transistor included in the buffer unit in the second gate driving unit. The signal output by the first output pole among the output poles included in the buffer unit in the second gate driving unit is the waveform corresponding to Ngate(N+2), the signal output by the second output pole among the output poles is the waveform corresponding to Pgate(N+2), and the signal output by the third output pole among the output poles is the waveform corresponding to Pgate(N+3).

[0150] As shown in Figures 8A and 8B, the timing of the maximum pull-down potential of the first gate signal line VGHO due to the load and the timing of the maximum pull-down potential of the second gate signal line VGHE due to the load do not overlap, that is, they are staggered with each other, so that there is a large area between the maximum pull-down potentials of the first gate signal line VGHO and the second gate signal line VGHE due to the load, so that the first gate signal, the second gate signal and the third gate signal output by the output electrode of the buffer unit will not interfere with each other.

[0151] As shown in FIG8B , in the odd-row pixel group, the low voltage signal in the second gate signal (the waveform corresponding to Pgate(N)) and the low voltage signal in the third gate signal (the waveform corresponding to Pgate(N+1)) do not overlap in timing, and the fluctuation of the first gate signal Ngate(N) (the waveform corresponding to Ngate(N)) due to the fluctuation of the first gate signal line VGHO is separated from the second gate signal and the third gate signal, thereby avoiding interference.

[0152] In pixel groups in even rows, the low voltage signal in the second gate signal (the waveform corresponding to Pgate(N+2)) and the low voltage signal in the third gate signal (the waveform corresponding to Pgate(N+3)) do not overlap in timing. Fluctuations in the first gate signal Ngate(N+2) (the waveform corresponding to Ngate(N+2)) due to fluctuations in the second gate signal line VGHE are separated from the second and third gate signals, thereby avoiding interference.

[0153] In some embodiments of the present disclosure, the display substrate further includes a first clock signal line CK, a second clock signal line CB, an initial signal line, and a control signal line, which are respectively connected to the scanning units included in the first gate driving unit and the second gate driving unit.

[0154] Figure 9A is a simulation waveform diagram of the gate control signal on the first gate signal line without a voltage-stabilizing capacitor and the gate control signal on the second gate signal line. Figure 9B is a simulation waveform diagram of the gate control signal on the first gate signal line and the gate control signal on the second gate signal line with a voltage-stabilizing capacitor according to an embodiment of the present disclosure.

[0155] As shown in Figure 9A, when the first gate signal line VGHO and the second gate signal line VGHE are not respectively provided with voltage-stabilizing capacitors before the short-circuit connection point, although the voltage waveforms on the two gate signal lines are different, since no voltage-stabilizing capacitors are respectively provided before the short-circuit connection point, the waveforms on the two gate signal lines will interfere with each other. For example, when the voltage signal on the first gate signal line fluctuates due to the load, it will affect the voltage signal on the second gate signal line, thereby resulting in poor display effect.

[0156] As shown in FIG9B , by providing stabilizing capacitors C before the short-circuit connection point on the first gate signal line VGHO and the second gate signal line VGHE, for example, providing a first stabilizing capacitor C1 on the first gate signal line VGHO and a second stabilizing capacitor C2 on the second gate signal line VGHE, interference between the first gate signal line VGHO and the second gate signal line VGHE is eliminated, effectively improving the display effect of the display substrate.

[0157] Figure 10A is a circuit structure diagram of a first gate drive unit according to an embodiment of the present disclosure. Figure 10B is a circuit structure diagram of a first gate drive unit according to an embodiment of the present disclosure. Figure 10C is a circuit structure diagram of a first gate drive unit according to an embodiment of the present disclosure. Figure 10D is a circuit structure diagram of a first gate drive unit according to an embodiment of the present disclosure. Figure 10E is a circuit structure diagram of a first gate drive unit according to an embodiment of the present disclosure. Figure 10F is a circuit structure diagram of a first gate drive unit according to an embodiment of the present disclosure. Figure 10G is a circuit structure diagram of a first gate drive unit according to an embodiment of the present disclosure. Figure 10H is a circuit structure diagram of a first gate drive unit according to an embodiment of the present disclosure.

[0158] 10A to 10H show circuit diagrams of a first gate driving unit that can be applied to a display substrate according to an embodiment of the present disclosure. In an embodiment of the present disclosure, the circuit structures of the first gate driving unit and the second gate driving unit can be completely the same.

[0159] In one embodiment, as shown in FIG10A , the circuit structures of the first gate driving unit and the second gate driving unit are as follows:

[0160] The first gate driving unit includes a buffer unit BM and a scanning unit SM.

[0161] The buffer unit includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is connected to a pull-up node N4, and the gate of the second transistor T2 is connected to a pull-down node N7. The first electrodes of the first and second transistors T1 and T2 are connected to the output electrode Nout_n of the buffer unit. The second electrode of the first transistor T1 is connected to a first gate signal line VGHO, and the second electrode of the second transistor is connected to a reference gate signal line VGL.

[0162] A first clock signal line CK, a second clock signal line CB, an initial signal line STV, a reference gate signal line VGL, and a control signal line NCX are connected to the scanning unit.

[0163] In the embodiment shown in FIG3A , if the circuit structures of the first gate driving unit and the second gate driving unit are as shown in FIG10A , the scanning unit 112 in the first gate driving unit is further connected to the first gate signal line VGHO. For example, one electrode of the fifth transistor T5 and one electrode of the eighth transistor T8 and one electrode of the thirteenth transistor T13 in the circuit diagram are all connected to the first gate signal line VGHO. The scanning unit 122 in the second gate driving unit is further connected to the second gate signal line VGHE. For example, one electrode of the fifth transistor T5 and one electrode of the eighth transistor T8 and one electrode of the thirteenth transistor T13 in the circuit diagram are all connected to the second gate signal line VGHO.

[0164] In the embodiment shown in FIG3B , if the circuit structures of the first gate driving unit and the second gate driving unit are as shown in FIG10A , the scanning unit 112 in the first gate driving unit is further connected to the second gate signal line VGHE. For example, one electrode of the fifth transistor T5 and one electrode of the eighth transistor T8 and one electrode of the thirteenth transistor T13 in the circuit diagram are all connected to the second gate signal line VGHE. The scanning unit 122 in the second gate driving unit is further connected to the first gate signal line VGHO. For example, one electrode of the fifth transistor T5 and one electrode of the eighth transistor T8 and one electrode of the thirteenth transistor T13 in the circuit diagram are all connected to the first gate signal line VGHO.

[0165] In the embodiment shown in Figure 3C, if the circuit structure of the first gate driving unit and the second gate driving unit is as shown in Figure 10A, the scanning unit 112 in the first gate driving unit and the scanning unit 122 in the second gate driving unit are both connected to the third gate signal line VGHC, that is, in the first gate driving unit and the second gate driving unit, for example, one electrode of the fifth transistor T5 and one electrode of the eighth transistor T8 and the thirteenth transistor T13 in the circuit diagram are all connected to the first gate signal line VGHC.

[0166] As shown in FIG. 10B to FIG. 10H , the first gate driving unit and the second gate driving unit both adopt the same circuit structure, and both include a buffer unit BM and a scanning unit SM.

[0167] Each buffer unit BM includes a first transistor T1 and a second transistor T2. The second electrodes of the first transistors T1 in each buffer unit BM are connected to corresponding gate signal lines. For example, in the case of the first gate driving unit, the corresponding gate signal line is the first gate signal line. In the case of the second gate driving unit, the corresponding gate signal line is the second gate signal line. The second electrodes of the second transistors are connected to the reference gate signal line.

[0168] In the embodiment of the present disclosure, the scanning unit SM is different with different circuit designs. The connection method between the gate signal line and the buffer unit BM and the scanning unit SM specifically includes three methods shown in Figures 3A, 3B and 3C.

[0169] Scanning Unit SM In the embodiment of FIG. 3A , the scanning unit in the first gate driving unit is connected to the first gate signal line VGHO, and the scanning unit in the second gate driving unit is connected to the second gate signal line VGHE.

[0170] Scanning Unit SM In the embodiment of FIG. 3B , the scanning unit in the first gate driving unit is connected to the second gate signal line VGHE, and the scanning unit in the second gate driving unit is connected to the first gate signal line VGHO.

[0171] Scanning Unit SM In the embodiment of FIG. 3C , both the scanning units in the first gate driving unit and the second gate driving unit are connected to the third gate signal line VGHC.

[0172] According to an embodiment of the present disclosure, by setting the gate signal line to a first gate signal line connected to the first gate driving unit and a second gate signal line connected to the second gate driving unit, the first gate signal line can provide a gate control signal for the pixel group of odd rows, and the second gate signal line can provide a gate control signal for the pixel group of even rows, that is, segmented control of the gate control signal is realized, thereby effectively avoiding the problem of uneven display of two rows of pixel circuits in the pixel group caused by noise generated by the gate signal line being affected by the load, thereby effectively improving the display effect of the display substrate.

[0173] FIG. 11 is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0174] As shown in FIG11 , at least some embodiments of the present disclosure further provide a display device 200. The display device 200 may include the display substrate 100 described above. The display device 200 includes a display area AA and a non-display area NA. The non-display area NA has a smaller width and a higher pixel density, thereby achieving a display device with a narrow bezel and a high-density PPI.

[0175] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0176] It should be understood that the display device according to the embodiment of the present disclosure has all the characteristics and advantages of the above-mentioned display substrate. Please refer to the above description for details, which will not be repeated here.

[0177] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0178] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, Comprising: Gate signal lines, including a first gate signal line and a second gate signal line, each of the first gate signal line and the second gate signal line is applied with a first voltage, and the first gate signal line and the second gate signal line are spaced apart from each other; A first gate driving unit and a second gate driving unit, both the first gate driving unit and the second gate driving unit include buffer units, The buffer unit includes a first transistor, a second transistor, and an output terminal for outputting a gate control signal; A first electrode of the first transistor and a first electrode of the second transistor are connected to the output terminal, and a second electrode of the first transistor is connected to the gate signal line; A pixel circuit, electrically connected to the output terminal of the buffer unit, the pixel circuit includes a pixel group of odd rows and a pixel group of even rows, and the pixel group includes at least two rows of pixel circuits; The first gate signal line is connected to a second electrode of the first transistor included in the first gate driving unit, so that the first gate driving unit provides a gate control signal for the pixel group of odd rows, The second gate signal line is connected to a second electrode of the first transistor included in the second gate driving unit, so that the second gate driving unit provides a gate control signal for the pixel group of even rows.

2. The display substrate according to claim 1, wherein, Further comprising: A reference gate signal line, the reference gate signal line is applied with a second voltage, and the reference gate signal line is connected to a second pole of the second transistor included in the buffer unit.

3. The display substrate according to claim 2, wherein, The first gate driving unit and the second gate driving unit further both include a scanning unit, and the scanning unit is connected to the gate signal line.

4. The display substrate according to claim 3, wherein, The scanning unit in the first gate driving unit is electrically connected to the first gate signal line; The scanning unit in the second gate driving unit is electrically connected to the second gate signal line.

5. The display substrate according to claim 3, wherein, The scanning unit in the first gate driving unit is electrically connected to the second gate signal line; The scanning unit in the second gate driving unit is electrically connected to the first gate signal line.

6. The display substrate according to claim 3, wherein, The gate signal line further includes a third gate signal line, the third gate signal line is applied with the first voltage, and the third gate signal line is spaced apart from the first gate signal line and the second gate signal line; The third gate signal line is connected to the scanning unit in the first gate driving unit, and The third gate signal line is connected to the scanning unit in the second gate driving unit.

7. The display substrate according to any one of claims 4 to 6, wherein, The reference gate signal line is connected to the scanning unit in the first gate driving unit, and The reference gate signal line is connected to the scanning unit in the second gate driving unit.

8. The display substrate according to claim 6, wherein, The gate signal line includes: A first connection point where the first gate signal line is connected to the first gate driving unit; The second connection point where the second gate signal line is connected to the second gate driving unit; and / or The third connection point where the third gate signal line is connected to the first gate driving unit or the second gate driving unit; and A short - circuit connection point on the gate signal line far from the first connection point, the second connection point, and / or the third connection point to short - circuit connect the first gate signal line, the second gate signal line, and / or the third gate signal line.

9. The display substrate according to claim 8, wherein, At a position on the gate signal line far from the first connection point, the second connection point, and / or the third connection point, a voltage - stabilizing capacitor connected to the first gate signal line, the second gate signal line, and / or the third gate signal line is provided.

10. The display substrate according to claim 9, wherein, The voltage - stabilizing capacitor is arranged between the first connection point, the second connection point, and / or the third connection point and the short - circuit connection point.

11. The display substrate according to claim 10, wherein, The voltage - stabilizing capacitor includes: A first voltage - stabilizing capacitor connected to the first gate signal line; A second voltage - stabilizing capacitor connected to the second gate signal line; and / or A third voltage - stabilizing capacitor connected to the third gate signal line.

12. The display substrate according to claim 11, wherein, The short - circuit connection point is located at the edge of the display area of the display substrate; or The short - circuit connection point is located in the flexible circuit board included in the display substrate; or The short - circuit connection point is located in the driving integrated circuit included in the display substrate.

13. The display substrate according to claim 12, wherein, The voltage - stabilizing capacitor is arranged inside the flexible circuit board included in the display substrate.

14. The display substrate according to any one of claims 1 to 6, 8 to 13, wherein, The first gate signal line includes at least two, and the second gate signal line includes at least two.

15. The display substrate according to claim 1, wherein, Each pixel group in the pixel circuit includes a first - row pixel circuit and a second - row pixel circuit arranged in parallel, The first - row pixel circuit and the second - row pixel circuit include a common N - type gate; The first - row pixel circuit includes a first P - type gate, and the second - row pixel circuit includes a second P - type gate.

16. The display substrate according to claim 15, wherein, The output pole includes a first output pole, a second output pole, and a third output pole; The first output pole is connected to the N - type gate to provide a first gate signal for the N - type gate; The second output pole is connected to the first P - type gate to provide a second gate signal for the first P - type gate; The third output pole is connected to the second P - type gate to provide a third gate signal for the second P - type gate.

17. The display substrate according to claim 16, wherein, The low - voltage signals in the second gate signal and the low - voltage signals in the third gate signal do not overlap in time sequence.

18. The display substrate according to claim 3, wherein, It further includes: A first clock signal line, a second clock signal line, an initial signal line, and a control signal line connected to the scanning unit.

19. The display substrate according to claim 16 or 17, wherein, When the first gate signal line provides a gate control signal to the pixel groups of the odd rows, and when the second gate signal line provides a gate control signal to the pixel groups of the even rows, the timing of the maximum pull-down potential generated by the load of the first gate signal line does not overlap with the timing of the maximum pull-down potential generated by the load of the second gate signal line; The timing of the low voltage signal of the second gate signal and the timing of the low voltage signal of the third gate signal do not overlap with the timing of the maximum pull-down potential generated by the load of the first gate signal line and the timing of the maximum pull-down potential generated by the load of the second gate signal line.

20. A display device, wherein, It includes a display substrate according to any one of claims 1 to 19.

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