Array substrate and preparation method therefor

Abstract

An array substrate and a preparation method therefor. The array substrate comprises a substrate (30), a first conductive layer, a second insulating layer, a first insulating layer, and a third conductive layer; the first conductive layer comprises a first conductive portion (41), and the third conductive layer comprises a third conductive portion (43); the first insulating layer comprises a first through hole (D1), the second insulating layer comprises a second through hole (D2), the orthographic projections of the first through hole (D1) and the second through hole (D2) on the substrate (30) at least partially overlap and are communicated with each other, part of the first conductive portion (41) is located in the second through hole (D2), part of the third conductive portion (43) is located in the first through hole (D1) and the second through hole (D2), and the first conductive portion (41) is in contact with the third conductive portion (43) in the second through hole (D2); and in the plane perpendicular to the substrate (30), the difference between an included angle formed between a hole wall of the first through hole (D1) and the horizontal plane parallel to the substrate (30) and an included angle formed between a hole wall of the second through hole (D2) and the horizontal plane is Δθ, and 0°≤|Δθ|≤|10°.

Description

Array substrate and preparation method thereof Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to an array substrate and a preparation method thereof. Background Art

[0002] Liquid crystal displays (LCDs) are a common type of display. LCDs use two polarized materials with a liquid crystal solution (liquid crystal) between them. Applying a voltage across the two polarized materials causes the liquid crystal to deflect. The degree of deflection can be controlled by controlling the applied voltage. Currently, LCDs are being developed to be lightweight, thin, short, and compact.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide an array substrate and a method for manufacturing the same.

[0006] In one aspect, embodiments of the present disclosure provide an array substrate. The array substrate includes a substrate, a first conductive layer located on one side of the substrate, a second insulating layer located on a side of the first conductive layer away from the substrate, a first insulating layer located on a side of the second insulating layer away from the substrate, and a third conductive layer located on a side of the first insulating layer away from the substrate.

[0007] The first conductive layer includes a first conductive portion, and the third conductive layer includes a third conductive portion; the first insulating layer includes a first through hole, and the second insulating layer includes a second through hole, wherein the orthographic projections of the first through hole and the second through hole on the substrate at least partially overlap, and the first through hole is connected to the second through hole;

[0008] Part of the first conductive portion is located in the second through hole, and part of the third conductive portion is located in the first through hole and the second through hole, and the first conductive portion is in contact with the third conductive portion in the second through hole;

[0009] In a plane perpendicular to the substrate, a difference between angles formed between the hole walls of the first through hole and the second through hole and a horizontal plane parallel to the substrate is Δθ, and 0°≤|Δθ|≤10°.

[0010] In an exemplary embodiment, the first through hole includes a first sidewall; in a plane perpendicular to the substrate, a gap exists between the third conductive portion and the first sidewall, and the gap is greater than 0 nanometers and less than or equal to 50 nanometers.

[0011] In an exemplary embodiment, the second through hole includes a second sidewall; in a plane perpendicular to the substrate, there is a gap between the third conductive portion and the second sidewall, and the gap is greater than 0 nanometers and less than or equal to 50 nanometers.

[0012] In an exemplary embodiment, the first through hole includes a first sidewall, and the second through hole includes a second sidewall; in a plane perpendicular to the substrate, the first sidewall has a first slope angle with a horizontal plane parallel to the substrate, and the second sidewall has a second slope angle with a horizontal plane parallel to the substrate, and the first slope angle and the second slope angle are both greater than or equal to 40 degrees and less than or equal to 50 degrees.

[0013] In an exemplary embodiment, the first through hole includes a first sidewall, at least a portion of which protrudes toward the center of the first through hole to form a bulging structure, and a size range of the bulging structure along the radial direction of the first through hole is greater than 0 nanometers and less than or equal to 50 nanometers.

[0014] In an exemplary embodiment, the first through hole includes a first sidewall, and the third conductive portion contacts the entire first sidewall.

[0015] In an exemplary embodiment, at least a portion of the first side wall is an inclined plane.

[0016] In an exemplary embodiment, the first through hole includes a first sidewall, and the second through hole includes a second sidewall; in a plane perpendicular to the substrate, there is a gap between the third conductive portion and the first sidewall, the gap is greater than 0 nanometers and less than or equal to 50 nanometers, and the third conductive portion is in contact with at least a portion of the second sidewall.

[0017] In an exemplary embodiment, in a plane perpendicular to the substrate, a gap exists between the third conductive portion and the second sidewall, and the gap is greater than 0 nanometers and less than or equal to 50 nanometers.

[0018] In an exemplary embodiment, the array substrate includes a display area and a non-display area located at least on one side of the display area, and the first through hole and the second through hole are both located in the non-display area.

[0019] In one exemplary embodiment, a material of the first insulating layer includes silicon oxide, and a material of the second insulating layer includes silicon nitride.

[0020] In an exemplary embodiment, the first through hole includes a first sidewall, and at least a portion of the first sidewall is made of a carbon compound.

[0021] In another aspect, an embodiment of the present disclosure provides a method for preparing an array substrate, comprising:

[0022] forming a first conductive layer on one side of the substrate, wherein the first conductive layer includes at least one first conductive portion;

[0023] forming a second insulating film on a side of the first conductive layer away from the substrate;

[0024] forming a first insulating film on a side of the second insulating film away from the substrate, patterning the first insulating film and the second insulating film through a patterning process to form a first insulating layer and a second insulating layer, respectively, wherein the first insulating layer includes a first through hole, and the second insulating layer includes a second through hole, wherein orthographic projections of the first through hole and the second through hole on the substrate at least partially overlap, and the first through hole is connected to the second through hole;

[0025] forming a third conductive layer on a side of the first insulating layer away from the substrate, the third conductive layer comprising at least one third conductive portion;

[0026] Part of the first conductive portion is located in the second through hole, part of the third conductive portion is located in the first through hole and the second through hole, and the first conductive portion is in contact with the third conductive portion in the second through hole; in a plane perpendicular to the substrate, the difference between the angles formed by the hole walls of the first through hole and the second through hole and the horizontal plane parallel to the substrate is Δθ, and 0°≤|Δθ|≤10°.

[0027] In an exemplary embodiment, patterning the first insulating film and the second insulating film by a patterning process to form the first insulating layer and the second insulating layer respectively includes:

[0028] forming a photoresist layer on a side of the first insulating film away from the substrate;

[0029] The photoresist layer is exposed using a mask to form a photoresist pattern, wherein the photoresist pattern includes a covered area and a hollow area, wherein the covered area includes a third top wall, a third bottom wall, and a third side wall connecting the third top wall and the third bottom wall, wherein the third top wall is farther away from the substrate than the third bottom wall, and a slope angle is formed between the third side wall and the third bottom wall, wherein the slope angle is greater than or equal to 80 degrees and less than or equal to 90 degrees.

[0030] In an exemplary embodiment, patterning the first insulating film and the second insulating film by a patterning process to form the first insulating layer and the second insulating layer respectively includes:

[0031] A two-step etching process is performed on the first insulating film and the second insulating film to form the first through hole and the second through hole.

[0032] In an exemplary embodiment, the two-step etching process includes a first etching step and a second etching step, the oxygen in the etching gas used in the first etching step has a first content ratio, and the oxygen in the etching gas used in the second etching step has a second content ratio, and the first content ratio is different from the second content ratio.

[0033] In an exemplary embodiment, the second content ratio is greater than the first content ratio.

[0034] In an exemplary embodiment, the first content ratio ranges from 20% to 30%, and the second content ratio ranges from 30% to 40%.

[0035] In an exemplary embodiment, the supply rate of oxygen in the first etching step ranges from 250 ml / min to 350 ml / min; and the supply rate of oxygen in the second etching step ranges from 450 ml / min to 550 ml / min.

[0036] In an exemplary embodiment, patterning the first insulating film and the second insulating film by a patterning process to form the first insulating layer and the second insulating layer respectively further includes:

[0037] The substrate on which the first insulating layer and the second insulating layer are formed is baked, wherein the baking temperature ranges from 128 degrees Celsius to 132 degrees Celsius, and the baking time ranges from 105 seconds to 110 seconds.

[0038] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0039] Summary of the Figures

[0040] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0041] FIG1 is a schematic front view of an array substrate according to an embodiment of the present disclosure;

[0042] FIG2 is a partial top view of an array substrate according to an embodiment of the present disclosure;

[0043] FIG2A is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0044] FIG3 is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0045] FIG4 is a partial cross-sectional schematic diagram of a conductive structure according to an embodiment of the present disclosure;

[0046] FIG5 is a partial cross-sectional schematic diagram 1 of a conductive structure according to another embodiment of the present disclosure;

[0047] FIG6 is a second partial cross-sectional diagram of a conductive structure according to another embodiment of the present disclosure;

[0048] FIG7 is a third partial cross-sectional diagram of a conductive structure according to another embodiment of the present disclosure;

[0049] FIG8 is a fourth partial cross-sectional diagram of a conductive structure according to another embodiment of the present disclosure;

[0050] FIG9 is a fifth partial cross-sectional diagram of a conductive structure according to another embodiment of the present disclosure;

[0051] FIG10 is a partial cross-sectional schematic diagram 1 of a conductive structure according to another embodiment of the present disclosure;

[0052] FIG11 is a second partial cross-sectional diagram of a conductive structure according to another embodiment of the present disclosure;

[0053] FIG12 is a third partial cross-sectional diagram of a conductive structure according to another embodiment of the present disclosure;

[0054] FIG13 is a partial cross-sectional schematic diagram of a conductive structure according to yet another embodiment of the present disclosure;

[0055] 14A to 14J are schematic diagrams of a process for preparing an array substrate according to an embodiment of the present disclosure.

[0056] Reference numerals:

[0057] 10-pixel electrode, 11-buffer layer, 12-gate insulating layer, 12-1-second insulating film, 12-2-initial pattern of gate insulating layer, 13-first passivation layer, 13-1-third insulating film, 13-2-initial pattern of first passivation layer, 14-planarization layer, 14-1-fourth insulating film, 15-second passivation layer, 16-active layer, 16-1-first region, 16-2-second region, 16-3-channel region, 17-gate, 18-common electrode, 20-transistor, 30-substrate, 40-conductive structure, 41-first conductive portion, 42-second conductive portion, 43-third conductive portion, 50-protrusion structure;

[0058] 60 - photoresist layer, 70 - ultraviolet light, 80 - photoresist pattern, 80 - 1 - covered area, 80 - 2 - hollow area, 80 - 3 - third top wall, 80 - 4 - third bottom wall, 80 - 5 - third side wall;

[0059] D11-first top wall, D12-first bottom wall, D13-first side wall, D13-1-first part, D13-2-second part, D13-3-slant area, D13-4-curved area, D21-second top wall, D22-second bottom wall, D23-second side wall.

[0060] Details

[0061] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0062] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0063] The ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion among constituent elements, and are not intended to limit the number. The "plurality" in this disclosure includes two or more.

[0064] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0065] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0066] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0067] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0068] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged.

[0069] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0070] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0071] In the present disclosure, “about” and “approximately” refer to values ​​that are not strictly defined but allow for process and measurement errors.

[0072] The triangles, rectangles, trapezoids, pentagons or hexagons in the present disclosure are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0073] An embodiment of the present disclosure provides an array substrate. The array substrate includes a substrate, a first conductive layer located on one side of the substrate, a second insulating layer located on a side of the first conductive layer away from the substrate, a first insulating layer located on a side of the second insulating layer away from the substrate, and a third conductive layer located on a side of the first insulating layer away from the substrate.

[0074] The first conductive layer includes a first conductive portion, and the third conductive layer includes a third conductive portion; the first insulating layer includes a first through hole, and the second insulating layer includes a second through hole, wherein the orthographic projections of the first through hole and the second through hole on the substrate at least partially overlap, and the first through hole is connected to the second through hole;

[0075] Part of the first conductive portion is located in the second through hole, and part of the third conductive portion is located in the first through hole and the second through hole, and the first conductive portion is in contact with the third conductive portion in the second through hole;

[0076] In a plane perpendicular to the substrate, a difference between angles formed between the hole walls of the first through hole and the second through hole and a horizontal plane parallel to the substrate is Δθ, and 0°≤|Δθ|≤10°.

[0077] In the embodiment of the present disclosure, by limiting the difference between the angles formed between the hole walls of the first through hole and the second through hole and the horizontal plane parallel to the substrate, a large step difference between the contact parts of the third conductive part and the hole walls of the first through hole and the second through hole can be avoided, and problems such as poor bonding of the third conductive part in the first through hole and the second through hole can be avoided, thereby improving the signal transmission capability of the third conductive part.

[0078] FIG1 is a schematic front view of an array substrate according to an embodiment of the present disclosure. As shown in FIG1 , the array substrate may include a display area AA and a border area BB located on at least one side of the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. For example, the first border area B1 may include the bottom border of the array substrate, and the second border area B2 may include the top border, left border, and right border of the array substrate. In the embodiment of the present disclosure, the border area may also be referred to as a non-display area.

[0079] In one exemplary embodiment, as shown in FIG1 , the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate. The plurality of gate lines GL may extend along a first direction X and be sequentially arranged along a second direction Y different from the first direction X. The plurality of data lines DL may extend along the second direction Y and be sequentially arranged along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located in different film layers; for example, the plurality of data lines DL may be located on a side of the plurality of gate lines GL closer to the substrate.

[0080] In an exemplary embodiment, as shown in FIG1 , a plurality of data lines DL and a plurality of gate lines GL may intersect to form a plurality of sub-pixel areas. The area defined by the intersection of adjacent data lines DL and adjacent gate lines GL may be a sub-pixel area. A sub-pixel may be provided in a corresponding sub-pixel area. The sub-pixel area may include an opening area and a non-opening area surrounding the opening area. The non-opening area may be an area obscured by the black matrix of the opposing substrate of the array substrate, and the opening area may be an area not obscured by the black matrix of the opposing substrate. Adjacent gate lines GL and data lines DL may both be located within the non-opening area. The array substrate of the disclosed embodiment may be used to implement a display function, and the opening area of ​​each sub-pixel area may be configured for display. The non-opening area may surround the opening area and not display. However, the disclosed embodiment is not limited to this. In some examples, the array substrate may be used to implement other functions.

[0081] In one exemplary embodiment, the display area AA may include: a plurality of pixel units disposed on a substrate. At least one pixel unit may include: three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of blue sub-pixel, red sub-pixel, and green sub-pixel. As shown in FIG1 , at least one sub-pixel may include: a pixel electrode 10 and a common electrode (not shown in FIG1 ), and the orthographic projections of the pixel electrode 10 and the common electrode of the sub-pixel on the substrate may partially overlap. The common electrode of the plurality of sub-pixels in the display area AA may be an integral structure. For example, the common electrode may be located on the side of the pixel electrode 10 closest to the substrate. The sub-pixel may also include a transistor 20. The transistor 20 may be located adjacent to the intersection of a data line DL and a gate line GL. The transistor 20 may include a gate, a first electrode, and a second electrode. The gate may be electrically connected to the gate line GL, the first electrode of the transistor 20 may be electrically connected to the data line DL, and the second electrode may be electrically connected to the pixel electrode 10 of a sub-pixel. The transistor 20 may be configured to provide a data signal transmitted by the data line DL to the pixel electrode 10 of the sub-pixel under the control of the gate line GL.

[0082] In an exemplary embodiment, the second border area B2 may include at least a gate drive circuit (e.g., including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected to the plurality of gate lines GL in the display area AA. The gate drive circuit may further include a transistor. The structure of the transistor located in the second border area B2 may be the same as or different from the structure of the transistor located in the display area AA.

[0083] Figure 2 is a partial top view of an array substrate according to an embodiment of the present disclosure. Figure 2A is a partial cross-sectional view of the array substrate according to an embodiment of the present disclosure. Figure 2A is a cross-sectional view taken along line AA in Figure 2. As shown in Figure 2A, in the present embodiment, a direction perpendicular to the plane of the array substrate is defined as a third direction Z. The third direction Z may also be referred to as the thickness direction of the array substrate. As shown in Figures 2 and 2A, the array substrate may include a substrate 30, and a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on one side of the substrate 30. The array substrate may further include a buffer layer 11 located between the substrate 30 and the first conductive layer, a gate insulating layer 12 located between the first conductive layer and the second conductive layer, a first passivation layer 13 located between the second conductive layer and the third conductive layer, a planarizing layer 14 located between the third conductive layer and the fourth conductive layer, and a second passivation layer 15 located between the fourth conductive layer and the fifth conductive layer. In the present embodiment, the first passivation layer may also be referred to as the first insulating layer, and the gate insulating layer may also be referred to as the second insulating layer.

[0084] As shown in FIG2A , the second border region B2 may include a plurality of conductive structures 40. For example, the conductive structure 40 may be configured to connect a gate line to a gate driver. The conductive structure 40 may include a first conductive portion 41, a second conductive portion 42, and a third conductive portion 43. The first conductive portion 41 may be located in a first conductive layer, the second conductive portion 42 may be located in a second conductive layer, and the third conductive portion 43 may be located in a third conductive layer. The conductive structure 40 uses a multi-layer routing method to reduce resistance and improve signal transmission capability.

[0085] As shown in Figure 2A, the first passivation layer 13 may have a plurality of vias, and the plurality of vias may include at least a first via K1 and a second via K2. The first via K1 exposes at least a portion of the surface of the first conductive portion 41 away from the substrate 30, and the second via K2 exposes at least a portion of the surface of the second conductive portion 42 away from the substrate 30. A portion of the third conductive portion 43 may be located within the first via K1 and in contact with at least a portion of the surface of the first conductive portion 41 away from the substrate 30. A portion of the third conductive portion 43 may be located within the second via K2 and in contact with at least a portion of the surface of the second conductive portion 42 away from the substrate 30. For example, the first conductive portion 41 may be configured to be connected to a gate driver, and the gate driver may provide a scan signal to the sub-pixels in the display area. The second conductive portion 42 may be configured to be connected to a gate line.

[0086] In an exemplary embodiment, the first via hole K1 and the second via hole K2 can be manufactured using the same patterning process, which can simplify the manufacturing process of the array substrate, shorten the manufacturing cycle of the array substrate, and reduce the manufacturing cost of the array substrate.

[0087] In an exemplary embodiment, the substrate 30 may be a transparent substrate. For example, the substrate 30 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. However, the present disclosure is not limited to this.

[0088] In an exemplary embodiment, the materials of the buffer layer 11, the gate insulating layer 12, the first passivation layer 13 and the second passivation layer 15 may be inorganic materials. For example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x ) or silicon oxide (SiO x The buffer layer 11, the gate insulating layer 12, the first passivation layer 13 and the second passivation layer 15 may be a single layer or a multi-layer or composite layer structure.

[0089] In an exemplary embodiment, the gate insulating layer 12 and the first passivation layer 13 are made of different materials. For example, the gate insulating layer 12 may include silicon nitride (SiN x ), the material of the first passivation layer 13 may include silicon oxide (SiO x ).

[0090] In one exemplary embodiment, the planarization layer 14 can be made of an organic material. Examples of such organic materials include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, and polyether resin. Planarization layer 14 can be a single layer, a multi-layer structure, or a composite layer. In the disclosed embodiment, providing an insulating layer of organic material can reduce crosstalk from the gate to the common electrode.

[0091] In an exemplary embodiment, the materials of the first conductive layer, the second conductive layer, and the fourth conductive layer can be metal materials, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the materials of the first conductive layer, the second conductive layer, and the fourth conductive layer can be alloy materials of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), and molybdenum-nickel-titanium alloy (MoNiTi). The first conductive layer, the second conductive layer, and the fourth conductive layer can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi, etc.

[0092] In one exemplary embodiment, the third and fifth conductive layers may be made of a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the third and fifth conductive layers may be single-layer structures or multi-layer composite structures, such as ITO / Al / ITO. Using a transparent conductive oxide material for the conductive layer can improve the conductive layer's climbing ability, resulting in a more stable connection reliability between the third conductive portion 43 and the pixel electrode 10.

[0093] In one exemplary embodiment, as shown in FIG2A , the display area AA may include multiple transistors 20, multiple data lines DL, multiple gate lines GL, multiple common electrodes 18, and multiple pixel electrodes 10. The transistor 20 may include a stacked active layer 16 and a gate electrode 17. The gate electrode 17 may be located in the second conductive layer, and the active layer 16 may be located on a side of the second conductive layer closer to the substrate 30. For example, the active layer 16 and the first conductive layer may be located on the same layer of the array substrate and fabricated using different patterning processes. Alternatively, the active layer 16 and the first conductive layer may be located on different layers of the array substrate. The active layer 16 may include a channel region 16-3, a first region 16-1, and a second region 16-2 located on opposite sides of the channel region 16-3. For example, during the fabrication of the array substrate, a portion of the active layer 16 may be subjected to a conductorization process so that portions of the active layer 16 form the first region 16-1 and the second region 16-2, respectively. The first region 16-1 of the active layer 16 can be used as the first electrode of the transistor, and the second region 16-2 of the active layer 16 can be used as the second electrode of the transistor. By partially conducting the active layer to form the first and second electrodes of the transistor, the area of ​​the transistor gate can be reduced, thereby preventing the gate from affecting the aperture ratio of the display area and improving the aperture ratio of the display area.

[0094] In an exemplary embodiment, as shown in Figure 2A, the orthographic projection of the gate 17 on the plane where the array substrate is located may at least partially overlap with the orthographic projection of the channel region 16-3 on the plane where the array substrate is located. The gate may block at least part of the influence of light on the channel region, thereby improving the performance of the transistor.

[0095] In an exemplary embodiment, as shown in FIG2A , the fourth conductive layer may include a plurality of common electrodes 18, and the fifth conductive layer may include a plurality of pixel electrodes 10. The orthographic projections of the common electrodes 18 on the plane where the array substrate is located may partially overlap with the orthographic projections of the pixel electrodes 10 on the plane where the array substrate is located. In the disclosed embodiment, the pixel electrode may also be referred to as the first electrode of a sub-pixel, and the common electrode may also be referred to as the second electrode of a sub-pixel. Alternatively, the pixel electrode may also be referred to as the second electrode of a sub-pixel, and the common electrode may also be referred to as the first electrode of a sub-pixel.

[0096] In one exemplary embodiment, the thickness of the first passivation layer 13 may range from 2000 angstroms to 3000 angstroms.

[0097] In an exemplary embodiment, the thickness of the third conductive portion 43 may range from 400 angstroms to 700 angstroms.

[0098] Figure 3 is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure. As shown in Figure 3, the second border area B2 may include a plurality of conductive structures 40. For example, the conductive structure 40 may be configured to connect the gate line and the gate driver. The conductive structure 40 may include a first conductive portion 41 and a third conductive portion 43. The first conductive portion 41 may be located in the first conductive layer, and the third conductive portion 43 may be located in the third conductive layer. For example, the first conductive portion 41 may be configured to be connected to the gate line, and the third conductive portion 43 may be configured to be connected to the gate driver. In the embodiment of the present disclosure, there is no limitation on the actual type of signal line for achieving electrical connection using the conductive structure.

[0099] Figure 4 is a partial cross-sectional schematic diagram of a conductive structure according to an embodiment of the present disclosure. As shown in Figure 4 , the first passivation layer 13 may have a plurality of first through holes D1, which extend through the first passivation layer 13 along a third direction Z. As shown in Figure 4 , the gate insulation layer 12 may have a plurality of second through holes D2, which extend through the gate insulation layer 12 along a third direction Z. A first via K1 may include one first through hole D1 and one second through hole D2, which are connected.

[0100] As shown in FIG4 , the first through hole D1 may include a first top wall D11 and a first bottom wall D12 that are oppositely disposed, and a first side wall D13 connecting the first top wall D11 and the first bottom wall D12. The first top wall D11 is farther from the first conductive portion 41 than the first bottom wall D12. The first side wall D13 and the first bottom wall D12 have a first slope angle α1 therebetween. The first slope angle α1 may be greater than or equal to 40 degrees and less than or equal to 50 degrees. For example, the first slope angle α1 may be 45 degrees. For example, the first bottom wall D12 may be parallel to the plane on which the array substrate is located.

[0101] The second through hole D2 may include an oppositely disposed second top wall D21, a second bottom wall D22, and a second side wall D23 connecting the second top wall D21 and the second bottom wall D22. The first bottom wall D12 and the second top wall D21 may be coplanar, with the second top wall D21 being further away from the first conductive portion 41 than the second bottom wall D22. A second slope angle α2 is formed between the second side wall D23 and the second bottom wall D22. The second slope angle α2 may be greater than or equal to 40 degrees and less than or equal to 50 degrees. For example, the second slope angle α2 may be 45 degrees. For example, the second bottom wall D22 may be parallel to the plane of the array substrate.

[0102] In one exemplary embodiment, the first slope angle α1 is less than or equal to the second slope angle α2, which facilitates signal transmission from the third conductive portion 43 to the first conductive portion 41, thereby improving the overall signal transmission capability of the conductive structure 40. The absolute value of the angle difference between the first slope angle α1 and the second slope angle α2 can be less than or equal to 10 degrees. In the disclosed embodiment, the angle difference between the first slope angle α1 and the second slope angle α2 can be denoted as Δθ.

[0103] In an exemplary embodiment, the roughness (Ra) of the first sidewall D13 may be in a range of 0.1 micrometers to 0.2 micrometers.

[0104] In an exemplary embodiment, the roughness (Ra) of the second sidewall D23 may be in a range of 0.1 micrometers to 0.2 micrometers.

[0105] In an exemplary embodiment, the first sidewall D13 and the second sidewall D23 may be coplanar.

[0106] In an exemplary embodiment, the first top wall D11 and the first bottom wall D12 may be parallel to each other. The second top wall D21 and the second bottom wall D22 may be parallel to each other.

[0107] In an exemplary embodiment, the flatness of the first top wall D11 may be greater than that of the first bottom wall D12 , which is beneficial for increasing the contact area between the third conductive portion 43 and the first passivation layer 13 and improving the connection strength between the two.

[0108] In one exemplary embodiment, the first side wall D13 has a first end and a second end that are oppositely disposed, with the second end of the first side wall D13 being closer to the second side wall D23 than the first end of the first side wall D13. The second side wall D23 has a first end and a second end that are oppositely disposed, with the first end of the second side wall D23 being closer to the first side wall D13 than the second end of the second side wall D23. The second end of the first side wall D13 and the first end of the second side wall D23 are smoothly connected, thereby avoiding a large step difference at the connection between the first side wall D13 and the second side wall D23, and preventing problems such as poor bonding of the third conductive portion 43 at this connection.

[0109] In an exemplary embodiment, the second through hole may have a diameter ranging from 4.0 microns to 5.0 microns, and in an exemplary embodiment, the diameter of the second through hole may be 4.5 microns. The second through hole may have a depth ranging from 0.8 microns to 1.2 microns, and in an exemplary embodiment, the depth of the second through hole may be 1.0 micron.

[0110] FIG5 is a partial cross-sectional schematic diagram of a conductive structure according to another embodiment of the present disclosure. As shown in FIG5 , at least a portion of the first side wall D13 may be a curved surface. As shown in FIG5 , the third conductive portion 43 is in contact with and cooperates with the first side wall D13. As shown in FIG5 , the second side wall D23 may be an inclined plane. The first side wall D13 has a first end and a second end that are relatively disposed, and the second end of the first side wall D13 is closer to the second side wall D23 than the first end of the first side wall D13. The second side wall D23 has a first end and a second end that are relatively disposed, and the first end of the second side wall D23 is closer to the first side wall D13 than the second end of the second side wall D23. The second end of the first side wall D13 and the first end of the second side wall D23 are smoothly connected, which can avoid a large step difference at the connection between the first side wall D13 and the second side wall D23, and can avoid problems such as poor bonding of the third conductive portion 43 at this connection.

[0111] In an exemplary embodiment, a second slope angle α2 is defined between the second side wall D23 and the second bottom wall D22. The second slope angle α2 may have an angle range greater than or equal to 40 degrees and less than or equal to 50 degrees. For example, the second slope angle α2 may be 45 degrees. For example, the second bottom wall D22 may be parallel to the plane on which the array substrate is located. In the embodiments of the present disclosure, taking the first side wall as an example, when the slope angle between the first side wall and the plane on which the array substrate is located is non-single, all angle values ​​of the slope angle between the first side wall and the plane on which the array substrate is located must satisfy the requirement of being greater than or equal to 40 degrees and less than or equal to 50 degrees. Taking the first side wall as an example, when the first side wall has a curved surface, a tangent line drawn through any point on the first side wall in a plane perpendicular to the plane on which the array substrate is located must satisfy the requirement of being greater than or equal to 40 degrees and less than or equal to 50 degrees between the tangent line and the plane on which the array substrate is located.

[0112] FIG6 is a second partial cross-sectional diagram of a conductive structure according to another embodiment of the present disclosure. As shown in FIG6 , the first side wall D13 may be an inclined plane, and a first slope angle α1 is formed between the first side wall D13 and the first bottom wall D12. The first slope angle α1 may be greater than or equal to 40 degrees and less than or equal to 50 degrees. For example, the first slope angle α1 may be 45 degrees. For example, the first bottom wall D12 may be parallel to the plane on which the array substrate is located.

[0113] As shown in Figure 6, a gap L1 may exist between the first side wall D13 and the third conductive portion 43. The range of gap L1 can be greater than or equal to 0 nanometers and less than or equal to 50 nanometers. In the disclosed embodiment, the gap between the first side wall D13 and the third conductive portion 43 is defined as the maximum length of a perpendicular line from any point on the edge of the third conductive portion 43 near the first side wall D13 to the edge of the first side wall D13 near the third conductive portion 43 within the plane formed by the first direction X and the third direction Z. Limiting gap L1 to less than or equal to 50 nanometers can ensure good bonding strength between the third conductive portion 43 and the first side wall D13, and can ensure that the array substrate has high electrical connection reliability. During the preparation of the array substrate, the gate insulating layer 12 and the first passivation layer 13 need to be etched to form a first through hole and a second through hole. After etching, a polymer is usually formed on the hole wall of the first through hole. Before or after the third conductive portion 43 is formed, the polymer may fall off from the hole wall of the first through hole, resulting in a gap between the hole wall of the first through hole and the third conductive portion 43. By limiting the range of the gap, good coverage between the third conductive portion 43 and the first side wall can be ensured to obtain better bonding strength.

[0114] FIG7 is a third partial cross-sectional schematic diagram of a conductive structure according to another embodiment of the present disclosure. As shown in FIG7 , the first side wall D13 may include a first portion D13-1 and a second portion D13-2. The first portion D13-1 may be located between the second portion D13-2 and the third conductive portion 43. At least a portion of the surface of the first portion D13-1 away from the second portion D13-2 is in contact with the third conductive portion 43. For example, the entire surface of the first portion D13-1 away from the second portion D13-2 is in contact with the third conductive portion 43. The surface of the first portion D13-1 in contact with the third conductive portion 43 may be a curved surface. In the embodiment of the present disclosure, the first portion may also be referred to as a raised structure.

[0115] In an exemplary embodiment, the material of the first portion D13-1 is different from the material of the second portion D13-2. For example, the material of the first portion D13-1 may be a polymer. For example, the polymer may include at least a carbon compound. For example, the carbon compound may be (CF2)n, etc., where n represents the degree of polymerization. The material of the second portion D13-2 may be silicon oxide (SiO x ), etc. For example, the silicon oxide may be silicon dioxide.

[0116] FIG8 is a fourth partial cross-sectional schematic diagram of a conductive structure according to another embodiment of the present disclosure. As shown in FIG8 , a gap L2 may exist between the first portion D13-1 and the third conductive portion 43. The gap L2 may range from greater than or equal to 0 nanometers to less than or equal to 50 nanometers. In the embodiment of the present disclosure, the gap between the first portion D13-1 and the third conductive portion 43 is defined as the maximum length from any point on the edge of the third conductive portion 43 near the first portion D13-1 to a perpendicular line drawn from the edge of the first portion D13-1 near the third conductive portion 43 within the plane formed by the first direction X and the third direction Z. Limiting the gap L2 to less than or equal to 50 nanometers ensures good bonding strength between the third conductive portion 43 and the first portion D13-1, and thus ensures high electrical connection reliability for the array substrate.

[0117] Figure 9 is a partial cross-sectional schematic diagram five of the conductive structure of another embodiment of the present disclosure. As shown in Figure 9, the first side wall D13 may include a first portion D13-1 and a second portion D13-2. The first portion D13-1 may be located between the second portion D13-2 and the third conductive portion 43. At least a portion of the surface of the first portion D13-1 away from the second portion D13-2 is in contact with the third conductive portion 43, and there may be a gap L3 between the second portion D13-2 and the third conductive portion 43. The range of the gap L3 may be greater than or equal to 0 nanometers and less than or equal to 50 nanometers.

[0118] Figure 10 is a partial cross-sectional schematic diagram of a conductive structure according to another embodiment of the present disclosure. As shown in Figure 10 , a portion of the first side wall D13 contacts and mates with the third conductive portion 43, and the portion of the first side wall D13 that contacts and mates with the third conductive portion 43 may be an oblique plane. A gap L4 may exist between the first side wall D13 and the third conductive portion 43. The gap L4 may range from greater than or equal to 0 nanometers to less than or equal to 50 nanometers.

[0119] In an exemplary embodiment, a slope angle α may be present between the portion of the first side wall D13 that contacts and cooperates with the third conductive portion 43 and the plane where the array substrate is located. The slope angle α may be greater than or equal to 40 degrees and less than or equal to 50 degrees. For example, the slope angle α may be 45 degrees.

[0120] FIG11 is a second partial cross-sectional schematic diagram of a conductive structure according to another embodiment of the present disclosure. As shown in FIG11 , the first sidewall D13 may include a bevel region D13-3 and a curved region D13-4 connected to each other. The bevel region D13-3 includes a first end and a second end disposed opposite each other. The first end of the bevel region D13-3 may be connected to the first top wall D11, and the second end of the bevel region D13-3 may extend toward the first bottom wall D12. The curved region D13-4 includes a first end and a second end disposed opposite each other. The first end of the curved region D13-4 may be connected to the second end of the bevel region D13-3, and the second end of the curved region D13-4 may extend toward and be connected to the first bottom wall D12.

[0121] In an exemplary embodiment, there may be a slope angle α between the slope area D13-3 and the plane where the array substrate is located. The angle range of the slope angle α may be greater than or equal to 40 degrees and less than or equal to 50 degrees. For example, the slope angle α may be 45 degrees.

[0122] FIG12 is a third partial cross-sectional diagram of a conductive structure according to another embodiment of the present disclosure. As shown in FIG12 , the first sidewall D13 may include a bevel region D13-3 and a curved region D13-4 connected to each other. The material of the bevel region D13-3 may be silicon oxide (SiO x ), etc. For example, the silicon oxide may be silicon dioxide. The material of the curved surface area D13-4 may be a polymer, for example, the polymer may include at least a carbon compound.

[0123] FIG13 is a partial cross-sectional schematic diagram of a conductive structure according to yet another embodiment of the present disclosure. As shown in FIG13 , the array substrate may further include at least one protruding structure 50. The at least one protruding structure 50 may be located at the bottom of the first via hole K1, and the third conductive portion 43 may be in contact with the at least one protruding structure 50. As shown in FIG13 , the plurality of protruding structures 50 may be arranged at intervals along the first direction X.

[0124] In an exemplary embodiment, within the plane defined by the first direction X and the third direction Z, the cross-section of the protrusion structure 50 may be semicircular, trapezoidal, or semi-elliptical.

[0125] In one exemplary embodiment, the height (along the third direction Z) of the protrusion structure 50 may range from 20 nanometers to 30 nanometers.

[0126] The structure of the array substrate is described below using an example of its fabrication process. The "patterning process" referred to in the embodiments of this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials. For organic materials, it includes processes such as organic material coating, mask exposure, and development. The deposition process can be any one or more of sputtering, evaporation, and chemical vapor deposition; the coating process can be any one or more of spray coating, spin coating, and inkjet printing; and the etching process can be any one or more of dry etching and wet etching, although this disclosure does not limit this. A "thin film" refers to a thin layer of a material formed on a substrate using deposition, coating, or other processes. If a "thin film" does not require a patterning process during the entire fabrication process, it can also be referred to as a "layer." If a "thin film" requires a patterning process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning process contains at least one "pattern." The term "A and B in the same layer" as used in this disclosure means that A and B are formed through the same patterning process.

[0127] The preparation process of the array substrate may include the following steps, taking the structure of an array substrate as an example:

[0128] (11) Forming a semiconductor layer pattern. Forming the semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film on one side of the substrate 30, and patterning the semiconductor film through a patterning process to form a semiconductor layer pattern located on a side of the buffer layer 11 away from the substrate 30. The semiconductor layer may include an active layer 16 of a transistor, as shown in FIG14A. The semiconductor layer pattern may be located in the display area AA of the array substrate.

[0129] As shown in FIG14A , forming the semiconductor layer pattern may further include using a mask to partially conduction-process the active layer 16, so that the active layer 16 forms a first region 16-1 and a second region 16-2. The first region 16-1 of the active layer 16 can be used as a first electrode of a transistor, and the second region 16-2 of the active layer 16 can be used as a second electrode of the transistor.

[0130] (12) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include depositing a first conductive film on one side of the substrate 30 having the aforementioned pattern formed thereon, and patterning the first conductive film through a patterning process to form a first conductive layer pattern located on one side of the substrate 30. The first conductive layer may include a plurality of first conductive portions 41, as shown in FIG14B . The plurality of first conductive portions 41 may be located in the second border region B2 of the array substrate.

[0131] (13) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: sequentially depositing a second insulating film 12-1 and a second conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the second conductive film through a patterning process to form a second conductive layer pattern located on the side of the second insulating film 12-1 away from the substrate 30. The second conductive layer may include a plurality of second conductive portions 42, a plurality of gate lines GL, and a plurality of gate electrodes 17. As shown in FIG14C , the plurality of gate lines GL and the plurality of gate electrodes 17 may be located in the display area AA of the array substrate. The plurality of second conductive portions 42 may be located in the second border area B2 of the array substrate.

[0132] As shown in FIG. 14C , the orthographic projection of the first conductive portion 41 on the plane where the array substrate is located does not overlap with the orthographic projection of the second conductive portion 42 on the plane where the array substrate is located.

[0133] As shown in Figure 14C, the orthographic projection of the gate 17 on the plane where the array substrate is located may overlap at least partially with the orthographic projection of the channel region 16-3 on the plane where the array substrate is located. The gate may block at least part of the influence of light on the channel region, thereby improving the performance of the transistor.

[0134] (14) Forming a first passivation layer initial pattern. Forming the first passivation layer initial pattern may include sequentially forming a third insulating film 13-1 and a photoresist layer 60 on one side of the substrate 30 having the aforementioned pattern formed thereon, as shown in FIG14D. For example, the thickness of the photoresist layer 60 may range from 2.5 μm to 3.5 μm.

[0135] Forming the initial pattern of the first passivation layer may also include: using a mask to expose the photoresist layer 60 with ultraviolet light 70 to form a photoresist pattern 80, and then using an etching process to make the second insulating film form the initial pattern 12-2 of the gate insulating layer, and to make the third insulating film 13-1 form the initial pattern 13-2 of the first passivation layer, as shown in Figure 14E, and then stripping the photoresist pattern, as shown in Figure 14F.

[0136] As shown in FIG14E , the photoresist pattern 80 may include a covered area 80-1 and a hollow area 80-2. The covered area 80-1 may surround the hollow area 80-2. The orthographic projection of the hollow area 80-2 on the plane of the array substrate may be circular, rectangular, hexagonal, or elliptical.

[0137] As shown in Figure 14E, the covering area 80-1 may include a third top wall 80-3 and a third bottom wall 80-4 disposed opposite each other, and a third side wall 80-5 connecting the third top wall 80-3 and the third bottom wall 80-4. The third top wall 80-3 is further away from the first passivation layer initial pattern 13-2 than the third bottom wall 80-4. A third slope angle α3 is defined between the third side wall 80-5 and the third bottom wall 80-4. The third slope angle α3 may have an angle range greater than or equal to 80 degrees and less than or equal to 90 degrees. For example, the third slope angle α3 may be 85 degrees. In the disclosed embodiment, by limiting the angle range of the third slope angle α3, the covering area 80-1 can effectively shield the walls of the subsequently formed first via K1, second via K2, and third via K3. This can improve the connection performance between the subsequently formed third conductive portion and the data line and the vias, thereby enhancing the reliability of the electrical connection of the array substrate.

[0138] As shown in FIG14E , the first passivation layer initial pattern 13-2 may have multiple vias, which may include a first via K1, a second via K2, and a third via K3. The third and second insulating films within the first via K1 are both etched away, and the first via K1 exposes at least a portion of the surface of the first conductive portion 41 facing away from the substrate 30. The first via K1 is configured to connect a subsequently formed third conductive portion to the first conductive portion 41 via this via. The third and second insulating films within the second via K2 are etched away, and the second via K2 exposes at least a portion of the surface of the second conductive portion 42 facing away from the substrate 30. The second via K2 is configured to connect a subsequently formed third conductive portion to the second conductive portion 42 via this via. The third and second insulating films within the third via K3 are both etched away, and the third via K3 exposes at least a portion of the surface of the first region 16-1 facing away from the substrate 30. The third via K3 is configured to connect a subsequently formed data line to the first region 16-1 via this via.

[0139] In an exemplary embodiment, the first via K1 can be formed through a two-step etching process. The two-step etching process may include a first etching step and a second etching step. In the first etching step, oxygen has a first content ratio. In the embodiment of the present disclosure, the oxygen content ratio is the percentage of oxygen to the total amount of etching gas, and the etching gas includes oxygen. In the second etching step, oxygen has a second content ratio, and the second content ratio is greater than the first content ratio. The first content ratio can range from 20% to 30%. For example, the first content ratio can be 25%. The second content ratio can range from 30% to 40%. For example, the second content ratio can be 35%, or the second content ratio can be 36%, etc. By setting the first via K1 as a two-step etching process and limiting the oxygen content ratio in the first etching process to be less than the oxygen content ratio in the second etching process, it can be ensured that the photoresist in the covering area 80-1 will not be excessively oxidized, and the covering area 80-1 can better cover the first top wall of the first via hole, and can effectively remove the polymer formed in the etching process, and can ensure the covering contact between the subsequently formed film layer and the via hole, thereby improving the connection performance of the array substrate.

[0140] In an exemplary embodiment, in the first etching step, the supply rate of oxygen gas may be in a range of 250 sccm to 350 sccm. For example, the supply rate of oxygen gas may be 300 sccm.

[0141] In an exemplary embodiment, during the second etching step, the supply rate of oxygen gas may be in a range of 450 sccm to 550 sccm. For example, the supply rate of oxygen gas may be 500 sccm.

[0142] In an exemplary embodiment, the etching gas may include tetrafluoromethane (CF4), etc. For example, the supply rate of tetrafluoromethane may range from 850 sccm to 950 sccm, and for example, the supply rate of tetrafluoromethane may be 900 sccm.

[0143] In an exemplary embodiment, forming the first passivation layer preliminary pattern may further include baking the first passivation layer preliminary pattern at a temperature ranging from 128 degrees Celsius to 132 degrees Celsius for a time ranging from 105 seconds to 110 seconds. For example, the first passivation layer preliminary pattern may be baked at 130 degrees Celsius for 108 seconds.

[0144] In an exemplary embodiment, the adhesive material of the photoresist layer 60 may include a photosensitive resin, an additive, a solvent, and the like.

[0145] (15) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on the side of the first passivation layer initial pattern 13-2 away from the substrate 30. The third conductive layer may include a plurality of third conductive portions 43 and a plurality of data lines DL, as shown in FIG14G.

[0146] 14G , the third conductive portion 43 may be connected to the first conductive portion 41 via the first via K1 and to the second conductive portion 42 via the second via K2. The data line DL may be connected to the first region 16-1 via the third via K3.

[0147] (16) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include sequentially depositing a fourth insulating film 14-1 and a fourth conductive film on one side of the substrate 30 having the aforementioned pattern formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern located on a side of the fourth insulating film 14-1 away from the substrate 30. The fourth conductive layer may include a common electrode 18, as shown in FIG14H.

[0148] (17) Forming a second passivation layer pattern. Forming the second passivation layer pattern may include depositing a fifth insulating film on one side of the substrate 30 having the aforementioned pattern formed thereon, and patterning the fifth insulating film through a patterning process to form a second passivation layer pattern located on a side of the fourth conductive layer away from the substrate 30. The second passivation layer 15 may include a plurality of connecting holes K4, as shown in FIG14I.

[0149] As shown in Figure 14I, the fifth insulating film, the fourth insulating film, the third insulating film and the second insulating film located in the connecting hole K4 are all etched away, and at least part of the surface of the second area 16-2 away from the substrate 30 is exposed. The connecting hole K4 is configured so that the pixel electrode formed subsequently is connected to the second area 16-2 via the connecting hole.

[0150] (18) Forming a fifth conductive layer pattern. Forming the fifth conductive layer pattern may include depositing a fifth conductive film on one side of the substrate 30 having the aforementioned pattern formed thereon, and patterning the fifth conductive film through a patterning process to form a fifth conductive layer pattern located on a side of the second passivation layer 15 away from the substrate 30. The fifth conductive layer may include a pixel electrode 10, as shown in FIG14J.

[0151] As shown in FIG. 14J , a portion of the pixel electrode 10 may be located within the communication hole K4 and connected to the second region 16 - 2 .

[0152] The present disclosure also provides a method for preparing an array substrate, including:

[0153] forming a first conductive layer on one side of the substrate, wherein the first conductive layer includes at least one first conductive portion;

[0154] forming a second insulating film on a side of the first conductive layer away from the substrate;

[0155] forming a first insulating film on a side of the second insulating film away from the substrate, patterning the first insulating film and the second insulating film through a patterning process to form a first insulating layer and a second insulating layer, respectively, wherein the first insulating layer includes a first through hole, and the second insulating layer includes a second through hole, wherein orthographic projections of the first through hole and the second through hole on the substrate at least partially overlap, and the first through hole is connected to the second through hole;

[0156] forming a third conductive layer on a side of the first insulating layer away from the substrate, the third conductive layer comprising at least one third conductive portion;

[0157] Part of the first conductive portion is located in the second through hole, part of the third conductive portion is located in the first through hole and the second through hole, and the first conductive portion is in contact with the third conductive portion in the second through hole; in a plane perpendicular to the substrate, the difference between the angles formed by the hole walls of the first through hole and the second through hole and the horizontal plane parallel to the substrate is Δθ, and 0°≤|Δθ|≤10°.

[0158] In an exemplary embodiment, patterning the first insulating film and the second insulating film by a patterning process to form the first insulating layer and the second insulating layer respectively includes:

[0159] forming a photoresist layer on a side of the first insulating film away from the substrate;

[0160] The photoresist layer is exposed using a mask to form a photoresist pattern, wherein the photoresist pattern includes a covered area and a hollow area, wherein the covered area includes a third top wall, a third bottom wall, and a third side wall connecting the third top wall and the third bottom wall, wherein the third top wall is farther away from the substrate than the third bottom wall, and a slope angle is formed between the third side wall and the third bottom wall, wherein the slope angle is greater than or equal to 80 degrees and less than or equal to 90 degrees.

[0161] In an exemplary embodiment, patterning the first insulating film and the second insulating film by a patterning process to form the first insulating layer and the second insulating layer respectively includes:

[0162] A two-step etching process is performed on the first insulating film and the second insulating film to form the first through hole and the second through hole.

[0163] In an exemplary embodiment, the two-step etching process includes a first etching step and a second etching step, the oxygen in the etching gas used in the first etching step has a first content ratio, and the oxygen in the etching gas used in the second etching step has a second content ratio, and the first content ratio is different from the second content ratio.

[0164] In an exemplary embodiment, the second content ratio is greater than the first content ratio.

[0165] In an exemplary embodiment, the first content ratio ranges from 20% to 30%, and the second content ratio ranges from 30% to 40%.

[0166] In an exemplary embodiment, the supply rate of oxygen in the first etching step ranges from 250 ml / min to 350 ml / min; and the supply rate of oxygen in the second etching step ranges from 450 ml / min to 550 ml / min.

[0167] In an exemplary embodiment, patterning the first insulating film and the second insulating film by a patterning process to form the first insulating layer and the second insulating layer respectively further includes:

[0168] The substrate on which the first insulating layer and the second insulating layer are formed is baked, wherein the baking temperature ranges from 128 degrees Celsius to 132 degrees Celsius, and the baking time ranges from 105 seconds to 110 seconds.

[0169] The present disclosure also provides a display device. The display device includes the array substrate described in any of the preceding embodiments. The display device can be any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. The present disclosure is not limited thereto.

[0170] Although the embodiments disclosed herein are as described above, the contents described are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementations without departing from the scope of the present disclosure.

Claims

1. An array substrate, comprising a substrate, a first conductive layer on one side of the substrate, a second insulating layer on a side of the first conductive layer away from the substrate, a first insulating layer on a side of the second insulating layer away from the substrate, and a third conductive layer on a side of the first insulating layer away from the substrate; The first conductive layer includes a first conductive portion, and the third conductive layer includes a third conductive portion; the first insulating layer includes a first through hole, and the second insulating layer includes a second through hole. A positive projection of the first through hole and the second through hole on the substrate at least partially overlaps, and the first through hole communicates with the second through hole; A part of the first conductive portion is located in the second through hole, a part of the third conductive portion is located in the first through hole and the second through hole, and the first conductive portion contacts the third conductive portion in the second through hole; In a plane perpendicular to the substrate, a difference in an included angle formed between a hole wall of the first through hole and the second through hole and a horizontal plane parallel to the substrate is Δθ, and 0° ≤ |Δθ| ≤ 10°; 2. The array substrate according to claim 1, wherein, The first through hole includes a first side wall; in a plane perpendicular to the substrate, there is a gap between the third conductive portion and the first side wall, and the gap is greater than 0 nanometers and less than or equal to 50 nanometers; 3. The array substrate according to claim 1, wherein, The second through hole includes a second side wall; in a plane perpendicular to the substrate, there is a gap between the third conductive portion and the second side wall, and the gap is greater than 0 nanometers and less than or equal to 50 nanometers; 4. The array substrate according to claim 1, wherein, The first through hole includes a first side wall, and the second through hole includes a second side wall; in a plane perpendicular to the substrate, a first slope angle is formed between the first side wall and a horizontal plane parallel to the substrate, a second slope angle is formed between the second side wall and a horizontal plane parallel to the substrate, and both the first slope angle and the second slope angle are greater than or equal to 40 degrees and less than or equal to 50 degrees; 5. The array substrate according to claim 1, wherein, The first through hole includes a first side wall, and at least a part of the first side wall bulges towards the center of the first through hole to form a bulging structure, and a dimension range of the bulging structure in a radial direction of the first through hole is greater than 0 nanometers and less than or equal to 50 nanometers; 6. The array substrate according to claim 1, wherein, The first through hole includes a first side wall, and the third conductive portion is in full contact with the first side wall; 7. The array substrate according to claim 6, wherein, At least a part of the first side wall is an inclined plane; 8. The array substrate according to claim 1, wherein, The first through hole includes a first side wall, and the second through hole includes a second side wall; in a plane perpendicular to the substrate, there is a gap between the third conductive portion and the first side wall, and the gap is greater than 0 nanometers and less than or equal to 50 nanometers, and at least a part of the third conductive portion contacts the second side wall; 9. The array substrate according to claim 8, wherein, In a plane perpendicular to the substrate, there is a gap between the third conductive portion and the second side wall, and the gap is greater than 0 nanometers and less than or equal to 50 nanometers; 10. The array substrate according to any one of claims 1 to 9, wherein, The array substrate includes a display area and a non-display area on at least one side of the display area, and both the first through hole and the second through hole are located in the non-display area.

11. The array substrate according to any one of claims 1 to 9, wherein, The material of the first insulating layer includes silicon oxide, and the material of the second insulating layer includes silicon nitride.

12. The array substrate according to any one of claims 1 to 9, wherein, The first through hole includes a first sidewall, and at least part of the material of the first sidewall includes a carbon compound.

13. A method for manufacturing an array substrate, comprising: forming a first conductive layer on one side of a substrate, the first conductive layer including at least one first conductive portion; forming a second insulating film on a side of the first conductive layer away from the substrate; forming a first insulating film on a side of the second insulating film away from the substrate, and patterning the first insulating film and the second insulating film through a patterning process to respectively form a first insulating layer and a second insulating layer. The first insulating layer includes a first through hole, and the second insulating layer includes a second through hole. The orthographic projections of the first through hole and the second through hole on the substrate at least partially overlap, and the first through hole communicates with the second through hole; forming a third conductive layer on a side of the first insulating layer away from the substrate, the third conductive layer including at least one third conductive portion; wherein, a part of the first conductive portion is located in the second through hole, a part of the third conductive portion is located in the first through hole and the second through hole, and the first conductive portion contacts the third conductive portion in the second through hole; in a plane perpendicular to the substrate, the difference in the included angle formed between the hole walls of the first through hole and the second through hole and a horizontal plane parallel to the substrate is Δθ, and 0° ≤ |Δθ| ≤ 10°.

14. The manufacturing method of the array substrate according to claim 13, wherein, The patterning of the first insulating film and the second insulating film through a patterning process to respectively form the first insulating layer and the second insulating layer includes: forming a photoresist layer on a side of the first insulating film away from the substrate; exposing the photoresist layer using a mask to form a photoresist pattern. The photoresist pattern includes a covered area and a hollowed area. The covered area includes a third top wall, a third bottom wall arranged oppositely, and a third sidewall connecting the third top wall and the third bottom wall. The third top wall is farther from the substrate than the third bottom wall, and there is a slope angle between the third sidewall and the third bottom wall. The range of the slope angle is greater than or equal to 80 degrees and less than or equal to 90 degrees.

15. The method for preparing an array substrate according to claim 13, wherein, The patterning of the first insulating film and the second insulating film through a patterning process to respectively form the first insulating layer and the second insulating layer includes: performing a two-step etching process on the first insulating film and the second insulating film to obtain the first through hole and the second through hole.

16. The method for preparing an array substrate according to claim 15, wherein, The two-step etching process includes a first etching step and a second etching step. The oxygen in the etching gas used in the first etching step has a first content ratio, and the oxygen in the etching gas used in the second etching step has a second content ratio. The first content ratio is different from the second content ratio.

17. The method for preparing an array substrate according to claim 16, wherein, The second content ratio is greater than the first content ratio.

18. The manufacturing method of the array substrate according to claim 16, wherein, The range of the first content ratio is from 20% to 30%, and the range of the second content ratio is from 30% to 40%.

19. The method for preparing an array substrate according to claim 16, wherein, The supply rate range of oxygen in the first etching step is from 250 milliliters per minute to 350 milliliters per minute; the supply rate range of oxygen in the second etching step is from 450 milliliters per minute to 550 milliliters per minute.

20. The method for preparing an array substrate according to claim 13, wherein, The patterning of the first insulating film and the second insulating film by the patterning process to form the first insulating layer and the second insulating layer respectively further includes: Baking the substrate on which the first insulating layer and the second insulating layer are formed, the baking temperature range is from 128 degrees Celsius to 132 degrees Celsius, and the baking time range is from 105 seconds to 110 seconds.

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