Driving backplane, display panel and display device

Abstract

A driving backplane, comprising a substrate and a first transistor. The first transistor comprises an active layer, a gate insulating layer, a gate electrode, a first electrode and a second electrode, wherein an intermediate dielectric layer is further disposed between the gate electrode and the first and second electrodes; the orthographic projections of the first and second electrodes on the substrate are located at two opposite ends of the orthographic projection of the active layer on the substrate; the active layer is made of an oxide semiconductor material; the gate insulating layer comprises a first portion and second portions; the first portion overlaps with the orthographic projections of the gate electrode and the active layer on the substrate; the second portions do not overlap with the orthographic projection of the gate electrode and overlap with the orthographic projection of the active layer on the substrate; the second portions are located on two opposite sides of the first portion; the first electrode and the second electrode are separately electrically connected to the active layer by means of vias formed in the intermediate dielectric layer and the second portions; and the average value of the distances between all points on a surface of the side of the first portion facing away from the substrate and the active layer is greater than the average value of the distances between all points on a surface of the side of each second portion facing away from the substrate and the active layer.

Description

Driving backplane, display panel and display device Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and particularly relate to a driving backplane, a display panel, and a display device. Background Art

[0002] Since its introduction, oxide semiconductor (IGZO as a representative) display backplane technology has rapidly gained widespread attention and developed rapidly. Oxide semiconductor thin-film transistors play an important role in the preparation of LCD (Liquid Crystal Display) panels and OLED (Organic Light-Emitting Diode) panels due to their low leakage current, low preparation cost, low manufacturing process temperature and applicability to large-scale tenth-generation lines. In particular, the rise of LTPO (Low Temperature Polycrystalline Oxide) display backplane technology in recent years has made the application of oxide semiconductor display backplane technology more extensive, especially in the field of small and medium-sized high-resolution display backplanes.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a driving backplane, comprising a substrate and a first transistor, wherein the first transistor is located on one side of the substrate.

[0005] The first transistor includes an active layer, a gate insulating layer, a gate, a first electrode and a second electrode,

[0006] The active layer, the gate insulating layer, the gate, the first electrode and the second electrode are stacked in sequence away from the substrate,

[0007] An intermediate dielectric layer is further provided between the gate and the first and second electrodes. The orthographic projections of the first and second electrodes on the substrate are located at opposite ends of the orthographic projection of the active layer on the substrate.

[0008] The active layer is made of oxide semiconductor material;

[0009] The gate insulating layer includes a first portion and a second portion, the first portion overlaps with the orthographic projection of the gate and the active layer on the substrate, and the second portion does not overlap with the orthographic projection of the gate and overlaps with the orthographic projection of the active layer on the substrate;

[0010] The second portion is located on opposite sides of the first portion; the first electrode and the second electrode are electrically connected to the active layer through a first via hole and a second via hole respectively opened in the intermediate dielectric layer and the second portion;

[0011] An average value of distances between all points on a surface of the first portion facing away from the substrate and the active layer is greater than an average value of distances between all points on a surface of the second portion facing away from the substrate and the active layer.

[0012] In some embodiments, the thickness of the second portion varies by less than 100 angstroms.

[0013] In some embodiments, along the first direction, the thickness of the second portion gradually increases.

[0014] The first direction is a direction of the second portion from an end away from the first portion to an end close to the first portion.

[0015] In some embodiments, along the second direction, the thickness of the second portion gradually increases.

[0016] The second direction is a direction of the second portion from an end close to the first portion to an end away from the first portion.

[0017] In some embodiments, along the first direction, the thickness of the second portion gradually increases and then gradually decreases.

[0018] The first direction is a direction of the second portion from an end away from the first portion to an end close to the first portion.

[0019] In some embodiments, along the first direction, the thickness of the second portion gradually decreases and then gradually increases.

[0020] The first direction is a direction of the second portion from an end away from the first portion to an end close to the first portion.

[0021] In some embodiments, along the first direction, the thickness of the second portion increases and decreases alternately.

[0022] The first direction is a direction of the second portion from an end away from the first portion to an end close to the first portion.

[0023] In some embodiments, a thickness maintaining portion is further provided between the thickness increasing portion and the thickness decreasing portion of the second portion, and the thickness of the thickness maintaining portion remains consistent.

[0024] In some embodiments, the thickness of the first portion varies by less than 100 angstroms.

[0025] In some embodiments, the thickness of the first portion is greater than the thickness of the second portion;

[0026] Alternatively, the thickness of the first portion is equal to the maximum thickness of the second portion.

[0027] In some embodiments, the first portion includes a first sub-portion, a second sub-portion, and a third sub-portion, and the second sub-portion is located between the first sub-portion and the third sub-portion.

[0028] Along the third direction, the thicknesses of the first sub-portion and the third sub-portion gradually increase.

[0029] The third direction is the direction of the first sub-section and the third sub-section from one end close to the second section to one end away from the second section;

[0030] The thickness of the second sub-portion remains constant;

[0031] The thickness of the second sub-section is consistent with the maximum thickness of the first sub-section and the third sub-section.

[0032] In some embodiments, the first portion includes a first sub-portion, a second sub-portion, and a third sub-portion, and the second sub-portion is located between the first sub-portion and the third sub-portion.

[0033] The first sub-section and the third sub-section both include a thickness gradually increasing portion and a thickness maintaining portion,

[0034] The gradually increasing thickness portions and the thickness maintaining portions of the first sub-portion and the third sub-portion are arranged in sequence along the third direction, respectively. The thickness of the gradually increasing thickness portions gradually increases along the third direction, while the thickness of the thickness maintaining portions remains consistent.

[0035] The third direction is the direction of the first sub-section and the third sub-section from one end close to the second section to one end away from the second section;

[0036] The thickness of the thickness maintaining portion of the first sub-portion and the third sub-portion is consistent with the maximum thickness of the thickness gradually increasing portion;

[0037] The thickness of the second sub-portion remains constant;

[0038] The second subsection has a thickness smaller than thicknesses of thickness maintaining portions of the first and third subsections.

[0039] In some embodiments, the first sub-portion and the third sub-portion further include a gradually decreasing thickness portion, wherein the thickness of the gradually decreasing thickness portion gradually decreases along the third direction.

[0040] The gradually decreasing thickness portion of the first sub-section is located between the thickness maintaining portion thereof and the second sub-section,

[0041] The gradually decreasing thickness portion of the third sub-section is located between the thickness maintaining portion thereof and the second sub-section.

[0042] In some embodiments, a thickness of a first edge region of the first portion joined to the second portion is greater than a thickness of a second edge region of the second portion joined to the first portion.

[0043] In some embodiments, the thickness of the second portion increases and decreases alternately, and the amplitude of the alternating increase and decrease of the thickness of the second portion ranges from 60 to 600 angstroms.

[0044] In some embodiments, a difference between an average thickness of the first portion and an average thickness of the second portion ranges from 50 to 2000 angstroms.

[0045] In some embodiments, the second portion includes a first sub-portion and a second sub-portion, wherein the first sub-portion and the second sub-portion are located on opposite sides of the first portion.

[0046] The length of the first section extending along the fourth direction is greater than the length of the second section extending along the fourth direction;

[0047] The fourth direction is the arrangement direction of the first part and the second part.

[0048] In some embodiments, the concentration of the particles in the active layer overlapping the second portion that make it conductive is in the range of 1.0×10 20 atoms / cm 3 ~5.0×10 20 atoms / cm 3 .

[0049] In some embodiments, the concentration of particles in the second portion that make the active layer conductive increases gradually along the fifth direction.

[0050] The concentration of particles in the second portion that make the active layer conductive is ≤5.0×10 20 atoms / cm 3 ;

[0051] The fifth direction is a direction of the second portion from a side away from the substrate to a side close to the substrate.

[0052] In some embodiments, the present invention further includes an inorganic insulating layer and an organic insulating layer, wherein the inorganic insulating layer and the organic insulating layer are sequentially stacked on a side of the first electrode and the second electrode away from the substrate.

[0053] The shape of the surface of the inorganic insulating layer facing away from the substrate and overlapping with the orthographic projection of the active layer on the substrate is adapted to the shape of the surface of the gate insulating layer facing away from the substrate and overlapping with the orthographic projection of the active layer on the substrate;

[0054] The inorganic insulating layer has a uniform thickness.

[0055] In some embodiments, a pixel circuit is further included, wherein the pixel circuit is located on one side of the substrate.

[0056] The pixel circuit includes a plurality of transistors, and at least one of the transistors uses the first transistor.

[0057] In some embodiments, some of the transistors are second transistors.

[0058] The active layer of the second transistor is made of low-temperature polysilicon material;

[0059] The active layer and the gate of the second transistor are located on a side of the first transistor close to the substrate, and the first electrode and the second electrode of the second transistor are arranged in the same layer as the first electrode and the second electrode of the first transistor;

[0060] The first transistor is used as a switching transistor in the pixel circuit, and the second transistor is used as a driving transistor in the pixel circuit. The driving transistor is used to drive a light-emitting element to emit light.

[0061] In some embodiments, the oxide semiconductor material includes indium gallium zinc oxide;

[0062] The material of the gate insulating layer includes any one or more of aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0063] In a third aspect, an embodiment of the present disclosure further provides a display panel, which includes the above-mentioned driving backplane.

[0064] In some embodiments, the driving backplane further includes a pixel electrode, or the driving backplane further includes a pixel electrode and a common electrode;

[0065] The display panel further includes a cell substrate and liquid crystal, wherein the cell substrate includes a common electrode.

[0066] The cell substrate and the driving back plate are aligned to form an alignment gap, and the liquid crystal is filled in the alignment gap.

[0067] In some embodiments, it further includes a light-emitting element, an encapsulation layer, and a protective cover.

[0068] The light emitting element, the encapsulation layer and the protective cover are stacked in sequence on one side of the driving backplane;

[0069] The light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode, wherein the first electrode, the light-emitting functional layer, and the second electrode are stacked in sequence, and the first electrode is electrically connected to the first transistor in the driving backplane;

[0070] The light-emitting element includes an organic electroluminescent element, a Mini LED or a Micro LED.

[0071] In a fourth aspect, an embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0073] FIG1a is a schematic diagram of a local conductorization process of an active layer of a top-gate IGZO thin-film transistor in the related art.

[0074] FIG1 b is a schematic cross-sectional view of a top-gate IGZO thin film transistor.

[0075] FIG1c is a schematic diagram showing the relationship between the designed channel region and the actual channel region of the top-gate IGZO thin film transistor in FIG1b.

[0076] 1d-1e are schematic diagrams of current methods for extracting ΔL from thin film transistors.

[0077] FIG2 a is a schematic cross-sectional view of a local structure of a driving backplane according to an embodiment of the present disclosure.

[0078] FIG. 2 b is a schematic diagram of a partial conductorization process of the active layer of the first transistor in an embodiment of the present disclosure.

[0079] FIG. 2 c is a schematic diagram showing actual verification results of the shortening amplitude of the effective channel region of the first transistor in the embodiment of the present disclosure.

[0080] 2d-2e are scanning electron microscope images of the first portion and the second portion of the gate insulation layer of the first transistor in an embodiment of the present disclosure.

[0081] FIG3 a is a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure.

[0082] FIG3 b is a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure.

[0083] FIG3 c is a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure.

[0084] FIG3 d is a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure.

[0085] FIG3e is a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure.

[0086] FIG3 f is a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure.

[0087] FIG3g is a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure.

[0088] FIG4 a is a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure.

[0089] FIG4 b is a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure.

[0090] FIG4 c is a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure.

[0091] FIG5 a is an actual top view of the second portion of the gate insulation layer of the first transistor in an embodiment of the present disclosure, the region not covered by the gate, the first electrode, and the second electrode.

[0092] FIG5 b is a schematic top view of the area of ​​the second portion of the gate insulation layer of the first transistor not covered by the gate, the first electrode and the second electrode in an embodiment of the present disclosure.

[0093] FIG5c is a cross-sectional view of the structure along the AA′ section line in FIG5b.

[0094] FIG6 is a comparison diagram of the concentration of particles injected along the direction of the second portion close to the substrate after and before the second portion is thinned in an embodiment of the present disclosure.

[0095] FIG7 a is a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure.

[0096] FIG7 b is another scanning electron microscope image of the first portion and the second portion of the gate insulation layer of the first transistor in an embodiment of the present disclosure.

[0097] FIG8 is a circuit diagram of an LTPO pixel circuit according to an embodiment of the present disclosure.

[0098] FIG9 is an operation timing diagram of the pixel circuit shown in FIG8 .

[0099] FIG10 is a circuit diagram of another LTPO pixel circuit in an embodiment of the present disclosure.

[0100] FIG11 is an operation timing diagram of the pixel circuit shown in FIG10 . DETAILED DESCRIPTION

[0101] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a driving backplane, a display panel and a display device provided by the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0102] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully enable those skilled in the art to understand the scope of this disclosure.

[0103] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions, but are not intended to be limiting.

[0104] In related technologies, to meet the real-world demand for high resolution, thin-film transistors (TFTs) must be as small as possible to ensure the highest possible pixel density and aperture ratio. IGZO (Indium Gallium Zinc Oxide) is a thin-film transistor (TFT) technology used in the channel layer (i.e., active layer) of next-generation thin-film transistors, a type of metal oxide panel technology.

[0105] The technology for conducting the active layer regions corresponding to the source and drain (SD) electrodes in IGZO thin-film transistors (TFTs) is a key technology limiting thin-film transistor fabrication. Currently, ion implantation is used in mass-produced LTPO processes to conduct these regions. Specifically, using the gate metal as a mask, high-speed particles are implanted into the active layer regions corresponding to the source and drain electrodes using specific process parameters. The oxide semiconductor material in these regions loses its semiconducting properties and becomes a conductor. Compared to traditional IGZO conductorization methods, this method offers the advantage of high implantation precision, which is beneficial for ensuring the characteristics of small-scale thin-film transistor devices. However, during the particle implantation process, the gate insulating layer, which is not shielded by the gate, is inevitably bombarded by high-energy particles, causing its structure to become loose and the contact interface between the gate insulating layer and the active layer to become loose, which is detrimental to the subsequent characteristics and stability of the thin-film transistor device. On the other hand, due to the concentration difference of the implanted particles between the regions corresponding to the source and drain electrodes of the active layer and the channel region of the active layer, diffusion of the implanted particles is inevitable during the subsequent high-temperature process, resulting in a shortened effective channel region of the thin film transistor device. Both theory and experiment show that, referring to FIG1a, which is a schematic diagram of the local conductorization process of the active layer of a top-gate IGZO thin film transistor in the related art, after the implanted particles (such as boron ions B) conductorize the regions corresponding to the source 25 and drain 26 of the active layer 2, and then undergo subsequent high-temperature processes such as annealing, due to the concentration difference between the implanted particles in the conductive region 22 of the active layer 2 and the effective channel region (i.e., the non-conductive region) 21, the implanted particles will diffuse from the desired conductive region 22 and its existing region (such as the gate insulating layer) to the effective channel region (i.e., the non-conductive region) 21, thereby causing the actual size of the effective channel region 21 of the thin film transistor device to be smaller than the designed size. Especially for small-sized thin film transistor devices, this diffusion often causes the thin film transistor device to have a large current, making it unusable.

[0106] 1b is a schematic cross-sectional view of a top-gate IGZO thin-film transistor; FIG1c is a schematic diagram showing the relationship between the designed channel region and the actual channel region of the top-gate IGZO thin-film transistor in FIG1b; FIG1c shows that the gate-source voltage (V GS ) increases, the carrier concentration induced by the thin-film transistor increases, and the shortening of the designed channel region of the thin-film transistor, ΔL, decreases. L is the designed channel region length of the thin-film transistor, Leff is the actual channel region length of the thin-film transistor, and ΔL is the length of the conductive channel region due to diffusion of the implanted particles. However, the higher the gate-source voltage of a top-gate IGZO thin-film transistor, the higher the power consumption of the thin-film transistor.

[0107] At present, the actual value of the effective channel area is usually evaluated by the transfer characteristic curve and ΔL value of small-size thin film transistor devices. Referring to Figures 1d and 1e, there are schematic diagrams of the current method of extracting ΔL from thin film transistors. In Figure 1d, the vertical axis represents the resistance R between the source and drain of the thin film transistor, the horizontal axis represents the channel area length L, and the gate-source voltage V of the thin film transistor is ΔL. GS The value range is 1~5V, and the gate-source voltage V GS Within this value range, the value is increased by 0.2V each time to obtain multiple correspondence curves between gate-source voltage, source-drain resistance and channel region length. The intersection of two correspondence curves between gate-source voltage, source-drain resistance and channel region length corresponds to a ΔL, that is, the intersection of the two correspondence curves between gate-source voltage, source-drain resistance and channel region length can determine a ΔL.

[0108] In order to avoid increasing the power consumption of the top-gate IGZO thin film transistor, how to reduce the shortening amplitude ΔL of the effective channel region of the thin film transistor without increasing the gate-source voltage of the top-gate IGZO thin film transistor has become an urgent problem to be solved.

[0109] In order to solve the problem of reducing the shortening amplitude ΔL of the effective channel region of the thin film transistor without increasing the gate-source voltage of the top-gate IGZO thin film transistor in the related art, in the first aspect, an embodiment of the present disclosure provides a driving backplane. Referring to Figure 2a, it is a schematic cross-sectional view of a local structure of a driving backplane in the embodiment of the present disclosure; wherein, the driving backplane includes a substrate 1 and a first transistor 100, the first transistor 100 is located on one side of the substrate 1, the first transistor 100 includes an active layer 2, a gate insulating layer 3, a gate 4, a first electrode 5 and a second electrode 6, the active layer 2, the gate insulating layer 3, the gate 4 and the first electrode 5 and the second electrode 6 are stacked away from the substrate 1 in sequence, and an intermediate dielectric layer 7 is further provided between the gate 4 and the first electrode 5 and the second electrode 6, and the orthographic projections of the first electrode 5 and the second electrode 6 on the substrate 1 are located on the active layer 2, the gate insulating layer 3, the gate 4 and the first electrode 5 and the second electrode 6 Layer 2 is at opposite ends of the orthographic projection on the substrate 1, and the active layer 2 is made of oxide semiconductor material; the gate insulating layer 3 includes a first part 31 and a second part 32, the first part 31 overlaps with the orthographic projection of the gate 4 and the active layer 2 on the substrate 1, and the second part 32 does not overlap with the orthographic projection of the gate 4, and overlaps with the orthographic projection of the active layer 2 on the substrate 1; the second part 32 is located on opposite sides of the first part 31; the first pole 5 and the second pole 6 are electrically connected to the active layer 2 through a first via 301 and a second via 302 respectively provided in the intermediate dielectric layer 7 and the second part 32; the average value of the distance h1 between all points on the surface of the first part 31 on the side facing away from the substrate 1 and the active layer 2 is greater than the average value of the distance h2 between all points on the surface of the second part 32 on the side facing away from the substrate 1 and the active layer 2.

[0110] The active layer 2 is formed on a flat surface, so the surface of the active layer 2 facing away from the substrate 1 is flat. The area of ​​the active layer 2 that overlaps with the gate 4 is its effective channel region 21. The area of ​​the active layer 2 that overlaps with the gate insulating layer 3 and does not overlap with the gate 4 is the conductive region 22 that needs to be achieved through particle implantation. In some embodiments, the oxide semiconductor material includes indium gallium zinc oxide (IGZO). In other words, in this embodiment, the first transistor 100 is an oxide semiconductor transistor.

[0111] In this embodiment, referring to FIG2b, a schematic diagram of the conductorization process of the active layer of the first transistor in the embodiment of the present disclosure is shown; the average value of the distance h1 between all points on the surface of the first portion 31 on the side facing away from the substrate 1 and the active layer 2 is greater than the average value of the distance h2 between all points on the surface of the second portion 32 on the side facing away from the substrate 1 and the active layer 2, that is, the average thickness of the first portion 31 is greater than the average thickness of the second portion 32, so that the thickness of the second portion 32 is thinner than that of the first portion 31, thereby making the particle injection condition of the second portion 32 more moderate, and the acceleration voltage during particle injection is significantly increased. The bombardment energy of the injected particles is weaker, and the injected particles cause less damage to the gate insulating layer 3 and the contact interface between the gate insulating layer 3 and the active layer 2, thereby making the first transistor 100 have better stability; on the other hand, the diffusion ability of the injected particles is weaker, so that the amount of injected particles diffused from the area of ​​the active layer 2 overlapping with the second part 32 to the area of ​​the active layer 2 overlapping with the first part 31 is smaller, thereby reducing the shortening amplitude ΔL of the effective channel region 21 of the first transistor 100, which is beneficial to ensuring the characteristics of the small-sized first transistor 100, and thus is beneficial to the design and preparation of a high-resolution driving backplane.

[0112] Referring to Figure 2c, there is a schematic diagram of the actual verification results of the shortening amplitude of the effective channel region of the first transistor in the embodiment of the present disclosure; as can be seen from Figure 2c, while ensuring the conductor effect of the area overlapping with the second part 32 of the active layer 2 of the first transistor 100, if the thickness of the second part 32 is thinned, the voltage of the particle injection device during particle injection is smaller (such as 35KV, when the second part 32 is not thinned, the injection device voltage needs to be 40KV), and the bombardment energy of the particles on the gate insulating layer 3 is weaker, which not only causes less damage to the gate insulating layer 3 and the contact interface between the gate insulating layer 3 and the active layer 2, but also the diffusion ability of the injected particles is weaker, and the shortening amplitude ΔL of the effective channel region of the first transistor is smaller. In Figure 2c, Vg-Vth represents the gate-source voltage of the first transistor 100 (such as the voltage between the gate 4 and the first electrode 5), and Vd represents the source-drain voltage of the first transistor 100 (i.e., the voltage between the first electrode 5 and the second electrode 6). Referring to Figures 2d and 2e, there are scanning electron microscope images of the first and second parts of the gate insulating layer of the first transistor in the embodiment of the present disclosure.

[0113] In some embodiments, referring to FIG. 3 a , which is a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure; the average thickness of the first portion 31 is greater than the average thickness of the second portion 32 .

[0114] The thickness of the first portion 31 and the second portion 32 is the dimension thereof in a direction away from the substrate 1 .

[0115] 3 a , in some embodiments, the thickness of the second portion 32 may vary by less than 100 angstroms, that is, the thickness of the second portion 32 may be approximately uniform.

[0116] In some embodiments, referring to Figure 3b, a schematic cross-sectional view of the partial structure of another driving backplane in an embodiment of the present disclosure is shown; wherein, along the first direction X, the thickness of the second portion 32 gradually increases, and the first direction X is the direction of the second portion 32 from the end away from the first portion 31 to the end close to the first portion 31.

[0117] In some embodiments, referring to FIG. 3 b , the thickness of the second portion 32 gradually increases along the first direction X in a linear manner, an arc-shaped manner, a step-shaped manner, or other forms of gradually increasing trends.

[0118] In some embodiments, referring to Figure 3b, on the one hand, the portion with a smaller thickness of the second part 32 is more conducive to making the ion implantation conditions milder, thereby making the bombardment energy of the implanted particles weaker, and thereby making the implanted particles less damaging to the gate insulating layer 3 and the contact interface between the gate insulating layer 3 and the active layer 2, so that the first transistor 100 has better stability; on the other hand, the diffusion ability of the implanted particles is weaker, and the implanted particles need to pass through the portion with a larger thickness of the second part 32 during the diffusion process before they can diffuse to the effective channel region 21 of the active layer 2. Therefore, the amount of implanted particles diffused from the area of ​​the active layer 2 overlapping with the second part 32 to the area of ​​the active layer 2 overlapping with the first part 31 will be further reduced, thereby further reducing the shortening amplitude ΔL of the effective channel region 21 of the first transistor 100, which is more conducive to ensuring the characteristics of the small-sized first transistor 100.

[0119] In some embodiments, referring to Figure 3c, which is a schematic cross-sectional view of the partial structure of another driving backplane in an embodiment of the present disclosure; wherein, along the second direction Y, the thickness of the second portion 32 gradually increases, and the second direction Y is the direction of the second portion 32 from one end close to the first portion 31 to the end away from the first portion 31.

[0120] In some embodiments, referring to FIG. 3 c , the thickness of the second portion 32 gradually increases along the second direction Y in a linear manner, an arc-shaped manner, a step-shaped manner, or other forms of gradually increasing trends.

[0121] In some embodiments, referring to FIG. 3 c , since the average thickness of the second portion 32 is less than the average thickness of the first portion 31 , on the one hand, the thicker portion of the second portion 32 is still conducive to making the ion implantation conditions milder, thereby making the bombardment energy of the implanted particles weaker, thereby reducing the damage of the implanted particles to the gate insulating layer 3 and the contact interface between the gate insulating layer 3 and the active layer 2, and thus improving the stability of the first transistor 100. On the other hand, the diffusion ability of the implanted particles is weaker, and during the diffusion process, the implanted particles need to pass through the thinner portion of the second portion 32 before they can diffuse into the effective channel region 21 of the active layer 2. During the diffusion process, a large portion of the implanted particles cannot diffuse into the effective channel region 21 through the thinner portion of the second portion 32. Therefore, the amount of implanted particles diffused from the region of the active layer 2 overlapping with the second portion 32 to the region of the active layer 2 overlapping with the first portion 31 is further reduced, thereby further reducing the shortening amplitude ΔL of the effective channel region 21 of the first transistor 100, which is more conducive to ensuring the characteristics of the small-sized first transistor 100.

[0122] In some embodiments, referring to Figure 3d, a schematic cross-sectional view of the partial structure of another driving backplane in an embodiment of the present disclosure is shown; wherein, along the first direction X, the thickness of the second portion 32 first gradually increases and then gradually decreases, and the first direction X is the direction of the second portion 32 from the end away from the first portion 31 to the end close to the first portion 31.

[0123] In some embodiments, referring to FIG. 3 d , the thickness of the second portion 32 along the first direction X may first gradually increase and then gradually decrease, which may be a linear increase and decrease, an arc-shaped increase and decrease, a step-shaped increase and decrease, or other forms of gradually increasing and decreasing trends.

[0124] In some embodiments, the portion where the thickness of the second portion 32 in Figure 3d gradually increases has the advantages of the second portion 32 in Figure 3b, and the portion where the thickness of the second portion 32 in Figure 3d gradually decreases has the advantages of the second portion 32 in Figure 3c, that is, the second portion 32 of the structure in Figure 3d has the advantages of the second portion 32 of the structure in both Figures 3b and 3c. On the one hand, the injected particles can cause less damage to the gate insulating layer 3 and the contact interface between the gate insulating layer 3 and the active layer 2, so that the first transistor 100 has better stability; on the other hand, the amount of injected particles diffusing from the area of ​​the active layer 2 overlapping with the second portion 32 to the area of ​​the active layer 2 overlapping with the first portion 31 can be further reduced, thereby further reducing the shortening amplitude ΔL of the effective channel region 21 of the first transistor 100, which is more conducive to ensuring the characteristics of the small-sized first transistor 100.

[0125] In some embodiments, referring to Figure 3e, which is a schematic cross-sectional view of the partial structure of another driving backplane in an embodiment of the present disclosure; wherein, along the first direction X, the thickness of the second portion 32 first gradually decreases and then gradually increases, and the first direction X is the direction of the second portion 32 from the end away from the first portion 31 to the end close to the first portion 31.

[0126] In some embodiments, referring to FIG. 3e , the thickness of the second portion 32 along the first direction X may first gradually decrease and then gradually increase, which may be a linear decrease and increase, an arc-shaped decrease and increase, a step-shaped decrease and increase, or other forms of gradually decreasing and increasing trends.

[0127] In some embodiments, the portion where the thickness of the second portion 32 in Figure 3e gradually decreases has the advantages of the second portion 32 in Figure 3c, and the portion where the thickness of the second portion 32 in Figure 3e gradually increases has the advantages of the second portion 32 in Figure 3b, that is, the second portion 32 of the structure in Figure 3e has the advantages of the second portion 32 of the structure in both Figures 3b and 3c. On the one hand, the injected particles can cause less damage to the gate insulating layer 3 and the contact interface between the gate insulating layer 3 and the active layer 2, so that the first transistor 100 has better stability; on the other hand, the amount of the injected particles diffusing from the area of ​​the active layer 2 overlapping with the second portion 32 to the area of ​​the active layer 2 overlapping with the first portion 31 can be further reduced, thereby further reducing the shortening amplitude ΔL of the effective channel region 21 of the first transistor 100, which is more conducive to ensuring the characteristics of the small-sized first transistor 100.

[0128] In some embodiments, referring to Figure 3f, a schematic cross-sectional view of the partial structure of another driving backplane in an embodiment of the present disclosure is shown; wherein, along the first direction X, the thickness of the second portion 32 alternately increases and decreases, and the first direction X is the direction of the second portion 32 from the end away from the first portion 31 to the end close to the first portion 31.

[0129] In some embodiments, the thickness of the second portion 32 alternates between increasing and decreasing, and the amplitude of the alternating increase and decrease of the thickness of the second portion 32 ranges from 60 to 600 angstroms. In some embodiments, referring to FIG. 3 f , the cross-section of the second portion 32 perpendicular to the substrate 1 on the side facing away from the substrate 1 is wavy, with the crest of the wavy line having an arc, triangle, rectangle, or trapezoidal shape, and the trough of the wavy line having an arc, triangle, rectangle, or inverted trapezoidal shape.

[0130] In some embodiments, the second portion 32 of the structure in Figure 3f is a repeated continuous arrangement of the second portion 32 of the structure in Figure 3d or Figure 3e, that is, the second portion 32 of the structure in Figure 3f has the advantages of the second portion 32 of the structure in Figure 3d and Figure 3e. On the one hand, the injected particles can cause less damage to the gate insulating layer 3 and the contact interface between the gate insulating layer 3 and the active layer 2, so that the first transistor 100 has better stability; on the other hand, the amount of injected particles diffusing from the area of ​​the active layer 2 overlapping with the second portion 32 to the area of ​​the active layer 2 overlapping with the first portion 31 can be further reduced, thereby further reducing the shortening amplitude ΔL of the effective channel region 21 of the first transistor 100, which is more conducive to ensuring the characteristics of the small-sized first transistor 100.

[0131] In some embodiments, referring to FIG. 3g , a schematic cross-sectional view of a partial structure of another embodiment of the driver backplane is shown. The second portion 32 of the structure in FIG. 3g is based on the structure of the second portion 32 in FIG. 3d . A thickness-maintaining portion is further provided between the increased-thickness portion and the decreased-thickness portion of the second portion 32 , maintaining a consistent thickness. Specifically, to account for thickness variations, the thickness of the thickness-maintaining portion is less than 100 angstroms.

[0132] In some embodiments, based on the structure of the second part 32 in Figures 3e and 3f, a thickness maintaining portion may be provided between the thickness increasing portion and the thickness decreasing portion of the second part 32, and the thickness of the thickness maintaining portion may remain consistent.

[0133] In some embodiments, referring to FIG. 3 a - FIG 3 g , the thickness difference of the first portion 31 is less than 100 angstroms.

[0134] In some embodiments, referring to FIG. 3 a - FIG 3 g , the thickness of the first portion 31 is greater than the thickness of the second portion 32 .

[0135] In some embodiments, the thickness of the first portion 31 is equal to the maximum thickness of the second portion 32 .

[0136] In some embodiments, the thickness of the first portion 31 is less than the maximum thickness of the second portion 32 .

[0137] In some embodiments, refer to Figure 4a, which is a schematic cross-sectional view of the partial structure of another driving backplane in an embodiment of the present disclosure; wherein, the first part 31 includes a first sub-part 311, a second sub-part 312 and a third sub-part 313, and the second sub-part 312 is located between the first sub-part 311 and the third sub-part 313. Along the third direction Z, the thickness of the first sub-part 311 and the third sub-part 313 gradually increases, and the third direction Z is the direction of the first sub-part 311 and the third sub-part 313 from one end close to the second part 32 to the other end away from the second part 32; the thickness of the second sub-part 312 remains consistent; the thickness of the second sub-part 312 is consistent with the maximum thickness of the first sub-part 311 and the third sub-part 313.

[0138] In some embodiments, referring to FIG4b, a schematic cross-sectional view of a partial structure of another driving backplane in an embodiment of the present disclosure is shown; wherein, the first portion 31 includes a first sub-portion 311, a second sub-portion 312, and a third sub-portion 313, the second sub-portion 312 is located between the first sub-portion 311 and the third sub-portion 313, the first sub-portion 311 and the third sub-portion 313 both include a gradually increasing thickness portion and a thickness maintaining portion, the gradually increasing thickness portion and the thickness maintaining portion of the first sub-portion 311 and the third sub-portion 313 are respectively arranged in sequence along the third direction Z, along The thickness of the gradually increasing portion in the third direction Z gradually increases, while the thickness of the thickness-maintaining portion remains consistent. The third direction Z is the direction from the end of the first sub-portion 311 and the third sub-portion 313 closer to the end farther from the second portion 32. The thickness of the thickness-maintaining portion of the first sub-portion 311 and the third sub-portion 313 remains consistent with the maximum thickness of the gradually increasing portion. The thickness of the second sub-portion 312 remains consistent. The thickness of the second sub-portion 312 is less than the thickness of the thickness-maintaining portion of the first sub-portion 311 and the third sub-portion 313. Considering the existence of thickness errors, the thickness difference of the film layers that maintain consistent thickness is less than 100 angstroms.

[0139] In some embodiments, referring to Figure 4c, there is a schematic cross-sectional view of the partial structure of another driving backplane in an embodiment of the present disclosure; wherein, the first sub-section 311 and the third sub-section 313 also include a thickness gradually decreasing portion, and the thickness of the thickness gradually decreasing portion gradually decreases along the third direction Z. The thickness gradually decreasing portion of the first sub-section 311 is located between its thickness maintaining portion and the second sub-section 312, and the thickness gradually decreasing portion of the third sub-section 313 is located between its thickness maintaining portion and the second sub-section 312.

[0140] In some embodiments, referring to Figures 4a-4c, the thickness of a first edge region 310 of the first portion 31 where it joins the second portion 32 is greater than the thickness of a second edge region 320 of the second portion 32 where it joins the first portion 31. With this configuration, because the average thickness of the second portion 32 is less than the average thickness of the first portion 31, the diffusion capability of the injected particles is weaker. Furthermore, during the diffusion process, the injected particles must pass through the thinner second edge region 320 of the second portion 32 before they can reach the effective channel region 21 of the active layer 2. During the diffusion process, a significant portion of the injected particles cannot pass through the thinner second edge region 320 of the second portion 32 to reach the effective channel region 21. This further reduces the amount of injected particles that diffuse from the region of the active layer 2 overlapping with the second portion 32 to the region of the active layer 2 overlapping with the first portion 31. This further reduces the shortening amplitude ΔL of the effective channel region 21 of the first transistor 100, further facilitating the performance of the small-sized first transistor 100.

[0141] In some embodiments, referring to Figures 4a-4c, the difference between the average thickness of the first portion 31 and the average thickness of the second portion 32 ranges from 50 to 2000 angstroms. For the first transistor 100 whose channel region uses an oxide semiconductor material, the purpose of forming this special structure is, on the one hand, to enhance the stability of the device; on the other hand, to ensure that the actual length of the device's effective channel region is closer to the designed value, that is, to reduce the amount of implanted particles diffusing from the region of the active layer 2 overlapping with the second portion 32 to the region of the active layer 2 overlapping with the first portion 31, thereby reducing the shortening amplitude ΔL of the effective channel region 21 of the first transistor 100. The first transistor 100 with this special structure has superior performance in terms of higher gate-source voltage (Vgs), higher source-drain voltage (Vds), high annealing temperature in subsequent processes, and stability testing in high temperature and high humidity environments.

[0142] In the related art, for low-temperature polysilicon transistors, the thickness of the gate insulating layer corresponding to the channel region is set to be greater than the thickness of the gate insulating layer corresponding to the source and drain regions. For example, the difference between the thickness of the gate insulating layer corresponding to the channel region and the thickness of the gate insulating layer corresponding to the source and drain regions is in the range of 100 to 1500 angstroms. However, the purpose and principle of adopting this structural design for the gate insulating layer of the low-temperature polysilicon transistor are completely different from those of the oxide semiconductor transistor in this embodiment. The purpose of adopting this structural design for the gate insulating layer of the low-temperature polysilicon transistor is to form a lightly doped drain region (i.e., LDD region) of the low-temperature polysilicon transistor, that is, to increase the source-drain barrier, thereby reducing the leakage current of the low-temperature polysilicon transistor and weakening the thermal electron emission effect caused by the presence of the drain electric field. This structural design of the gate insulating layer of the low-temperature polysilicon transistor can only play a relatively beneficial role under a relatively large source-drain voltage (Vds). When the low-temperature polysilicon transistor has a relatively small source-drain voltage, there is no need to worry about excessive leakage current.

[0143] In some embodiments, referring to Figure 5a, it is an actual top view of the area of ​​the second part of the gate insulation layer of the first transistor not covered by the gate, the first pole and the second pole in the embodiment of the present disclosure; referring to Figure 5b, it is a schematic top view of the area of ​​the second part of the gate insulation layer of the first transistor not covered by the gate, the first pole and the second pole in the embodiment of the present disclosure; Figure 5c is a structural cross-sectional view along the AA' section line in Figure 5b; wherein, the second part 32 includes a first sub-section 321 and a second sub-section 322, the first sub-section 321 and the second sub-section 322 are located on opposite sides of the first part 31, and the length s1 of the first sub-section 321 extending along the fourth direction P is greater than the length s2 of the second sub-section 322 extending along the fourth direction P; the fourth direction P is the arrangement direction of the first part 31 and the second part 32.

[0144] In some embodiments, referring to FIG6 , a comparison diagram of the concentration of particles injected along the direction of the second portion close to the substrate after and before the second portion is thinned is shown in the embodiment of the present disclosure; the concentration of particles in the active layer 2 overlapping with the second portion 32 to make it conductive is in the range of 1.0×10 20 atoms / cm 3 ~5.0×10 20 atoms / cm 3 .

[0145] In some embodiments, the left vertical axis in FIG6 represents the concentration of particles that make the active layer 2 conductive, and the unit is atoms / cm 3The horizontal axis represents the film depth reached along the fifth direction M from the surface of the second portion 32 on the side facing away from the substrate 1, in nm. Referring to FIG6 , the concentration of the particles making the active layer 2 conductive along the fifth direction M in the second portion 32 gradually increases, and the concentration of the particles making the active layer 2 conductive in the second portion 32 is ≤5.0×10 20 atoms / cm 3 The fifth direction M is the direction of the second portion 32 from the side away from the substrate 1 to the side close to the substrate 1. The side of the second portion 32 close to the substrate 1 is sequentially provided with the active layer 2 and the buffer layer 9.

[0146] In some embodiments, referring to FIG6 , particles such as boron ions (B) and fluorine ions (F) are used to make the active layer 2 conductive. The vertical axis on the right side of FIG6 represents the current intensity of the first transistor 100, which is determined by the silicon (Si) and oxygen (O) concentrations in the second portion 32, the active layer 2, and the buffer layer 9, in units of C / s.

[0147] In some embodiments, referring to Figures 7a and 7b, Figure 7a is a schematic cross-sectional view of a partial structure of another embodiment of the present invention; Figure 7b is another scanning electron microscope image of the first and second portions of the gate insulating layer of the first transistor in the embodiment of the present invention; wherein the driving backplane further comprises an inorganic insulating layer 10 and an organic insulating layer 11, which are sequentially stacked on the side of the first electrode 5 and the second electrode 6 facing away from the substrate 1, and the shape of the surface of the inorganic insulating layer 10 facing away from the substrate 1 that overlaps with the orthographic projection of the active layer 2 on the substrate 1 and the shape of the surface of the gate insulating layer 3 facing away from the substrate 1 that overlaps with the orthographic projection of the active layer 2 on the substrate 1 are adapted; the thickness of the inorganic insulating layer 10 is consistent. That is, considering the actual thickness error of the inorganic insulating layer 10, the thickness difference of the inorganic insulating layer 10 is less than 100 angstroms.

[0148] In some embodiments, the material of gate insulating layer 3 includes any one or more of aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride. Gate insulating layer 3 may be a stack of multiple sub-layers, each made of a different material. The material of intermediate dielectric layer 7 and inorganic insulating layer 10 is the same as that of gate insulating layer 3.

[0149] In some embodiments, the inorganic insulating layer 10 is stacked sequentially on the first passivation layer 101 and the second passivation layer 102 on the side of the first electrode 5 and the second electrode 6 facing away from the substrate 1, and the organic insulating layer 11 is stacked on the first planar layer on the side of the second passivation layer facing away from the substrate 1. In a scanning electron microscope image of the driving backplane, even if the inorganic insulating film layers such as the gate insulating layer 3, the intermediate dielectric layer 7, the first passivation layer 101, and the second passivation layer 102 are not deposited continuously, it is difficult to see the boundary between any two adjacent film layers. However, after the organic insulating layer 11 is applied, a very clear and distinct boundary between the organic insulating layer 11 and the second passivation layer 102 can be seen. Based on this, the total thickness H1 of all inorganic insulating film layers between the active layer 2 and the organic insulating layer 11 overlapping with the second part 32 is calculated, and the thickness H2 of the first part 31 and the total thickness H3 of all inorganic insulating film layers between the gate 4 and the organic insulating layer 11 are calculated. Then (H2+H3-H1) is the thickness of the second part 32 that is thinned relative to the first part 31; for example: H1=8854 angstroms; H2=1480 angstroms; H3=7940 angstroms; then H2+H3-H1=566 angstroms.

[0150] It should be noted that the method for calculating the reduced thickness of the second portion 32 relative to the first portion 31 is only applicable to the case where the thickness of the first portion 31 and the thickness of the second portion 32 are consistent.

[0151] In some embodiments, referring to FIG. 3 a , the driving backplane further includes a pixel circuit 8 . The pixel circuit 8 is located on one side of the substrate 1 . The pixel circuit 8 includes a plurality of transistors, and at least one transistor is a first transistor 100 .

[0152] In some embodiments, all transistors in the pixel circuit 8 are first transistors 100 (ie, oxide semiconductor transistors). The pixel circuit 8 is, for example, a pixel circuit in an OLED display panel, a pixel circuit in a Mini LED display panel, or a pixel circuit in a Micro LED display panel.

[0153] In some embodiments, referring to FIG3a, some transistors use a second transistor 200, and the active layer 201 of the second transistor 200 uses a low-temperature polysilicon material; the active layer 201 and the gate 202 of the second transistor 200 are located on the side of the first transistor 100 close to the substrate 1, and the first electrode 203 and the second electrode 204 of the second transistor 200 are arranged in the same layer as the first electrode 5 and the second electrode 6 of the first transistor 100; the first transistor 100 is used as a switching transistor in the pixel circuit 8, and the second transistor 200 is used as a driving transistor in the pixel circuit 8, and the driving transistor is used to drive the light-emitting element to emit light. That is, the second transistor 200 is a low-temperature polysilicon transistor. The pixel circuit 8 is an LTPO (low-temperature polycrystalline oxide) pixel circuit, such as a pixel circuit in an OLED display panel, a pixel circuit in a Mini LED display panel, and a pixel circuit in a Micro LED display panel.

[0154] In some embodiments, referring to Figure 3a, a first gate insulating layer 205 is provided between the active layer 201 and the gate 202 of the second transistor 200, and a first intermediate dielectric layer 12 and a buffer layer 9 are provided between the gate 202 of the second transistor 200 and the active layer 2 of the first transistor 100; a first buffer layer 13 is also provided between the second transistor 200 and the substrate 1; a light-shielding layer 14 is also provided on the side of the active layer 201 of at least part of the second transistor 200 close to the substrate 1, and the light-shielding layer 14 blocks the overlapping area of ​​the active layer 201 and the gate 202 of the second transistor 200, thereby preventing external light from irradiating the channel area of ​​the active layer 201 of the second transistor 200, thereby improving or avoiding an increase in the leakage current of the second transistor 200.

[0155] In some embodiments, referring to Figure 8, which is a circuit diagram of an LTPO pixel circuit in an embodiment of the present disclosure, the pixel circuit includes: a first reset sub-circuit 15, a threshold compensation sub-circuit 16, a driving sub-circuit 17, a data writing sub-circuit 18, a first light-emitting control sub-circuit 19, a second light-emitting control sub-circuit 20, a second reset sub-circuit 23 and a storage sub-circuit 24.

[0156] The first reset sub-circuit 15 is connected to the control terminal of the driver sub-circuit 17 and is configured to reset the control terminal of the driver sub-circuit 17 under the control of a first reset signal. The threshold compensation sub-circuit 16 is electrically connected to the control terminal and the second terminal of the driver sub-circuit 17 and is configured to perform threshold compensation for the driver sub-circuit 17. The data write sub-circuit 18 is electrically connected to the first terminal of the driver sub-circuit 17 and is configured to write a data signal into the storage sub-circuit under the control of a scan signal. The storage sub-circuit 24 is electrically connected to the control terminal of the driver sub-circuit 17 and the first power supply voltage line VDD and is configured to store the data signal. The first light emission control sub-circuit 19 is electrically connected to the first power supply voltage line VDD and the first terminal of the driver sub-circuit 17 and is configured to connect or disconnect the driver sub-circuit 17 and the first power supply voltage line VDD. The second light emission control sub-circuit 20 is electrically connected to the second terminal of the driver sub-circuit 17 and the first electrode of the light-emitting device D and is configured to connect or disconnect the driver sub-circuit 17 and the light-emitting device D. The second reset sub-circuit 23 is electrically connected to the first electrode of the light emitting device D, and is configured to reset the control terminal of the driving sub-circuit 17 and the first electrode of the light emitting device D under the control of a second reset control signal.

[0157] Continuing with FIG8 , the first reset sub-circuit 15 includes a first reset transistor T1, the threshold compensation sub-circuit 16 includes a threshold compensation transistor T2, the driver sub-circuit 17 includes a driver transistor T3, the control terminal of the driver sub-circuit 17 includes the control electrode of the driver transistor T3, the first terminal of the driver sub-circuit 17 includes the first electrode of the driver transistor T3, and the second terminal of the driver sub-circuit 17 includes the second electrode of the driver transistor T3. The data write sub-circuit 18 includes a data write transistor T4, the storage sub-circuit 24 includes a storage capacitor Cst, the first light emission control sub-circuit 19 includes a first light emission control transistor T5, the second light emission control sub-circuit 20 includes a second light emission control transistor T6, and the second reset sub-circuit 23 includes a second reset transistor T7.

[0158] The transistors T1 to T7 in the embodiments of the present disclosure may be classified as N-type transistors or P-type transistors. The embodiments of the present disclosure are described in detail by taking the transistors as P-type transistors as an example.

[0159] Continuing with reference to Figure 8, the drain of the data write transistor T4 is electrically connected to the source of the drive transistor T3, the source of the data write transistor T4 is configured to be electrically connected to the data line Data to receive the data signal, and the gate of the data write transistor T4 is configured to be electrically connected to the first scan signal line Ga1 to receive the scan signal; the second plate of the storage capacitor Cst is electrically connected to the first power supply voltage line VDD, and the first plate of the storage capacitor Cst is electrically connected to the gate of the drive transistor T3; the source of the threshold compensation transistor T2 is electrically connected to the gate of the drive transistor T3, the drain of the threshold compensation transistor T2 is electrically connected to the drain of the drive transistor T3, and the gate of the threshold compensation transistor T2 is configured to be electrically connected to the second scan signal line Ga2 to receive the compensation control signal; the source of the first reset transistor T1 is configured to be electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal, the drain of the first reset transistor T1 is electrically connected to the gate of the drive transistor T3, and the gate of the first reset transistor T1 is configured to be electrically connected to the first reset control signal line Rst1 to receive the first reset control signal; the drain of the second reset transistor T7 is configured to be electrically connected to the second reset power supply terminal Vinit2 to receive the second reset signal, the source of the second reset transistor T7 is electrically connected to the first electrode of the light-emitting device D, and the gate of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Rst2 to receive the second reset control signal; the source of the first light-emitting control transistor T5 is electrically connected to the first power supply voltage line VDD, the drain of the first light-emitting control transistor T5 is electrically connected to the source of the driving transistor T3, and the gate of the first light-emitting control transistor T5 is configured to be electrically connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal; the source of the second light-emitting control transistor T6 is electrically connected to the drain of the driving transistor T3, the drain of the second light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting device D, and the gate of the second light-emitting control transistor T6 is configured to be electrically connected to the second light-emitting control signal line EM2 to receive the second light-emitting control signal; the second electrode of the light-emitting device D is electrically connected to the second power supply terminal VSS.

[0160] In some embodiments, the first scan signal line Ga1 and the second scan signal line Ga2 transmit the same signal. In this embodiment, the gate of the data write transistor T4 and the gate of the threshold compensation transistor T2 are electrically connected to the first scan signal line Ga(A). The first emission control signal line EM1 and the second emission control signal line EM2 transmit the same signal. In this embodiment, the gates of the first emission control transistor T5 and the second emission control transistor T6 are both connected to the emission control line EM. The first reset control signal line Rst1 and the second reset control signal line Rst2 transmit the same signal. In this embodiment, the gates of the first reset transistor T1 and the second reset transistor T7 are both electrically connected to the reset control signal line Rst. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be the same. In this embodiment, the source of the first reset transistor T1 and the drain of the second reset transistor T7 are both electrically connected to the reset power signal line Init.

[0161] The driving sub-circuit, data writing sub-circuit, storage sub-circuit, threshold compensation sub-circuit and reset sub-circuit in the pixel circuit shown in Figure 8 are only schematic. The specific structures of the sub-circuits such as the driving sub-circuit, data writing sub-circuit, storage sub-circuit, threshold compensation sub-circuit and reset sub-circuit can be set according to actual application requirements, and the embodiments of the present disclosure do not specifically limit this.

[0162] It should be noted that in the embodiment of the present disclosure, in addition to the 7T1C (i.e., seven transistors and one capacitor) structure shown in Figure 8, the pixel circuit can also be a circuit structure including other numbers of transistors and capacitors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, and the embodiment of the present disclosure is not limited to this.

[0163] The light-emitting device D can be a micro inorganic light-emitting diode, and further, can be a current-type light-emitting diode, such as a micro light-emitting diode (Micro LED) or a mini light-emitting diode (Mini LED). Of course, the light-emitting device D in the embodiment of the invention can also be an organic light-emitting diode (OLED). One of the first electrode and the second electrode of the light-emitting device D is an anode, and the other is a cathode. In the embodiment of the present invention, the first electrode of the light-emitting device D is an anode, and the second electrode is a cathode.

[0164] 9 , which is a timing diagram of the operation of the pixel circuit shown in FIG8 ; as shown in FIG8 and FIG9 , the driving method of the pixel circuit may include the following stages:

[0165] Reset phase (t1): A low-level signal is written to the reset control signal line Rst, while high-level signals are written to the scan line Ga(A) and the emission control line EM. The first reset transistor T1 and the second reset transistor T7 are turned on, and the gate of the drive transistor T3 is written with the initial voltage Vinit from the reset power signal line Init, preparing for the writing of the next frame data voltage Vdata. The anode of the light-emitting device D is written with the initialization voltage (Vinit ≤ VSS) via the second reset transistor T7, eliminating the forward conduction state of the light-emitting device D. This gradually dissipates the internal electric field created by the directional movement of impurity ions within the light-emitting device D, thereby restoring the characteristics of the light-emitting device D.

[0166] Data writing and threshold compensation stage (t2): The scan line Ga (A) is written as a low-level signal, and the reset control signal line Rst and the first light-emitting control line EM are written as high-level signals; the data writing transistor T4 and the threshold compensation transistor T2 are turned on. The driving transistor T3 is connected by the threshold compensation transistor T2 to form a diode structure, and the data voltage Vdata written on the data line Data is written to the gate of the driving transistor T3 through the data writing transistor T4 and the threshold compensation transistor T2 until the driving transistor T3 is turned off. The gate voltage of the driving transistor T3 is Vdata + Vth (Vth < 0, Vth is the threshold voltage of the driving transistor T3) and is stored in the storage capacitor Cst. The voltages of the first plate and the second plate of the storage capacitor Cst are Vdata + Vth and Vd, respectively.

[0167] Light-emitting phase (t3): A low-level signal is written to the light-emitting control line EM, and high-level signals are written to the scan line Ga(A) and the reset control signal line Rst. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both turned on. The source of the driving transistor T3 is connected to the first power supply voltage line VDD, which is at Vdd. The source voltage of the driving transistor T3 changes instantaneously from Vdata in the previous phase to Vdd. The light-emitting device D emits light under the drive transistor T3. At this time, the driving transistor T3 operates in the saturation region. The gate voltage of the driving transistor T3 is Vdata + Vth, and the source voltage of the driving transistor T3 is Vdd. Therefore, the gate-source voltage of the driving transistor T3 is: Vgs = (Vdata + Vth) - Vdd, until the reset phase of the next frame.

[0168] The light-emitting current of the light-emitting device D is equal to the current flowing through the driving transistor T3, and its expression is as follows: I D =β(Vgs-Vth) 2=β(Vdata+Vth-Vdd-Vth) 2 =β(Vdata-Vdd) 2 ;

[0169] in, μ n is the electron mobility of the driving transistor T3, C ox is the insulation capacitance per unit area, is the width-to-length ratio of the driving transistor T3.

[0170] In this embodiment, referring to Figure 8, the threshold compensation transistor T2 uses an oxide semiconductor transistor (such as an IGZO transistor); the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the second reset transistor T7 all use low-temperature polysilicon transistors (i.e., LTPS transistors).

[0171] Among them, low-temperature polysilicon transistors have better switching speed, fast response, and stronger current driving capability, but the high electron mobility of low-temperature polysilicon transistors makes the leakage current relatively large, the low-frequency driving power consumption is large, it is difficult to maintain static black, and the picture is poor; if the low-temperature polysilicon transistor is made larger to reduce the leakage current, it will affect the screen resolution; in addition, the low-temperature polysilicon transistor has a large hysteresis and is prone to afterimages; oxide semiconductor transistors have low leakage and high uniformity, which can complement the above-mentioned shortcomings of low-temperature polysilicon transistors.

[0172] In the disclosed embodiment, the threshold compensation transistor T2 is an oxide semiconductor transistor because the voltage of the storage capacitor Cst is equivalent to the stored data signal. When the screen display is not refreshed, the storage capacitor Cst will slowly leak through the threshold compensation transistor T2, causing the voltage of the storage capacitor Cst to gradually decrease. If it is not recharged by refreshing, the brightness of the light-emitting device D will change. From a macroscopic perspective, the screen image will become dirty or discolored. In fact, the light-emitting device D may be directly extinguished due to leakage. Oxide semiconductor transistors have the characteristic of low leakage. Using an oxide semiconductor transistor for the threshold compensation transistor T2 can alleviate the above-mentioned problem, that is, the refresh rate can be reduced to a lower level without worrying about the display problems caused by leakage. Using an oxide semiconductor transistor for the threshold compensation transistor T2 can reduce the power consumption of the light-emitting device D at low refresh rates, while avoiding the low refresh rate display anomalies caused by leakage when the threshold compensation transistor T2 is a low-temperature polysilicon transistor. Oxide semiconductor transistors have better uniformity, which can reduce the problems of dirty screen and color cast at low brightness when the pixel circuits are all low-temperature polysilicon transistors.

[0173] In some embodiments, referring to Figure 10, which is a circuit diagram of another LTPO pixel circuit in an embodiment of the present disclosure, wherein the pixel circuit includes: a first light-emitting control circuit 27, a light-emitting element, a driving circuit 28 and a light-emitting selection circuit; it also includes: a data writing circuit 51, a compensation control circuit 52, a first initialization circuit 53, a second initialization circuit 54 and a third capacitor C3; the light-emitting selection circuit includes a second light-emitting control circuit 291, a first selection control circuit 292 and a first capacitor C1; the light-emitting element is a micro light-emitting diode M1; and the driving circuit 28 includes a driving transistor T0.

[0174] 10 , a first terminal of the first capacitor C1 is electrically connected to the gate control terminal ch, and a second terminal of the first capacitor C1 is electrically connected to the first initial voltage terminal I1 ; the first initial voltage terminal I1 is used to provide a first initial voltage Vini1 .

[0175] The first gating control circuit 292 includes a first transistor T1 , a second transistor T2 , and a third transistor T3 .

[0176] A gate of the first transistor T1 is electrically connected to the first reset control terminal R1 , a source of the first transistor T1 is electrically connected to the light emitting data voltage terminal DT, and a drain of the first transistor T1 is electrically connected to the strobe control terminal ch.

[0177] The gate of the second transistor T2 is electrically connected to the selection control terminal ch, the source of the second transistor T2 is electrically connected to the light emitting control voltage terminal VF, and the drain of the second transistor T2 is electrically connected to the second light emitting control terminal EM2; the light emitting control voltage terminal VF is used to provide a light emitting control voltage HF.

[0178] The gate of the third transistor T3 is electrically connected to the gate control terminal ch, the source of the third transistor T3 is electrically connected to the first emission control terminal EM1, and the drain of the third transistor T3 is electrically connected to the second emission control terminal EM2.

[0179] The second light emitting control circuit 291 includes a fourth transistor T4.

[0180] The gate of the fourth transistor T4 is electrically connected to the second light-emitting control terminal EM2, the source of the fourth transistor T4 is electrically connected to the second terminal of the driving circuit 10, and the drain of the fourth transistor T4 is electrically connected to the anode of the micro light-emitting diode M1; the cathode of the micro light-emitting diode M1 is electrically connected to the low voltage terminal VSS.

[0181] The first initialization circuit 53 includes an eighth transistor T8 , the compensation control circuit 52 includes a ninth transistor T9 , the data writing circuit 51 includes a tenth transistor T10 , and the second initialization circuit 54 includes an eleventh transistor T11 .

[0182] The gate of the eighth transistor T8 is electrically connected to the first reset control terminal R1 , the source of the eighth transistor T8 is electrically connected to the first initial voltage terminal I1 , and the drain of the eighth transistor T8 is electrically connected to the gate of the driving transistor T0 .

[0183] The gate of the ninth transistor T9 is electrically connected to the first control terminal G1 , the source of the ninth transistor T9 is electrically connected to the gate of the driving transistor T0 , and the drain of the ninth transistor T9 is electrically connected to the drain of the driving transistor T0 .

[0184] The gate of the tenth transistor T10 is electrically connected to the second control terminal G2 , the source of the tenth transistor T10 is electrically connected to the light emitting data voltage terminal DT, and the gate of the tenth transistor T10 is electrically connected to the source of the driving transistor T0 .

[0185] The gate of the eleventh transistor T11 is electrically connected to the second reset control terminal R2 , the source of the eleventh transistor T11 is electrically connected to the first initial voltage terminal I1 , and the drain of the eleventh transistor T11 is electrically connected to the anode of the micro light emitting diode M1 .

[0186] The first light emitting control circuit 27 includes a twelfth transistor T12 .

[0187] A gate of the twelfth transistor T12 is electrically connected to the first light emitting control terminal EM1 , a source of the twelfth transistor T12 is electrically connected to the high voltage terminal VDD, and a drain of the twelfth transistor T12 is electrically connected to the source of the driving transistor T0 .

[0188] In FIG10 , the node labeled N1 is a first node, and the first node N1 is electrically connected to the gate of T0.

[0189] In at least one embodiment of the pixel circuit shown in FIG. 10 , T1 is an n-type transistor, T2 is a p-type transistor, T3 is an n-type transistor, and T4 is a p-type transistor, but the present invention is not limited thereto.

[0190] In at least one embodiment of the pixel circuit shown in FIG10 , T12 , T0 , T10 , and T11 are p-type transistors, T8 and T9 are n-type transistors, and T12 , T0 , T10 , and T11 are low-temperature polysilicon thin-film transistors; but the present invention is not limited thereto.

[0191] In at least one embodiment shown in FIG. 10 , T8 and T9 are oxide thin film transistors to reduce leakage and help maintain the potential of the gate of T0 .

[0192] In at least one embodiment of the pixel circuit shown in FIG10 , T2 and T3 form an inverter-like structure, and the first light-emitting control signal and the light-emitting control voltage HF provided by EM1 are respectively connected to two sides of the inverter-like structure as input signals.

[0193] In at least one embodiment of the pixel circuit shown in FIG. 10 , T8 may be replaced by a p-type transistor, T9 may be replaced by a p-type transistor, and T10 may be replaced by an n-type transistor, but the present invention is not limited thereto.

[0194] In at least one embodiment of the pixel circuit shown in FIG10 , when working, R1 first provides a high voltage signal, and the light emitting data voltage provided by DT charges ch. Then, G2 provides a low voltage signal, T10 is turned on, and the data voltage provided by DT charges C3.

[0195] 11 , which is a timing diagram of the operation of the pixel circuit shown in FIG10 ; when at least one embodiment of the pixel circuit shown in FIG10 is in operation, the first display cycle includes a first initialization phase S11 , a first data writing phase S12 , and a first light-emitting phase S13 , which are sequentially arranged.

[0196] In the first initialization phase S11, R1 provides a high voltage signal, R2 provides a low voltage signal, G1 provides a low voltage signal, G2 provides a high voltage signal, EM1 provides a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 provides the first initial voltage Vini1 to the gate of T0 and the anode of M1, so that when the first data writing phase S12 begins, T0 can be turned on and clear the residual charge on the anode of M1; T1 is turned on, DT provides a light-emitting data voltage, and the light-emitting data voltage provided by DT is a high voltage. C1 is charged by the light-emitting data voltage, so that the potential of ch is a high voltage, T3 is turned on, and T2 is turned off to control the connection between EM1 and EM2.

[0197] In the first initialization phase S11 , T9 is turned off, T10 is turned off, and T12 is turned off.

[0198] In the first data writing phase S12, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, DT provides a data voltage Vdata, T10 is turned on to write Vdata into the source of T0, and T1 is turned off.

[0199] At the beginning of the first data writing phase S12, T0 is turned on, T9 is turned on, and C3 is charged by Vdata to change the potential of the gate of T0 until T0 is turned off. The gate potential of T0 is related to the threshold voltage of T0.

[0200] In the first light-emitting stage S13, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a low voltage signal, G2 provides a high voltage signal, EM1 provides a low voltage signal, T12 is turned on, C1 maintains the potential of ch at a high voltage, T2 is turned off, T3 is turned on to control the connection between EM1 and EM2, the potential of EM2 is a low voltage signal, T4 is turned on, and T0 drives M1 to emit light to perform PAM (pulse amplitude modulation) long-term light emission.

[0201] The second display period includes a second initialization phase S21, a second data writing phase S22 and a second light emitting phase S23 which are arranged in sequence.

[0202] In the second initialization stage S21, R1 provides a high voltage signal, R2 provides a low voltage signal, G1 provides a low voltage signal, G2 provides a high voltage signal, EM1 provides a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 provides the first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the beginning of the third write time period S221, T0 can be turned on and clear the residual charge on the anode of M1; DT provides the light-emitting data voltage, and the light-emitting data voltage provided by DT is a low voltage. T8 and T11 are turned off, T12 is turned off, and T1 is turned on to control the connection between DT and ch, the potential of ch is a low voltage, T2 is turned on, and T3 is turned off to control EM2 to access HF.

[0203] In the second initialization phase S21 , T9 is turned off, T10 is turned off, and T12 is turned off.

[0204] In the second data writing phase S22 , R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, DT provides a data voltage Vdata, and T10 is turned on to write Vdata into the source of T0 .

[0205] At the beginning of the second data writing phase S221, T0 is turned on, T9 is turned on, and C3 is charged by Vdata to change the potential of the gate of T0 until T0 is turned off. The gate potential of T0 is related to the threshold voltage of T0.

[0206] In the second light-emitting stage S23, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a low voltage signal, G2 provides a high voltage signal, EM1 provides a low voltage signal, T12 is turned on, C1 maintains the potential of ch at a low voltage, T2 is turned on, and T3 is turned off to control EM2 to access HF. When the voltage value of HF is low voltage, T4 is turned on. When T4 is turned on, T0 drives M1 to emit light, so as to perform PWM (pulse width modulation) high-frequency short-time light emission and perform low grayscale display.

[0207] The driving backplane provided by the embodiment of the present disclosure makes the second part of the gate insulating layer thinner than the first part. On the one hand, the particle injection conditions of the second part are milder, the acceleration voltage during particle injection is significantly reduced, the bombardment energy of the injected particles is weaker, and the injected particles cause less damage to the gate insulating layer and the contact interface between the gate insulating layer and the active layer, thereby making the first transistor have better stability; on the other hand, the diffusion ability of the injected particles is weaker, so that the amount of injected particles diffused from the area of ​​the active layer overlapping with the second part to the area of ​​the active layer overlapping with the first part is smaller, thereby reducing the shortening of the effective channel region of the first transistor, which is beneficial to ensuring the characteristics of the small-sized first transistor, and thus is beneficial to the design and preparation of a high-resolution driving backplane.

[0208] Based on the above structure of the driving backplane, an embodiment of the present disclosure also provides a method for preparing the driving backplane, including: using a composition process to sequentially prepare a light-shielding layer, a first buffer layer, an active layer of the second transistor, a first gate insulating layer, a gate of the second transistor and a first intermediate dielectric layer on one side of the substrate.

[0209] A buffer layer, an active layer of the first transistor, a gate insulating layer, a gate of the first transistor and an intermediate dielectric layer are sequentially prepared on a side of the first intermediate dielectric layer away from the substrate by adopting a patterning process.

[0210] A first electrode and a second electrode of the first transistor and a first electrode and a second electrode of the second transistor are prepared on a side of the intermediate dielectric layer away from the substrate by adopting a single patterning process.

[0211] The specific process of preparing the active layer of the first transistor, the gate insulating layer and the gate of the first transistor is: depositing an active layer film, and patterning (such as etching) to form a pattern of the active layer.

[0212] A gate insulating layer and a gate metal film layer are deposited in sequence.

[0213] Photoresist is coated, exposed, developed, and etched (such as wet etching) to form a pattern of the gate electrode, and at the same time, a pattern of the second portion of the gate insulating layer is etched to form a pattern.

[0214] The region of the active layer overlapping the second portion is made conductive by ion implantation technology. The implanted ions may be boron ions, phosphine ions, argon ions, helium ions or fluorine ions.

[0215] In the embodiment of the present disclosure, the patterning process includes steps such as film deposition, photoresist coating, exposure, development, and etching.

[0216] In the disclosed embodiment, each film layer in the driver backplane is prepared using traditional processes, which will not be described in detail here.

[0217] In a second aspect, an embodiment of the present disclosure further provides a display panel, comprising the driving backplane in the above embodiment.

[0218] In some embodiments, the driving backplane further includes pixel electrodes, and the display panel further includes an alignment substrate and liquid crystal. The alignment substrate includes a common electrode. The alignment substrate and the driving backplane align to form an alignment gap, and the liquid crystal fills the alignment gap. That is, the display panel is a liquid crystal display panel. In the liquid crystal display panel, the transistors in the pixel circuit of the driving backplane can all be first transistors, or can also partially use first transistors and partially use second transistors.

[0219] In some embodiments, the driving backplane further includes pixel electrodes and a common electrode; the display panel further includes an alignment substrate and liquid crystal, the alignment substrate including the common electrode, the alignment substrate and the driving backplane being aligned to form an alignment gap, and the liquid crystal is filled in the alignment gap. That is, the display panel is a liquid crystal display panel. In the liquid crystal display panel, the transistors in the pixel circuit of the driving backplane can all be first transistors, or can also partially use first transistors and partially use second transistors.

[0220] In some embodiments, the display panel further includes a light-emitting element, an encapsulation layer, and a protective cover plate, which are stacked in sequence on one side of the driving backplane; the light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode, which are stacked in sequence, and the first electrode is electrically connected to the first transistor in the driving backplane.

[0221] The first electrode is the anode of the light-emitting element. If all transistors in the pixel circuit are first transistors, the first electrode is directly electrically connected to the first transistor used as a driving transistor. If the pixel circuit does not use the first transistor as a driving transistor, the first electrode is indirectly electrically connected to the first transistor in the pixel circuit.

[0222] In some embodiments, the light-emitting element includes an organic electroluminescent element (i.e., an OLED light-emitting element), a Mini LED, or a Micro LED. That is, the display panel can be an OLED display panel, a Mini LED display panel, or a Micro LED display panel. In the OLED display panel, the Mini LED display panel, and the Micro LED display panel, the transistors in the pixel circuit driving the backplane can all be first transistors, or can also partially use the first transistors and partially use the second transistors.

[0223] The display panel provided by the embodiment of the present disclosure, by adopting the driving backplane in the above embodiment, is conducive to the stable display, design and preparation of a high-resolution display panel.

[0224] In a third aspect, an embodiment of the present disclosure further provides a display device, comprising the display panel in the above embodiment.

[0225] The use of the display panel in the above embodiment is beneficial to the stable display, design and preparation of a high-resolution display device.

[0226] The display device provided in the embodiments of the present disclosure can be any product or component with a display function, such as an LCD panel, an LCD TV, an OLED panel, an OLED TV, a Mini LED panel, a Micro LED panel, an OLED billboard, a monitor, a mobile phone, a navigator, or the like.

[0227] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A driving backplane, wherein: The device comprises a substrate and a first transistor, wherein the first transistor is located on one side of the substrate. The first transistor includes an active layer, a gate insulating layer, a gate, a first electrode and a second electrode, The active layer, the gate insulating layer, the gate, the first electrode and the second electrode are stacked in sequence away from the substrate, An intermediate dielectric layer is further provided between the gate and the first and second electrodes. The orthographic projections of the first and second electrodes on the substrate are located at opposite ends of the orthographic projection of the active layer on the substrate. The active layer is made of oxide semiconductor material; The gate insulating layer includes a first portion and a second portion, the first portion overlaps with the orthographic projection of the gate and the active layer on the substrate, and the second portion does not overlap with the orthographic projection of the gate and overlaps with the orthographic projection of the active layer on the substrate; The second portion is located on opposite sides of the first portion; the first electrode and the second electrode are electrically connected to the active layer through a first via hole and a second via hole respectively opened in the intermediate dielectric layer and the second portion; An average value of distances between all points on a surface of the first portion facing away from the substrate and the active layer is greater than an average value of distances between all points on a surface of the second portion facing away from the substrate and the active layer.

2. The driving backplane according to claim 1, wherein: The thickness of the second portion varies by less than 100 angstroms.

3. The driving backplane according to claim 1, wherein: Along the first direction, the thickness of the second portion gradually increases, The first direction is a direction of the second portion from an end away from the first portion to an end close to the first portion.

4. The driving backplane according to claim 1, wherein: Along the second direction, the thickness of the second portion gradually increases, The second direction is a direction of the second portion from an end close to the first portion to an end away from the first portion.

5. The driving backplane according to claim 1, wherein: Along the first direction, the thickness of the second portion gradually increases and then gradually decreases. The first direction is a direction of the second portion from an end away from the first portion to an end close to the first portion.

6. The driving backplane according to claim 1, wherein: Along the first direction, the thickness of the second portion gradually decreases and then gradually increases. The first direction is a direction of the second portion from an end away from the first portion to an end close to the first portion.

7. The driving backplane according to claim 1, wherein: Along the first direction, the thickness of the second portion increases and decreases alternately, The first direction is a direction of the second portion from an end away from the first portion to an end close to the first portion.

8. The driving backplane according to any one of claims 5 to 7, wherein: A thickness maintaining portion is further provided between the thickness increasing portion and the thickness decreasing portion of the second portion, and the thickness of the thickness maintaining portion remains consistent.

9. The driving backplane according to claim 1, wherein: The thickness of the first portion varies by less than 100 angstroms.

10. The driving backplane according to claim 9, wherein: The thickness of the first portion is greater than the thickness of the second portion; Alternatively, the thickness of the first portion is equal to the maximum thickness of the second portion.

11. The driving backplane according to claim 1, wherein: The first portion includes a first sub-portion, a second sub-portion, and a third sub-portion, wherein the second sub-portion is located between the first sub-portion and the third sub-portion. Along the third direction, the thicknesses of the first sub-portion and the third sub-portion gradually increase. The third direction is the direction of the first sub-section and the third sub-section from one end close to the second section to one end away from the second section; The thickness of the second sub-portion remains constant; The thickness of the second sub-section is consistent with the maximum thickness of the first sub-section and the third sub-section.

12. The driving backplane according to claim 1, wherein: The first portion includes a first sub-portion, a second sub-portion, and a third sub-portion, wherein the second sub-portion is located between the first sub-portion and the third sub-portion. The first sub-section and the third sub-section both include a thickness gradually increasing portion and a thickness maintaining portion, The gradually increasing thickness portions and the thickness maintaining portions of the first sub-portion and the third sub-portion are arranged in sequence along the third direction, respectively. The thickness of the gradually increasing thickness portions gradually increases along the third direction, while the thickness of the thickness maintaining portions remains consistent. The third direction is the direction of the first sub-section and the third sub-section from one end close to the second section to one end away from the second section; The thickness of the thickness maintaining portion of the first sub-portion and the third sub-portion is consistent with the maximum thickness of the thickness gradually increasing portion; The thickness of the second sub-portion remains constant; The second subsection has a thickness smaller than thicknesses of thickness maintaining portions of the first and third subsections.

13. The driving backplane according to claim 12, wherein: The first sub-portion and the third sub-portion further include a gradually decreasing thickness portion, wherein the thickness of the gradually decreasing thickness portion gradually decreases along the third direction. The gradually decreasing thickness portion of the first sub-section is located between the thickness maintaining portion thereof and the second sub-section, The gradually decreasing thickness portion of the third sub-section is located between the thickness maintaining portion thereof and the second sub-section.

14. The driving backplane according to any one of claims 11 to 13, wherein: A thickness of a first edge region of the first portion joined to the second portion is greater than a thickness of a second edge region of the second portion joined to the first portion.

15. The driving backplane according to claim 7, wherein: The thickness of the second portion increases and decreases alternately, and the amplitude of the alternating increase and decrease of the thickness of the second portion ranges from 60 to 600 angstroms.

16. The driving backplane according to claim 1, wherein: The difference between the average thickness of the first portion and the average thickness of the second portion ranges from 50 to 2000 angstroms.

17. The driving backplane according to claim 1, wherein: The second portion includes a first sub-portion and a second sub-portion, wherein the first sub-portion and the second sub-portion are located on opposite sides of the first portion. The length of the first section extending along the fourth direction is greater than the length of the second section extending along the fourth direction; The fourth direction is the arrangement direction of the first part and the second part.

18. The driving backplane according to claim 17, wherein: The concentration of the particles making the active layer conductive in the active layer overlapping the second portion is in the range of 1.0×10 20 atoms / cm 3 ~5.0×10 20 atoms / cm 3 .

19. The driving backplane according to claim 18, wherein: The concentration of particles making the active layer conductive gradually increases along the fifth direction in the second portion. The concentration of particles in the second portion that make the active layer conductive is ≤5.0×10 20 atoms / cm 3 ; The fifth direction is a direction of the second portion from a side away from the substrate to a side close to the substrate.

20. The driving backplane according to claim 1, wherein: It also includes an inorganic insulating layer and an organic insulating layer, wherein the inorganic insulating layer and the organic insulating layer are sequentially stacked on the side of the first electrode and the second electrode away from the substrate. The shape of the surface of the inorganic insulating layer facing away from the substrate and overlapping with the orthographic projection of the active layer on the substrate is adapted to the shape of the surface of the gate insulating layer facing away from the substrate and overlapping with the orthographic projection of the active layer on the substrate; The inorganic insulating layer has a uniform thickness.

21. The driving backplane according to claim 1, wherein: It also includes a pixel circuit, wherein the pixel circuit is located on one side of the substrate. The pixel circuit includes a plurality of transistors, and at least one of the transistors uses the first transistor.

22. The driving backplane according to claim 21, wherein: Some of the transistors use a second transistor, The active layer of the second transistor is made of low-temperature polysilicon material; The active layer and the gate of the second transistor are located on a side of the first transistor close to the substrate, and the first electrode and the second electrode of the second transistor are arranged in the same layer as the first electrode and the second electrode of the first transistor; The first transistor is used as a switching transistor in the pixel circuit, and the second transistor is used as a driving transistor in the pixel circuit. The driving transistor is used to drive a light-emitting element to emit light.

23. The driving backplane according to claim 1, wherein: The oxide semiconductor material includes indium gallium zinc oxide; The material of the gate insulating layer includes any one or more of aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride.

24. A display panel, wherein: Comprising the drive backplane described in any one of claims 1-23.

25. The display panel according to claim 24, wherein: The driving backplane further includes a pixel electrode, or the driving backplane further includes a pixel electrode and a common electrode; The display panel also includes a cell substrate and a liquid crystal. The cell substrate and the driving back plate are aligned to form an alignment gap, and the liquid crystal is filled in the alignment gap.

26. The display panel according to claim 24, wherein: It also includes a light-emitting element, a packaging layer and a protective cover. The light emitting element, the encapsulation layer and the protective cover are stacked in sequence on one side of the driving backplane; The light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode, wherein the first electrode, the light-emitting functional layer, and the second electrode are stacked in sequence, and the first electrode is electrically connected to the first transistor in the driving backplane; The light-emitting element includes an organic electroluminescent element, a Mini LED or a Micro LED.

27. A display device, wherein: A display panel comprising any one of claims 24-26.

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