Semiconductor device and manufacturing method for semiconductor device

Abstract

Disclosed in the present invention is a power semiconductor device, comprising: a substrate; a semiconductor layer arranged on the substrate; source contact areas, gate electrodes, and a first dielectric layer which are arranged on the semiconductor layer; and a first metal layer, a second dielectric layer and a second metal layer which are sequentially stacked. The first metal layer is electrically coupled to the source contact areas by means of first conductive members in the first dielectric layer; the second metal layer is electrically coupled to the first metal layer by means of second conductive members in the second dielectric layer; the second metal layer is provided with a wiring position, and in a direction away from the wiring position, the second conductive members are arranged in a plurality of areas; and for adjacent areas, the total resistance value of the second conductive member in the area relatively close to the wiring position is set to be greater than the total resistance value of the second conductive member in the area relatively distant from the wiring position. That is, according to the present application, by setting the total resistance values of the second conductive members in different areas, currents flowing through the areas tend to be consistent, thereby effectively mitigating the problems of the premature aging and failure of devices, and improving the performance and reliability of the devices.

Description

Semiconductor device and method for preparing semiconductor device Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] In the application process of integrated circuits, when the device is on, its performance will be affected by the equivalent parasitic resistance.

[0003] During actual operation, the researchers of this application discovered that in the current MOSFET tube, the parasitic resistance of the metal layer is located at the source end of the MOSFET tube. When it is turned on, the equivalent parasitic resistance of each region is different, resulting in differences in the current size of each region and inconsistent junction temperatures in different regions, causing premature aging and failure of the semiconductor device, affecting the performance and reliability of the semiconductor device. Technical Solutions

[0004] The main technical problem solved by the present invention is: to provide a power semiconductor device, which adopts a double-layer metal layer as the source layer, and is provided with a dielectric layer containing multiple through-holes in the source layer. By adjusting the spacing between the through-holes, the conductivity coefficient and / or width of the conductive material, the current in each area tends to be consistent, effectively alleviating the premature aging and failure problems caused by inconsistent current and temperature, and improving the performance and reliability of the semiconductor device.

[0005] To solve the above technical problems, a technical solution adopted in the present application is: to provide a power semiconductor device, comprising: a substrate, a semiconductor layer, a plurality of source contact regions, a plurality of gate electrodes, a first dielectric layer, a first metal layer, a second dielectric layer, and a second metal layer; the semiconductor layer is disposed on the substrate; the source contact region is disposed on the semiconductor layer; the gate electrode is disposed on the semiconductor layer; the first dielectric layer is disposed on the semiconductor layer; the first metal layer is disposed on the first dielectric layer, the first metal layer is electrically coupled to the source contact region via a first conductive member, the first conductive member being disposed in the first dielectric layer; the second dielectric layer is disposed on the first metal layer; the second metal layer is disposed on the second dielectric layer, the second metal layer is electrically coupled to the first metal layer via a second conductive member, the second conductive member being disposed in the second dielectric layer; wherein the second metal layer has a wiring position for wiring, and the second conductive member is disposed in a plurality of regions in a direction away from the wiring position, wherein, between adjacent regions, the total resistance value of the second conductive member in a region relatively close to the wiring position is configured to be greater than the total resistance value of the second conductive member in a region relatively far from the wiring position.

[0006] To solve the above technical problems, the second technical solution adopted in the present application is: to provide a power semiconductor device, comprising: a substrate, a semiconductor layer, a plurality of source contact regions, a plurality of gate electrodes, a first dielectric layer, a first conductive structure, a second dielectric layer, and a second conductive structure; the semiconductor layer is arranged on the substrate, the source contact region is arranged on the semiconductor layer, the gate electrode is arranged on the semiconductor layer, the first dielectric layer is arranged on the semiconductor layer, and the first conductive structure is at least partially arranged on the first dielectric layer; the second dielectric layer is arranged on the second conductive structure; and the second conductive structure is at least partially arranged on the second dielectric layer; wherein the source contact regions are respectively configured to connect to the first conductive structure and to connect to the second conductive structure through the first conductive structure, and the second conductive structure has a wiring position for wiring on a surface away from the semiconductor layer; the total resistance between any of the source contact regions and the wiring position is configured so that the difference between the total resistance between any other of the source contact regions and the wiring position is less than a resistance difference threshold.

[0007] In order to solve the above technical problems, the third technical solution adopted in this application is: to provide a power semiconductor device, including: a drift layer, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, a plurality of first conductive members, and a plurality of second conductive members; the first dielectric layer is arranged on the drift layer, and the first metal layer is arranged on the first dielectric layer; the second dielectric layer is arranged on the first metal layer; the second metal layer is arranged on the second dielectric layer, so that at least a portion of the second metal layer provides a wiring position; the first conductive member is electrically coupled to the first metal layer and isolated by the first dielectric layer; the second conductive member is electrically coupled to the first metal layer and the second metal layer and isolated by the second dielectric layer; wherein, in a working state, the semiconductor device is configured to conduct in each of the second conductive members and each of the first conductive members based on the current signal provided by the wiring position, wherein the current difference between any two of the second conductive members is less than the current difference threshold.

[0008] In order to solve the above technical problems, the fourth technical solution adopted in the present application is: to provide a power semiconductor device, comprising: a drift layer, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, a plurality of first conductive members, and a plurality of second conductive members; the first dielectric layer is arranged on the drift layer; the first metal layer is arranged on the first dielectric layer; the second dielectric layer is arranged on the first metal layer; the second metal layer is arranged on the second dielectric layer; the plurality of first conductive members are respectively electrically coupled to the first metal layer and isolated from each other by the first dielectric layer; the plurality of second conductive members are respectively electrically coupled to the second metal layer and isolated from each other by the second dielectric layer; wherein the second metal layer includes a wiring position for wiring, and the second conductive members are arranged in a plurality of regions of equal width in a direction away from the wiring position; in adjacent regions, the total resistance value of the second conductive members in the region relatively close to the wiring position is configured to be smaller than the total resistance value of the second conductive members in the region relatively far away from the wiring position.

[0009] In order to solve the above technical problems, the fifth technical solution adopted in this application is: to provide a power semiconductor device, including: a drift layer, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, a plurality of first conductive members, and a plurality of second conductive members; the first dielectric layer is arranged on the drift layer; the first metal layer is arranged on the first dielectric layer; the second dielectric layer is arranged on the first metal layer; the second metal layer is arranged on the second dielectric layer; the plurality of first conductive members are respectively electrically coupled to the first metal layer and isolated from each other by the first dielectric layer; the plurality of second conductive members are respectively electrically coupled to the second metal layer and isolated from each other by the second dielectric layer; wherein the second metal layer includes a wiring position for wiring, and the spacing between the second conductive members tends to decrease in the direction away from the wiring position.

[0010] In order to solve the above technical problems, the sixth technical solution adopted in this application is: to provide a power semiconductor device, including: a drift layer, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, a plurality of first conductive members, and a plurality of second conductive members; the first dielectric layer is arranged on the drift layer; the first metal layer is arranged on the first dielectric layer; the second dielectric layer is arranged on the first metal layer; the second metal layer is arranged on the second dielectric layer; the plurality of first conductive members are respectively electrically coupled to the first metal layer and isolated from each other by the first dielectric layer; the plurality of second conductive members are respectively electrically coupled to the second metal layer and isolated from each other by the second dielectric layer; wherein the second metal layer includes a wiring position for wiring, and the conductivity of the conductive material of the second conductive member tends to increase in the direction away from the wiring position.

[0011] In order to solve the above technical problems, the seventh technical solution adopted in this application is: to provide a power semiconductor device, including: a drift layer, a first dielectric layer, a first metal layer, a second dielectric layer, a plurality of first conductive members, and a plurality of second conductive members; the first dielectric layer is arranged on the drift layer; the first metal layer is arranged on the first dielectric layer; the second dielectric layer is arranged on the first metal layer; the second metal layer is arranged on the second dielectric layer; the plurality of first conductive members are respectively electrically coupled to the first metal layer and isolated from each other by the first dielectric layer; the plurality of second conductive members are respectively electrically coupled to the second metal layer and isolated from each other by the second dielectric layer; wherein the second metal layer includes a wiring position for wiring, and the cross-sectional area of ​​the second conductive member tends to increase in the direction away from the wiring position.

[0012] Different from the current technical solutions, the power semiconductor device provided by the present application includes: a substrate, a semiconductor layer, a plurality of source contact regions, a plurality of gate electrodes, a first dielectric layer, a first metal layer, a second dielectric layer, and a second metal layer; the semiconductor layer is arranged on the substrate; the source contact region is arranged on the semiconductor layer; the gate electrode is arranged on the semiconductor layer; the first dielectric layer is arranged on the semiconductor layer; the first metal layer is arranged on the first dielectric layer, the first metal layer is electrically coupled to the source contact region through a first conductive member, the first conductive member is arranged in the first dielectric layer; the second dielectric layer is arranged on the first metal layer; the second metal layer is arranged on the second dielectric layer, the second metal layer is electrically coupled to the source contact region through the second conductive member The first metal layer is electrically coupled, and the second conductive member is arranged in the second dielectric layer; wherein the second metal layer has a wiring position for wiring, and the second conductive member is arranged in several areas in the direction away from the wiring position, wherein, between adjacent areas, the total resistance value of the second conductive member in the area relatively close to the wiring position is configured to be greater than the total resistance value of the second conductive member in the area relatively away from the wiring position; that is, the second conductive member is set in the second dielectric layer in the present application, and by adjusting the spacing, cross-sectional area and / or conductivity coefficient of the second conductive member, the current flowing to the wiring position in each area tends to be consistent, effectively alleviating the premature aging and failure problems caused by the inconsistency of current and temperature, and improving the performance and reliability of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0014] FIG1 is a schematic structural diagram of a first embodiment of a power semiconductor device in the present application;

[0015] FIG2 is a schematic diagram of the specific structure of the first embodiment of the present application;

[0016] FIG3 is a schematic structural diagram of an embodiment of a doped region in the present application;

[0017] FIG4 is a schematic structural diagram of a second embodiment of a power semiconductor device in the present application;

[0018] FIG5 is a schematic diagram of the specific structure of the second embodiment of the present application;

[0019] FIG6 is a schematic structural diagram of a third embodiment of a power semiconductor device of the present application;

[0020] FIG7 is a schematic diagram of the specific structure of the third embodiment of the present application;

[0021] FIG8 is a top view of the structure of the gate layer in the third embodiment of the present application;

[0022] FIG9 is a schematic top view of an embodiment of the surface structure of a power semiconductor device in the present application;

[0023] FIG10 is a schematic structural diagram of a fourth embodiment of a power semiconductor device of the present application;

[0024] FIG11 is a schematic diagram of the specific structure of the fourth embodiment of the present application;

[0025] FIG12 is a schematic structural diagram of a fifth embodiment of a power semiconductor device in the present application;

[0026] FIG13 is a schematic diagram of the specific structure of the fifth embodiment of the present application;

[0027] FIG14 is a schematic structural diagram of a sixth embodiment of a power semiconductor device in the present application;

[0028] FIG15 is a schematic diagram of the specific structure of the sixth embodiment of the present application;

[0029] FIG16 is a schematic structural diagram of a seventh embodiment of a power semiconductor device in the present application;

[0030] FIG17 is a schematic diagram of the specific structure of the seventh embodiment of the present application.

[0031] In the accompanying drawings, there are a drift layer 10, a substrate 100, a semiconductor layer 200, a doped region 210, a semiconductor material layer 220, a source contact region 300, a gate layer 40, a first gate layer 41, a second gate layer 42, a third gate layer 43, a gate electrode 400, a first dielectric layer 500, a first through hole, a terminal protection layer 510, a first conductive structure 60, a first metal layer 600, a first conductive member 610, a second dielectric layer 700, a second through hole, a second conductive structure 80, a second metal layer 800, a second conductive member 810, a wiring position 820, a transition protection layer 830, a source contact pad 840, a drain electrode 900, a first region R1, a second region R2, and a third region R3. Modes for Carrying Out the Invention

[0032] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0033] Current semiconductor devices, particularly MOSFETs, are typically designed with the wire boundary located at the center of the chip. After flowing upward from the substrate epitaxy through the ohmic (OC) contact holes, the current in the chip's edge cells must flow laterally along the chip's surface metal, ultimately reaching the first solder joint at the source wire boundary. The equivalent parasitic resistance is located at the MOSFET's source terminal. During forward conduction, this equivalent parasitic resistance at the source terminal generates a voltage drop, reducing both the MOSFET's actual GS and DS voltage drops, leading to a decrease in on-state current. Variations in the equivalent parasitic resistance of cells located at different locations on the chip result in varying current levels during on-state, leading to inconsistent junction temperatures at different locations on the chip. Although MOSFETs have a positive temperature coefficient of on-resistance and self-regulate their temperature distribution, this regulation exhibits hysteresis, making it impossible to improve or eliminate current and temperature variations across different regions of the chip during on-state. Long-term current and temperature unevenness can lead to premature aging and failure of semiconductor devices, reducing their reliability.

[0034] Therefore, a semiconductor device is provided, which arranges a plurality of second conductive members in a second dielectric layer between two metal layers, and adjusts the spacing, cross-sectional area and / or conductivity between the second conductive members so that the current flowing to the wiring position in each area tends to be consistent, thereby effectively alleviating the premature aging and failure problems caused by inconsistent current and temperature, and improving the performance and reliability of the power semiconductor device.

[0035] Please refer to FIG1 , which is a schematic structural diagram of a first embodiment of a power semiconductor device in the present application.

[0036] As shown in Figure 1, the power semiconductor device includes a substrate 100, a semiconductor layer 200, several source contact regions 300, several gate electrodes 400, a first dielectric layer 500, a first metal layer 600, a second dielectric layer 700, and a second metal layer 800; wherein, the semiconductor layer 200 is arranged on the substrate 100, the source contact region 300 is arranged on the semiconductor layer 200, the gate electrode 400 is arranged on the semiconductor 200, the first dielectric layer 500 is arranged on the semiconductor layer 200, the first metal layer 600 is arranged on the semiconductor layer 200, the first metal layer 600 is arranged on the semiconductor layer 200, the first metal layer 600 is coupled to the source contact region 300 through a first conductive member 610, and the first conductive member 610 is arranged in the first dielectric layer 500; the second dielectric layer 700 is arranged on the first metal layer 600; the second metal layer 800 is arranged on the second dielectric layer 700, the second metal layer 800 is coupled to the first metal layer 600 through a second conductive member 810, and the second conductive member 810 is arranged in the second dielectric layer 700.

[0037] Among them, the second metal layer 800 has a wiring position 820 for wiring. In the direction away from the wiring position 820, the second conductive member 810 is arranged in several areas. Between adjacent areas, the total resistance value of the second conductive member 810 in the area relatively close to the wiring position 820 is configured to be greater than the total resistance value of the second conductive member 810 in the area relatively away from the wiring position 820; so as to reduce the current difference at different positions of the power semiconductor device when the device is turned on, thereby improving the current sharing effect of the device.

[0038] The substrate 100 may be any suitable base material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI); the substrate 100 may be an N+ type substrate, and the semiconductor layer 200 may be N-EPI (N-Epitaxial), which is an N-type epitaxial layer.

[0039] The material of the first conductive member 610 and / or the second conductive member 810 may be a conductive-type doped semiconductor material, or the material of the first conductive member 610 and / or the second conductive member 810 may be a metal material.

[0040] It should be noted that there may be one wiring position 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the region where the wiring position 820 is located. In other embodiments, there may be two or more wiring positions 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the region surrounded by the plurality of wiring positions 820. For example, as shown in FIG1 , there are two wiring positions 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the line connecting the two wiring positions 820.

[0041] Please refer to FIG2 , which is a schematic diagram of the specific structure of the first embodiment of the present application.

[0042] In some embodiments, the power semiconductor device is a vertical conductive MOSFET. Therefore, the structure of the power semiconductor device in the present application is as follows from bottom to top: the substrate 100, the semiconductor layer 200, the source contact region 300, the gate electrode 400 and the first dielectric layer 500 are all arranged on the semiconductor layer 200, and the gate electrode 400 is separated from the source contact region 300 by the first dielectric layer 500, and the gate electrode 400 is separated from the first metal layer 600 by the first dielectric layer 500; further, the power semiconductor device may also include a drain electrode 900, and the substrate 100 is arranged on the drain electrode 900.

[0043] When the device is in the on-state, the current difference between any two adjacent source contact areas is configured to be zero, that is, the currents in adjacent source contact areas are equal to ensure that the currents flowing from the source contact area 300 to the second conductive member 810 are equal; therefore, when the device is in the on-state, the current difference between any two adjacent source contact areas is less than the current difference threshold, thereby achieving the device current sharing effect. The current difference threshold here is 10%, that is, the current difference between any two adjacent source contact areas is less than 10%.

[0044] In some embodiments, the source contact region 300 may be provided with an ohmic contact layer (not marked in the drawings) for electrical coupling between the first conductive member 610 and the source contact region 300 to ensure the input and output of current, wherein the thickness of the ohmic contact layer is less than the thickness of the gate electrode 400 .

[0045] In some embodiments, for example, the first conductive member 610 and the second conductive member 810 are made of metal. A plurality of first through-holes penetrating the first dielectric layer 500 are provided in the first dielectric layer 500. The first conductive member 610 is a first metal conductor filled in the plurality of first through-holes. The first metal conductor electrically couples the first metal layer 600 and the source contact region 300, allowing the source contact region 300 to transmit current to the first metal layer 600 through the first conductive member 610, thereby forming a pathway.

[0046] The second dielectric layer 700 is provided with a plurality of second through holes penetrating the second dielectric layer 700. The second conductive member 810 is a second metal conductor filled in the plurality of second through holes. The second metal conductor electrically couples the second metal layer 800 and the first metal layer 600, so that the first metal layer 600 can transmit current to the second metal layer 800 through the second conductive member 810, thereby forming a path.

[0047] The first metal conductor and the second metal conductor can be silver, copper, gold, aluminum, tin, zinc, nickel, etc. The first metal layer 600 serves as the first source layer, and the second metal layer 800 serves as the second source layer. The first metal layer 600 and the second metal layer 800 form a composite source layer, forming a current-sharing structure, so that the current flowing through different regions tends to be consistent, achieving a current-sharing effect.

[0048] In some embodiments, a terminal protection layer 510 may be included, which is disposed on the semiconductor layer 200 ; a transition protection layer 830 may be included, which covers a portion of the second dielectric layer 700 and a portion of the second metal layer 800 , wherein the transition protection layer 830 may be a surface passivation layer.

[0049] In some embodiments, a doped region 210 is provided on a surface of the semiconductor layer 200 away from the substrate 100 , that is, the semiconductor layer 200 includes a semiconductor material layer 220 and a doped region 210 .

[0050] Please refer to FIG3 , which is a schematic structural diagram of an embodiment of a doped region in the present application.

[0051] As shown in Figure 3, a doping region 210 is formed on the surface of the semiconductor layer 200 away from the substrate 100, and the doping region 210 includes a first doping region 211, a second doping region 212 and a third doping region 213; the third doping region 213 is located on a portion of the second doping region 212, the first doping region 211 is coupled to the second doping region 212 and the third doping region 213 respectively, the gate electrode 400 is coupled to the second doping region 212, and the source contact region 300 is coupled to the first doping region 211.

[0052] Specifically, the first doping region 211 can be a doped P+ region, the second doping region 212 can be a P- region, and the third doping region 213 can be an N+ region. The current flows vertically to the substrate 100, the semiconductor layer 200, and the doping region 210 through the drain electrode 900, and flows laterally in the doping region 210, flows through the channel region of the second doping region 212 to the third doping region 213, and then flows vertically to the first metal layer 600 through the source contact region 300 and the first conductive member 610, and then flows to the second metal layer 800 through the second conductive member 810, and then flows to the outside through the wiring position 820.

[0053] In some embodiments, the gate electrode 400 is disposed on the semiconductor layer 200 with the first dielectric layer 500 and the source contact region 300 spaced apart, and the gate electrode 400 is isolated from the first metal layer 600 by the first dielectric layer 500 to form a gate-source junction (GS junction), thereby playing the role of controlling the signal.

[0054] In some embodiments, the second dielectric layer 700 is divided into several regions in a direction away from the wiring position 820, and the region widths of any two adjacent regions are the same, and the direction of the region width is the direction away from the wiring position, thereby dividing multiple regions with the same region width to avoid the influence of current differences caused by different region widths, so as to prepare for the settings in each region in subsequent regions.

[0055] In some embodiments, the resistance values ​​of the second conductive elements 810 are the same, and there are multiple second conductive elements 810 in each region. Between two adjacent regions, the spacing between any two adjacent second conductive elements 810 in the region close to the wiring position 820 is greater than the spacing between any two adjacent second conductive elements 810 in the region away from the wiring position 820.

[0056] In other embodiments, when the widths of any two adjacent regions are the same, the resistance values ​​of the second conductive elements 810 are the same, and there are multiple second conductive elements 810 in each region. Between two adjacent regions, the spacing between any two adjacent second conductive elements 810 in the region close to the wiring position 820 is greater than the spacing between any two adjacent second conductive elements 810 in the region away from the wiring position 820.

[0057] Taking three regions as an example, the region within a first distance range from the wiring position 820 is the first region R1, the range greater than the first distance and less than the second distance is the second region R2, and the range greater than the second distance and less than the third distance is the third region R3, where the third distance is greater than the second distance and greater than the first distance; wherein the resistance values ​​of the second conductive elements in the first region R1, the second region R2, and the third region R3 are the same; the difference is that the spacing between any two adjacent second conductive elements 810 in the first region R1 is greater than the spacing between any two adjacent second conductive elements 810 in the second region R2; the spacing between any two adjacent second conductive elements 810 in the second region R2 is greater than the spacing between any two adjacent second conductive elements 810 in the third region R3; that is, by setting the spacing between the second conductive elements 810, the total resistance value of the second conductive elements 810 in the region close to the wiring position 820 is configured to be greater than the total resistance value of the second conductive elements 810 in the region away from the wiring position 820.

[0058] In addition, it can be understood that the area widths of any two adjacent areas can be the same or different, and can be set according to design requirements, as long as the total resistance value of the second conductive member 810 in the area relatively close to the wiring position 820 between adjacent areas is configured to be greater than the total resistance value of the second conductive member 810 in the area relatively far away from the wiring position 820.

[0059] In some embodiments, the number of second conductive members 810 in each region is the same, and the conductivity coefficient of each second conductive member 810 is the same. Between two adjacent regions, the cross-sectional area of ​​the second conductive member 810 in the region close to the wiring position 820 is smaller than the cross-sectional area of ​​the second conductive member 810 in the region away from the wiring position 820, wherein the cross-sectional area is a section parallel to the surface of the second conductive member 810 and the first metal layer 600.

[0060] In other embodiments, when the widths of any two adjacent regions are the same, the number of second conductive members 810 in each region is the same, and the conductivity coefficient of each second conductive member 810 is the same. Between two adjacent regions, the cross-sectional area of ​​the second conductive member 810 in the region close to the wiring position 820 is smaller than the cross-sectional area of ​​the second conductive member 810 in the region away from the wiring position 820, wherein the cross-sectional area is a section parallel to the surface of the second conductive member 810 and the first metal layer 600.

[0061] Taking three regions as an example, the number of second conductive members 810 in the first region R1, the second region R2 and the third region R3 is the same, and the conductivity coefficients of the second conductive members 810 are the same; the difference is that: the cross-sectional area of ​​the second conductive member 810 in the first region R1 is smaller than the cross-sectional area of ​​the second conductive member 810 in the second region R2; the cross-sectional area of ​​the second conductive member 810 in the second region R2 is smaller than the cross-sectional area of ​​the second conductive member 810 in the third region R3, wherein the cross-sectional area is a cross-sectional area of ​​the second conductive member 810 parallel to the surface of the first metal layer 600.

[0062] In addition, it can be understood that the area widths of any two adjacent areas can be the same or different, and can be set according to design requirements, as long as the total resistance value of the second conductive member 810 in the area relatively close to the wiring position 820 between adjacent areas is configured to be greater than the total resistance value of the second conductive member 810 in the area relatively far away from the wiring position 820.

[0063] In some embodiments, the number of second conductive members 810 in each region is the same, and the cross-sectional area of ​​each second conductive member 810 is the same. Between two adjacent regions, the conductivity coefficient of the second conductive member 810 in the region close to the wiring position 820 is smaller than the conductivity coefficient of the second conductive member 810 in the region away from the wiring position 820, wherein the cross section is parallel to the surface of the first metal layer 600.

[0064] Taking three regions as an example, the number of second conductive elements 810 contained in the first region R1, the second region R2 and the third region R3 is the same, and the cross-sectional area of ​​the second conductive elements 810 is the same. The difference is that the conductivity coefficient of the second conductive element 810 in the first region R1 is smaller than the conductivity coefficient of the second conductive element 810 in the second region R2, and the conductivity coefficient of the second conductive element 810 in the second region R2 is smaller than the conductivity coefficient of the second conductive element 810 in the third region R3. As long as the total resistance value of the second conductive elements 810 in the region relatively close to the wiring position 820 between adjacent regions is configured to be greater than the total resistance value of the second conductive elements 810 in the region relatively far from the wiring position 820, it will be sufficient.

[0065] Its working principle is: the current flows vertically upward from the bottom of the power semiconductor device, passing through the substrate 100, the semiconductor layer 200, the first conductive element 610 in the first dielectric layer 500, the first metal layer 600, the second conductive element 810 in the second dielectric layer 700, the second metal layer 800 to the wiring position 820, and then flows to the outside through the wiring position 820.

[0066] When current flows through the second conductive member 810, the total resistance in the current path varies depending on the cross-sectional area, conductivity, and / or spacing between the second conductive members 810. To reduce the impact of the resistance of the second conductive member 810 on the total resistance of the current path, the cross-sectional area, conductivity, and / or spacing between the second conductive members 810 are set as needed based on the distance between the second conductive member 810 and the connection point 820. This allows the total resistance of the second conductive member 810 in adjacent regions that are relatively close to the connection point 820 to be smaller than the total resistance of the second conductive member 810 in regions that are relatively far from the connection point 820. This results in a more consistent current flowing from each region to the connection point 820, and also a more consistent temperature across the various regions of the power semiconductor device.

[0067] In this embodiment, the cross-sectional area, conductivity and / or spacing between the second conductive members 810 are set to change in a gradient according to the distance between the second conductive member 810 and the wiring position 820, so that the resistance of the second conductive member 810 gradually decreases in the direction away from the wiring position 820, so that the current flowing from the substrate 100 to the wiring position 820 in each region tends to be consistent, achieving a current balancing effect, and also making the temperature of each region of the power semiconductor device tend to be consistent, effectively alleviating the premature aging and failure problems caused by the inconsistency of current and temperature, and improving the performance and reliability of the power semiconductor device.

[0068] Please refer to FIG4 , which is a schematic structural diagram of a second embodiment of a power semiconductor device in the present application.

[0069] As shown in Figure 4, the power semiconductor device includes a substrate 100, a semiconductor layer 200, several source contact regions 300, several gate electrodes 400, a first dielectric layer 500, a first conductive structure 60, a second dielectric layer 700, and a second conductive structure 80; the semiconductor layer 200 is arranged on the substrate 100, the source contact region 300 is arranged on the semiconductor layer 200, the gate electrode 400 is arranged on the semiconductor layer 200, the first dielectric layer 500 is arranged on the semiconductor layer 200, the first conductive structure 60 is at least partially arranged on the first dielectric layer 500, the second dielectric layer 700 is arranged on the first conductive structure 60, and the second conductive structure 80 is at least partially arranged on the second dielectric layer 700.

[0070] Among them, the source contact area 300 is configured to connect to the first conductive structure 60 and to the second conductive structure 80 through the first conductive structure 60. The second conductive structure 80 has a wiring position 820 for wiring on the surface away from the semiconductor layer 200. The total resistance value between any source contact area 300 and the wiring position 820 is configured to be less than the resistance difference threshold value between the total resistance value between any other source contact area 300 and the wiring position 820; when the device is turned on, the current difference at different positions of the power semiconductor device is reduced, thereby improving the current sharing effect of the device.

[0071] The resistance difference threshold is 1.46 ohms, that is, the difference between the total resistance between any source contact region 300 and the wiring point 820 and the total resistance between any other source contact region 300 and the wiring point 820 is less than 1.46 ohms.

[0072] In some embodiments, the gate electrode 400 is isolated from the source contact region 300 and the first conductive structure 60 by the first dielectric layer 500 to form a gate-source junction (GS junction), thereby playing a role in controlling signals.

[0073] In some embodiments, the resistance value between any source contact area 300 and the wiring position 820 is configured to have a difference of zero from the resistance value between other source contact areas 300 and the wiring position 820; that is, from the perspective of the relationship between a single source contact area 300 and the wiring position 820, by setting the resistance value between the source contact area 300 and the wiring position to zero compared with the resistance values ​​of other source contact areas 300 and the wiring position, when the device is turned on, the current difference at different positions of the power semiconductor device is reduced, thereby improving the current sharing effect of the device.

[0074] Please refer to FIG5 , which is a schematic diagram of the specific structure of the second embodiment of the present application.

[0075] As shown in Figure 5, in some embodiments, taking the example that the materials of the first conductive member 610 and the second conductive member 810 can be metal materials, the first conductive structure 60 includes a first metal layer 600 arranged on the first dielectric layer 500, and a first conductive member 610 connected to the first metal layer 600; a plurality of first through holes penetrating the first dielectric layer 500 are provided in the first dielectric layer 500, and the first conductive member 610 is a first metal conductor filling the plurality of first through holes, and the first metal conductor electrically couples the first metal layer 600 and the source contact area 300.

[0076] There can be multiple first conductive structures 60, each of which includes a first conductive part 610 and a portion of the first metal layer 600 corresponding to the position between the first conductive part 610 and the wiring position 820, that is, there can be as many first conductive structures 60 as there are first conductive parts 610.

[0077] That is, the first conductive structure 60 as a whole can effectively reduce the situation where the current flows differently due to the different materials of the first metal layer 600 and the first conductive member 610 , thereby improving the current sharing effect of the device.

[0078] In some embodiments, the second conductive structure 80 includes: a second metal layer 800 arranged on the second dielectric layer 700, and a second conductive member 810 connected to the second metal layer 800; a plurality of second through holes penetrating the second dielectric layer 700 are provided in the second dielectric layer 700, and the second conductive member 810 is a second metal conductor filling the plurality of second through holes, and the second metal conductor couples the second metal layer 800 with the first conductive structure 60.

[0079] The second conductive structure 80 may also include multiple ones, each of which includes a second conductive element 810 and a portion of the second metal layer 800 from the second conductive element 810 to the wiring position 820 , that is, there are as many second conductive structures 80 as there are second conductive elements 810 .

[0080] That is, the second conductive structure 80 as a whole can effectively reduce the difference in runoff current caused by the different materials of the second metal layer 800 and the second conductive member 810 , thereby improving the current sharing effect of the device.

[0081] It can be understood that in some embodiments, the first conductive member 610 can be used as a source electrode, so that multiple source electrodes can be respectively configured to connect the source contact area 300 and the first conductive structure 60, and then connected to the second conductive structure 80 through the first conductive structure 60; or the first conductive structure 60 can be used as a source electrode, so that multiple source electrodes can be respectively configured to connect to the second conductive structure 80; or the first conductive structure 60 and the second conductive structure 80 can be used to form a composite source electrode, that is, the first conductive structure 60 and the second conductive structure 80 can be used as source electrodes; the source electrode thus formed forms a gate-source junction (GS junction) with the separated gate layer 400, thereby playing the role of controlling the signal and completing the current flow.

[0082] In some embodiments, a doped region 210 is provided on the surface of the semiconductor layer 200 away from the substrate 100 , that is, the semiconductor layer 200 includes a semiconductor material layer 220 and a doped region 210 . The specific structure can be found in the description of the first embodiment and will not be repeated here.

[0083] In some embodiments, the second conductive member 810 is configured in several regions of equal width in a direction away from the wiring position 820; and in adjacent regions, the total resistance value of the second conductive member 810 in the region relatively close to the wiring position 820 is configured to be smaller than the total resistance value of the second conductive member 810 in the region relatively far from the wiring position 820, thereby making the current flowing from each region to the docking position 820 tend to be consistent, achieving a device current sharing effect, and also making the temperature of each region of the power semiconductor device tend to be consistent.

[0084] Between two adjacent regions, the total cross-sectional area of ​​the second conductive member 810 in the region close to the wiring position 820 is smaller than the total cross-sectional area of ​​the second conductive member 810 in the region away from the wiring position 820; that is, the total cross-sectional area of ​​the second conductive member 810 in the region is set so that the total resistance value of the second conductive member 810 in the region close to the wiring position 820 is smaller than the total resistance value of the second conductive member 810 in the region relatively away from the wiring position 820, thereby enabling the power semiconductor device to achieve a current sharing effect.

[0085] In some embodiments, the cross-sectional areas of the second conductive members 810 in the same region are the same. In two adjacent regions, the spacing between two adjacent second conductive members 810 in the region near the connection point 820 is greater than the spacing between two adjacent second conductive members 810 in the region away from the connection point 820. Specifically, the spacing between two adjacent second conductive members 810 within a region is set such that the total resistance of the second conductive members 810 in the region near the connection point 820 is less than the total resistance of the second conductive members 810 in the region relatively far from the connection point 820, thereby achieving a current-sharing effect for the power semiconductor device.

[0086] Taking three regions as an example, the region within the first distance range from the wiring position 820 is the first region R1, the range greater than the first distance and less than the second distance is the second region R2, and the range greater than the second distance and less than the third distance is the third region R3, and the third distance is greater than the second distance and greater than the first distance; the total cross-sectional area of ​​the second conductive member 810 in the first region R1 is smaller than the total cross-sectional area of ​​the second conductive member 810 in the second region R2, and the total cross-sectional area of ​​the second conductive member 810 in the second region R2 is smaller than the total cross-sectional area of ​​the second conductive member 810 in the third region R3, so that the device achieves a current equalization effect.

[0087] Furthermore, the second conductive members 810 can be coordinated and set by the total cross-sectional area and the spacing between two adjacent second conductive members 810; for example, the spacing between two adjacent second conductive members 810 in the first region R1 is greater than the spacing between two adjacent second conductive members 810 in the second region R2; the spacing between two adjacent second conductive members 810 in the second region R2 is greater than the spacing between two adjacent second conductive members 810 in the third region R3; so that when the cross-sectional areas of the second conductive members 810 in the same region are the same, in adjacent regions, the total resistance value of the second conductive members 810 in the region relatively close to the wiring position 820 is configured to be smaller than the total resistance value of the second conductive members 810 in the region relatively far from the wiring position 820; and thus the total resistance value between any source contact region 300 and the wiring position 820 is configured to have a difference between the total resistance value and the total resistance value between any other source contact region 300 and the wiring position 820 that is smaller than the resistance difference threshold, thereby enabling the power semiconductor device to achieve a current sharing effect.

[0088] In other embodiments, the cross-sectional areas of the second conductive members 810 in the same region are the same. The number of second conductive members 810 in each region is the same, and between two adjacent regions, the conductivity of the conductive material of the second conductive members 810 in the region close to the wiring position 820 is smaller than the conductivity of the conductive material of the second conductive members 810 in the region far from the wiring position 820.

[0089] Taking three regions as an example, the number of second conductive elements 810 in the first region R1, the second region R2, and the third region R3 is the same, the cross-sectional area of ​​the second conductive elements 810 in the same region is the same, the conductivity of the conductive material of the second conductive elements 810 in the first region R1 is smaller than the conductivity of the conductive material of the second conductive elements 810 in the second region R2, and the conductivity of the conductive material of the second conductive elements 810 in the second region R2 is smaller than the conductivity of the conductive material of the second conductive elements 810 in the third region R3. Similarly, when the cross-sectional area of ​​the second conductive elements in the same region is the same and the number of second conductive elements 810 in each region is the same, the total resistance of the second conductive elements 810 in the region relatively close to the connection point 820 is configured to be smaller than the total resistance of the second conductive elements 810 in the region relatively far from the connection point 820. Consequently, the total resistance between any source contact region 300 and the connection point 820 is configured to have a difference of less than a resistance difference threshold from the total resistance between any other source contact region 300 and the connection point 820, thereby achieving a current sharing effect for the power semiconductor device.

[0090] In some embodiments, the spacing between the second conductive elements decreases in a direction away from the wiring position 820 .

[0091] That is, by setting the spacing between the second conductive members 810 , the total resistance between any source contact region 300 and the wiring point 820 is configured to have a difference smaller than the total resistance between any other source contact region 300 and the wiring point 820 .

[0092] In some embodiments, the spacing between the second conductive elements tends to decrease.

[0093] The conductive materials of the second conductive members 810 have the same conductivity coefficient, and the cross-sectional areas of the second conductive members 810 are the same, wherein the cross-sectional areas are parallel to the surface of the first metal layer 600. In this case, the second conductive members 810 are not divided into different regions. That is, the spacing between the second conductive members 810 in the second dielectric layer decreases in a direction away from the wiring position 820, so that the difference in the total resistance between each source contact region 300 and the wiring position 820 is less than the resistance difference threshold.

[0094] The spacing between the second conductive elements 810 gradually decreases in a direction away from the wiring position 820 , that is, the resistance of each second conductive element 810 is adjusted so that the device achieves a current-sharing effect.

[0095] In other embodiments, when the conductivity coefficients of the conductive materials of the second conductive elements 810 are the same and the cross-sectional areas of the second conductive elements 810 are the same, the second conductive elements 810 are arranged in several areas, and the spacing between two adjacent second conductive elements 810 in the same area is the same; in adjacent areas, the spacing between adjacent second conductive elements 810 in areas close to the wiring position 820 is smaller than the spacing between adjacent second conductive elements 810 in areas away from the wiring position 820; that is, the spacing between two adjacent second conductive elements 810 in different areas is adjusted to adjust the resistance of the second conductive elements 810 in each area, so that the device achieves a current sharing effect.

[0096] In some embodiments, the conductivity of the conductive material of the second conductive member 810 increases in a direction away from the wiring position 820 .

[0097] That is, by setting the conductivity of the conductive material of the second conductive member 810 , the difference between the total resistance values ​​between each source contact region 300 and the wiring point 820 is smaller than the resistance difference threshold.

[0098] In a direction away from the wiring position 820 , the spacing between adjacent second conductive elements 810 is the same, and the cross-sectional areas of the second conductive elements 810 are the same, wherein the cross-sectional area is parallel to the surface of the first metal layer 600 .

[0099] That is, when the spacing between adjacent second conductive members 810 is the same and the cross-sectional area of ​​the second conductive members 810 is the same, the conductivity coefficient of the conductive material of the second conductive member 810 is set to show a changing trend, thereby making the difference between the total resistance values ​​between each source contact area 300 and the wiring position 820 less than the resistance difference threshold.

[0100] In this case, the conductivity of the conductive material of the second conductive member 810 gradually increases in a direction away from the wiring position 820 .

[0101] This refers to the case where the areas are not divided, and the conductivity coefficients of the conductive materials of the second conductive member 810 are compared, that is, in the direction away from the wiring position 820, the conductivity coefficient of the conductive material of any second conductive member 810 close to the wiring position 820 is smaller than the conductivity coefficient of the conductive material of another second conductive member 810 away from the wiring position 820, so that the total resistance value between any source contact area 300 and the wiring position 820 is configured to be less than the resistance difference threshold value between the total resistance value between any other source contact area 300 and the wiring position 820.

[0102] In another embodiment, the second conductive member 810 is configured in several regions, and the conductivity coefficient of the conductive material of the second conductive member in the same region is the same; in adjacent regions, the conductivity coefficient of the conductive material of the second conductive member 810 in the region close to the wiring position 820 is smaller than the conductivity coefficient of the conductive material of the second conductive member in the region far from the wiring position; similarly, the total resistance value between any source contact region 300 and the wiring position 820 is configured to be smaller than the total resistance value between any other source contact region 300 and the wiring position 820, which is smaller than the resistance difference threshold.

[0103] That is, the device is divided into regions, and the conductivity coefficient of the conductive material of the second conductive member 810 in different regions is set to be different, thereby adjusting the total resistance value in the region, so that the difference in the total resistance value between the source contact area and the wiring position 820 in adjacent regions is less than the resistance difference threshold, thereby achieving a current equalization effect on the device and improving the reliability of the device.

[0104] In some embodiments, the cross-sectional area of ​​the second conductive member 810 increases in a direction away from the connection position.

[0105] That is, by adjusting the cross-sectional area of ​​the second conductive member 810 , the difference between the total resistance values ​​between each source contact region 300 and the wiring point 820 is smaller than the resistance difference threshold.

[0106] In the direction away from the wiring position 820, the spacing between adjacent second conductive members 810 is the same, and the conductivity coefficient of the conductive material of the second conductive members 810 is the same, while the cross-sectional area of ​​the second conductive member 810 gradually increases; that is, when the spacing and the conductivity coefficient are the same, by adjusting the cross-sectional area of ​​the second conductive member 810, the difference between the total resistance values ​​between each source contact area 300 and the wiring position 820 is made less than the resistance difference threshold.

[0107] That is, in the case where no areas are divided, the cross-sectional area of ​​any second conductive member 810 close to the wiring position 820 will be larger than the cross-sectional area of ​​the corresponding second conductive member 810 away from the wiring position 820, so that the total resistance value between any source contact region 300 and the wiring position 820 is configured to be less than the resistance difference threshold value between the total resistance value between any other source contact region 300 and the wiring position 820.

[0108] In other embodiments, when the spacing between adjacent second conductive members 810 is the same and the conductivity coefficient of the conductive material of the second conductive members 810 is the same, the second conductive members 810 are arranged in several areas, and the cross-sectional area of ​​the second conductive members 810 in the same area is the same; in adjacent areas, the cross-sectional area of ​​the second conductive member 810 in the area close to the wiring position 820 is smaller than the cross-sectional area of ​​the second conductive member in the area away from the wiring position 820.

[0109] That is, the second conductive member 810 is divided into regions, and the cross-sectional area of ​​the second conductive member in each region is set differently so that the difference in the total resistance between the source contact region 300 and the wiring point 820 in each region is smaller than the resistance difference threshold.

[0110] Taking three regions as an example, the region within a first distance range from the wiring position 820 is the first region R1, the range greater than the first distance and less than the second distance is the second region R2, the range greater than the second distance and less than the third distance is the third region R3, and the third distance is greater than the second distance and greater than the first distance; the cross-sectional area of ​​the second conductive member 810 in the first region R1 is smaller than the cross-sectional area of ​​the second conductive member 810 in the second region R2, and the cross-sectional area of ​​the second conductive member 810 in the second region R2 is smaller than the cross-sectional area of ​​the second conductive member 810 in the third region R3; so that the total resistance value between any source contact region 300 and the wiring position 820 is configured to be less than the resistance difference threshold value between the total resistance value and any other source contact region 300 and the wiring position 820.

[0111] In this embodiment, the metal layer and the conductive member are taken as a whole, and the difference in overall resistance is set to be small. Then, by setting the cross-sectional area, conductivity and / or spacing between the second conductive members 810 to change in a gradient, the total resistance value between any source contact region 300 and the wiring position 820 is configured to be less than the resistance difference threshold value between the total resistance value of any other source contact region 300 and the wiring position 820, thereby making the current flowing from the substrate 100 to the wiring position 820 in each region tend to be consistent, achieving a current balancing effect, and also making the temperature of each region of the power semiconductor device tend to be consistent, effectively alleviating the premature aging and failure problems caused by the inconsistency of current and temperature, and improving the performance and reliability of the power semiconductor device.

[0112] Please refer to FIG6 , which is a schematic structural diagram of a third embodiment of a power semiconductor device of the present application.

[0113] As shown in Figure 6, the power semiconductor device includes: a drift layer 10, a first dielectric layer 500, a first metal layer 600, a second dielectric layer 700, a second metal layer 800, a plurality of first conductive members 610, and a plurality of second conductive members 810; the first dielectric layer 500 is arranged on the drift layer 10, the first metal layer 600 is arranged on the first dielectric layer 500, the second dielectric layer 700 is arranged on the first metal layer 600, and the second metal layer 800 is arranged on the second dielectric layer 700, the first conductive member 610 is electrically coupled to the first metal layer 600 and isolated by the first dielectric layer 500; the second conductive member 810 is electrically coupled to the first metal layer 600 and the second metal layer 800, and isolated by the second dielectric layer 700.

[0114] In which, in the working state, the power semiconductor device is configured to conduct in each second conductive member 810 and each first conductive member 610 based on the current signal provided by the wiring position 820, and the current difference between any two second conductive members 810 is less than the current difference threshold, so that the device achieves a current sharing effect and improves the stability of the device.

[0115] The current difference threshold value ranges from 0 to 10%.

[0116] The material of the first conductive member 610 and / or the second conductive member 810 may be a conductive-type doped semiconductor material, or the material of the first conductive member 610 and / or the second conductive member 810 may be a metal material.

[0117] It should be noted that there may be one wiring position 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the region where the wiring position 820 is located. In other embodiments, there may be two or more wiring positions 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the region surrounded by the plurality of wiring positions 820. For example, as shown in FIG5 , there are two wiring positions 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the line connecting the two wiring positions 820.

[0118] Please refer to FIG7 , which is a schematic diagram of the specific structure of the third embodiment of the present application.

[0119] As shown in FIG. 7 , based on FIG. 6 , the drift layer 10 may include a substrate 100 and a semiconductor layer 200 .

[0120] In some embodiments, a doped region 210 is provided on the surface of the semiconductor layer 200 away from the substrate 100 , that is, the semiconductor layer 200 includes a semiconductor material layer 220 and a doped region 210 . The specific structure can be found in the description of the first embodiment and will not be repeated here.

[0121] In some embodiments, taking the first conductive member 610 as a conductive doped semiconductor material as an example, a plurality of first through holes penetrating the first dielectric layer 500 are provided in the first dielectric layer 500, and the plurality of first through holes are isolated by the first dielectric layer 500, wherein the first conductive member 610 is provided in the first through holes.

[0122] The first metal layer 600 can be electrically coupled through the first conductive member 610 in the first through hole to couple with the drift layer 10 to form a path.

[0123] In some embodiments, taking the second conductive member 810 as a conductive type doped semiconductor material as an example, a plurality of second through holes penetrating the second dielectric layer 700 are provided in the second dielectric layer 700, and the plurality of second through holes are isolated by the second dielectric layer 700, wherein the second conductive member 810 is provided in the second through holes.

[0124] The second metal layer 800 can be electrically coupled to the first metal layer 600 through the second conductive member 810 in the second through hole, thereby forming a path among the drift layer 10 , the first metal layer 600 , and the second metal layer 800 .

[0125] In some embodiments, the power semiconductor device further includes a gate layer 40, which is disposed on the drift layer 10. At least a portion of the gate layer 40 is flush with the second metal layer 800 and serves as a gate contact pad. Because the portion of the gate layer 40 that is flush with the second metal layer 800 is staggered with the first metal layer 600, the cross-sectional area of ​​the first metal layer 600 can be set to be larger than the cross-sectional area of ​​the second metal layer 800. The first metal layer 600 and the second metal layer 800 constitute a composite source electrode layer. Therefore, by increasing the area of ​​the first metal layer 600, the area of ​​the active region of the semiconductor layer 200 can be increased to improve the performance of the power semiconductor device. The gate layer 40 is isolated from the first metal layer 600 and the second metal layer 800 by the first dielectric layer 500 and the second dielectric layer 700, forming a gate-source junction (GS junction), thereby playing a role in controlling the signal.

[0126] Please refer to FIG. 8 , which is a top view of the gate layer in the third embodiment of the present application.

[0127] As shown in FIG8 , the gate layer 40 may include: a plurality of first gate layers 41, a second gate layer 42, and a third gate layer 43; the first gate layer 41 is disposed on the drift layer 10 and extends along a first direction, and the plurality of first gate layers 41 are isolated from the first conductive member 610 and the first metal layer 600 by a first dielectric layer 500; the second gate layer 42 is disposed on the drift layer 10 and extends along a second direction, and the second gate layer 42 is isolated from the first conductive member 610 and the first metal layer 600 by a first dielectric layer 500. 00 isolation, wherein the second gate layer 42 is connected to multiple first gate layers 41 in the same row; the third gate layer 43 is arranged on the drift layer 10 and extends along the third direction, and the third gate layer 43 is isolated from the first metal layer 600 and the second metal layer 800 by the first dielectric layer 500 and the second dielectric layer 700, and the third gate layer 43 is flush with the second metal layer 800, serving as a gate contact pad, wherein the third gate layer 43 is connected to the second gate layer 42 and is configured to control the multiple first gate layers 41.

[0128] Moreover, while the third gate layer 43 is flush with the second metal layer 800, the third gate layer 43 and the first metal layer 600 can be staggered, that is, the cross-sectional area of ​​the portion where the third gate layer 43 is flush with the second metal layer 800 is greater than the cross-sectional area of ​​the portion where the third gate layer 43 contacts the drift layer 10, that is, the third gate layer 43 gradually increases the corresponding cross-sectional area in the direction away from the drift layer 10, thereby forming a staggered arrangement between the third gate layer 43 and the first metal layer 600; and because the first metal layer 600 and the first conductive member 610 constitute the source, and the current is transmitted to the wiring position 820 through the second conductive member 810 and the second metal layer 800, the first metal layer 600 can be set to have a cross-sectional area greater than the cross-sectional area of ​​the second metal layer 800, thereby increasing the area of ​​the active region of the semiconductor layer 200 to improve the performance of the power semiconductor device.

[0129] Figure 7 is a cross-sectional view taken along the Y1 direction of Figure 8 , i.e., Figure 7 shows only the first gate layer 41. The first direction and the second direction intersect at the same horizontal plane, and the third direction is perpendicular to the first and second directions. For example, the first direction is the X-axis direction, the second direction is the Y-axis direction, and the third direction is the Z-axis direction. The X-axis direction, the Y-axis direction, and the Z-axis direction intersect at the origin of the coordinate system.

[0130] That is, the first gate layer 41 and the second gate layer 42 form a gate-source junction (GS junction) with the first metal layer 600 on the drift layer 10, and the second gate layer 42 is connected to all the first gate layers 41 and to the third gate layer 43. The third gate layer 43 can also be connected to the outside as a gate contact pad, and then the control signal is transmitted to the second gate layer 42 and the first gate layer 41 through the third gate layer 43, thereby playing the role of a control signal for all gate layers.

[0131] Furthermore, in order to illustrate the surface structure of the power semiconductor device, FIG. 9 is used for explanation.

[0132] Please refer to FIG9 , which is a top view schematically illustrating an embodiment of the surface structure of a power semiconductor device in the present application.

[0133] As shown in FIG9 , the second metal layer 800 may include a plurality of source contact pads spaced apart from each other, wherein the wiring bit 820 is located within the range of the source contact pads, and the cross-sectional area of ​​the source contact pads may be larger than that of the gate contact pads.

[0134] Specifically, taking two source contact pads and one gate contact pad as an example, the second metal layer 800 has two source contact pads 840 spaced apart, and each source contact pad 840 can be provided with two wiring positions 820. FIG7 is a cross-sectional view along the A-A1 direction.

[0135] In some embodiments, the second conductive element 810 is disposed in a plurality of regions, and the total current difference flowing through the second conductive element 810 between any two adjacent regions is less than a current difference threshold.

[0136] Moreover, the current difference between the current values ​​of any two second conductive elements 810 in the same area is less than the current difference threshold, that is, the current values ​​of the second conductive elements 810 in the same area can be set to be consistent, and then set based on the total current value of the second conductive elements in the entire area.

[0137] That is, by dividing the regions and setting the total current of the second conductive element 810 flowing through each region, the total current difference between the second conductive elements of any two adjacent regions is smaller than the current difference threshold, thereby achieving a current balancing effect in the device and improving the stability of the device.

[0138] The current difference threshold is 10%, that is, the total current difference between the second conductive elements 810 in any two adjacent regions is less than 10%.

[0139] In some embodiments, between two adjacent regions, the cross-sectional area of ​​the second conductive member 810 in the region close to the wiring position 820 is smaller than the cross-sectional area of ​​the second conductive member 810 in the region away from the wiring position 820, wherein the cross section is parallel to the surface of the first metal layer.

[0140] As described above, with respect to the division of the first region R1, the second region R2, and the third region R3, the cross-sectional area of ​​the second conductive member 810 in the first region R1 is smaller than the cross-sectional area of ​​the second conductive member 810 in the second region R2, and the cross-sectional area of ​​the second conductive member 810 in the second region R2 is smaller than the cross-sectional area of ​​the second conductive member 810 in the third region R3; that is, by setting the cross-sectional area of ​​the second conductive member 810, the total current difference between the second conductive members 810 in any two adjacent regions is smaller than the current difference threshold, thereby enabling the device to achieve a current equalization effect and improve the stability of the device.

[0141] In another embodiment, the spacing can be set such that, specifically, the spacing between two adjacent second conductive members 810 in the area close to the wiring position 820 is greater than the spacing between two adjacent second conductive members 810 in the area away from the wiring position 820 .

[0142] As described above, as the first region R1, the second region R2, and the third region R3 are divided, the spacing between two adjacent second conductive elements 810 in the first region R1 is smaller than the cross-sectional area of ​​two adjacent second conductive elements 810 in the second region R2, and the spacing between two adjacent second conductive elements 810 in the second region R2 is smaller than the spacing between two adjacent second conductive elements 810 in the third region R3; that is, by setting the spacing between the second conductive elements 810, the total current difference between the second conductive elements 810 in any two adjacent regions is smaller than the current difference threshold, thereby achieving a current equalization effect in the device and improving the stability of the device.

[0143] In another embodiment, the conductivity coefficient can be set. Specifically, between two adjacent areas, the conductivity coefficient of the conductive material of the second conductive member 810 in the area close to the wiring position 820 is smaller than the conductivity coefficient of the conductive material of the second conductive member 810 in the area away from the wiring position 820.

[0144] As described above, with respect to the division of the first region R1, the second region R2, and the third region R3, the conductivity coefficient of the conductive material of the second conductive member 810 in the first region R1 is smaller than the conductivity coefficient of the conductive material of the second conductive member 810 in the second region R2, and the conductivity coefficient of the conductive material of the second conductive member 810 in the second region R2 is smaller than the conductivity coefficient of the conductive material of the second conductive member 810 in the third region R3; that is, by setting the conductivity coefficient of the conductive material of the second conductive member 810, the total current difference between the second conductive members 810 in any two adjacent regions is smaller than the current difference threshold, thereby enabling the device to achieve a current sharing effect and improve the stability of the device.

[0145] In some embodiments, the resistance of the second conductive member is configured to gradually decrease in a direction away from the connection position 820. This can be achieved by configuring the cross-sectional area of ​​the second conductive member 810 to gradually increase.

[0146] In other embodiments, the conductivity coefficient of the conductive material of the second conductive member 810 can also be configured to gradually increase, so that the total current difference between the second conductive members 810 in any two adjacent areas is less than the current difference threshold, thereby achieving a current equalization effect in the device and improving the stability of the device.

[0147] Please refer to FIG10 , which is a schematic structural diagram of a fourth embodiment of a power semiconductor device of the present application.

[0148] As shown in Figure 10, the same parts as the third embodiment are not repeated here. The power semiconductor device includes: a drift layer 10, a first dielectric layer 500, a first metal layer 600, a second dielectric layer 700, a second metal layer 800, a plurality of first conductive members 610, and a plurality of second conductive members 810; the first dielectric layer 500 is arranged on the drift layer 10; the first metal layer 600 is arranged on the first dielectric layer 500; the second dielectric layer 700 is arranged on the first metal layer 600; the second metal layer 800 is arranged on the second dielectric layer 700, the plurality of first conductive members 610 are respectively electrically coupled to the first metal layer 600, and are isolated from each other by the first dielectric layer 500; the plurality of second conductive members 810 are respectively electrically coupled to the second metal layer 800, and are isolated from each other by the second dielectric layer 700.

[0149] In which, the second metal layer 800 includes a wiring position 820 for wiring, and the second conductive member 810 is arranged in several areas of equal width along the direction away from the wiring position 820; in adjacent areas, the total resistance value of the second conductive member 810 in the area relatively close to the wiring position 820 is configured to be smaller than the total resistance value of the second conductive member 810 in the area relatively away from the wiring position 820.

[0150] The drift layer 10 may include a substrate 100 and a semiconductor layer 200. In some embodiments, a doped region 210 is provided on a surface of the semiconductor layer 200 away from the substrate 100. That is, the semiconductor layer 200 includes a semiconductor material layer 220 and a doped region 210. The specific structure can be found in the description of the first embodiment and will not be repeated here.

[0151] The material of the first conductive member 610 and / or the second conductive member 810 may be a conductive-type doped semiconductor material, or the material of the first conductive member 610 and / or the second conductive member 810 may be a metal material.

[0152] It should be noted that there may be one wiring position 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the region where the wiring position 820 is located. In other embodiments, there may be two or more wiring positions 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the region surrounded by the plurality of wiring positions 820. For example, as shown in FIG9 , there are two wiring positions 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the line connecting the two wiring positions 820.

[0153] That is, the second conductive member is divided into areas of equal width, and the total resistance value of the second conductive member 810 in the area relatively close to the wiring position 820 is configured to be smaller than the total resistance value of the second conductive member 810 in the area relatively far from the wiring position 820, so that the entire device achieves a current equalization effect, that is, the current flowing from the drift layer to the wiring position 820 is uniform, improving the phenomenon of damage caused by overheating of local areas of the device due to current concentration, and improving the stability of the device.

[0154] Please refer to FIG11 , which is a schematic diagram of the specific structure of the fourth embodiment of the present application.

[0155] As shown in FIG11 , parts identical to those in the third embodiment are not further described. In some embodiments, taking the metal material of the first conductive member 610 and the second conductive member 810 as an example, the first dielectric layer 500 is provided with a plurality of first vias penetrating the first dielectric layer 500 , and the plurality of first vias are isolated by the first dielectric layer 500 . The first conductive members 610 are disposed in the first vias, so that the drift layer 10 can be coupled to the first metal layer 600 through the first conductive members 610 in the first vias, forming a pathway.

[0156] A plurality of second through holes penetrating the second dielectric layer 700 are provided in the second dielectric layer 700, and the plurality of second through holes are isolated by the second dielectric layer, wherein a second conductive member 810 is provided in the second through hole; so that the first metal layer 600 can be coupled with the second metal layer through the second conductive member 810 in the second through hole, forming a path from the drift layer 10 and the first metal layer 600 to the second metal layer 800.

[0157] Taking three areas as an example, the area within the first distance range from the wiring position 820 is the first area R1, the range greater than the first distance and less than the second distance is the second area R2, and the range greater than the second distance and less than the third distance is the third area R3, and the third distance is greater than the second distance and greater than the first distance; the area widths of the first area R1, the second area R2 and the third area R3 are the same.

[0158] In some embodiments, when the widths of the regions are equal, between two adjacent regions, the total cross-sectional area of ​​the second conductive member 810 in the region close to the wiring position 820 is smaller than the total cross-sectional area of ​​the second conductive member in the region away from the wiring position 820; this ensures that the current flowing from the drift layer 10 to the wiring position 820 in each region is uniform, and the device achieves a current equalization effect.

[0159] Among them, the cross-sectional areas of the second conductive members in the same area can be the same or different, as long as the total cross-sectional area of ​​the second conductive members 810 in the area close to the wiring position 820 is smaller than the total cross-sectional area of ​​the second conductive members in the area far from the wiring position 820.

[0160] That is, when the region widths are equal, the total cross-sectional area of ​​the second conductive member 810 in the first region R1 is smaller than the total cross-sectional area of ​​the second conductive member 810 in the second region R2; the total cross-sectional area of ​​the second conductive member 810 in the second region R2 is smaller than the total cross-sectional area of ​​the second conductive member 810 in the third region R3.

[0161] Furthermore, when the widths of the regions are equal and the cross-sectional areas of the second conductive elements 810 within the same region are the same, the above-mentioned effect can also be achieved by setting the spacing between two adjacent second conductive elements 810 within the region. For example, between two adjacent regions, the spacing between two adjacent second conductive elements 810 in the region near the connection point 820 is greater than the spacing between the second conductive elements 810 in the region far from the connection point 820. Specifically, the spacing between two adjacent second conductive elements 810 in the first region R1 is greater than the spacing between two adjacent second conductive elements 810 in the second region R2; and the spacing between two adjacent second conductive elements 810 in the second region R2 is greater than the spacing between two adjacent second conductive elements 810 in the third region R3. This configuration allows the total resistance of the second conductive elements 810 in the region near the connection point 820 within the adjacent regions to be smaller than the total resistance of the second conductive elements 810 in the region far from the connection point 820. This ensures that the current flowing from the drift layer 10 to the connection point 820 in each region is uniform, achieving a current-sharing effect for the device.

[0162] In other embodiments, when the widths of the regions are equal and the cross-sectional areas of the second conductive elements 810 in the same region are the same, the above-mentioned effect can also be achieved by setting the number of second conductive elements 810 in each region to be the same, while the conductivity coefficients of the conductive materials of the second conductive elements 810 are different. For example, between two adjacent regions, the conductivity coefficient of the conductive material of the second conductive element 810 in the region close to the wiring position 820 is smaller than the conductivity coefficient of the conductive material of the second conductive element 810 in the region away from the wiring position 820.

[0163] Taking three regions as an example, the region within a first distance range from the wiring point 820 is the first region R1, the range greater than the first distance and less than the second distance is the second region R2, and the range greater than the second distance and less than the third distance is the third region R3, where the third distance is greater than the second distance and greater than the first distance; the conductivity coefficient of the conductive material of the second conductive element 810 in the first region R1 is smaller than the conductivity coefficient of the conductive material of the second conductive element 810 in the second region R2, and the conductivity coefficient of the conductive material of the second conductive element 810 in the second region R2 is smaller than the conductivity coefficient of the conductive material of the second conductive element 810 in the third region R3; for the same reason, in adjacent regions, the total resistance value of the second conductive element 810 in the region relatively close to the wiring point 820 is configured to be smaller than the total resistance value of the second conductive element 810 in the region relatively far from the wiring point 820, so that the current flowing from the drift layer 10 to the wiring point 820 in each region is uniform, and the device achieves a current sharing effect.

[0164] In this embodiment, the second dielectric layer 700 is divided into equal widths so that the second conductive member is located in regions with equal widths, and the cross-sectional area, spacing or conductivity coefficient of the second conductive member 810 in different regions are set based on the regional division, so that the total resistance value of the second conductive member 810 in the region relatively close to the wiring position 820 is configured to be smaller than the total resistance value of the second conductive member 810 in the region relatively far from the wiring position 820, thereby making the current flowing from the drift layer 10 to the wiring position 820 in each region uniform, and the device achieves a current equalization effect.

[0165] Please refer to FIG12 , which is a schematic structural diagram of a fifth embodiment of a power semiconductor device in the present application.

[0166] As shown in Figure 12, the power semiconductor device includes a drift layer 10, a first dielectric layer 500, a first metal layer 600, a second dielectric layer 700, a second metal layer 800, a plurality of first conductive members 610, and a plurality of second conductive members 810; the first dielectric layer 500 is arranged on the drift layer 10; the first metal layer 600 is arranged on the first dielectric layer 500; the second dielectric layer 700 is arranged on the first metal layer 600; the second metal layer 800 is arranged on the second dielectric layer 700; the plurality of first conductive members 610 are respectively electrically coupled to the first metal layer 600 and isolated from each other by the first dielectric layer 500; the plurality of second conductive members 810 are respectively electrically coupled to the second metal layer 800 and isolated from each other by the second dielectric layer 700.

[0167] The drift layer 10 may include a substrate 100 and a semiconductor layer 200. In some embodiments, a doped region 210 is provided on a surface of the semiconductor layer 200 away from the substrate 100. That is, the semiconductor layer 200 includes a semiconductor material layer 220 and a doped region 210. The specific structure can be found in the description of the first embodiment and will not be repeated here.

[0168] The second metal layer 800 includes wiring locations 820 for wiring, and the spacing between the second conductive members 810 decreases in a direction away from the wiring locations 820 .

[0169] That is, by setting different intervals between the second conductive elements 810 , the current flowing from the drift layer 10 to the wiring position 820 in each region is made uniform, and the device achieves a current-sharing effect.

[0170] The material of the first conductive member 610 and / or the second conductive member 810 may be a conductive-type doped semiconductor material, or the material of the first conductive member 610 and / or the second conductive member 810 may be a metal material.

[0171] It should be noted that there may be one wiring position 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the region where the wiring position 820 is located. In other embodiments, there may be two or more wiring positions 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the region surrounded by the plurality of wiring positions 820. For example, as shown in FIG12 , there are two wiring positions 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the line connecting the two wiring positions 820.

[0172] Please refer to FIG13 , which is a schematic diagram of the specific structure of the fifth embodiment of the present application.

[0173] As shown in FIG13 , parts identical to those in the fourth embodiment are not further described. In some embodiments, taking the metal material as an example, the first conductive member 610 and the second conductive member 810 are provided in the first dielectric layer 500 . A plurality of first through-holes are provided through the first dielectric layer 500 , and the plurality of first through-holes are isolated by the first dielectric layer 500 . The first conductive members 610 are provided in the first through-holes, so that the drift layer 10 can be coupled to the first metal layer 600 through the first conductive members 610 in the first through-holes, forming a path.

[0174] A plurality of second through holes penetrating the second dielectric layer 700 are provided in the second dielectric layer 700, and the plurality of second through holes are isolated by the second dielectric layer 700, wherein a second conductive member 810 is provided in the second through hole; so that the second metal layer 800 can be coupled with the first metal layer through the second conductive member 810 in the second through hole, forming a path from the drift layer 10 and the first metal layer 600 to the second metal layer 800.

[0175] In some embodiments, the conductive materials of the second conductive members 810 have the same conductivity coefficient, and the cross-sectional areas of the second conductive members 810 are the same, wherein the cross-sectional area is parallel to the surface of the first metal layer 600 .

[0176] In the direction away from the wiring position 820 , the intervals between the second conductive elements 810 gradually decrease.

[0177] That is, when the conductivity coefficient and cross-sectional area of ​​the conductive material of the second conductive member 810 are the same, by setting the spacing between the second conductive members 810, the current flowing from the drift layer 10 to the wiring position 820 in each region is uniform, the device achieves a current equalization effect, and the stability of the device is ensured.

[0178] In some embodiments, when the conductivity coefficient of the conductive material of the second conductive members 810 is the same and the cross-sectional area of ​​the second conductive members 810 is the same, the second conductive members 810 are arranged in several areas, and the spacing between two adjacent second conductive members 810 in the same area is the same; and in adjacent areas, the spacing between adjacent second conductive members 810 in the area close to the wiring position 820 is smaller than the spacing between adjacent second conductive members 810 in the area away from the wiring position 820.

[0179] That is, when the conductivity coefficient and cross-sectional area of ​​the conductive material of the second conductive member 810 are the same, by setting the spacing between two adjacent second conductive members 810 in the same area to be the same, and the spacing between the second conductive members in different areas to be different, the current flowing from the drift layer 10 to the wiring position 820 in each area is made uniform, the device achieves a current equalization effect, and the stability of the device is guaranteed.

[0180] Taking three regions as an example, the region within a first distance range from the wiring position 820 is the first region R1, the range greater than the first distance and less than the second distance is the second region R2, and the range greater than the second distance and less than the third distance is the third region R3, where the third distance is greater than the second distance and greater than the first distance; the spacing between adjacent second conductive elements 810 in the first region R1 is the same, and similarly, the spacing between adjacent second conductive elements 810 in the second region R2 and the third region R3 are also the same; the spacing between adjacent second conductive elements 810 in the first region R1 is smaller than the spacing between adjacent second conductive elements 810 in the second region R2; the spacing between adjacent second conductive elements 810 in the second region R2 is smaller than the spacing between adjacent second conductive elements 810 in the third region R3; thereby, in the adjacent regions, the total resistance value of the second conductive elements 810 in the region relatively close to the wiring position 820 is configured to be smaller than the total resistance value of the second conductive elements 810 in the region relatively far from the wiring position 820, forming a current sharing structure.

[0181] In this embodiment, by setting different spacings between the second conductive members 810, the total resistance value of the second conductive members 810 in the area relatively close to the wiring position 820 is configured to be smaller than the total resistance value of the second conductive members 810 in the area relatively far from the wiring position 820, thereby making the current flowing from the drift layer 10 to the wiring position 820 in each area uniform, and the device achieves a current equalization effect.

[0182] Please refer to FIG. 14 , which is a schematic structural diagram of a sixth embodiment of a power semiconductor device in the present application.

[0183] As shown in Figure 14, the parts that are the same as the fifth embodiment are not repeated here. The power semiconductor device includes a drift layer 10, a first dielectric layer 500, a first metal layer 600, a second dielectric layer 700, a second metal layer 800, a plurality of first conductive members 610, and a plurality of second conductive members 810; the first dielectric layer 500 is arranged on the drift layer 10; the first metal layer 600 is arranged on the first dielectric layer 500; the second dielectric layer 700 is arranged on the first metal layer 600; the second metal layer 800 is arranged on the second dielectric layer 700; the plurality of first conductive members 610 are respectively electrically coupled to the first metal layer 600 and isolated from each other by the first dielectric layer 500, and the plurality of second conductive members 810 are respectively electrically coupled to the second metal layer 800 and isolated from each other by the second dielectric layer 700.

[0184] The drift layer 10 may include a substrate 100 and a semiconductor layer 200. In some embodiments, a doped region 210 is provided on a surface of the semiconductor layer 200 away from the substrate 100. That is, the semiconductor layer 200 includes a semiconductor material layer 220 and a doped region 210. The specific structure can be found in the description of the first embodiment and will not be repeated here.

[0185] The second metal layer 800 includes a wiring position 820 for wiring. The conductivity of the conductive material of the second conductive member 810 increases in a direction away from the wiring position 820 .

[0186] That is, by setting the conductivity of the conductive material of the second conductive element 810 to be different, the current flowing from the drift layer 10 to the connection point 820 in each region is made uniform, and the device achieves a current-sharing effect.

[0187] The material of the first conductive member 610 and / or the second conductive member 810 may be a conductive-type doped semiconductor material, or the material of the first conductive member 610 and / or the second conductive member 810 may be a metal material.

[0188] It should be noted that there may be one wiring position 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the region where the wiring position 820 is located. In other embodiments, there may be two or more wiring positions 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the region surrounded by the plurality of wiring positions 820. For example, as shown in FIG14 , there are two wiring positions 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the line connecting the two wiring positions 820.

[0189] Please refer to FIG15 , which is a schematic diagram of the specific structure of the sixth embodiment of the present application.

[0190] As shown in FIG15 , based on FIG14 , parts identical to those of the fifth embodiment are not further described. In some embodiments, a first dielectric layer 500 is provided with a plurality of first vias extending through the first dielectric layer 500 , and the plurality of first vias are isolated by the first dielectric layer 500 . First conductive members 610 are disposed in the first vias, allowing the drift layer 10 to be coupled to the first metal layer 600 via the first conductive members 610 in the first vias, thereby forming a pathway.

[0191] A second through hole penetrating the second dielectric layer 700 is provided in the second dielectric layer 700, and a plurality of second through holes are isolated by the second dielectric layer 700, wherein a second conductive member 810 is provided in the second through hole; so that the second metal layer 800 can be coupled with the first metal layer through the second conductive member 810 in the second through hole, forming a path from the drift layer 10 and the first metal layer 600 to the second metal layer 800.

[0192] In some embodiments, the spacing between adjacent second conductive elements 810 in a direction away from the wiring position 820 is the same; and the cross-sectional areas of the second conductive elements 810 are the same, wherein the cross-sectional areas are parallel to the surface of the first metal layer 600 .

[0193] Furthermore, the conductivity of the conductive material of the second conductive member 810 gradually increases in a direction away from the wiring position 820 .

[0194] That is, in the direction away from the wiring position 820, when the spacing between adjacent second conductive members 810 is the same and the cross-sectional area of ​​the second conductive members 810 is the same, by setting the conductivity coefficient of the conductive material of the second conductive member 810 to gradually increase, the current flowing from the drift layer 10 to the wiring position 820 in each region is uniform, the device achieves a current equalization effect, and the stability of the device is ensured.

[0195] In some embodiments, the spacing between adjacent second conductive elements 810 in a direction away from the connection point 820 is the same, and the cross-sectional areas of the second conductive elements 810 are the same. The second conductive elements 810 are arranged in several regions, and the conductivity of the conductive material of the second conductive elements in the same region is the same. However, in adjacent regions, the conductivity of the conductive material of the second conductive elements 810 in regions close to the connection point 820 is lower than the conductivity of the conductive material of the second conductive elements 810 in regions away from the connection point 820.

[0196] Taking three regions as an example, the region within a first distance from the wiring position 820 is the first region R1, the region greater than the first distance and less than the second distance is the second region R2, and the region greater than the second distance and less than the third distance is the third region R3, where the third distance is greater than the second distance and greater than the first distance; the conductivity coefficient of the conductive material of the second conductive member 810 in the first region R1 is the same, and similarly, the conductivity coefficient of the conductive material of the second conductive member 810 in the second region R2 and the third region R3 is also the same; and the conductivity coefficient of the conductive material of the second conductive member 810 in the first region R1 is less than that of the conductive material of the second conductive member 810 in the second region R2. The conductivity coefficient of the conductive material of the second conductive member 810 in the second region R2 is smaller than the conductivity coefficient of the conductive material of the second conductive member 810 in the third region R3; thereby, in adjacent regions, the total resistance value of the second conductive member 810 in the region relatively close to the wiring position 820 is configured to be smaller than the total resistance value of the second conductive member 810 in the region relatively far away from the wiring position 820, that is, by dividing the regions into different areas, the conductivity coefficient of the conductive material of the second conductive member 810 in different regions tends to increase in the direction away from the wiring position 820, so that the device achieves a current sharing effect, forms a current sharing structure, and ensures the stability of the device.

[0197] In this embodiment, the conductivity coefficient of the second conductive member 810 is set according to its change rule, and the current flowing from the drift layer 10 to the wiring position 820 is uniform from the gradual change without regional division and the gradient change in regional division, so that the device achieves the current equalization effect and ensures the stability of the device.

[0198] Please refer to FIG. 16 , which is a schematic structural diagram of a seventh embodiment of a power semiconductor device in the present application.

[0199] As shown in Figure 16, the power semiconductor device includes a drift layer 10, a first dielectric layer 500, a first metal layer 600, a second dielectric layer 700, a second metal layer 800, a plurality of first conductive members 610, and a plurality of second conductive members 810; the first dielectric layer 500 is arranged on the drift layer 10; the first metal layer 600 is arranged on the first dielectric layer 500; the second dielectric layer 700 is arranged on the first metal layer 600; the second metal layer 800 is arranged on the second dielectric layer 700; the plurality of first conductive members 610 are respectively electrically coupled to the first metal layer 600, and the first conductive members 610 are isolated from each other by the first dielectric layer 500; the plurality of second conductive members 810 are respectively electrically coupled to the second metal layer 800, and the second conductive members 810 are isolated from each other by the second dielectric layer 700.

[0200] The drift layer 10 may include a substrate 100 and a semiconductor layer 200. In some embodiments, a doped region 210 is provided on a surface of the semiconductor layer 200 away from the substrate 100. That is, the semiconductor layer 200 includes a semiconductor material layer 220 and a doped region 210. The specific structure can be found in the description of the first embodiment and will not be repeated here.

[0201] The second metal layer 800 includes a wiring position 820 for wiring, and the cross-sectional area of ​​the second conductive member 810 increases in a direction away from the wiring position 820 .

[0202] That is, by setting the cross-sectional areas of the second conductive member 810 to be different, the current flowing from the drift layer 10 to the connection point 820 in each region is made uniform, and the device achieves a current-sharing effect.

[0203] The material of the first conductive member 610 and / or the second conductive member 810 may be a conductive-type doped semiconductor material, or the material of the first conductive member 610 and / or the second conductive member 810 may be a metal material.

[0204] It should be noted that there may be one wiring position 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the region where the wiring position 820 is located. In other embodiments, there may be two or more wiring positions 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the region surrounded by the plurality of wiring positions 820. For example, as shown in FIG16 , there are two wiring positions 820, and the direction away from the wiring position 820 can be understood as the direction away from the midpoint of the line connecting the two wiring positions 820.

[0205] Please refer to FIG17 , which is a schematic diagram of the specific structure of the seventh embodiment of the present application.

[0206] As shown in FIG17 , parts identical to those in the sixth embodiment are not further described. In some embodiments, taking the first conductive member 610 and the second conductive member 810 as metal materials, a plurality of first through-holes penetrating the first dielectric layer 500 are provided in the first dielectric layer 500 , and the plurality of first through-holes are isolated by the first dielectric layer 500 . The first conductive members 610 are provided in the first through-holes, so that the drift layer 10 can be coupled to the first metal layer 600 through the first conductive members 610 in the first through-holes, forming a path.

[0207] A plurality of second through holes penetrating the second dielectric layer 700 are provided in the second dielectric layer 700, and the plurality of second through holes are isolated by the second dielectric layer 700, wherein a second conductive member 810 is provided in the second through hole; so that the second metal layer 800 can be coupled with the first metal layer 600 through the second conductive member 810 in the second through hole, forming a path from the drift layer 10 and the first metal layer 600 to the second metal layer 800.

[0208] In some embodiments, along a direction away from the wiring position 820 , the spacing between adjacent second conductive elements is the same, and the conductivity coefficients of the conductive materials of the second conductive elements 810 are the same.

[0209] Furthermore, the cross-sectional area of ​​the second conductive member gradually increases in a direction away from the wiring position.

[0210] That is, in the direction away from the wiring position 820, the spacing between adjacent second conductive members 810 is the same, and the conductivity coefficient of the conductive material of the second conductive members 810 is the same. By setting the cross-sectional area of ​​the second conductive member 810 to gradually increase, the current flowing from the drift layer 10 to the wiring position 820 in each region is uniform, the device achieves a current equalization effect, and the stability of the device is guaranteed.

[0211] In some embodiments, the spacing between adjacent second conductive members is the same along the direction away from the wiring position; and when the conductivity coefficient of the conductive material of the second conductive members is the same, the second conductive members 810 are arranged in several areas, and the cross-sectional area of ​​the second conductive members 810 in the same area is the same; and in adjacent areas, the cross-sectional area of ​​the second conductive member 810 in the area close to the wiring position 820 is smaller than the cross-sectional area of ​​the second conductive member 810 in the area away from the wiring position 820.

[0212] Taking three regions as an example, the region within a first distance range from the wiring position 820 is the first region R1, the region greater than the first distance and less than the second distance is the second region R2, and the region greater than the second distance and less than the third distance is the third region R3, where the third distance is greater than the second distance and greater than the first distance; the cross-sectional area of ​​the second conductive member 810 in the first region R1 is the same, and similarly, the cross-sectional area of ​​the second conductive member 810 in the second region R2 and the third region R3 is also the same; and the cross-sectional area of ​​the second conductive member 810 in the first region R1 is smaller than that in the second region R2. Cross-sectional area; the cross-sectional area of ​​the second conductive member 810 in the second region R2 is smaller than the cross-sectional area of ​​the second conductive member 810 in the third region R3; thereby, in adjacent regions, the total resistance value of the second conductive member 810 in the region relatively close to the wiring position 820 is configured to be smaller than the total resistance value of the second conductive member 810 in the region relatively far away from the wiring position 820, that is, by dividing the regions into different areas, the cross-sectional areas of the second conductive members 810 in different regions tend to increase in the direction away from the wiring position 820, so that the device achieves a current sharing effect, forms a current sharing structure, and ensures the stability of the device.

[0213] In this embodiment, the second conductive member 810 is set according to the cross-sectional area or size change rule, and the gradual change without regional division and the gradient change in regional division are adopted, so that the current flowing from the drift layer 10 to the wiring position 820 is uniform, and the device achieves a current balancing effect, thereby making the temperature of each region of the semiconductor device tend to be consistent, improving the reliability problem of the semiconductor device caused by uneven temperature when it is turned on, improving the performance of the semiconductor device, and ensuring the stability of the device.

[0214] The above description is only an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A power semiconductor device, wherein, Comprising: A substrate; A semiconductor layer disposed on the substrate; A plurality of source contact regions disposed on the semiconductor layer; A plurality of gate electrodes disposed on the semiconductor layer; A first dielectric layer disposed on the semiconductor layer; A first conductive structure disposed at least partially on the first dielectric layer; A second dielectric layer disposed on the first conductive structure; A second conductive structure disposed at least partially on the second dielectric layer; Wherein, the source contact regions are respectively configured to connect to the first conductive structure and connect to the second conductive structure through the first conductive structure, and there is a wiring position for wiring on the surface of the second conductive structure away from the semiconductor layer; the total resistance value between any one of the source contact regions and the wiring position is configured to have a difference less than a resistance difference threshold from the total resistance value between any other one of the source contact regions and the wiring position.

2. The power semiconductor device according to claim 1, wherein, The second conductive structure includes: a second metal layer disposed on the second dielectric layer and a second conductive member connected to the second metal layer; A plurality of second through holes penetrating the second dielectric layer are provided in the second dielectric layer, and the second conductive member is a second metal conductor filling the plurality of second through holes, and the second metal conductor couples the second metal layer to the first conductive structure.

3. The power semiconductor device according to claim 2, wherein, In the direction away from the wiring position, the second conductive members are configured in a plurality of regions with equal widths; In adjacent regions, the total resistance value of the second conductive members in the region relatively closer to the wiring position is configured to be less than the total resistance value of the second conductive members in the region relatively farther away from the wiring position.

4. The power semiconductor device according to claim 3, wherein, Between two adjacent regions, the total cross-sectional area of the second conductive members in the region closer to the wiring position is smaller than the total cross-sectional area of the second conductive members in the region farther away from the wiring position.

5. The power semiconductor device according to claim 4, wherein, The cross-sectional areas of the second conductive members in the same region are the same.

6. The power semiconductor device according to claim 5, wherein, Between two adjacent regions, the distance between two adjacent second conductive members in the region closer to the wiring position is greater than the distance between two adjacent second conductive members in the region farther away from the wiring position.

7. The power semiconductor device according to claim 5, wherein, The number of the second conductive members in each region is the same, and between two adjacent regions, the conductivity coefficient of the conductive material of the second conductive members in the region closer to the wiring position is less than the conductivity coefficient of the conductive material of the second conductive members in the region farther away from the wiring position.

8. The power semiconductor device according to claim 2, wherein, In the direction away from the wiring position, the distance between the second conductive members shows a decreasing trend.

9. The power semiconductor device according to claim 8, wherein, the conductivity coefficients of the conductive materials of the second conductive members are the same, and the cross-sectional areas of the second conductive members are the same, wherein the cross-section is parallel to the surface of the first metal layer.

10. The power semiconductor device according to claim 9, wherein, in the direction away from the connection position, the distance between the second conductive members gradually decreases.

11. The power semiconductor device according to claim 9, wherein, the second conductive members are arranged in several regions, and the distance between two adjacent second conductive members in the same region is the same; in adjacent regions, the distance between adjacent second conductive members in the region close to the connection position is smaller than the distance between adjacent second conductive members in the region away from the connection position.

12. The power semiconductor device according to claim 2, wherein, in the direction away from the connection position, the conductivity coefficient of the conductive material of the second conductive member shows an increasing trend.

13. The power semiconductor device according to claim 12, wherein, in the direction away from the connection position, the distance between adjacent second conductive members is the same; and the cross-sectional areas of the second conductive members are the same, wherein the cross-section is parallel to the surface of the first metal layer.

14. The power semiconductor device according to claim 13, wherein, in the direction away from the connection position, the conductivity coefficient of the conductive material of the second conductive member gradually increases.

15. The power semiconductor device according to claim 13, wherein, the second conductive members are arranged in several regions, and the conductivity coefficients of the conductive materials of the second conductive members in the same region are the same; in adjacent regions, the conductivity coefficient of the conductive material of the second conductive member in the region close to the connection position is smaller than the conductivity coefficient of the conductive material of the second conductive member in the region away from the connection position.

16. The power semiconductor device according to claim 2, wherein, in the direction away from the connection position, the cross-sectional area of the second conductive member shows an increasing trend.

17. The power semiconductor device according to claim 16, wherein, in the direction away from the connection position, the distance between adjacent second conductive members is the same; and the conductivity coefficients of the conductive materials of the second conductive members are the same.

18. The power semiconductor device according to claim 17, wherein, in the direction away from the connection position, the cross-sectional area of the second conductive member gradually increases.

19. The power semiconductor device according to claim 17, wherein, the second conductive members are arranged in several regions, and the cross-sectional areas of the second conductive members in the same region are the same; in adjacent regions, the cross-sectional area of the second conductive member in the region close to the connection position is smaller than the cross-sectional area of the second conductive member in the region away from the connection position.

20. The power semiconductor device according to claim 1, wherein, the gate electrode is isolated from the source contact region and the first conductive structure by the first dielectric layer.

21. The power semiconductor device according to claim 1, wherein the resistance value between any one of the source contact regions and the connection terminal is configured to have a difference of zero from the resistance values between the other source contact regions and the connection terminal.

22. A power semiconductor device, wherein, Comprising: a drift layer; a first dielectric layer disposed on the drift layer; a first metal layer disposed on the first dielectric layer; a second dielectric layer disposed on the first metal layer; a second metal layer disposed on the second dielectric layer such that at least a part of the second metal layer provides a connection terminal; a plurality of first conductive members electrically coupled to the first metal layer and isolated by the first dielectric layer; a plurality of second conductive members electrically coupling the first metal layer and the second metal layer and isolated by the second dielectric layer; wherein, in an operating state, the power semiconductor device is configured to conduct in each of the second conductive members and each of the first conductive members based on the current signal provided by the connection terminal, and wherein the current difference between any two of the second conductive members is less than a current difference threshold.

23. A power semiconductor device, wherein, Comprising: a drift layer; a first dielectric layer disposed on the drift layer; a first metal layer disposed on the first dielectric layer; a second dielectric layer disposed on the first metal layer; a second metal layer disposed on the second dielectric layer; a plurality of first conductive members respectively electrically coupled to the first metal layer and isolated from each other by the first dielectric layer; a plurality of second conductive members respectively electrically coupled to the second metal layer and isolated from each other by the second dielectric layer; wherein the second metal layer includes a connection terminal for connection, and in a direction away from the connection terminal, the second conductive members are configured in a plurality of regions with equal widths; in adjacent regions, the total resistance value of the second conductive members in the region relatively closer to the connection terminal is configured to be less than the total resistance value of the second conductive members in the region relatively farther from the connection terminal.

24. A power semiconductor device, wherein, Comprising: a drift layer; a first dielectric layer disposed on the drift layer; a first metal layer disposed on the first dielectric layer; a second dielectric layer disposed on the first metal layer; a second metal layer disposed on the second dielectric layer; a plurality of first conductive members respectively electrically coupled to the first metal layer and isolated from each other by the first dielectric layer; a plurality of second conductive members respectively electrically coupled to the second metal layer and isolated from each other by the second dielectric layer; wherein the second metal layer includes a connection terminal for connection, and in a direction away from the connection terminal, the spacing between the second conductive members shows a decreasing trend.

25. A power semiconductor device, wherein, Comprising: a drift layer; a first dielectric layer disposed on the drift layer; a first metal layer disposed on the first dielectric layer; a second dielectric layer disposed on the first metal layer; a second metal layer disposed on the second dielectric layer; a plurality of first conductive members respectively electrically coupled to the first metal layer and isolated from each other by the first dielectric layer; a plurality of second conductive members respectively electrically coupled to the second metal layer and isolated from each other by the second dielectric layer; Wherein, the second metal layer includes a wiring position for wiring, and in a direction away from the wiring position, the conductivity coefficient of the conductive material of the second conductive member shows an increasing trend.

26. A power semiconductor device, wherein, Comprising: Drift layer; A first dielectric layer disposed on the drift layer; A first metal layer disposed on the first dielectric layer; A second dielectric layer disposed on the first metal layer; A second metal layer disposed on the second dielectric layer; A plurality of first conductive members respectively electrically coupled to the first metal layer and isolated from each other by the first dielectric layer; A plurality of second conductive members respectively electrically coupled to the second metal layer and isolated from each other by the second dielectric layer; Wherein, the second metal layer includes a wiring position for wiring, and in a direction away from the wiring position, the cross-sectional area of the second conductive member shows an increasing trend.

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