Power semiconductor board-level test system and method

Abstract

The invention discloses a power semiconductor board-level test system and method, and belongs to the technical field of power semiconductor device test. According to the system, a reactive aging test and a dynamic characteristic test are creatively integrated on a single test platform, and the problems of low efficiency and high cost of a traditional substation test are solved through modular design. The system comprises a multifunctional test head arranged at a test station and capable of being connected with a power terminal and a signal terminal of a power module at the same time; the reactive load loop is formed by a three-phase adjustable reactor; the high-precision signal acquisition module comprises a flexible current probe and a differential voltage probe; the oscilloscope realizes multi-channel synchronous acquisition; and accurate control is realized based on the main control board card of the FPGA. According to the testing method, Vge, Vce, Ic and other parameters are collected in real time in the reactive aging process, online monitoring of dynamic characteristics is achieved through a current triggering mechanism, and a fault recording function is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor device testing, in particular to a power semiconductor board-level testing system and method, which is especially suitable for the integrated testing scheme of reactive aging test and dynamic characteristic test of power modules. BACKGROUND

[0002] Power semiconductor modules need to be tested for reactive aging and dynamic characteristics before being shipped, to ensure their reliability and yield. Existing tests often use a three-step or two-step testing method, i.e., dynamic test-reactive aging-dynamic test, or reactive aging-dynamic test, which is a multi-station step-by-step test. This process not only increases the testing time, but also leads to low testing efficiency, affecting the production capacity of large-scale production. Existing testing devices often focus on a single testing function (such as only reactive aging test or dynamic test), lack of integrated design, leading to complex testing process and doubled equipment cost. Currently, there is no testing device that can integrate reactive aging and dynamic test.

[0003] Due to the differences in measurement principles and circuit topologies between reactive aging and dynamic test, existing testing devices can only achieve single testing function (such as only reactive aging test or dynamic test), lack of integrated design, leading to the need for separate station design of testing process, high equipment cost, and low testing efficiency.

[0004] Currently, there is no power semiconductor testing system that can simultaneously integrate reactive aging and dynamic test. Therefore, there is an urgent need for an efficient and low-cost integrated testing scheme to solve the above problems. SUMMARY

[0005] The present application provides a power semiconductor board-level testing system, which aims to solve the problem of low efficiency and high cost caused by separate station testing of reactive aging and dynamic test in the prior art. Through integrated design, the present application simultaneously completes reactive aging test and dynamic parameter monitoring on a single machine, significantly improving testing efficiency and reducing equipment cost.

[0006] The technical solution of the present application is as follows:

[0007] A power semiconductor board-level testing system, characterized in that it comprises:

[0008] a testing station for placing a power module to be tested;

[0009] a testing station configured with a testing head and a three-phase reactor for testing the power module to be tested for reactive aging and dynamic test;

[0010] a handling gripper for transporting the power module to be tested from the testing station to the testing station;

[0011] A three-phase reactor is connected with AC terminals of the power module to be tested to form a reactive power aging test loop.

[0012] A DC power supply provides adjustable DC voltage for the reactive power aging test loop.

[0013] A signal acquisition module comprises at least two flexible current probes and four high-voltage differential probes, and is used to acquire collector current (Ic), gate-emitter voltage (Vge) and collector-emitter voltage (Vce) of the power module to be tested in real time.

[0014] An oscilloscope is connected with a signal output end of the signal acquisition module, has at least six acquisition channels, and is used to record signals acquired by the signal acquisition module.

[0015] A servo positioning system is used to control lifting movement of the test head to ensure reliable contact with the power module to be tested.

[0016] The test head comprises power connection terminals and signal connection terminals, forms electrical connection with probes of the signal acquisition module, and is used to connect signal terminals of the power module to be tested.

[0017] Further, the application further comprises:

[0018] An industrial computer runs special test software, sets amplitude and frequency of reactive power aging current through the host computer software, and controls the main control board to execute the reactive power aging test process.

[0019] The main control board is in communication connection with the industrial computer, is used to execute test instructions issued by the industrial computer and monitor test states.

[0020] A water removal station is configured with an air gun and a waste liquid recovery device, and is used to remove water from the power module after test completion.

[0021] Preferably, the oscilloscope takes the collector current (Ic) as a trigger signal, and records dynamic waveforms of the gate-emitter voltage (Vge) and the collector-emitter voltage (Vce) when the collector current (Ic) exceeds a preset threshold.

[0022] Preferably, the preset threshold is short-circuit current of the power module to be tested, and is used to realize a fault recording function.

[0023] Preferably, the three-phase reactor can be replaced with a three-phase motor load to realize dynamic parameter monitoring in an active power aging test process.

[0024] The application further provides a power semiconductor board-level test method, and the test method is applied to the test system.

[0025] S1: system initialization, including parameter setting, device self-checking and safety confirmation;

[0026] S2: placing the power module to be tested in a testing station, and moving the power module to be tested to a testing station through a moving clamp;

[0027] S3: driving a testing head to tightly contact power terminals and signal terminals of the power module to be tested, so as to form a testing loop, including power connection and signal connection;

[0028] S4: performing reactive aging test, and collecting collector current (Ic), gate-emitter voltage (Vge) and collector-emitter voltage (Vce) signals of the power module to be tested through a signal acquisition module;

[0029] S5: recording the signals by using an oscilloscope, and taking the collector current (Ic) as a trigger signal, and saving dynamic waveforms when the current exceeds a preset threshold;

[0030] S6: extracting dynamic parameters through a special testing software of an industrial computer, completing synchronous monitoring of reactive aging and dynamic test, generating a testing report and storing testing data;

[0031] S7: after the test is completed, moving the power module to be tested to a water removing station for water removing treatment.

[0032] Compared with the prior art, the present application has the following beneficial effects:

[0033] The existing testing device can only realize single test function (such as only performing reactive aging test or dynamic test), lacks integrated design, and thus requires separate design of testing procedures, resulting in high equipment cost and low testing efficiency. The present application realizes integration of reactive aging and dynamic test functions on a single machine by monitoring switch dynamic parameters of the power module during reactive aging test of the power module, which can avoid separate setting of testing procedures, reduce equipment cost of the power semiconductor testing line, and improve testing efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 Main circuit diagram of the power semiconductor board-level testing system

[0035] Figure 2 Schematic diagram of the power semiconductor board-level testing system.

[0036] In the figure: 1-testing station, 2-moving clamp, 3-testing station, 4-industrial computer, 5-direct current power supply, 6-servo system, 7-oscilloscope, 8-signal acquisition module, 9-main control board, 10-testing head, 11-water removing station, 12-three-phase reactor. DETAILED DESCRIPTION

[0037] The power semiconductor board-level test system and method of the present application will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can clearly understand the technical solutions and implementation process of the present application.

[0038] An integrated test method combines the reactive aging test of a power module with the dynamic parameter test. Without interrupting the reactive aging process, the dynamic parameters of the power module are monitored in real time by setting the oscilloscope trigger mode, thereby avoiding the low efficiency problem of traditional step-by-step test. Figure 1 As shown in FIG. 1, the U-phase bridge arm is taken as an example. The power module with a three-phase power bridge arm design (U / V / W) is adopted, each phase of which is composed of two power switches IGBT or SiC MOSFET (including anti-parallel continuous current diode) in series, and the midpoint is connected to a connection point (for connecting to a motor or an electric reactor). The three-phase electric reactors 12 are respectively connected to the midpoints of the power module, simulating inductive load, and forming a reactive circulating loop by the DC power supply to generate a continuous aging current stress. That is, the three-phase electric reactors in the reactive aging test are respectively connected to the three-phase bridge arms of the power module one by one.

[0039] The test method is as follows:

[0040] (1) Parameter setting stage: under the connection state of the reactive aging test circuit, the specific DC voltage is output by the DC power supply 5 controlled by the upper computer to perform the reactive aging test.

[0041] (2) Signal acquisition stage:

[0042] 2.1 Current measurement: two current flexible probes are used to measure the collector currents Ic1 and Ic2 of the upper and lower power switches of the U-phase bridge arm.

[0043] 2.2 Voltage measurement: four voltage differential probes are used to measure the gate-emitter voltages Vge1 and Vge2 and the collector-emitter voltages Vce1 and Vce2 of the upper and lower power switches of the U-phase bridge arm.

[0044] (3) Data acquisition stage:

[0045] 3.1 The output signals of the flexible current probes and the differential voltage probes are connected to the 8-channel oscilloscope to realize synchronous acquisition.

[0046] 3.2 The Ic1 signal channel of the oscilloscope is taken as the trigger channel, and the Ic1 current over the threshold value is taken as the trigger condition. When the Ic1 current flowing through the power switch exceeds the trigger threshold value during the reactive aging process, the oscilloscope acquires and records Vge1, Vce1, Ic1, Vge2, Vce2, and Ic2.

[0047] (4) Data analysis stage:

[0048] The host computer extracts the power module opening and closing dynamic parameters according to the signals recorded by the oscilloscope, and realizes online extraction of the dynamic parameters of the power module under the no-load aging condition.

[0049] Please refer to Figure 2 The power semiconductor board-level test system comprises the following modules:

[0050] The test site 1 is used for placing the power module (such as an IGBT module, a SiC MOSFET module, etc.) to be tested.

[0051] The carrying clamp 2 is driven by a servo motor to realize automatic carrying of the module to be tested from the test site 1 to the test site 3.

[0052] The test site 3 is a core test area, comprising a test head 10 and a three-phase reactor 12.

[0053] The DC power supply 5 provides a DC bus voltage (such as 600V / 1200V) for the power module to be tested.

[0054] The servo system 6 controls the lifting of the test head 10 to ensure that the test head 10 is in close contact with the terminals of the power module.

[0055] The oscilloscope 7 is an 8-channel high-frequency oscilloscope, which is used to collect dynamic signals such as Vge, Vce and Ic.

[0056] The signal acquisition module 8 is internally provided with a flexible current probe (such as a Rogowski coil) and a high-voltage differential probe, and the signal output end is connected to the oscilloscope 7.

[0057] The main control board 9 is designed based on an FPGA, receives instructions from the industrial computer 4, and controls the no-load aging test process.

[0058] The test head 10 adopts a crimping structure to realize rapid connection of power terminals (DC+, DC-, U / V / W phase) and signal terminals (Vge, Vce).

[0059] The three-phase reactor 12 has an adjustable inductance value (such as 100μH-1mH) and is used to simulate a no-load.

[0060] The above embodiments show the specific operation process and technical details of the present application, and those skilled in the art can adjust the parameters or module configuration according to the actual needs, and these variants should be included in the protection scope of the present application.

Claims

1. A power semiconductor board-level test system, characterized in that: include: A test station (1) is used to place the power module to be tested; A test station (3) is provided with a test head (10) and a three-phase reactor (12), and is used to perform reactive aging testing and dynamic testing on the power module to be tested; A transporting clamp (2) for transporting the power module to be tested from the to-be-tested station (1) to the testing station (3); A three-phase reactor (12) is connected to the AC end of the power module to be tested to form a reactive aging test loop; A DC power supply (5) provides an adjustable DC voltage for the reactive aging test circuit; A signal acquisition module (8), comprising at least two flexible current probes and four high-voltage differential probes, for real-time acquisition of the collector current (Ic), gate-emitter voltage (Vge), and collector-emitter voltage (Vce) of the power module to be tested; an oscilloscope (7), connected to the signal output end of the signal acquisition module (8), having at least 6 acquisition channels, and used for recording the signal acquired by the signal acquisition module (8); A servo positioning system (6) for controlling the lifting and lowering movement of the test head (10) to ensure reliable contact with the power module to be tested; The test head (10) comprises a power connection terminal and a signal connection terminal, which are electrically connected to the probe of the signal acquisition module (8) and are used to connect to the signal terminal of the power module to be tested.

2. The power semiconductor board-level test system according to claim 1, characterized in that: Also includes: An industrial control computer (4) runs a dedicated test software, wherein the industrial control computer (4) sets the amplitude and frequency of the reactive aging current through the host computer software, and controls the main control board (9) to execute the reactive aging test process; A main control board (9) is connected to the industrial computer (4) for executing the test instructions issued by the industrial computer (4) and monitoring the test status; The dewatering station (11) is equipped with an air gun and a waste liquid recovery device, and is used to dewater the power module after the test is completed.

3. The power semiconductor board-level test system according to claim 1 or 2, characterized in that: The oscilloscope (7) uses the collector current (Ic) as a trigger signal, and records the dynamic waveforms of the gate-emitter voltage (Vge) and the collector-emitter voltage (Vce) when the collector current (Ic) exceeds a preset threshold.

4. The power semiconductor board-level test system according to claim 3, characterized in that: The preset threshold is the short-circuit current of the power module to be tested, which is used to realize the fault recording function.

5. The power semiconductor board-level test system according to claim 1, characterized in that: The three-phase reactor (12) can be replaced by a three-phase motor load to achieve dynamic parameter monitoring during active aging testing.

6. A power semiconductor board-level testing method, using the testing system according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1: System initialization, including parameter setting, equipment self-test and safety confirmation; S2: placing the power module to be tested on the testing station (1), and transporting the power module to be tested to the testing station (3) by means of a transporting clamp (2); S3: driving the test head (10) to closely contact the power terminals and signal terminals of the power module to be tested, thereby forming a test loop including power connection and signal connection; S4: performing a reactive aging test, collecting collector current (Ic), gate-emitter voltage (Vge) and collector-emitter voltage (Vce) signals of the power module to be tested through a signal acquisition module (8); S5: using an oscilloscope (7) to record the signal, and using the collector current (Ic) as a trigger signal, and saving the dynamic waveform when the current exceeds a preset threshold; S6: extracting dynamic parameters through the dedicated test software of the industrial computer (4), completing the synchronous monitoring of reactive power aging and dynamic testing, generating a test report and storing the test data; S7: After the test is completed, the power module to be tested is transported to a dewatering station (11) for dewatering.

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