Pin position determination method and apparatus, and device and medium

Abstract

Disclosed are a pin position determination method and apparatus, and a device and a medium, wherein a first module and a second module are two submodules in a chip, the first module is fixed on the chip, and the first module is to be connected to the second module. The method comprises: acquiring first position information of each first pin among at least one first pin of a first module, wherein each first pin is a pin located in a junction area between of the first module and a second module; acquiring a design database of the second module; and on the basis of the design database and the first position information of each first pin among the at least one first pin, determining second position information of each second pin among at least one second pin of the second module, wherein the first module and the second module are connected by means of the at least one first pin and the at least one second pin.

Description

Pin position determination method, device, equipment and medium Technical Field

[0001] The present application belongs to the field of chip design technology, and in particular relates to a pin position determination method, device, equipment and medium. Background Art

[0002] When designing a chip based on a bottom-up design model, the individual submodules are usually designed first. Each submodule is a separate module, such as the memory subsystem, computing unit, and control logic system. The pins between the submodules are then connected to form a complete chip. However, when connecting the submodules, wiring personnel need to manually determine the position of each submodule's pins. Since each submodule has a large number of pins, determining the position of each submodule's pins is a cumbersome and inefficient process. Technical Solutions

[0003] The embodiment of the present application provides an implementation solution that is different from the related art to solve the technical problem in the related art that the process of determining the position of the pins of each sub-module in the chip is cumbersome and inefficient.

[0004] In a first aspect, the present application provides a method for determining a pin position, wherein a first module and a second module are two submodules in a chip, the first module is fixed on the chip, and the first module and the second module are to be connected, the method comprising:

[0005] Obtaining first position information of each of at least one first pin of the first module, wherein the first pin is a pin located in an interface area between the first module and the second module, and the first position information includes at least one or more of metal layer information, physical size information, and area information within the chip;

[0006] Acquire a design database of the second module, wherein the design database includes functional requirement information, logic design information, and interface definition information of the second module;

[0007] The second position information of each of the at least one second pin of the second module is determined based on the design database and the first position information of each of the at least one first pin, wherein the second pin is a pin located on the boundary area between the first module and the second module, and the first module and the second module are connected through the at least one first pin and the at least one second pin.

[0008] In a second aspect, the present application provides a pin position determination device, wherein a first module and a second module are two submodules in a chip, the first module is fixed on the chip, and the first module and the second module are to be connected, and the device includes:

[0009] an acquiring unit, configured to acquire first position information of each of the at least one first pin of the first module, wherein the first pin is a pin located in a boundary area between the first module and the second module, and the first position information includes at least one or more of metal layer information, physical size information, and area information within the chip;

[0010] The acquisition unit is further configured to acquire a design database of the second module, wherein the design database includes functional requirement information, logic design information, and interface definition information of the second module;

[0011] a determination unit, configured to determine second position information of each of at least one second pin of the second module based on the design database and the first position information of each of the at least one first pin, wherein the second pin is a pin located on a boundary area between the first module and the second module, and the first module and the second module are connected through the at least one first pin and the at least one second pin.

[0012] In a third aspect, the present application provides an electronic device, comprising:

[0013] processor; and

[0014] a memory for storing executable instructions of the processor;

[0015] The processor is configured to execute the first aspect, or any method in each possible implementation of the first aspect, by executing the executable instructions.

[0016] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the first aspect, or any method in any possible implementation of the first aspect.

[0017] The present application provides a method for obtaining first position information of each of at least one first pin of the first module, wherein the first pin is a pin located in the boundary area between the first module and the second module, and the first position information includes at least one or more of metal layer information, physical size information, and area information in the chip; obtaining a design database of the second module, wherein the design database includes functional requirement information, logic design information, and interface definition information of the second module; and determining second position information of each of at least one second pin of the second module based on the design database and the first position information of each of the at least one first pin, wherein the second pin is a pin located in the boundary area between the first module and the second module. The scheme for connecting the first module and the second module through the at least one first pin and the at least one second pin can use the first position information of the fixed first pin in the first module to automatically determine the second position information of the second pin to be aligned with the fixed pin of the second module to be connected, thereby achieving the technical effect of improving the efficiency of the process of determining the position of the pins of each sub-module in the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0019] FIG1 is a schematic diagram of a flow chart of a pin position determination method provided in an embodiment of the present application;

[0020] FIG2 is a wiring diagram of a first module provided in one embodiment of the present application;

[0021] FIG3 is a wiring diagram of a second module provided in one embodiment of the present application;

[0022] FIG4 is a schematic structural diagram of a pin position determination device provided in an embodiment of the present application;

[0023] FIG5 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to be used to explain the present application, but should not be understood as limiting the present application.

[0025] The terms "first" and "second" in the specification, claims and drawings of the embodiments of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that this solution is implemented in other orders except the order illustrated or described in this application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] The design of medium- and large-scale integrated circuits (ICs) is typically based on a bottom-up approach. This approach aims to meet the performance requirements of each submodule within the chip. Therefore, it's impossible to accurately assess the size and shape of each submodule at the outset of design. Consequently, each submodule must be individually designed and then connected to create the integrated circuit chip. This connection requires wiring personnel to manually determine the positions of numerous pins, a labor-intensive, time-consuming, and inefficient process.

[0027] In order to solve this technical problem, the present application provides a pin position determination method, device, equipment and medium, which are used to solve the technical problem in the related art that the process of determining the position of the pins of each sub-module in the chip is cumbersome and inefficient.

[0028] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0029] FIG1 is a flow chart of a pin position determination method provided by an exemplary embodiment of the present application. The method may be applicable to a computing device, wherein a first module and a second module are two submodules in a chip, the first module is fixed to the chip, and the first module and the second module are to be connected. The method includes at least the following steps S11-S13:

[0030] S11. Obtain first position information of each of at least one first pin of the first module, wherein the first pin is located at a junction area between the first module and the second module, and the first position information includes at least one or more of metal layer information, physical size information, and area information within the chip.

[0031] In some embodiments, the physical size information includes width and height.

[0032] In some embodiments, the location information also includes direction information.

[0033] The chip is composed of multiple sub-modules, and the first module and the second module are two of the multiple sub-modules of the chip.

[0034] In some embodiments, in S11, obtaining first position information of each first pin of at least one first pin of the first module includes the following S111-S114:

[0035] S111. Obtain a first location area of ​​the first module on the chip;

[0036] S112. Acquire a second location area of ​​the second module on the chip;

[0037] S113: Determine a boundary area between the first module and the second module based on the first location area and the second location area;

[0038] S114 . Acquire position information of pins located in the boundary area among all pins of the first module to obtain first position information of the at least one first pin.

[0039] In some embodiments, a design file of a chip including a first module and a second module is opened in an EDA tool, and a first position area and a second position area of ​​the first module and the second module on the chip are respectively found in the design file. Specifically, the first position area and the second position area respectively include the position coordinates of the first module and the second module on the chip and the size of the area occupied by the first module and the second module in the chip.

[0040] Furthermore, by observing the first position area and the second position area, the boundary area between the first module and the second module can be determined.

[0041] In some embodiments, obtaining the position information of the pins located on the junction area among all the pins of the first module in S114 includes: executing an electronic design automation (EDA) tool executable command script, wherein the EDA tool executable command script is used to obtain the position information of the pins located on the junction area among all the pins of the first module, and obtain the first position information of each first pin of at least one first pin.

[0042] More specifically, an EDA tool executable command script may be written using an EDA tool command language, and the EDA tool executable command script may be executed in the EDA tool to capture the first position information of each first pin in the at least one first pin.

[0043] Figure 2 is a wiring diagram of a first module provided by an exemplary embodiment of the present application. The first module has four boundary areas, corresponding to the four sides shown in Figure 2. The first boundary area of ​​the first module includes four first pins, namely pin 1, pin 2, pin 3, and pin 4. The positions of these four first pins on the first module have been determined.

[0044] By viewing the chip design file, the first location area of ​​the first module on the chip can be found, including the specific coordinates of the four boundary areas of the first module and the area occupied by the first module in the chip.

[0045] FIG3 is a wiring diagram of a second module provided by an exemplary embodiment of the present application. Referring to FIG3 , the second module also includes four boundary areas, corresponding to the four edges shown in FIG3 .

[0046] By viewing the chip design file, the second location area of ​​the second module on the chip can be found, including the specific coordinates of the four boundary areas of the second module and the area occupied by the second module in the chip.

[0047] Furthermore, by observing the first position area and the second position area, the boundary area between the first module and the second module can be determined, that is, the first boundary area shown in FIG. 2 and the second boundary area of ​​the second module shown in FIG. 3 .

[0048] By executing the above-mentioned EDA tool executable command script in the EDA tool, the metal layer information, physical size information, area information in the chip, etc. of the four first pins, pin 1, pin 2, pin 3, and pin 4, can be obtained.

[0049] S12. Acquire a design database of the second module, wherein the design database includes functional requirement information, logic design information, and interface definition information of the second module;

[0050] Specifically, when designing each submodule of a chip, it is necessary to consider the functional requirements, logic design information, and interface definition information of each submodule. This information constitutes the design database of each submodule. Logic design information includes the internal logic of the submodule, which determines how to implement the submodule's functions. This may involve circuit design and gate-level design. Interface definition information includes the interaction interface between the submodule and other submodules or external systems, involving design information such as input / output interfaces and control interfaces.

[0051] S13. Determine the second position information of each of the at least one second pin of the second module based on the design database and the first position information of each of the at least one first pin, wherein the second pin is a pin located on the boundary area between the first module and the second module, and the first module and the second module are connected through the at least one first pin and the at least one second pin.

[0052] In some embodiments, in S13, determining the second position information of each of the at least one second pin of the second module based on the design database and the first position information of each of the at least one first pin includes:

[0053] Importing and loading the design database into a place and route tool;

[0054] Importing the first position information of each first pin of the at least one first pin into a script program for determining the position information of the pin of the second module;

[0055] The script program is executed to obtain second position information of each second pin in the at least one second pin.

[0056] In the embodiment provided in the present application, the design database can be imported into a layout and routing tool, and the design database can be loaded into the layout and routing tool. Furthermore, a script program is written to obtain the position information of the pins of the second module, and the first position information of each first pin of the at least one first pin is imported into the script program. The script program is executed to enable the layout and routing tool to automatically generate a wiring schematic diagram of the second module and obtain the second position information of each second pin of the at least one second pin on the second module.

[0057] Referring to Figure 3, the number of second pins to be connected to the above-mentioned four first pins on the second boundary area of ​​the second module is also 4, such as pin 5, pin 6, pin 7, and pin 8 shown in Figure 3. The second position information of pin 5, pin 6, pin 7, and pin 8 on the second module can be obtained through the wiring schematic diagram of the second module.

[0058] In some embodiments, the method further comprises:

[0059] The first module is connected to the second module based on the second position information of each second pin of the at least one second pin and the first position information of each first pin of the at least one first pin.

[0060] In some embodiments, the first module is composed of a plurality of third modules.

[0061] Specifically, the pins of the plurality of third modules have been fixed and the plurality of third modules have been connected to each other, and the plurality of third modules with determined connection relationships can be regarded as a first module.

[0062] The plurality of third position information of the plurality of third pins used to connect the plurality of third modules is determined according to the pin position determination method provided in the above embodiment.

[0063] The present application provides a method for obtaining first position information of each of at least one first pin of the first module, wherein the first pin is a pin located in the boundary area between the first module and the second module, and the first position information includes at least one or more of metal layer information, physical size information, and area information in the chip; obtaining a design database of the second module, wherein the design database includes functional requirement information, logic design information, and interface definition information of the second module; and determining second position information of each of at least one second pin of the second module based on the design database and the first position information of each of the at least one first pin, wherein the second pin is a pin located in the boundary area between the first module and the second module. The scheme for connecting the first module and the second module through the at least one first pin and the at least one second pin can use the first position information of the fixed first pin in the first module to automatically determine the second position information of the second pin to be aligned with the fixed pin of the second module to be connected, thereby achieving the technical effect of improving the efficiency of the process of determining the position of the pins of each sub-module in the chip.

[0064] FIG4 is a schematic structural diagram of a pin position determination device provided by an exemplary embodiment of the present application;

[0065] The first module and the second module are two submodules in the chip, the first module is fixed on the chip, and the first module and the second module are to be connected. The device includes:

[0066] an acquiring unit 41, configured to acquire first position information of each of at least one first pin of the first module, wherein the first pin is a pin located in a boundary area between the first module and the second module, and the first position information includes at least one or more of metal layer information, physical size information, and area information of the pin in the chip;

[0067] The acquisition unit 41 is further configured to acquire a design database of the second module, wherein the design database includes functional requirement information, logic design information, and interface definition information of the second module;

[0068] A determination unit 42 is used to determine the second position information of each of the at least one second pin of the second module based on the design database and the first position information of each of the at least one first pin, wherein the second pin is a pin located on the boundary area between the first module and the second module, and the first module and the second module are connected through the at least one first pin and the at least one second pin.

[0069] In some embodiments, when the apparatus is used to obtain the first position information of each first pin of at least one first pin of the first module, it is specifically used to:

[0070] Acquire a first location area of ​​the first module on the chip, wherein the first location area includes coordinates of a boundary area of ​​the first module on the chip and a size of an area occupied by the first module on the chip;

[0071] Acquire a second location area of ​​the second module on the chip, wherein the second location area includes coordinates of a boundary area of ​​the second module on the chip and an area size occupied by the second module on the chip;

[0072] determining a boundary area between the first module and the second module based on the first location area and the second location area;

[0073] Position information of pins located in the boundary area among all pins of the first module is acquired to obtain first position information of the at least one first pin.

[0074] In some embodiments, when the apparatus is used to determine the second position information of each of the at least one second pin of the second module based on the design database and the first position information of each of the at least one first pin, the apparatus is specifically used to:

[0075] Importing and loading the design database into a place and route tool;

[0076] Importing the first position information of each first pin of the at least one first pin into a script program for determining the position information of the pin of the second module;

[0077] The script program is executed to obtain second position information of each second pin in the at least one second pin.

[0078] In some embodiments, the physical size information includes width and height.

[0079] In some embodiments, the location information also includes direction information.

[0080] In some embodiments, the device is further configured to:

[0081] The first module is connected to the second module based on the second position information of each second pin of the at least one second pin and the first position information of each first pin of the at least one first pin.

[0082] In some embodiments, the first module is composed of a plurality of third modules, and a plurality of third position information of a plurality of third pins for connecting the plurality of third modules is determined according to any pin position determination method in the above embodiments.

[0083] It should be understood that the device embodiments and the method embodiments may correspond to each other, and similar descriptions may refer to the method embodiments. To avoid repetition, they will not be described in detail here. Specifically, the device can perform the above-mentioned method embodiments, and the aforementioned and other operations and / or functions of each module in the device are the corresponding processes in each method in the above-mentioned method embodiments, which will not be described in detail here for the sake of brevity.

[0084] The apparatus of the embodiment of the present application is described above from the perspective of functional modules in conjunction with the accompanying drawings. It should be understood that the functional module can be implemented in hardware, can be implemented by instructions in software, or can be implemented by a combination of hardware and software modules. Specifically, the steps of the method embodiment in the embodiment of the present application can be completed by hardware integrated logic circuits and / or software instructions in the processor. The steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. Optionally, the software module can be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps in the above method embodiment in conjunction with its hardware.

[0085] FIG5 is a schematic block diagram of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0086] The memory 501 and the processor 502 are configured to store computer programs and transmit the program code to the processor 502. In other words, the processor 502 can call and run the computer program from the memory 501 to implement the method in the embodiment of the present application.

[0087] For example, the processor 502 may be configured to execute the above method embodiments according to instructions in the computer program.

[0088] In some embodiments of the present application, the processor 502 may include but is not limited to:

[0089] General-purpose processor, Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc.

[0090] In some embodiments of the present application, the memory 501 includes but is not limited to:

[0091] Volatile memory and / or non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus random access memory (DR RAM).

[0092] In some embodiments of the present application, the computer program may be divided into one or more modules, which are stored in the memory 501 and executed by the processor 502 to implement the method provided by the present application. The one or more modules may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program in the electronic device.

[0093] As shown in FIG5 , the electronic device may further include:

[0094] The transceiver 503 may be connected to the processor 502 or the memory 501 .

[0095] The processor 502 may control the transceiver 503 to communicate with other devices. Specifically, the processor 502 may send information or data to other devices or receive information or data sent by other devices. The transceiver 503 may include a transmitter and a receiver. The transceiver 503 may further include one or more antennas.

[0096] It should be understood that the various components in the electronic device are connected via a bus system, wherein the bus system includes not only a data bus but also a power bus, a control bus and a status signal bus.

[0097] The present application also provides a computer storage medium having a computer program stored thereon, which, when executed by a computer, enables the computer to perform the method of the above-mentioned method embodiment. In other words, the present application also provides a computer program product containing instructions, which, when executed by a computer, enables the computer to perform the method of the above-mentioned method embodiment.

[0098] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disc (DVD)), or a semiconductor medium (e.g., a solid state drive (SSD)).

[0099] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0100] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0101] Modules described as separate components may or may not be physically separate, and components displayed as modules may or may not be physical modules, i.e., they may be located in one place or distributed across multiple network elements. Some or all of the modules may be selected based on actual needs to achieve the purpose of the present embodiment. For example, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module.

[0102] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program that has a predetermined function and works together with other related parts to achieve a predetermined goal, and can be implemented in whole or in part by using software, hardware (such as processing circuits or memories) or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the function of the module or unit.

[0103] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for determining a pin position, wherein a first module and a second module are two submodules in a chip, the first module has been fixed on the chip, and the first module and the second module are to be connected, the method comprising: Acquire first position information of each first pin of at least one first pin of the first module, wherein the first pin is a pin located at a junction area between the first module and the second module, and the first position information includes at least one or more of metal layer information, physical size information, and area information in the chip; Acquire a design database of the second module, wherein the design database includes functional requirement information, logic design information, and interface definition information of the second module; The second position information of each of the at least one second pin of the second module is determined based on the design database and the first position information of each of the at least one first pin, wherein the second pin is a pin located on the boundary area between the first module and the second module, and the first module and the second module are connected through the at least one first pin and the at least one second pin.

2. The method according to claim 1, wherein, The acquiring first position information of each first pin of at least one first pin of the first module includes: Acquire a first location area of ​​the first module on the chip, wherein the first location area includes coordinates of a boundary area of ​​the first module on the chip and a size of an area occupied by the first module in the chip; Acquire a second location area of ​​the second module on the chip, wherein the second location The area includes the coordinates of the boundary area of ​​the second module on the chip and the size of the area occupied by the second module in the chip; Determine a boundary area between the first module and the second module based on the first location area and the second location area; The position information of the pins located in the boundary area among all the pins of the first module is acquired to obtain the first position information of the at least one first pin.

3. The method according to claim 1, wherein, Determining second position information of each second pin of at least one second pin of the second module based on the design database and first position information of each first pin of the at least one first pin includes: Importing and loading the design database in a placement and routing tool; Importing the first position information of each first pin of the at least one first pin into a script program for determining the position information of the pin of the second module; The script program is executed to obtain second position information of each second pin in the at least one second pin.

4. The method according to claim 1, wherein The physical size information includes width and height.

5. The method according to claim 1, wherein, The location information also includes direction information.

6. The method according to claim 1, wherein The method further comprises: The first module is connected to the second module based on the second position information of each second pin of the at least one second pin and the first position information of each first pin of the at least one first pin.

7. The method according to claim 1, wherein, The first module is composed of a plurality of third modules, and a plurality of third position information of a plurality of third pins for connecting the plurality of third modules is determined according to the method according to any one of claims 1-6.

8. A pin position determination device, wherein a first module and a second module are two submodules in a chip, the first module is fixed on the chip, and the first module and the second module are to be connected, and the device comprises: an acquisition unit, configured to acquire first position information of each first pin of at least one first pin of the first module, wherein the first pin is a pin located at a junction area between the first module and the second module, and the first position information includes at least one or more of metal layer information, physical size information, and area information in the chip; The acquisition unit is further used to acquire a design database of the second module, wherein the design database includes functional requirement information, logic design information, and interface definition information of the second module; A determination unit is used to determine the second position information of each second pin of at least one second pin of the second module based on the design database and the first position information of each first pin of the at least one first pin, wherein the second pin is a pin located on the boundary area between the first module and the second module, and the first module and the second module are connected through the at least one first pin and the at least one second pin.

9. An electronic device, comprising: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to perform the method of any one of claims 1 to 7 by executing the executable instructions.

10. A computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the method according to any one of claims 1 to 7 when executed by a processor.

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