Continuous data transmission method and apparatus, electronic device and storage medium

Abstract

Embodiments of the present application disclose a continuous data transmission method and apparatus, an electronic device and a storage medium. The method comprises: in a preset period, acquiring a data packet from a continuous data sensor by means of an FPGA; sending a trigger signal and the data packet to a DSP on the basis of a clock signal of an internal timer; by means of the DSP and on the basis of the trigger signal, reading data in the data packet sent by the FPGA; and if the FPGA receives within a preset duration a confirmation signal sent by the DSP, updating the data packet by means of the FPGA on the basis of the confirmation signal.

Description

Continuous data transmission method, device, electronic device and storage medium

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 28, 2023, with application number 202311846229.2, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of semiconductor detection, for example, to a continuous data transmission method, device, electronic device and storage medium. Background Art

[0003] With the increasing demand for precision and high resolution in semiconductor inspection solutions, continuous scanning motion control systems are widely used in inspection equipment. The use of high-precision scanning systems requires high speed uniformity, which places increasingly stringent demands on the stability of data packet reading by different host control system communication protocols. Current industrial control systems include high-speed serial data communication protocols such as Serial Rapid IO (SRIO) and PCI Express (PCIE). However, these protocols present significant challenges in meeting the requirements for large data bandwidth and data stability during operation.

[0004] In the continuous data transmission method of the related art, the Field-Programmable Gate Array (FPGA) is timed by the FPGA crystal oscillator clock. When the value of the FPGA register reaches a fixed value, a trigger signal is generated to send the SRIO data packet to the Digital Signal Processor (DSP). The DSP interrupt generates an interrupt signal based on the CPU clock timing, and notifies the CPU to read the data through the interrupt signal. In this method, due to the cross-clock domain problem between the two main control devices (FPGA and DSP) (the FPGA clock is based on the physical crystal oscillator, and the DSP is based on the CPU clock), the DSP timing will fluctuate relative to the FPGA interrupt, and during the continuous data transmission process, the hardware clock difference will accumulate. As a result, for continuous scanning control systems, the system scan data fluctuates between two adjacent cycles, resulting in poor motion uniformity of the system.

[0005] Summary of the Invention

[0006] The present application provides a continuous data transmission method, device, electronic device and storage medium, which uniformly manage the clocks of DSP and FPGA, ensure the stability of data transmission between FPGA and DSP, and improve the motion uniformity of the system.

[0007] In a first aspect, an embodiment of the present application provides a continuous data transmission method, which is applied to a continuous data transmission system. The system includes a continuous data sensor, a digital signal processor (DSP), and a field programmable gate array (FPGA), wherein the FPGA includes an internal timer. The method includes:

[0008] Collecting data packets from the continuous data sensor via the FPGA within a preset period;

[0009] Sending a trigger signal and the data packet to the DSP based on a clock signal of the internal timer;

[0010] Reading data of the data packet sent by the FPGA based on the trigger signal through the DSP;

[0011] If the FPGA receives a confirmation signal sent by the DSP within a preset time period, the data packet is updated based on the confirmation signal via the FPGA.

[0012] In a second aspect, an embodiment of the present application further provides a continuous data transmission system, the system comprising a continuous data sensor, a digital signal processor (DSP), and a field programmable gate array (FPGA), wherein the FPGA comprises an internal timer;

[0013] The FPGA is configured to collect data packets from the continuous data sensor within a preset period; send a trigger signal and the data packet to the DSP based on a clock signal of the internal timer; and update the data packet based on the confirmation signal if a confirmation signal sent by the DSP is received within a preset time period;

[0014] The DSP is configured to read the data of the data packet sent by the FPGA based on the trigger signal, and if the reading is successful, send the confirmation signal to the FPGA.

[0015] In a third aspect, an embodiment of the present application further provides a continuous data transmission device, the device comprising:

[0016] a data acquisition module configured to acquire data packets from the continuous data sensor via the FPGA within a preset period;

[0017] a signal sending module, configured to send a trigger signal and the data packet to the DSP based on a clock signal of the internal timer;

[0018] A data reading module, configured to read data of a data packet sent by the FPGA based on the trigger signal through the DSP;

[0019] The signal receiving module is configured to update the data packet based on the confirmation signal through the FPGA if the FPGA receives the confirmation signal sent by the DSP within a preset time period.

[0020] In a fourth aspect, an embodiment of the present application further provides an electronic device, including:

[0021] at least one processor;

[0022] a memory configured to store at least one program;

[0023] When the at least one program is executed by the at least one processor, the at least one processor implements the continuous data transmission method provided in any embodiment of the present application.

[0024] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the continuous data transmission method provided in any embodiment of the present application is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a first flow chart of a continuous data transmission method provided by an embodiment of the present application;

[0026] FIG2 is a second flow chart of the continuous data transmission method provided in an embodiment of the present application;

[0027] FIG3 is a first structural diagram of a continuous data transmission system provided in an embodiment of the present application;

[0028] FIG4 is a second structural diagram of the continuous data transmission system provided in an embodiment of the present application;

[0029] FIG5 is a first time domain diagram of a continuous data transmission system provided by an embodiment of the present application;

[0030] FIG6 is a first timing diagram of a continuous data transmission system provided in an embodiment of the present application;

[0031] FIG7 is a second time domain diagram of the continuous data transmission system provided in an embodiment of the present application;

[0032] FIG8 is a second timing diagram of the continuous data transmission system provided in an embodiment of the present application;

[0033] FIG9 is a schematic structural diagram of a continuous data transmission device provided in an embodiment of the present application;

[0034] FIG10 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] Figure 1 is a first flow chart of a continuous data transmission method provided by an embodiment of the present application. The method of this embodiment uniformly manages the clocks of the DSP and FPGA, ensuring the stability of data transmission between the FPGA and DSP and improving the motion uniformity of the system. This method can be performed by a continuous data transmission device in an embodiment of the present application, which can be integrated into an electronic device, which can be a server. The server includes a continuous data transmission system. This method can be implemented using at least one of software and hardware. The continuous data transmission method provided by this embodiment, for example, includes the following steps:

[0037] Step 101: Collect data packets from a continuous data sensor via FPGA within a preset period.

[0038] Among them, the preset period is related to the data transmission protocol used between the FPGA and DSP and the transmission mode of the data transmission protocol. Different data transmission protocols and data transmission modes correspond to different preset periods. Commonly used transmission protocols include SRIO, PCIE, serial port (Serial Advanced Technology Attachment, SATA) and Aurora. These data transmission protocols can be set as data communication interfaces, but their design purposes, characteristics and application scenarios are different, so the data capture period (preset period) is also different. A continuous data sensor is a sensor that can generate a continuous signal, and its output directly corresponds to the input quantity. A continuous data sensor can provide continuous position data, high position resolution and high-speed response.

[0039] The continuous data transmission system in this solution includes a continuous data sensor, a DSP, and an FPGA. The FPGA includes an internal timer. The internal timer is a hardware clock within the FPGA that sends clock signals to the FPGA at regular intervals. Based on the received clock signal, the FPGA collects continuous data from the continuous data sensor and generates data packets based on the collected continuous data.

[0040] Step 102: Send a trigger signal and a data packet to the DSP based on the clock signal of the internal timer.

[0041] The trigger signal is sent by the FPGA to the DSP, instructing the DSP to read the data packet. In this solution, the trigger signal can be a TRIG pulse. When the FPGA receives a clock signal from an internal timer, it sends a high-level pulse (lasting at least 10 microseconds) to the DSP, effectively sending a trigger signal.

[0042] In this solution, optionally, the data packet includes an SRIO data packet, and based on the clock signal of the internal timer, sending the data packet to the DSP includes: the FPGA sends the SRIO data packet to the DSP through the SWRITE mode of the SRIO.

[0043] SRIO is a high-speed serial communication protocol widely used in high-performance computing, data storage, and data transmission. During data transmission between FPGAs and DSPs, SRIO provides high-speed communication, low latency, and powerful debugging and diagnostic capabilities. SWRITE mode is a write operation in the SRIO protocol, whose main function is to write data to a specified address space. This mode allows direct write operations to the target address, eliminating the need to first read data through an NREAD transaction and then write data through an NWRITE transaction, as required for read operations. This reduces overall transmission latency. In an optional implementation, the FPGA packages data packets into the SRIO protocol through an input port and uses SRIO to send the data packets to the DSP via high-speed serial communication. During this process, the FPGA can utilize different SRIO transaction types to perform different operations. For example, when reading data from the DSP, an NREAD transaction can be used; when writing data to a specific address on the DSP, an NWRITE transaction can be used.

[0044] The above steps enable Swrite SRIO to be applied to continuous scanning multi-master interactive systems without affecting the SRIO Swrite bandwidth, thereby enhancing data stability.

[0045] Step 103: Read the data of the data packet sent by the FPGA based on the trigger signal through the DSP.

[0046] The trigger signal is sent by the FPGA to the DSP, instructing the DSP to read a data packet. For example, after the DSP receives the trigger signal from the FPGA, it needs to notify the DSP that the data is ready through a hardware interrupt or software trigger during the process of reading the data packet sent by the FPGA based on the trigger signal. For example, the FPGA can send an interrupt to the DSP via a general-purpose input / output (GPIO). When the DSP receives the interrupt from the FPGA, it will read and write the corresponding memory area of ​​the FPGA.

[0047] In this solution, when an internal timer issues a clock signal, the FPGA generates a packet identifier for the data packet. Based on the packet identifier, a trigger signal is generated and sent to the DSP via a pre-configured shared transmission line or transmission interface. The trigger signal is then identified as an interrupt signal for the DSP, and based on the interrupt signal, the DSP is switched from its current state to an interrupt state. While in the interrupt state, the DSP reads the data in the data packet sent by the FPGA based on the trigger signal.

[0048] Step 104 : In response to the FPGA receiving the confirmation signal sent by the DSP within a preset time period, the FPGA updates the data packet based on the confirmation signal.

[0049] The preset duration is a predetermined duration determined by the continuous data transmission system based on a clock signal, a data transmission protocol, and the like. The acknowledgment signal is a signal sent by the DSP to the FPGA, instructing the FPGA to continue acquiring data packets from the continuous data sensor. In this solution, the acknowledgment signal can be an acknowledgment character (ACK).

[0050] For example, after receiving a data packet, the DSP reads the data from the packet. After completing the data read, the DSP can pull high the ACK (an acknowledgement signal output by the DSP to the FPGA). If the FPGA detects a rising edge on the ACK, it refreshes the FPGA's register data, essentially updating the data packet based on the acknowledgement signal. Otherwise, the register data is not updated and is latched. In this solution, if the FPGA does not receive an acknowledgement signal from the DSP within a preset time period, the FPGA repeatedly sends a trigger signal to the DSP based on a clock signal until the FPGA receives an acknowledgement signal from the DSP.

[0051] In an optional embodiment, the DSP reads the data packet. If the read is successful, the DSP can send an acknowledgment signal to the FPGA within a preset time period. The FPGA can then update the data packet based on the acknowledgment signal. If the FPGA does not receive the acknowledgment signal within the preset time period, the FPGA can pull TRIG high again to start the next cycle.

[0052] The technical solution of this embodiment is applied to a continuous data transmission system. The system includes a continuous data sensor, a digital signal processor (DSP), and a field-programmable gate array (FPGA). The FPGA includes an internal timer. The continuous data transmission method includes: collecting data packets from the continuous data sensor via the FPGA within a preset period; sending a trigger signal and data packets to the DSP based on a clock signal from the internal timer; reading the data in the data packets sent by the FPGA via the DSP based on the trigger signal; and updating the data packets based on the confirmation signal if the FPGA receives an acknowledgment signal from the DSP within a preset time. In the technical solution of this embodiment, the clocks of the DSP and FPGA are uniformly managed to ensure the stability of data transmission between the FPGA and DSP and improve the motion uniformity of the system.

[0053] FIG2 is a second flow chart of the continuous data transmission method provided in an embodiment of the present application. As shown in FIG2 , the method mainly includes the following steps:

[0054] Step 201: Collect data packets from a continuous data sensor via FPGA within a preset period.

[0055] Step 202: When the internal timer sends a clock signal, a packet identifier of the data packet is generated by the FPGA.

[0056] The packet identifier, also known as a packet ID (Identity document), is used to identify different data packets. In an optional embodiment, the FPGA can configure a counter to increment during each clock cycle. When the counter value reaches a preset threshold, the FPGA can send the current data packet and reset the counter to prepare for the next data packet. For example, suppose the FPGA has a 16-bit counter. Each time the rising edge of the clock triggers, the counter value increases by 1. When the counter value reaches 1024, the FPGA can send the current data packet and reset the counter to 0. In this way, the FPGA can generate a new data packet and a packet identifier at every 1-second time interval and send them out.

[0057] Step 203: Generate a trigger signal based on the packet identifier, and send the trigger signal to the DSP through a preset shared transmission line or transmission interface.

[0058] For example, after generating a packet identifier, the FPGA can generate a trigger signal by configuring corresponding logic circuits and transmit the trigger signal to the DSP via a shared transmission line or a specific transmission interface. For example, a universal asynchronous receiver / transmitter (UART) serial communication interface can be used to transmit the trigger signal to the DSP. The UART serial communication interface is a widely used short-distance serial transmission interface. In actual applications, the trigger signal generation method and transmission interface can be determined based on actual application requirements and hardware device characteristics.

[0059] Step 204: Send a data packet to the DSP based on the clock signal of the internal timer.

[0060] Step 205: Determine the trigger signal as an interrupt signal of the DSP, and adjust the DSP from the current state to the interrupt state based on the interrupt signal.

[0061] The trigger signal is sent by the FPGA to the DSP, instructing it to read a data packet. Interrupts are a crucial technology in the DSP, enabling operations such as real-time control, fault handling, and data transfer. An interrupt is a hardware or software-generated signal that instructs the DSP to suspend its program execution and instead execute a task called an interrupt service routine.

[0062] In an alternative implementation, the FPGA can send a TRIG pulse to the DSP based on the clock signal. Upon receiving the TRIG pulse, the DSP interprets it as an interrupt signal. Based on the interrupt signal, the DSP can suspend the current program and jump to the interrupt service routine, effectively switching the DSP from its current state to an interrupted state. After the interrupt service routine completes, the DSP returns to the interrupted program and continues execution.

[0063] Step 206: The DSP reads the data packet sent by the FPGA based on the trigger signal in the interrupt state.

[0064] For example, when the DSP is in an interrupt state, after receiving a data packet sent by the FPGA, the DSP will pause the currently executing program and jump to the interrupt service routine (ISR). In the ISR, the DSP needs to parse the data packet to determine the format and content of the data packet. The reading method can be determined based on the format and content of the data packet, and the data packet is read according to the reading method of the data packet. For example, if the data packet is a byte stream, the DSP can use direct memory access technology to copy the data from the FPGA's memory space to the DSP's memory space. If the data packet is a structure or array, the DSP can directly access the data through a pointer.

[0065] Step 207: If the FPGA receives a confirmation signal sent by the DSP within a preset time period, the FPGA updates the data packet based on the confirmation signal.

[0066] Step 208: If the FPGA does not receive the confirmation signal sent by the DSP within the preset time, the FPGA repeatedly sends a trigger signal to the DSP according to the clock signal until the FPGA receives the confirmation signal sent by the DSP.

[0067] The continuous data transmission method provided in an embodiment of the present application collects data packets from a continuous data sensor through an FPGA within a preset period. A trigger signal is generated based on the packet identifier, and the trigger signal is sent to the DSP through a pre-set shared transmission line or transmission interface. A data packet is sent to the DSP based on the clock signal of the internal timer. The trigger signal is determined to be an interrupt signal for the DSP, and the DSP is adjusted from the current state to the interrupt state based on the interrupt signal. In the interrupt state, the DSP reads the data of the data packet sent by the FPGA based on the trigger signal. If the FPGA receives a confirmation signal sent by the DSP within a preset time length, the data packet is updated based on the confirmation signal through the FPGA. If the FPGA does not receive a confirmation signal sent by the DSP within the preset time length, the trigger signal is repeatedly sent to the DSP according to the clock signal through the FPGA until the FPGA receives the confirmation signal sent by the DSP. The technical solution of this embodiment adopts a double handshake mechanism between the FPGA and the DSP in combination with the data packet ID to uniformly manage the clock of the DSP+FPGA system, shift the DSP interrupt clock down to the FPGA, and ensure the stability of data packets sent between the FPGA and the DSP.

[0068] Figure 3 is a first structural diagram of a continuous data transmission system provided by an embodiment of the present application. As shown in Figure 3, the continuous data transmission system includes a continuous data sensor, a DSP, and an FPGA. The FPGA includes an internal timer. The FPGA is configured to collect data packets from the continuous data sensor within a preset period. Based on the clock signal of the internal timer, the FPGA sends a trigger signal to the DSP. Based on the clock signal of the internal timer, the FPGA sends a trigger signal and a data packet to the DSP. If a confirmation signal from the DSP is received within a preset time period, the DSP updates the data packet based on the confirmation signal. The DSP is configured to read the data in the data packet sent by the FPGA based on the trigger signal and, if the reading is successful, sends a confirmation signal to the FPGA.

[0069] The preset period is related to the data transmission protocol used between the FPGA and DSP, as well as the transmission mode of the data transmission protocol. A continuous data sensor is a sensor that generates a continuous signal, whose output directly corresponds to the input quantity. A continuous data sensor can provide continuous position data, high position resolution, and high-speed response. In an optional embodiment, the FPGA is configured to generate a packet identifier for a data packet when an internal timer issues a clock signal; generate a trigger signal based on the packet identifier, and transmit the trigger signal to the DSP via a pre-configured shared transmission line or transmission interface.

[0070] Figure 4 is a second structural schematic diagram of the continuous data transmission system provided in an embodiment of the present application. As shown in Figure 4, the continuous data transmission system includes a DSP, an FPGA, and a continuous data sensor. The FPGA includes a data driver module, a data acquisition module, an ID generation module, a signal transceiver module, and a register. The DSP includes a signal transceiver module, an interface module, and a storage device. Among them, the register of the FPGA can instruct the FPGA's data driver module to send data parameters to the continuous data sensor, and the data acquisition module receives the data packet sent by the continuous data sensor and sends the data packet to the register. After the register generates the packet ID through the ID generation module, it sends a trigger signal to the DSP through the signal transceiver module, and the register sends the data packet to the storage device through the data interface. The DSP receives the trigger signal through the signal transceiver module, determines an interrupt signal based on the trigger signal, and reads the data packet received by the storage device based on the interrupt signal. The storage device can send the read data to the interface module and generate a confirmation signal, and send the confirmation signal to the signal transceiver module of the FPGA through the signal transceiver module.

[0071] In this system, if the FPGA receives a confirmation signal sent by the DSP within a preset time, the FPGA updates the data packet based on the confirmation signal. If the FPGA does not receive a confirmation signal sent by the DSP within the preset time, the FPGA repeatedly sends a trigger signal to the DSP according to the clock signal until the FPGA receives the confirmation signal sent by the DSP. For example, Figure 5 is a first time domain diagram provided by an embodiment of the present application. As shown in Figure 5, the FPGA receives a confirmation signal sent by the DSP within the preset time. The left side of Figure 5 is the FPGA time domain, and the right side is the DSP time domain. The FPGA sends data packets with packet identifiers X (ID=X) and X+1 (ID=X+1) to the DSP via SRIO. When the FPGA sends a data packet with packet identifier X+2 to the DSP, it simultaneously sends a TRIG signal to the DSP via the signal transceiver module (TRIG&ACK). After receiving the TRIG signal, the DSP sends the data packet to the DSP's storage device. For example, the FPGA continues to send data packets with packet identifiers X+3 (ID=X+3) and X+4 (ID=X+4) to the DSP via SRIO. Figure 6 is a first timing diagram of the continuous data transmission system provided by an embodiment of the present application. As shown in Figure 6, the FPGA receives the confirmation signal sent by the DSP within a preset time length. FPGA_CLK represents the clock signal, FPGA_data packet represents the data packet obtained by the FPGA (reflected by the packet identifier in the figure), and SRIO_data packet represents the data packet sent by the FPGA to the DSP via SRIO. DSP TRIG (FPGA output) represents the TRIG signal sent by the FPGA received by the DSP. It can be seen from Figure 6 that when the FPGA sends a data packet with a packet identifier of X+2 to the DSP, it also sends a TRIG signal to the DSP. DSP ACK (FPGA input) is the confirmation signal returned to the FPGA after the DSP receives the data packet with a packet identifier of X+2. It can be seen from Figure 6 that the DSP successfully received the data packet with a packet identifier of X+2 and sent a confirmation signal to the FPGA.

[0072] For example, Figure 7 is a second time domain diagram of the continuous data transmission system provided by an embodiment of the present application. As shown in Figure 7, when the FPGA does not receive an acknowledgment signal sent by the DSP within a preset time, the FPGA will repeatedly send a TRIG signal and a data packet until the DSP receives the data packet. The left side of Figure 7 is the FPGA time domain, and the right side is the DSP time domain. The FPGA sends data packets with packet identifiers X (ID=X) and X+1 (ID=X+1) to the DSP via SRIO. When the FPGA sends a data packet with packet identifier X+2 to the DSP, it also sends a TRIG signal to the DSP via the signal transceiver module (TRIG&ACK). The DSP does not receive it or the read fails, so the FPGA does not receive the return signal sent by the DSP. For example, the FPGA repeatedly sends a data packet with packet identifier X+2 and a TRIG signal to the DSP via SRIO until the DSP receives the TRIG signal and sends the data packet to the DSP's storage device. After receiving the data packet, the DSP sends an ACK signal to the FPGA. After receiving the ACK signal, the FPGA sends the data packet and packet ID obtained at the current moment. If the packet ID at the current moment is X+3, a data packet with packet ID X+3 is sent to the DSP. Exemplarily, continue to send data packets with packet identification X+4 (ID=X+4) to complete the data transmission process of the current cycle. Figure 8 is a second timing diagram of the continuous data transmission system provided by an embodiment of the present application. As shown in Figure 8, the FPGA did not receive the confirmation signal sent by the DSP within the preset time length. It can be seen from Figure 8 that when the FPGA sends a data packet with packet identification X+2 to the DSP, it also sends a TRIG signal to the DSP. Since the DSP did not receive the data packet or the reading failed, the FPGA did not receive the return signal sent by the DSP, then the FPGA repeatedly sends the data packet with packet identification X+2 and the TRIG signal to the DSP through SRIO. The 6 horizontal lines of DSP TRIG (FPGA output) in Figure 8 are raised, indicating that it was sent 6 times. After the DSP successfully receives the data packet with packet identification X+2, it sends a confirmation signal to the FPGA.

[0073] The system provided in this embodiment includes a continuous data sensor, a DSP, and an FPGA. The FPGA includes an internal timer. The FPGA is configured to collect data packets from the continuous data sensor within a preset period. Based on the clock signal of the internal timer, the FPGA sends a trigger signal to the DSP. Based on the clock signal of the internal timer, the DSP sends a trigger signal and a data packet to the DSP. If an acknowledgment signal from the DSP is received within a preset time, the data packet is updated based on the acknowledgment signal. The DSP is configured to read the data in the data packet sent by the FPGA based on the trigger signal and, if the read is successful, send a acknowledgment signal to the FPGA. The system provided in this embodiment uniformly manages the clocks of the DSP and FPGA, ensuring the stability of data transmission between the FPGA and DSP and improving the motion uniformity of the system.

[0074] FIG9 is a schematic diagram of the structure of a continuous data transmission device provided in an embodiment of the present application. The present application provides a continuous data transmission device, the device comprising:

[0075] The data acquisition module 901 is configured to collect data packets from the continuous data sensor via the FPGA within a preset period;

[0076] a signal sending module 902 configured to send a trigger signal and the data packet to the DSP based on the clock signal of the internal timer;

[0077] A data reading module 903 is configured to read the data of the data packet sent by the FPGA based on the trigger signal through the DSP;

[0078] The signal receiving module 904 is configured to update the data packet based on the confirmation signal via the FPGA if the FPGA receives the confirmation signal sent by the DSP within a preset time period.

[0079] Optionally, the signal sending module 902 is configured to: generate a packet identifier of the data packet through the FPGA when the internal timer sends a clock signal;

[0080] The trigger signal is generated based on the packet identifier, and the trigger signal is sent to the DSP through a preset shared transmission line or transmission interface.

[0081] Optionally, the data reading module 903 is configured to: determine the trigger signal as an interrupt signal of the DSP, and adjust the DSP from a current state to an interrupt state based on the interrupt signal;

[0082] In the interrupt state, the DSP reads the data packet sent by the FPGA based on the trigger signal.

[0083] Optionally, the signal receiving module 904 is configured, for example, to: if the FPGA does not receive the confirmation signal sent by the DSP within the preset time length, repeatedly send the trigger signal to the DSP through the FPGA according to the clock signal until the FPGA receives the confirmation signal sent by the DSP.

[0084] Optionally, the data packet includes a data packet of the SRIO serial bus protocol. Based on the clock signal of the internal timer, the signal sending module 902 is further configured such that: the FPGA sends the SRIO data packet to the DSP through the SWRITE mode of the SRIO.

[0085] The continuous data transmission device provided in the embodiment of the present application can execute the continuous data transmission method provided in any embodiment of the present application, and has the corresponding functional modules and effects of the execution method.

[0086] FIG10 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Referring to FIG10 , a schematic diagram of the structure of a computer system 12 suitable for implementing an electronic device in an embodiment of the present application is shown. The electronic device shown in FIG10 is merely an example and should not limit the functionality and scope of use of the embodiments of the present application. The components of the electronic device 12 may include, but are not limited to, at least one processor or processing unit 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processing unit 16).

[0087] Bus 18 represents at least one of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. Examples of such architectures include, but are not limited to, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0088] The electronic device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the electronic device 12, including volatile and non-volatile media, removable and non-removable media.

[0089] The system memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The electronic device 12 may include other removable or non-removable, volatile or non-volatile computer system storage media. By way of example only, the storage system 34 may be used to read and write non-removable, non-volatile magnetic media (not shown in FIG. 10 , commonly referred to as a “hard drive”). Although not shown in FIG. 10 , a disk drive for reading and writing to a removable non-volatile disk (such as a “floppy disk”) and an optical disk drive for reading and writing to a removable non-volatile optical disk (such as a CD-ROM, DVD-ROM or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 via at least one data medium interface. The memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the embodiments of the present application.

[0090] A program or utility 40 having a set (at least one) of program modules 42 may be stored, for example, in memory 28. Such program modules 42 include, but are not limited to, an operating system, at least one application program, other program modules, and program data, each of which, or various combinations thereof, may include an implementation of a network environment. Program modules 42 generally perform the functions and / or methods of the embodiments described herein.

[0091] The electronic device 12 can also communicate with at least one external device 14 (e.g., a keyboard, pointing device, display 24, etc.), at least one device that enables a user to interact with the electronic device 12, and / or any device that enables the electronic device 12 to communicate with at least one other computing device (e.g., a network card, a modem, etc.). This communication can be performed via an input / output (I / O) interface 22. Furthermore, in the electronic device 12 of this embodiment, the display 24 is not a separate entity, but is embedded in the mirror surface. When the display surface of the display 24 is not displayed, the display surface of the display 24 and the mirror surface are visually integrated. Furthermore, the electronic device 12 can also communicate with at least one network (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 20. As shown in the figure, the network adapter 20 communicates with other modules of the electronic device 12 via a bus 18. It should be understood that although not shown in Figure 10, other hardware and / or software modules may be used in conjunction with the electronic device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, disk arrays (Redundant Arrays of Independent Disks, RAID) systems, tape drives, and data backup storage systems.

[0092] The processing unit 16 executes various functional applications and continuous data transmission by running the program stored in the system memory 28, for example, implementing a continuous data transmission method provided in an embodiment of the present application: collecting data packets from the continuous data sensor through the FPGA within a preset period; sending a trigger signal and the data packet to the DSP based on the clock signal of the internal timer; reading the data of the data packet sent by the FPGA based on the trigger signal through the DSP; if the FPGA receives a confirmation signal sent by the DSP within a preset time length, updating the data packet based on the confirmation signal through the FPGA.

[0093] The embodiments of the present application provide a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, a continuous data transmission method as provided in all embodiments of the present application is implemented: collecting data packets from the continuous data sensor via the FPGA within a preset period; sending a trigger signal and the data packet to the DSP based on the clock signal of the internal timer; reading the data of the data packet sent by the FPGA via the DSP based on the trigger signal; and updating the data packet via the FPGA based on the confirmation signal if the FPGA receives a confirmation signal sent by the DSP within a preset time period. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or any combination thereof. Examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having at least one conductor, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fibers, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium may be any tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device.

[0094] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0095] The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wire, optical cable, radio frequency (RF), etc., or any suitable combination of the foregoing.

[0096] The computer program code for performing the operations of the present application can be written in at least one programming language or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

Claims

1. A continuous data transmission method is applied to a continuous data transmission system. The system includes a continuous data sensor, a digital signal processor (DSP), and a field-programmable gate array (FPGA). The FPGA includes an internal timer. The method includes: Collecting data packets from the continuous data sensor through the FPGA within a preset period; Sending a trigger signal and the data packet to the DSP based on the clock signal of the internal timer; Reading the data of the data packet sent by the FPGA by the DSP based on the trigger signal; In response to the FPGA receiving the acknowledgment signal sent by the DSP within a preset duration, updating the data packet by the FPGA based on the acknowledgment signal.

2. The method according to claim 1, wherein Sending a trigger signal to the DSP based on the clock signal of the internal timer includes: Generating a packet identifier of the data packet by the FPGA in response to the internal timer sending a clock signal; Generating the trigger signal based on the packet identifier and sending the trigger signal to the DSP through a pre-set shared transmission line or transmission interface.

3. The method according to claim 2, wherein, Reading the data of the data packet sent by the FPGA by the DSP based on the trigger signal includes: Determining the trigger signal as an interrupt signal of the DSP and adjusting the DSP from the current state to an interrupt state based on the interrupt signal; Reading the data of the data packet sent by the FPGA by the DSP in the interrupt state based on the trigger signal.

4. The method according to claim 1 further includes: In response to the FPGA not receiving the acknowledgment signal sent by the DSP within the preset duration, repeatedly sending the trigger signal to the DSP by the FPGA according to the clock signal until the FPGA receives the acknowledgment signal sent by the DSP.

5. The method according to claim 1, wherein The data packet includes a data packet of the Serial Rapid I / O (SRIO) serial bus protocol. Sending a trigger signal and the data packet to the DSP based on the clock signal of the internal timer includes: The FPGA sending the SRIO data packet to the DSP through the SWRITE mode of the SRIO.

6. A continuous data transmission system includes a continuous data sensor, a digital signal processor (DSP), and a field-programmable gate array (FPGA). The FPGA includes an internal timer; The FPGA is configured to collect data packets from the continuous data sensor within a preset period; Sending a trigger signal and the data packet to the DSP based on the clock signal of the internal timer; in response to receiving the acknowledgment signal sent by the DSP within a preset duration, updating the data packet based on the acknowledgment signal; The DSP is configured to read the data of the data packet sent by the FPGA based on the trigger signal and send the acknowledgment signal to the FPGA in response to successful reading.

7. The system according to claim 6, wherein, The FPGA is configured to generate a packet identifier of the data packet in response to the internal timer sending a clock signal; generate the trigger signal based on the packet identifier and send the trigger signal to the DSP through a pre-set shared transmission line or transmission interface.

8. A continuous data transmission device, comprising: A data acquisition module (901), configured to collect data packets from the continuous data sensor through the FPGA within a preset period; A signal sending module (902), configured to send a trigger signal and the data packet to the DSP based on the clock signal of the internal timer; A data reading module (903), configured to read the data of the data packet sent by the FPGA through the DSP based on the trigger signal; A signal receiving module (904), configured to update the data packet through the FPGA based on the acknowledgment signal in response to the FPGA receiving the acknowledgment signal sent by the DSP within a preset duration.

9. An electronic device, comprising a memory (28), a processor (16), and a computer program stored on the memory (28) and executable on the processor (16), wherein when the processor (16) executes the program, it implements the continuous data transmission method according to any one of claims 1 to 5.

10. A computer-readable storage medium, having stored thereon a computer program, which when executed by a processor, implements the continuous data transmission method according to any one of claims 1 - 5.

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