High-power vertical-cavity surface-emitting laser and manufacturing method therefor

Abstract

A high-power vertical-cavity surface-emitting laser and a manufacturing method therefor. The high-power vertical-cavity surface-emitting laser comprises: a substrate (10); a semiconductor epitaxial layer (20) located on one side of the substrate (10), wherein the semiconductor epitaxial layer (20) comprises at least one first region (E2) and a second region (E1) surrounding the first region (E2), and the semiconductor epitaxial layer (20) in the second region (E1) is etched to form a trench (201); a filling layer (30), the trench (201) being filled with the filling layer (30); a dielectric layer (40) comprising a first dielectric layer (41) and located on the side of the semiconductor epitaxial layer (20) distant from the substrate (10), wherein the dielectric layer (40) comprises a first opening (401), the vertical projection of the first opening (401) on the semiconductor epitaxial layer (20) is located in the first region (E2); and an upper electrode (50) located on the side of the first dielectric layer (41) distant from the substrate (10), wherein the upper electrode (50) is electrically connected to a light-emitting structure (24) by means of the first opening (401), and the upper electrode (50) and the filling layer (30) located in the second region (E1) are separated from each other by means of the first dielectric layer (41).

Description

High-power vertical cavity surface emitting laser and preparation method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 27, 2023, with application number 202311826348.1, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of semiconductor technology, for example, to a high-power vertical cavity surface emitting laser and a method for preparing the same. Background Art

[0003] With the rapid development of modern electronic technologies, such as new energy vehicles, the demand for vertical-cavity surface-emitting lasers (VCSELs), which are used as light sources for lidar, has increased significantly.

[0004] In LiDAR applications, operating conditions typically involve narrow pulse drive, with pulse widths between 3 and 8 ns. Precisely because of this small pulse width, the laser can be driven with a higher voltage or current compared to DC operating conditions. However, higher voltages or currents can pose challenges for VCSELs. For example, for VCSELs with high-aspect-ratio trenches, the reduced spacing between the light-emitting holes or the increased trench etch depth pose significant challenges to trench coverage, impacting device flatness and reliability. Furthermore, the laser's inherent capacitance can affect narrow pulse performance.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a high-power vertical cavity surface emitting laser and a method for manufacturing the same, which ensure the flatness of the device while improving the performance and reliability of the device.

[0007] According to one aspect of the present application, a high-power vertical cavity surface emitting laser is provided, comprising: a substrate; a semiconductor epitaxial layer, located on one side of the substrate; the semiconductor epitaxial layer comprising at least one first region and a second region arranged around the first region; the first region having at least one light-emitting structure; the second region having a groove; a filling layer, filling the groove; the material of the filling layer having high temperature resistance; a dielectric layer, the dielectric layer comprising a first dielectric layer, located on a side of the semiconductor epitaxial layer away from the substrate; wherein the dielectric layer comprises a first opening; the vertical projection of the first opening in the semiconductor epitaxial layer is located in the first region; an upper electrode, located on a side of the first dielectric layer away from the substrate; the upper electrode is electrically connected to the light-emitting structure through the first opening, and the upper electrode located in the second region is separated from the filling layer by the first dielectric layer.

[0008] Optionally, a difference between a distance between a surface of the filling layer away from the substrate and the substrate and a distance between a surface of the semiconductor epitaxial layer away from the substrate and the substrate is smaller than a preset value.

[0009] Optionally, the material of the filling layer includes metal material or dielectric material.

[0010] Optionally, the metal material includes Au or Cu; and the dielectric material includes nitride or oxide.

[0011] Optionally, along the direction from the second region to the first region, the width of the groove is less than or equal to 4 um; and the aspect ratio of the groove is greater than or equal to 2.

[0012] Optionally, the groove is annular in shape; the annular groove is arranged around the light-emitting structure; or, the groove is hole-shaped; a plurality of hole-shaped grooves are arranged around the light-emitting structure.

[0013] Optionally, the dielectric layer also includes: a second dielectric layer, the second dielectric layer is located between the semiconductor epitaxial layer and the first dielectric layer, and the sidewalls and bottom of the groove; wherein the dielectric layer includes a first opening, the first opening passes through the first dielectric layer and the second dielectric layer; the upper electrode is electrically connected to the light-emitting structure through the first opening.

[0014] Optionally, the semiconductor epitaxial layer includes a lower Bragg reflector layer, an upper Bragg reflector layer, and at least one active layer located between the lower Bragg reflector layer and the upper Bragg reflector layer; wherein the lower Bragg reflector layer is closer to the substrate; and the active layer located in the first region includes at least one oxide confinement layer for carrier confinement.

[0015] According to another aspect of the present application, a method for preparing a high-power vertical cavity surface emitting laser is provided, comprising: providing a substrate; forming a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer comprising at least one first region and a second region arranged around the first region; etching the semiconductor epitaxial layer in the second region to form a groove; wherein the semiconductor epitaxial layer located in the first region is used to form a light-emitting structure; forming a filling layer in the groove; forming a dielectric layer on a side of the semiconductor epitaxial layer away from the substrate; wherein the dielectric layer comprises a first dielectric layer; etching the dielectric layer to form a first opening in the dielectric layer; the vertical projection of the first opening on the semiconductor epitaxial layer is located in the first region; forming an upper electrode on a side of the first dielectric layer away from the substrate; the upper electrode is electrically connected to the light-emitting structure through the first opening, and the upper electrode located in the second region is separated from the filling layer by the first dielectric layer.

[0016] Optionally, the material of the filling layer includes a metal material; forming the filling layer in the groove includes: depositing a seed metal and then electroplating Cu or Au to form the filling layer; or, the material of the filling layer includes a dielectric material; forming the filling layer in the groove includes: depositing a nitride or oxide in the groove to form the filling layer.

[0017] Optionally, before forming a filling layer in the trench, the method further includes: forming a dielectric layer between the semiconductor epitaxial layer and the first dielectric layer, and on the sidewalls and bottom of the trench; wherein the formed dielectric layer also includes forming a second dielectric layer, and the second dielectric layer is located between the semiconductor epitaxial layer and the first dielectric layer, and on the sidewalls and bottom of the trench; etching the dielectric layer includes: etching the first dielectric layer and the second dielectric layer to form a first opening that penetrates the first dielectric layer and the second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG1 is a partial structural cross-sectional view of a vertical cavity surface emitting laser provided in the related art;

[0019] FIG2 is a partial structural cross-sectional view of another vertical cavity surface emitting laser provided in the related art;

[0020] FIG3 is a diagram showing the positional relationship between a groove and a light-emitting hole in a high-power vertical cavity surface emitting laser provided in an embodiment of the present application;

[0021] FIG4 is a diagram showing the positional relationship between the grooves and the light-emitting holes in another high-power vertical cavity surface emitting laser provided in an embodiment of the present application;

[0022] FIG5 is a schematic cross-sectional view of the structure along section line AA1 in FIG3 or along section line BB1 ​​in FIG4;

[0023] FIG6 is another cross-sectional structural schematic diagram along the section line AA1 in FIG3 or along the section line BB1 ​​in FIG4;

[0024] FIG7 is a schematic diagram of another cross-sectional structure along the section line AA1 in FIG3 or along the section line BB1 ​​in FIG4;

[0025] FIG8 is a flow chart of a method for preparing a high-power vertical cavity surface emitting laser provided in an embodiment of the present application;

[0026] FIG9 is a flow chart of another method for preparing a high-power vertical cavity surface emitting laser provided in an embodiment of the present application;

[0027] FIG10 is a cross-sectional view of the structure of a method for preparing a high-power vertical cavity surface emitting laser in step S210 provided in an embodiment of the present application;

[0028] FIG11 is a cross-sectional view of the structure of a method for preparing a high-power vertical cavity surface emitting laser in step S230 provided in an embodiment of the present application;

[0029] FIG12 is a cross-sectional view of the structure of a method for preparing a high-power vertical cavity surface emitting laser in step S230 provided in an embodiment of the present application;

[0030] FIG13 is a cross-sectional view of a high-power vertical cavity surface emitting laser manufacturing method according to an embodiment of the present application at step S240;

[0031] FIG14 is a cross-sectional view of the structure of a method for preparing a high-power vertical cavity surface emitting laser in step S250 provided in an embodiment of the present application;

[0032] FIG15 is a cross-sectional view of a high-power vertical cavity surface emitting laser manufacturing method according to an embodiment of the present application at step S260;

[0033] FIG16 is a cross-sectional view of the structure of multiple steps in step S270 to step S280 of a method for preparing a high-power vertical cavity surface emitting laser provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The following will describe the technical solutions in the embodiments of this application in conjunction with the drawings in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] As mentioned in the background, as the spacing between light-emitting holes decreases or the etching depth increases, high-aspect-ratio trenches are becoming increasingly common. Figure 1 is a partial structural cross-sectional view of a vertical-cavity surface-emitting laser (VCSEL) provided in the related art. Referring to Figure 1, the VCSEL comprises a substrate 1 and a semiconductor epitaxial layer 2 located on one side of the substrate. The semiconductor epitaxial layer 2 comprises a lower Bragg reflector layer, an upper Bragg reflector layer, and at least one active layer located between the lower and upper Bragg reflector layers. The semiconductor epitaxial layer 2 is etched to form trenches therein, thereby defining a light-emitting mesa structure. When forming the upper electrode 5 electrically connected to the light-emitting mesa structure, metal material is deposited in the trench. However, due to the uniformity of the sputtered seed metal and the step coverage of the electroplated Au, the metal deposited in the trench by the upper electrode 5 has holes 4. When the upper electrode 5 is energized, the metal in the trench becomes charged and generates heat accordingly. The thermal conductivity of the metal material is higher than that of the air in the holes 4. This difference in thermal expansion coefficient may reduce the reliability of the laser. At the same time, because the metal in the trench has opposite polarity to the lower Bragg reflector and is relatively close to it, a large capacitance is formed between the metal in the trench and the lower Bragg reflector; this large capacitance can affect the performance of lasers operating in short pulses. Furthermore, due to the characteristics of the manufacturing process, some metal is deposited in the trench when the upper electrode 5 is prepared. As a result, the height of the upper electrode 5 above the trench is less than that of the upper electrode 5 in the non-trench layer, affecting the flatness of the device and easily causing misjudgment in subsequent visual inspections, affecting the yield rate.

[0037] Figure 2 is a partial cross-sectional view of another VCSEL structure provided in related art. Referring to Figure 2 , related art also uses organic polymers, such as benzocyclobutene (BCB) and polyimide, to fill the trenches to form the organic filler layer 7. However, the raw material costs are high, and the reliability of organic polymers can be challenged in high-temperature and high-humidity environments, thus affecting device reliability.

[0038] An embodiment of the present application provides a high-power vertical cavity surface emitting laser. Figure 3 is a positional relationship diagram of a groove and a light-emitting hole in a high-power vertical cavity surface emitting laser provided in an embodiment of the present application. Figure 4 is a positional relationship diagram of a groove and a light-emitting hole in another high-power vertical cavity surface emitting laser provided in an embodiment of the present application. Figure 5 is a schematic diagram of a cross-sectional structure along section line AA1 in Figure 3 or along section line BB1 ​​in Figure 4. Figure 6 is a schematic diagram of another cross-sectional structure along section line AA1 in Figure 3 or along section line BB1 ​​in Figure 4. Figure 7 is a schematic diagram of another cross-sectional structure along section line AA1 in Figure 3 or along section line BB1 ​​in Figure 4. 3 to 7 , a high-power vertical cavity surface emitting laser includes: a substrate 10; a semiconductor epitaxial layer 20, located on one side of the substrate 10; the semiconductor epitaxial layer 20 includes at least one first region E2 and a second region E1 arranged around the first region E2; the first region E2 has at least one light-emitting structure 24; the second region E1 has a groove 201; a filling layer 30 filled in the groove; a dielectric layer 40, including a first dielectric layer 41, located on a side of the semiconductor epitaxial layer 20 away from the substrate 10; wherein the dielectric layer 40 includes a first opening 401; the vertical projection of the first opening 401 on the semiconductor epitaxial layer 20 is located in the first region E2; an upper electrode 50, located on a side of the first dielectric layer 41 away from the substrate 10; the upper electrode 50 is electrically connected to the light-emitting structure 24 through the first opening, and the upper electrode 50 located in the second region E1 is separated from the filling layer 30 by the first dielectric layer 41.

[0039] The substrate 10 can be any material suitable for forming a vertical cavity surface emitting laser, such as gallium arsenide (GaAs). The substrate 10 can be an N-type doped semiconductor substrate or a P-type doped semiconductor substrate. In some embodiments, if the N-ohmic metal and the P-ohmic metal are formed on the same side of the substrate 10, the substrate 10 does not need to act as a conductor to conduct the N-ohmic metal and the P-ohmic metal, and the substrate 10 can be a semi-insulating substrate 10. In other embodiments, if the N-ohmic metal and the P-ohmic metal are formed on opposite sides of the substrate 10, the substrate 10 needs to act as a conductor to conduct the N-ohmic metal and the P-ohmic metal, and the substrate 10 is a conductive substrate 10. In Figures 5 to 7, in this embodiment, the substrate 10 is an N-type doped semiconductor substrate, the P-ohmic metal 60 is located on the side of the semiconductor epitaxial layer 20 away from the substrate, and the upper electrode 50 contacts the P-ohmic metal 60 through the first opening 401, thereby achieving electrical connection with the light-emitting structure 24.

[0040] The semiconductor epitaxial layer 20 may include a lower Bragg reflector 21, an upper Bragg reflector 23, and at least one active layer 22 located between the lower Bragg reflector 21 and the upper Bragg reflector 23. The lower Bragg reflector 21 is closer to the substrate 10. The lower Bragg reflector 21, the upper Bragg reflector 23, and the active layer 22 may be formed by chemical vapor deposition. The lower Bragg reflector 21 may be formed by stacking two material layers with different refractive indices: an aluminum gallium arsenide layer and a gallium arsenide layer, or by stacking two material layers with different refractive indices: an aluminum gallium arsenide layer with a high aluminum content and an aluminum gallium arsenide layer with a low aluminum content. The active layer 22 is composed of a stacked arrangement of GaAs and AlGaAs, or InGaAs and AlGaAs materials, and is used to convert electrical energy into light energy. When the active layer 22 comprises multiple layers, tunnel junctions are provided between adjacent active layers 22, connecting them in series. The upper Bragg reflector 23 can be formed by stacking two material layers with different refractive indices: an AlGaAs layer and a GaAs layer, or by stacking two material layers with different refractive indices: an AlGaAs layer with a high aluminum content and an AlGaAs layer with a low aluminum content. The upper Bragg reflector 23 and the lower Bragg reflector 21 are used to enhance the reflection of light generated by the active layer 22 located between them. The light is then emitted from the surface of the upper Bragg reflector 23 to form laser light.

[0041] In some embodiments, the lower Bragg reflector 21 and the upper Bragg reflector 23 may also be formed of other materials. The lower Bragg reflector 21 and the upper Bragg reflector 23 include a series of alternating layers of materials with different refractive indices, wherein the effective optical thickness of each alternating layer (the layer thickness multiplied by the layer refractive index) is an odd integer multiple of one-quarter the operating wavelength of the vertical cavity surface emitting laser, that is, the effective optical thickness of each alternating layer is one-quarter the odd integer multiple of the operating wavelength of the vertical cavity surface emitting laser.

[0042] The semiconductor epitaxial layer 20 includes at least one first region E2 and a second region E1 surrounding the first region E2. The semiconductor epitaxial layer 20 in the first region E2 is used to form a light-emitting structure 24. The semiconductor epitaxial layer 20 in the second region E1 is provided with a trench 201. It can be understood that the trench 201 is formed by dry etching the semiconductor epitaxial structure in the second region E1, thereby forming the light-emitting structure in the first region E2. After the light-emitting structure 24 is formed, an oxidation restriction layer 202 is formed within the light-emitting structure 24. The oxidation restriction layer 202 has an opening that defines a light output aperture Q1 for the light-emitting structure 24. In this embodiment, the oxidation restriction layer 202 within each light-emitting structure 24 is a circular ring structure. If the light-emitting structure 24 is rectangular in top view, the oxidation restriction layer 202 may also be a rectangular ring. Optionally, the semiconductor epitaxial layer 20 in the first region E2 may be used to form a single light-emitting structure 24 or an array of light-emitting structures. A filling layer 30 is provided in the groove 201. The filling layer 30 fills the groove 201, so that the side of the semiconductor epitaxial layer 20 away from the substrate 10 has a relatively flat surface. On this basis, the upper electrode 50 is formed on the side of the first dielectric layer 41 away from the substrate 10, and the surfaces of the first dielectric layer 41 and the upper electrode 50 are flatter. This can improve the problem of poor device flatness caused by the reduction of the spacing between the light-emitting holes and the deepening of the etching depth of the groove 201 in the VCSEL with a high aspect ratio trench. The first dielectric layer 41 has a first opening 401 in the first region E2, so that the upper electrode 50 can be electrically connected to the light-emitting structure 24 located in the first region E2 through the first opening 401, while injecting current into the light-emitting structure 24 and isolating it from the filling layer 30 located in the second region E1. Therefore, the material of the filling layer 30 can be a dielectric material or a material with high thermal conductivity such as a metal material. The material of the filling layer 30 is a material with high temperature resistance and low cost, so as to achieve flatness while ensuring the reliability of the laser at high temperatures.

[0043] The first dielectric layer 41 separates the upper electrode 50 from the filling layer 30 in the trench 201. This prevents the metal in the trench 201 from becoming electrically charged and generating heat when the filling layer 30 in the trench 201 is made of a metal material. This improves the problem of the formation of voids 01 in the metal in the trench 201 due to poor step coverage of the metal material in the trench 201, as well as the difference in thermal conductivity and thermal expansion coefficient between the metal and the air in the void. This improves the reliability of the device. Furthermore, it prevents the formation of a large capacitance due to the opposite polarity and close proximity of the metal in the trench 201 to the lower Bragg reflector 21, thereby avoiding the impact on the performance of lasers operating in a short-pulse mode.

[0044] On the basis of the above-mentioned multiple embodiments, referring to FIG. 5 , in one embodiment of the present application, the metal material of the filling layer 30 includes Au, forming an Au filling layer 31 .

[0045] Due to the uniformity of the sputtered seed metal and the step coverage of the electroplated Au, holes 01 are formed in the metal within the groove 201. The first dielectric layer 41 separates the upper electrode 50 from the filling layer 30 located in the groove 201, preventing the metal within the groove 201 from being charged and generating heat due to contact with the upper electrode 50. This improves the problem of holes 01 being formed in the metal within the groove 201 due to poor step coverage of the metal material in the groove 201, as well as the difference in thermal conductivity and thermal expansion coefficient between the metal and the air within the hole 01, thereby improving the reliability of the device. It also prevents the metal within the groove 201 from having opposite polarity to the lower Bragg reflector 21 and being close to each other, which can form a large capacitance and affect the performance of lasers operating in short pulse modes.

[0046] Based on the above embodiments, referring to FIG6 , in another embodiment of the present application, the metal material of the filling layer 30 includes Cu, forming a Cu filling layer 32. Cu has better hole-filling performance than Au and is lower in cost.

[0047] Based on the above embodiments, referring to FIG7 , in another embodiment of the present application, the filling layer 30 is made of a dielectric material, forming a dielectric filling layer 33. The dielectric material includes nitride or oxide.

[0048] The trench 201 and the surface of the semiconductor epitaxial layer 20 are covered with a dielectric film to provide insulation. A filling layer 30 made of a nitride or oxide can be formed using techniques with good step coverage. For example, the nitride includes silicon nitride (SiN), which can be deposited using a plasma-enhanced chemical vapor deposition (PECVD) device with a tetraethyl orthosilicate (TEOS) source, or a high-density plasma chemical vapor deposition (HDPCVD) device. The oxide includes silicon dioxide (SiO2), which can be deposited using a plasma-enhanced atomic layer deposition (PE-ALD) device. Forming a nitride or oxide using techniques with good step coverage can form a filling layer 30 without voids 01, thereby preventing the voids 01 in the filling layer 30 from affecting device reliability.

[0049] When the material filled in the trench 201 is a metal material, the dielectric layer 40 of the high-power vertical cavity surface emitting laser further includes a second dielectric layer 42; the second dielectric layer 42 is located between the semiconductor epitaxial layer 20 and the first dielectric layer 41, as well as on the sidewalls and bottom of the trench 201. The dielectric layer 40 includes a first opening 401, which penetrates both the first dielectric layer 41 and the second dielectric layer 42. The vertical projection of the first opening 401 on the semiconductor epitaxial layer 20 is located in the first region E2; the upper electrode 50 is electrically connected to the light-emitting structure 24 through the first opening 401. By providing the second dielectric layer 42 in the high-power vertical cavity surface emitting laser, it is possible to prevent the metal layer in the trench 201 from directly connecting to the upper Bragg reflector layer 23 and the lower Bragg reflector layer 21, thereby preventing a short circuit in the high-power vertical cavity surface emitting laser and affecting the normal light emission of the active layer 22 located between the upper Bragg reflector layer 23 and the lower Bragg reflector layer 21. When the material filled in the trench 201 is a dielectric material, a second dielectric layer 42 may be provided between the semiconductor epitaxial layer 20 and the first dielectric layer 41 , and on the sidewalls and bottom of the trench 201 , or may not be provided.

[0050] Based on the above-described multiple embodiments, in one embodiment of the present application, the difference between the distance between the surface of the filling layer 30 on the side away from the substrate 10 and the substrate 10 and the distance between the surface of the semiconductor epitaxial layer 20 on the side away from the substrate 10 and the substrate 10 is less than a preset value. Optionally, the distance between the surface of the filling layer 30 on the side away from the substrate 10 and the substrate 10 is equal to the distance between the surface of the semiconductor epitaxial layer 20 on the side away from the substrate 10 and the substrate 10, which can further improve the flatness of the laser.

[0051] Based on the above embodiments, in one embodiment of the present application, the width d of the groove is less than or equal to 4 μm; and the aspect ratio of the groove is greater than or equal to 3.

[0052] Setting the width d of the groove 201 to be less than or equal to 4 μm can reduce the spacing between the light-emitting structures 24, thereby increasing the number of light-emitting structures 24 per unit area in the high-power vertical cavity surface emitting laser and improving the light output of the high-power vertical cavity surface emitting laser. Setting the groove aspect ratio to be greater than or equal to 2 can make the groove deeper, thereby increasing the number of active layers 22 included in the light-emitting structure 24, thereby increasing the light output of a single light-emitting structure 24, and further improving the light output of the high-power vertical cavity surface emitting laser.

[0053] Based on the above embodiments, referring to FIG3 , in one embodiment of the present application, the groove 201 is annular in shape; the annular groove 201 is disposed around the light-emitting structure 24. In another embodiment of the present application, referring to FIG4 , the groove 201 is hole-shaped; multiple hole-shaped grooves 201 are disposed around the light-emitting structure 24. The shape of the groove 201 can be set according to actual needs.

[0054] Optionally, an ion implantation layer is provided on a side surface of the trench 201 close to the light emitting structure 24 , and the ion implantation layer is used to isolate the filling layer 30 from the light emitting structure 24 .

[0055] It can be understood that due to the characteristics of the preparation process of the second dielectric layer 42, the thickness of the second dielectric layer 42 on the sidewalls of the trench 201 gradually decreases in the direction from the upper electrode 50 to the lower Bragg reflector 21. When the trench 201 is deep, the thickness of the second dielectric layer 42 on the sidewalls near the bottom of the trench is too small, or even absent, increasing the risk of device short circuits. By providing an ion implantation layer on the side of the trench 201 near the light-emitting structure 24, the electrical insulation between the filling layer 30 and the light-emitting structure 24 can be further enhanced.

[0056] An embodiment of the present application also provides a method for preparing a high-power vertical cavity surface emitting laser, which is used to prepare the high-power vertical cavity surface emitting laser described in any of the above embodiments. Figure 8 is a flow chart of a method for preparing a high-power vertical cavity surface emitting laser provided in an embodiment of the present application. Referring to Figure 8, the method for preparing a high-power vertical cavity surface emitting laser includes the following steps.

[0057] S110 , providing a substrate.

[0058] S120 , forming a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer includes at least one first region and a second region arranged around the first region.

[0059] S130 , etching the semiconductor epitaxial layer in the second region to form a trench; wherein the semiconductor epitaxial layer in the first region is used to form a light-emitting structure.

[0060] S140 , forming a filling layer in the trench.

[0061] A filling layer is provided in the trench to fill the trench with the filling layer, thereby improving the problem of poor device flatness caused by the reduction of the light-emitting hole spacing and the deepening of the trench etching depth in VCSELs with high aspect ratio trenches.

[0062] S150, forming a dielectric layer on a side of the semiconductor epitaxial layer away from the substrate; wherein the dielectric layer includes a first dielectric layer.

[0063] S160 , etching the dielectric layer to form a first opening in the dielectric layer; a vertical projection of the first opening on the semiconductor epitaxial layer is located in the first region.

[0064] S170, forming an upper electrode on a side of the first dielectric layer away from the substrate; the upper electrode is electrically connected to the light-emitting structure through the first opening, and the upper electrode located in the second area is separated from the filling layer by the first dielectric layer.

[0065] The upper electrode is arranged on a side of the first dielectric layer away from the substrate, wherein the dielectric layer has a first opening in the first region, so that the upper electrode can contact the light-emitting structure located in the first region through the first opening, injecting current into the light-emitting structure while isolating from the filling layer located in the second region. By separating the upper electrode from the filling layer located in the groove by the first dielectric layer, it is possible to prevent the metal in the groove from being charged and generating heat when the filling layer in the groove is made of a metal material, thereby improving the problem of temperature cycling caused by the formation of holes in the metal in the groove due to poor step coverage of the metal material in the groove, thereby improving the reliability of the device. In addition, it can also prevent the metal in the groove from having opposite polarity to the lower Bragg reflector layer and being close to each other, thereby preventing the formation of a large capacitance, which affects the performance of the laser operating in a short pulse mode.

[0066] The method for preparing a high-power vertical cavity surface emitting laser provided in the embodiment of the present application can improve the flatness of the device by providing a filling layer in the groove. In addition, the upper electrode is separated from the filling layer located in the groove by a first dielectric layer. Compared with the related art in which part of the metal material forming the upper electrode is formed in the groove, the present application can prevent the metal in the groove from being charged and generating heat due to contact with the upper electrode, thereby improving the problem of temperature cycling caused by the formation of holes in the metal in the groove due to poor step coverage of the metal material in the groove, thereby improving the reliability of the device. It can also prevent the metal in the groove from having opposite polarity to the lower Bragg reflection layer and being close to each other, thereby preventing the formation of a large capacitance and affecting the performance of the laser using a short pulse operation mode.

[0067] Figure 9 is a flow chart of another method for preparing a high-power vertical cavity surface emitting laser provided in an embodiment of the present application; Figures 10 to 16 are structural cross-sectional views of multiple steps in steps S210 to S280 of a method for preparing a high-power vertical cavity surface emitting laser provided in an embodiment of the present application. Referring to Figures 9 to 16, the method for preparing a high-power vertical cavity surface emitting laser includes the following steps.

[0068] S210 , providing a substrate.

[0069] Referring to FIG10 , the substrate 10 can be any material suitable for forming a vertical cavity surface emitting laser, such as gallium arsenide (GaAs). The substrate 10 can be an N-type doped semiconductor substrate or a P-type doped semiconductor substrate 10. In this embodiment, the substrate 10 is an N-type doped semiconductor substrate 10. In some embodiments, the substrate 10 can be a semi-insulating substrate 10. In other embodiments, the substrate 10 can be a conductive substrate 10.

[0070] S220 , forming a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer includes at least one first region and a second region arranged around the first region.

[0071] Continuing with FIG. 10 , forming a semiconductor epitaxial layer 20 on one side of the substrate 10 includes sequentially forming a lower Bragg reflector 21, at least one active layer 22, and an upper Bragg reflector 23. Both the lower Bragg reflector 21 and the upper Bragg reflector 23 can be formed by stacking two material layers with different refractive indices: an aluminum gallium arsenide layer and a gallium arsenide layer, or by stacking two material layers with different refractive indices: an aluminum gallium arsenide layer with a high aluminum content and an aluminum gallium arsenide layer with a low aluminum content. The active layer 22 is composed of a stack of GaAs and AlGaAs, or InGaAs and AlGaAs materials, and is used to convert electrical energy into light energy. When the active layer 22 is multilayer, tunnel junctions are provided between adjacent active layers 22, interconnecting them. In some embodiments, the lower Bragg reflector 21 and the upper Bragg reflector 23 can also be formed of other materials. The lower Bragg reflector layer 21 and the upper Bragg reflector layer 23 include a series of alternating layers of materials with different refractive indices, wherein the effective optical thickness of each alternating layer (the thickness of the layer multiplied by the refractive index of the layer) is an odd integer multiple of one quarter of the operating wavelength of the vertical cavity surface emitting laser, that is, the effective optical thickness of each alternating layer is one quarter of the odd integer multiple of the operating wavelength of the vertical cavity surface emitting laser.

[0072] S230 , etching the semiconductor epitaxial layer in the second region to form a trench; wherein the semiconductor epitaxial layer in the first region is used to form a light emitting structure.

[0073] 11 , the semiconductor epitaxial layer 20 in the second region is etched by dry etching to form a trench 201 , thereby forming a light-emitting mesa structure in the first region. The bottom of the trench 201 is etched at least to the lower Bragg reflector 21 .

[0074] Referring to Figure 12 , after the light-emitting structure 24 is formed in the first region, an oxidation confinement layer 202 is formed within the light-emitting structure 24. The oxidation confinement layer 202 has an opening that defines the light-emitting aperture Q1 of the light-emitting structure 24. In this embodiment, the sidewalls of the trench are oxidized by wet oxidation of highly doped aluminum under certain temperature conditions to form the oxidation confinement layer 202 within the upper Bragg reflector 23. The oxidation confinement layer 202 on both sides of the trench 201 has equal length. The aluminum oxide formed after oxidation has high resistance. The openings of the oxidation confinement layer 202 remain the highly doped aluminum gallium arsenide material. When current enters the light-emitting mesa structure, it flows through the openings in the oxidation confinement layer 202 to the active layer 22. In this embodiment, the oxidation confinement layer 202 within each light-emitting structure 24 is a circular ring structure. If the light-emitting structure 24 is rectangular in top view, the oxidation confinement layer 202 can also be a rectangular ring.

[0075] S240 , forming a second dielectric layer on a side of the semiconductor epitaxial layer away from the substrate and on the sidewalls and bottom of the trench.

[0076] 13 , before forming the second dielectric layer 42 , the process further includes forming an ohmic layer 60 on the surface of the semiconductor epitaxial layer 20 in the first region.

[0077] S250 , forming a filling layer in the trench.

[0078] Referring to FIG14 , the filling layer 30 formed in the trench can be a dielectric layer or a material with high thermal conductivity, such as a metal material. The metal material can be, for example, Cu or Au. FIG14 exemplarily illustrates the filling layer 30 as a Cu filling layer 32. When Au is used as the filling layer material, the Cu filling layer 32 in FIG14 is replaced with an Au filling layer.

[0079] S260, etching the filling layer at the edge of the hole of the trench so that the difference between the distance between the surface of the filling layer away from the substrate and the substrate and the distance between the surface of the second dielectric layer away from the substrate and the substrate is less than a preset value.

[0080] Referring to Figure 15 , the filling layer 30 at the edge of the trench hole is etched so that the difference between the distance between the surface of the filling layer 30 facing away from the substrate 10 and the substrate 10 and the distance between the surface of the second dielectric layer 42 facing away from the substrate 10 and the substrate 10 is less than a predetermined value. To increase device density, after electroplating the metal material, etching is performed to remove the Au / Cu that extends beyond the trench, minimizing the need to retain only the hole-filling portion to avoid affecting the spacing of other structures. If the filling layer 30 is a dielectric material, the dielectric material that extends beyond the trench can also be etched away, minimizing the need to retain only the hole-filling portion.

[0081] S270 , forming a first dielectric layer on a side of the second dielectric layer away from the substrate.

[0082] 16 , a first dielectric layer 41 is formed on a side of the second dielectric layer 42 away from the substrate 10. The material of the second dielectric layer 42 may be the same as or different from that of the first dielectric layer 41. Furthermore, when the filling layer 30 is made of a dielectric material, the materials of the three layers may be the same or different.

[0083] S280 , etching the first dielectric layer and the second dielectric layer to form a first opening penetrating the first dielectric layer and the second dielectric layer.

[0084] A vertical projection of the first opening 401 in the semiconductor epitaxial layer is located in the first region.

[0085] S290, forming an upper electrode on a side of the first dielectric layer away from the substrate; the upper electrode is electrically connected to the light-emitting structure through the first opening, and the upper electrode in the second region is separated from the filling layer by the first dielectric layer. (See FIG6 )

[0086] When the material of the filling layer 30 includes a metal material, forming the filling layer 30 in the trench includes: depositing a seed metal and then electroplating Cu or Au to form the filling layer 30. When the material of the filling layer 30 includes a dielectric material, forming the filling layer 30 in the trench includes: depositing a nitride or oxide in the trench to form the filling layer 30. If gold electroplating is used for hole filling, the seed metal can be titanium tungsten (TiW) deposited using a physical vapor deposition (PVD) process. If the filling metal is Cu, an ALD or PVD process can be used to deposit a seed layer metal, such as titanium nitride (TiN) or Ru.

[0087] When the trench is filled with a metal material, a second dielectric layer 42 is required in the high-power vertical cavity surface emitting laser to prevent the metal layer in the trench from directly connecting the upper Bragg reflector layer 23 and the lower Bragg reflector layer 21, thereby causing a short circuit in the high-power vertical cavity surface emitting laser and affecting the normal light emission of the active layer 22. When the trench is filled with a dielectric material, the second dielectric layer 42 may be provided between the semiconductor epitaxial layer 20 and the first dielectric layer 41, as well as on the sidewalls and bottom of the trench, or it may not be provided.

[0088] The method for preparing the high-power vertical cavity surface emitting laser described in any of the above embodiments is part of the device processing flow, which mainly reflects the technical solution of the present application. Other procedures or processes required to manufacture the device known in the art are omitted.

Claims

1. A high-power vertical cavity surface emitting laser, comprising: A substrate; A semiconductor epitaxial layer located on one side of the substrate; the semiconductor epitaxial layer includes at least one first region and a second region disposed around the first region; The first region has at least one light-emitting structure; the second region has trenches; A filling layer filled in the trenches; A dielectric layer, the dielectric layer includes a first dielectric layer located on the side of the semiconductor epitaxial layer away from the substrate; wherein, a first opening is included in the dielectric layer; a vertical projection of the first opening on the semiconductor epitaxial layer is located in the first region; An upper electrode located on the side of the first dielectric layer away from the substrate; the upper electrode is electrically connected to the light-emitting structure through the first opening, and the upper electrode located in the second region is separated from the filling layer by the first dielectric layer.

2. The high-power vertical cavity surface emitting laser according to claim 1, wherein The difference between the distance from the surface of the filling layer away from the substrate to the substrate and the distance from the surface of the semiconductor epitaxial layer away from the substrate to the substrate is less than a preset value.

3. The high-power vertical cavity surface emitting laser according to claim 1, wherein, The material of the filling layer includes a metal material or a dielectric material.

4. The high-power vertical cavity surface emitting laser according to claim 3, wherein, The metal material includes Au or Cu; the dielectric material includes a nitride or an oxide.

5. The high-power vertical cavity surface emitting laser according to claim 1, wherein, The width of the trench is less than or equal to 4um; The depth-to-width ratio of the trench is greater than or equal to 2.

6. The high-power vertical cavity surface emitting laser according to claim 1, wherein, The shape of the trench is annular; the annular trench is disposed around the light-emitting structure; Or, the shape of the trench is hole-shaped; A plurality of hole-shaped trenches are disposed around the light-emitting structure.

7. The high-power vertical cavity surface emitting laser according to claim 3, wherein, The dielectric layer further includes: A second dielectric layer, the second dielectric layer is located between the semiconductor epitaxial layer and the first dielectric layer, and on the sidewalls and bottom of the trench; Wherein, the dielectric layer includes a first opening, and the first opening penetrates through the first dielectric layer and the Second dielectric layer; the upper electrode is electrically connected to the light-emitting structure through the first opening.

8. The high-power vertical cavity surface emitting laser according to claim 1, wherein, The semiconductor epitaxial layer includes a lower Bragg reflector, an upper Bragg reflector, and at least one active layer located between the lower Bragg reflector and the upper Bragg reflector; wherein, the lower Bragg reflector is closer to the substrate; The active layer located in the first region includes at least one oxidation confinement layer for carrier confinement.

9. A method for manufacturing a high-power vertical cavity surface emitting laser, comprising: Providing a substrate; Forming a semiconductor epitaxial layer on one side of the substrate; The semiconductor epitaxial layer includes at least one first region and a second region disposed around the first region; Etching the semiconductor epitaxial layer in the second region to form trenches; wherein, the semiconductor epitaxial layer located in the first region is used to form a light-emitting structure; Forming a filling layer in the trenches; Forming a dielectric layer on the side of the semiconductor epitaxial layer away from the substrate; wherein, the dielectric layer includes a first dielectric layer; Etch the dielectric layer to form a first opening in the dielectric layer; a vertical projection of the first opening on the semiconductor epitaxial layer is located in the first region; Form an upper electrode on a side of the first dielectric layer away from the substrate; the upper electrode is electrically connected to the light-emitting structure through the first opening, and the first dielectric layer separates the upper electrode located in the second region from the filling layer.

10. The manufacturing method of the high-power vertical cavity surface emitting laser according to claim 9, wherein, The material of the filling layer includes a metal material; forming a filling layer in the trench includes: After depositing a seed metal, electroplating Cu or Au to form the filling layer; Alternatively, the material of the filling layer includes a dielectric material; forming a filling layer in the trench includes: Depositing a nitride or an oxide in the trench to form the filling layer.

11. The method for manufacturing a high-power vertical cavity surface emitting laser according to claim 9, further comprising, before forming the filling layer in the trench: Form a dielectric layer between the semiconductor epitaxial layer and the first dielectric layer and on sidewalls and a bottom of the trench; wherein, the formed dielectric layer further includes forming a second dielectric layer, and the second dielectric layer is located between the semiconductor epitaxial layer and the first dielectric layer and on sidewalls and a bottom of the trench; Etching the dielectric layer includes: Etching the first dielectric layer and the second dielectric layer to form a first opening penetrating through the first dielectric layer and the second dielectric layer.

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