Memory cell, memory, chip and memory cell manufacturing method

Abstract

The present application relates to a memory cell, a memory, a chip and a memory cell manufacturing method. The memory cell (200) comprises: a tunneling oxide layer (210), which is formed by a first oxide layer (120) and is arranged on a second silicon layer (130); a floating gate layer (220), which is formed by a first silicon layer (110) and is arranged on the tunneling oxide layer (210); an intermediate oxide layer (230), which is arranged on the floating gate layer (220); a control gate layer (240), which is arranged on the intermediate oxide layer (230); a control electrode (250), which is arranged on the control gate layer (240); and a source electrode (260) and a drain electrode (270), which are arranged on the second silicon layer (130) and are respectively arranged on two sides of the control electrode (250). In the present application, a channel operation area of a memory cell is in a second silicon layer, the second silicon layer of a DSOI wafer is not required to be fully depleted and the thickness of the second silicon layer can be far greater than that of a first silicon layer, so that a large current required by a write operation based on a hot carrier effect can be provided, so as to complete electron writing and erasing.

Description

Memory unit, memory, chip and memory unit manufacturing method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 26, 2023, with application number 2023118190315, and application name "Memory unit, memory, chip and memory unit manufacturing method", all of which are incorporated by reference in this application. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a storage unit, a memory, a chip, and a method for manufacturing a storage unit. Background Art

[0003] DSOI (Double Silicon On Insulator) wafers are formed by adding oxide and silicon layers to SOI (Silicon On Insulator) wafers. The DSOI structure combines the SOI structure's excellent single-event effect resistance and low leakage advantages with the ability to utilize the middle silicon layer to extend the back-gate terminal, enabling modulation by applying different back-bias voltages to different devices. However, in the DSOI structure, the top silicon layer must be relatively thin to achieve sufficient depletion, facilitating modulation of the back-bias voltage of the middle silicon layer. However, since the device channel is typically located in the top silicon layer, this structure cannot be applied to devices requiring high currents.

[0004] Summary of the Invention

[0005] Based on this, it is necessary to provide a storage unit, a memory, a chip and a storage unit manufacturing method that can be manufactured on a DSOI wafer to address the above technical problems.

[0006] In a first aspect, the present application provides a memory cell, wherein the memory cell is made of a DSOI wafer, wherein the DSOI wafer is stacked from top to bottom with: a first silicon layer, a first oxide layer, a second silicon layer, a second oxide layer, and a substrate;

[0007] The memory cell includes: a tunneling oxide layer, which is formed by the first oxide layer and is arranged on the second silicon layer; a floating gate layer, which is formed by the first silicon layer and is arranged on the tunneling oxide layer; an intermediate oxide layer, which is arranged on the floating gate layer; a control gate layer, which is arranged on the intermediate oxide layer; a control electrode, which is arranged on the control gate layer; a source electrode and a drain electrode, which are arranged on the second silicon layer, and the source electrode and the drain electrode are respectively arranged on both sides of the control electrode.

[0008] In one embodiment, the memory cell further includes: a selection gate layer, the selection gate layer is disposed on the second silicon layer, and the selection gate layer is disposed between the source electrode and the drain electrode.

[0009] In one embodiment, the memory cell further includes a selection electrode, wherein the selection electrode is disposed on the selection gate layer.

[0010] In one embodiment, the thickness of the second silicon layer is greater than 150 nanometers.

[0011] In one embodiment, the thickness of the tunnel oxide layer is 10 nanometers, and the thickness of the floating gate layer is 40 nanometers.

[0012] In one embodiment, the materials of the substrate, the first silicon layer, and the second silicon layer are all single crystal silicon, and the materials of the first oxide layer and the second oxide layer are both silicon dioxide.

[0013] In a second aspect, the present application further proposes a memory comprising the storage unit described in the embodiment of the first aspect above.

[0014] In a third aspect, the present application further proposes a chip comprising the memory cell described in the embodiment of the first aspect, and a transistor, wherein the transistor is arranged on a DSOI wafer.

[0015] In a fourth aspect, the present application also proposes a method for manufacturing a memory cell, which is used to manufacture the memory cell described in the embodiment of the first aspect, the method comprising: providing a DSOI wafer; wherein the DSOI wafer is stacked from top to bottom with: a first silicon layer, a first oxide layer, a second silicon layer, a second oxide layer and a substrate; performing photolithography and etching on the DSOI wafer to obtain a tunneling oxide layer and a floating gate layer, respectively; wherein the tunneling oxide layer is formed by the first oxide layer, and the floating gate layer is formed by the first silicon layer; forming an intermediate oxide layer on the floating gate layer; forming a control gate layer on the intermediate oxide layer; forming a control electrode on the control gate layer and forming a source electrode and a drain electrode on the second silicon layer; wherein the source electrode and the drain electrode are respectively arranged on both sides of the control electrode.

[0016] In one embodiment, the method further includes: forming a selection gate layer on the second silicon layer after forming an intermediate oxide layer on the floating gate layer; wherein the selection gate layer is arranged between the source electrode and the drain electrode; and forming a selection electrode on the selection gate layer.

[0017] The above-mentioned memory cell, memory, chip and memory cell manufacturing method form the tunneling oxide layer of the memory cell from the first oxide layer of the DSOI wafer and form the floating gate layer of the memory cell from the first silicon layer of the DSOI wafer. At this time, the channel working area of ​​the memory cell is in the second silicon layer. Since the second silicon layer of the DSOI wafer does not need to be completely depleted, its thickness can be much greater than the first silicon layer, which can provide the large current required for the hot carrier effect write operation, thereby completing the writing and erasing of electrons. Since the memory cell of the present application directly utilizes the structure of the DSOI wafer itself, the process is simpler and the cost is lower when manufacturing the memory cell. The memory cell of the present application can be directly integrated on the DSOI wafer, and has the advantages of small size and high reliability compared to external memory or back-end integrated memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] FIG1 is a schematic structural diagram of a DSOI wafer in one embodiment;

[0020] FIG2 is a schematic structural diagram of a storage unit in one embodiment;

[0021] FIG3 is a schematic structural diagram of a storage unit in another embodiment;

[0022] FIG4 is a schematic diagram of the structure of a chip in one embodiment;

[0023] FIG5 is a schematic structural diagram of a chip in another embodiment;

[0024] FIG6 is a schematic flow chart of a method for manufacturing a memory cell according to an embodiment;

[0025] FIG7 is a schematic flow chart of a method for manufacturing a memory cell according to another embodiment;

[0026] Description of reference numerals:

[0027] DSOI wafer 100, first silicon layer 110, first oxide layer 120, second silicon layer 130, second oxide layer 140, substrate 150, memory cell 200, tunneling oxide layer 210, floating gate layer 220, intermediate oxide layer 230, control gate layer 240, control electrode 250, source electrode 260, drain electrode 270, select gate layer 280, select electrode 290, transistor 300. DETAILED DESCRIPTION

[0028] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0030] It will be understood that the terms "first," "second," etc. used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.

[0031] Spatially relative terms such as "above", "below", etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "below" or "beneath" or "below" the other elements will be oriented as "above" the other elements or features. Therefore, the exemplary terms "above" and "below" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0032] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0033] As shown in Figure 1, the memory cell of the embodiment of the present application is made of a DSOI wafer 100, which is stacked from top to bottom with: a first silicon layer 110, a first oxide layer 120, a second silicon layer 130, a second oxide layer 140 and a substrate 150. In the DSOI wafer 100 structure, in addition to the top first silicon layer 110 and the second oxide layer 140 on the substrate 150, a silicon layer and an oxide layer are added on the second oxide layer 140, namely the second silicon layer 130 and the first oxide layer 120. This structure provides two insulating layers and is therefore called "double-sided silicon on insulator". The advantage of the DSOI wafer 100 structure is that it combines the advantages of the SOI structure and the traditional bulk silicon process, such as full dielectric isolation technology, which can eliminate the latch-up effect and has the advantages of small parasitic capacitance, high speed, low power consumption, and high integration. Secondly, the DSOI wafer 100 structure provides more flexibility by adding an insulating layer and a silicon layer. For example, the back gate terminal can be extended through the middle silicon layer, and different back-bias voltages can be applied to different devices to improve device performance and reliability. Furthermore, the DSOI wafer 100 structure offers significant improvements in radiation resistance, circuit suppression, and chip area savings, offering broad application prospects.

[0034] However, the DSOI wafer 100 structure has a drawback: the top silicon layer, or first silicon layer 110, is relatively thin. This thinness allows for sufficient depletion to facilitate back-bias voltage modulation of the middle silicon layer. However, because the device channel is located in the top silicon layer, the application of high-current devices (such as flash memory) on DSOI wafer 100 is hampered.

[0035] Based on the above reasons, the present application provides a memory unit, a memory, a chip and a memory unit manufacturing method, which can manufacture a memory unit 200 on a DSOI wafer 100, thereby improving the application scope of the DSOI wafer 100.

[0036] In one embodiment, as shown in Figure 2, a memory cell 200 is provided, including: a tunneling oxide layer 210, a floating gate layer 220, an intermediate oxide layer 230, a control gate layer 240, a control electrode 250, a source electrode 260 and a drain electrode 270. The tunneling oxide layer 210 is formed by the first oxide layer 120 and is disposed on the second silicon layer 130. The floating gate layer 220 is formed by the first silicon layer 110 and is disposed on the tunneling oxide layer 210. The intermediate oxide layer 230 is disposed on the floating gate layer 220. The control gate layer 240 is disposed on the intermediate oxide layer 230. The control electrode 250 is disposed on the control gate layer 240. The source electrode 260 and the drain electrode 270 are disposed on the second silicon layer 130. The source electrode 260 and the drain electrode 270 are respectively disposed on both sides of the control electrode 250.

[0037] In one embodiment, the tunneling oxide layer 210 of the memory cell 200 of the present invention is formed from the first oxide layer 120 of the DSOI wafer 100, and the floating gate layer 220 of the memory cell 200 is formed from the first silicon layer 110 of the DSOI wafer 100. Neither layer needs to be fabricated separately, and the second silicon layer 130 of the DSOI wafer 100 serves as the channel active region of the memory cell 200. Because the second silicon layer 130 does not need to be fully depleted, its thickness can be greater than that of the first silicon layer 110. In one embodiment, the thickness of the second silicon layer 130 is greater than 150 nanometers, while the thickness of the first silicon layer 110 is approximately 40 nanometers. The much greater thickness of the second silicon layer 130 than the first silicon layer 110 can provide the high current required for hot carrier effect write operations, thereby achieving performance similar to that of bulk silicon flash memory devices.

[0038] In one embodiment, the materials of substrate 150, first silicon layer 110, and second silicon layer 130 are all single-crystal silicon, and the materials of first oxide layer 120 and second oxide layer 140 are both silicon dioxide. Correspondingly, the material of tunnel oxide layer 210 formed by first oxide layer 120 is also silicon dioxide, and the material of floating gate layer 220 formed by first silicon layer 110 is also single-crystal silicon. In some other embodiments, the material of floating gate layer 220 may be polycrystalline silicon, and the material of tunnel oxide layer 210 may be silicon nitride, etc. The material of intermediate oxide layer 230 may be silicon dioxide or silicon nitride, etc. The material of control gate layer 240 may be undoped polycrystalline silicon, doped polycrystalline silicon, metal nanocrystals, or other suitable conductive metal materials, which generally have high conductivity and corrosion resistance to ensure the stability and reliability of the flash memory device. The control electrode 250, the source electrode 260 and the drain electrode 270 are leads, which are usually made of metal, such as copper, aluminum, gold, etc. These metal leads have good conductivity and mechanical strength to ensure the stability and reliability of the memory cell 200 under normal working conditions.

[0039] When the memory cell 200 of the embodiment of the present application performs a write operation, a positive voltage is applied to the control gate layer 240 through the control electrode 250, which draws electrons (negatively charged) into the floating gate layer 220. Since the intermediate oxide layer 230 and the tunnel oxide layer 210 above and below the floating gate layer 220 are not conductive, these electrons are trapped in the floating gate layer 220 and cannot escape. In this way, regardless of whether the control gate layer 240 is loaded with voltage, this state will be maintained, so the memory cell 200 can save data after power failure. When the memory cell 200 performs an erase operation, a positive voltage is applied to the source electrode 260. The tunnel effect between the floating gate layer 220 and the drain electrode 270 is used to attract the electrons injected into the floating gate layer 220 to the source electrode, thereby emptying the electrons in the floating gate layer 220.

[0040] In one embodiment, as shown in FIG3 , the memory cell 200 further includes a select gate layer 280 disposed on the second silicon layer 130 and between the source electrode 260 and the drain electrode 270. In one embodiment, by disposing the select gate layer 280 on the second silicon layer 130, when a voltage is applied to the select gate layer 280, the channel active region of the memory cell 200 can be turned off, thereby selecting the memory cell 200.

[0041] In one embodiment, as shown in FIG3 , the memory cell 200 further includes a selection electrode 290 disposed on the selection gate layer 280. In one embodiment, the selection electrode 290 is a lead, which is typically made of a metal such as copper, aluminum, or gold. These metal leads have good electrical conductivity and mechanical strength to ensure the stability and reliability of the memory cell 200 under normal operating conditions.

[0042] In one embodiment, the thickness of the tunneling oxide layer 210 is 10 nanometers, and the thickness of the floating gate layer 220 is 40 nanometers. In one embodiment, the thickness of the tunneling oxide layer 210 and the floating gate layer 220 is determined by the structure of the DSOI wafer 100. In this embodiment, the thickness of the first oxide layer 120 is 10 nanometers, and the thickness of the first silicon layer 110 is 40 nanometers. In some other embodiments, the thickness of the tunneling oxide layer 210 and the floating gate layer 220 can also be set to other thicknesses.

[0043] In one embodiment, the present application also proposes a memory, which includes the memory cell 200 in the above embodiment. It is understandable that a plurality of memory cells 200 are arranged in the memory, and through other circuit structures provided in the memory, read and write operations on the memory cell 200 can be completed, thereby completing data access. The memory cell 200 in the above memory is formed by forming the tunneling oxide layer 210 of the memory cell 200 from the first oxide layer 120 of the DSOI wafer 100, and forming the floating gate layer 220 of the memory cell 200 from the first silicon layer 110 of the DSOI wafer 100. At this time, the channel active area of ​​the memory cell 200 is in the second silicon layer 130. Since the second silicon layer 130 of the DSOI wafer 100 does not need to be completely depleted, its thickness can be much greater than the first silicon layer 110, which can provide the large current required for the hot carrier effect write operation, thereby completing the writing and erasing of electrons.

[0044] In one embodiment, the present application also proposes a chip, as shown in Figure 4, comprising the memory cell 200 and the transistor 300 in the above embodiment, wherein the transistor 300 is arranged on the DSOI wafer 100. Specifically, the memory cell 200 and the transistor 300 in the embodiment of the present application are both arranged on the DSOI wafer 100, and the transistor 300 is an ordinary field effect transistor. In some other embodiments, as shown in Figure 5, the transistor 300 may also be a back-gate modulatable transistor 300. The multiple transistors 300 in the chip together constitute a logic circuit. Since the chip of the present application integrates the memory cell 200 and the transistor 300 on the DSOI wafer 100, it has the advantages of small size and high reliability compared to external memory or back-end integrated memory.

[0045] In one embodiment, the present application further proposes a memory cell manufacturing method for manufacturing the memory cell 200 in the above embodiment. As shown in FIG6 , the memory cell manufacturing method includes:

[0046] Step S410: providing a DSOI wafer.

[0047] In one embodiment, the DSOI wafer 100 is stacked from top to bottom with: a first silicon layer 110, a first oxide layer 120, a second silicon layer 130, a second oxide layer 140, and a substrate 150. In some embodiments, the substrate 150, the first silicon layer 110, and the second silicon layer 130 are all made of single crystal silicon, the first oxide layer 120 and the second oxide layer 140 are both made of silicon dioxide, the second silicon layer 130 is greater than 150 nanometers thick, the first oxide layer 120 is 10 nanometers thick, and the first silicon layer 110 is 40 nanometers thick.

[0048] Step S420 , performing photolithography and etching on the DSOI wafer to obtain a tunneling oxide layer and a floating gate layer respectively.

[0049] In one embodiment, when performing photolithography on the DSOI wafer 100, a layer of photoresist is first coated on the surface of the first silicon layer 110. Then, light waves are passed through a photomask to illuminate the photoresist to selectively expose the photoresist. A developer is then used to dissolve the illuminated (or unilluminated) areas, transferring the pattern on the photomask to the photoresist. The DSOI wafer 100 is then etched. During the etching process, the first silicon layer 110 not covered by the photoresist is first etched away, and then the first oxide layer 120 not covering the first silicon layer 110 is etched, thereby obtaining the tunnel oxide layer 210 and floating gate layer 220 of the memory cell 200. The tunnel oxide layer 210 is formed by the first oxide layer 120, and the floating gate layer 220 is formed by the first silicon layer 110.

[0050] Step S430: forming an intermediate oxide layer on the floating gate layer.

[0051] In one embodiment, after the floating gate layer 220 is formed, an intermediate oxide layer 230 can be formed on the floating gate layer 220. The intermediate oxide layer 230 can be formed by deposition, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other techniques; or by thermal oxidation, where oxygen is introduced into the surface of the floating gate layer 220 to cause an oxidation reaction, thereby forming the intermediate oxide layer 230. The intermediate oxide layer 230 can be made of silicon dioxide or silicon nitride, for example.

[0052] Step S440: forming a control gate layer on the intermediate oxide layer.

[0053] In one embodiment, after obtaining the intermediate oxide layer 230, a control gate layer 240 can be obtained by deposition on the surface of the intermediate oxide layer 230. The material of the control gate layer 240 can be undoped polysilicon, doped polysilicon, metal nanocrystals or other suitable conductive metal materials, which usually have high conductivity and corrosion resistance to ensure the stability and reliability of the flash memory device. The specific process steps can be selected according to different materials.

[0054] Step S450 , forming a control electrode on the control gate layer and forming a source electrode and a drain electrode on the second silicon layer.

[0055] In one embodiment, after obtaining the control gate layer 240, a metal layer can be formed by deposition. The metal layer is then subjected to photolithography and etching to form a control electrode 250, a source electrode 260, and a drain electrode 270 having specific shapes and connections. The source electrode 260 and the drain electrode 270 are respectively disposed on either side of the control electrode 250. The control electrode 250, the source electrode 260, and the drain electrode 270 are leads, which are typically made of metal such as copper, aluminum, or gold. These metal leads have good electrical conductivity and mechanical strength to ensure the stability and reliability of the memory cell 200 under normal operating conditions.

[0056] The above-mentioned memory cell manufacturing method directly utilizes the structure of the DSOI wafer 100 itself when manufacturing the memory cell 200 . Therefore, when manufacturing the memory cell 200 , the process is simpler and the cost is lower.

[0057] In one embodiment, as shown in FIG. 7 , after forming an intermediate oxide layer on the floating gate layer in step S430 , the memory cell manufacturing method further includes:

[0058] Step S460: forming a select gate layer on the second silicon layer.

[0059] In one embodiment, after the intermediate oxide layer 230 is formed on the floating gate layer 220, a control gate layer 240 may be formed on the intermediate oxide layer 230 while a select gate layer 280 is formed on the second silicon layer 130. In this case, the control gate layer 240 and the select gate layer 280 are made of the same material. The select gate layer 280 is disposed between the source electrode 260 and the drain electrode 270. In other embodiments, the control gate layer 240 and the select gate layer 280 may be made of different materials and may be formed separately.

[0060] Step S470: forming a selection electrode on the selection gate layer.

[0061] In one embodiment, after forming the select gate layer 280 on the second silicon layer 130, the control electrode 250 can be formed on the control gate layer 240, and the source electrode 260 and the drain electrode 270 can be formed on the second silicon layer 130. At the same time, the select electrode 290 can be formed on the select gate layer 280. In this case, the select electrode 290, the control electrode 250, the source electrode 260, and the drain electrode 270 are made of the same material. In some other embodiments, the select electrode 290 and the other electrodes can also be formed separately.

[0062] Throughout this specification, references to "one embodiment," "some embodiments," and the like indicate that a particular feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0063] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A memory cell, wherein, The memory cell is made of a DSOI wafer, and the DSOI wafer is stacked from top to bottom with: a first silicon layer, a first oxide layer, a second silicon layer, a second oxide layer, and a substrate. The memory cell includes: A tunneling oxide layer, which is formed from the first oxide layer and is disposed on the second silicon layer; A floating gate layer, which is formed from the first silicon layer and is disposed on the tunneling oxide layer; An intermediate oxide layer, which is disposed on the floating gate layer; A control gate layer, which is disposed on the intermediate oxide layer; A control electrode, which is disposed on the control gate layer; A source electrode and a drain electrode, which are disposed on the second silicon layer, and the source electrode and the drain electrode are respectively disposed on both sides of the control electrode.

2. The memory cell according to claim 1, further comprising: A select gate layer, which is disposed on the second silicon layer and is disposed between the source electrode and the drain electrode.

3. The memory cell according to claim 2 further comprises: A select electrode, which is disposed on the select gate layer.

4. The memory cell according to claim 1, wherein, The thickness of the second silicon layer is greater than 150 nanometers.

5. The memory cell according to claim 1, wherein, The thickness of the tunneling oxide layer is 10 nanometers, and the thickness of the floating gate layer is 40 nanometers.

6. The memory cell according to claim 1, wherein, The materials of the substrate, the first silicon layer, and the second silicon layer are all single-crystalline silicon, and the materials of the first oxide layer and the second oxide layer are both silicon dioxide.

7. The memory cell according to claim 1, wherein, The material of the floating gate layer is polysilicon, the material of the tunneling oxide layer is silicon nitride, the material of the intermediate oxide layer is silicon dioxide or silicon nitride, and the material of the control gate layer is a conductive metal material.

8. The memory cell according to claim 1, wherein, The control electrode, the source electrode, and the drain electrode are all metal leads.

9. The memory cell according to claim 3, wherein, The select electrode is a metal lead.

10. The memory cell according to claim 1, wherein, The thickness of the second silicon layer is greater than the thickness of the first silicon layer.

11. A memory, comprising the memory cell according to any one of claims 1 to 10.

12. A chip, comprising the memory cell according to any one of claims 1 to 10, and a transistor, wherein the transistor is disposed on the DSOI wafer.

13. A method for manufacturing a memory cell, for manufacturing the memory cell according to claim 1, the method comprising: Providing a DSOI wafer; wherein, the DSOI wafer is stacked from top to bottom with: a first silicon layer, a first oxide layer, a second silicon layer, a second oxide layer, and a substrate; Performing photolithography and etching on the DSOI wafer to respectively obtain a tunneling oxide layer and a floating gate layer; wherein, the tunneling oxide layer is formed from the first oxide layer, and the floating gate layer is formed from the first silicon layer; Forming an intermediate oxide layer on the floating gate layer; Forming a control gate layer on the intermediate oxide layer; Forming a control electrode on the control gate layer and forming a source electrode and a drain electrode on the second silicon layer; wherein, the source electrode and the drain electrode are respectively disposed on both sides of the control electrode.

14. The method for manufacturing a storage cell according to claim 13, the method further comprising: After forming the intermediate oxide layer on the floating gate layer, Forming a select gate layer on the second silicon layer; wherein, the select gate layer is disposed between the source electrode and the drain electrode; Forming a select electrode on the select gate layer.

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