Display panel and display device

Abstract

The present application provides a display panel and a display device. Two control ends of a demultiplexing unit are connected to a first control signal line and a second control signal line, a time period occupied by one control signal of the first control signal line is within a time period occupied by a scan signal of an N-th scan line, and the starting moment of the falling edge of the scan signal of the N-th scan line and the starting moment of the falling edge of a scan signal of an (N+1)-th scan line are both within a time period occupied by one control signal of the second control signal line.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202311810622.6 filed on December 25, 2023. The contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as part of this application. Technical Field

[0002] The present application relates to, but is not limited to, the field of display technology, and specifically to a display panel and a display device. Background Art

[0003] The principle of the liquid crystal display panel is to control the liquid crystal inversion by adjusting the electrode polarity at both ends of the liquid crystal, thereby achieving display images of different brightness. The data signal used to display the image is first transmitted from the system chip or timing control chip to the data driver circuit, and then from the data driver circuit to the pixel array. A demultiplexing circuit is generally provided between the data driver circuit and the pixel array to reduce the wiring of the fan-shaped area of ​​the display panel.

[0004] The demultiplexing circuit enables data signals from one data line to be transmitted to multiple columns of pixels by opening the data transmission channels between pixels and data lines in a preset sequence. Existing demultiplexing circuits use multiple control signals to alternately open control switches. This requires each control signal line to switch between high and low levels twice during a single scan signal drive cycle, resulting in high power consumption for the display panel.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. SUMMARY OF THE INVENTION

[0006] The purpose of the present application is to provide a display panel and a display device to reduce the power consumption of the display panel when displaying images.

[0007] The present application proposes a display panel, comprising:

[0008] A pixel array comprising a plurality of pixels arranged in an array;

[0009] a plurality of data lines, the plurality of data lines being arranged along a first direction, and one data line being electrically connected to a column of pixels;

[0010] a plurality of scan lines, the plurality of scan lines being arranged along a second direction intersecting the first direction, one of the scan lines being electrically connected to a control terminal of a row of pixels, the scan line being configured to output a scan signal to the control terminal of the pixels;

[0011] a demultiplexing circuit, the demultiplexing circuit comprising at least one data signal input terminal, at least one demultiplexing unit, at least one first control signal line, and one second control signal line, wherein two control terminals of the demultiplexing unit are electrically connected to the first control signal line and the second control signal line, respectively; one demultiplexing unit is electrically connected to one data signal input terminal; and two output terminals of the demultiplexing unit are electrically connected to two data lines, respectively;

[0012] A time period occupied by a control signal of the first control signal line is within a time period occupied by a scan signal of the Nth scan line, and a starting moment of a falling edge of the scan signal of the Nth scan line and a starting moment of a falling edge of the scan signal of the N+1th scan line are both within a time period occupied by a control signal of the second control signal line, where N is a non-zero positive integer.

[0013] The present application proposes a display device, comprising the above-mentioned display panel and a driver chip, wherein the driver chip is used to transmit data signals to data lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG1 is a partial timing diagram of a display panel in the prior art;

[0015] FIG2 is a circuit diagram of a display panel according to Example 1 provided in the present application;

[0016] FIG3 is a timing diagram of the display panel shown in FIG2 ;

[0017] FIG4 is a circuit diagram of a display panel according to a second embodiment of the present application;

[0018] FIG5 is a timing diagram of the display panel shown in FIG4 ;

[0019] FIG6 is a circuit diagram of a display panel according to a third embodiment of the present application;

[0020] FIG7 is a timing diagram of the display panel shown in FIG6 ;

[0021] FIG8 is a schematic diagram of a display device provided in the present application. Modes for Carrying Out the Invention

[0022] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0023] Optionally, in some embodiments of the present application, the starting time of the rising edge of the control signal of the first control signal line is earlier than or equal to the starting time of the rising edge of the control signal of the second control signal line.

[0024] Optionally, in some embodiments of the present application, within the time period occupied by the scan signal of the Nth scan line, the time period occupied by the control signal of the second control signal line is greater than or equal to the time period occupied by the control signal of the first control signal line.

[0025] Optionally, in some embodiments of the present application, within the time period occupied by the scan signal of the Nth scan line, the starting time of the falling edge of the control signal of the first control signal line is equal to or later than the starting time of the rising edge of the control signal of the second control signal line.

[0026] Optionally, in some embodiments of the present application, the starting time of the rising edge of the control signal of the first control signal line is equal to the starting time of the rising edge of the scanning signal of the Nth scanning line.

[0027] Optionally, in some embodiments of the present application, the demultiplexing unit includes a first transistor and a second transistor, the gate of the first transistor is electrically connected to the first control signal line, the gate of the second transistor is electrically connected to the second control signal line, one of the drain or source of the first transistor is electrically connected to one of the data lines, the source or drain of the first transistor is electrically connected to the data signal input terminal, one of the drain or source of the second transistor is electrically connected to one of the data lines, and the other of the drain or source of the second transistor is electrically connected to the data signal input terminal, and within the time period occupied by two adjacent scanning signals, the first transistor is configured to periodically open and close according to the control signal of the first control signal line, and the second transistor is configured to be continuously opened according to the control signal of the second control signal line.

[0028] Optionally, in some embodiments of the present application, the display panel includes a control signal switching module, and the control signal switching module is electrically connected to the first control signal line and the second control signal line;

[0029] The control signal switching module is configured to control the first control signal line to transmit a first control signal, and control the second control signal line to transmit a second control signal when the display panel is in the first mode, wherein a time period occupied by the first control signal is within a time period occupied by one of the scan signals, a time period occupied by the second control signal is within a time period occupied by one of the scan signals, and a total duration of the time period occupied by the first control signal and the time period occupied by the second control signal is less than or equal to a duration of the time period occupied by one of the scan signals;

[0030] The control signal switching module is configured to control the first control signal line to transmit the first control signal, and control the second control signal line to transmit the third control signal when the display panel is in the second mode, wherein the starting time of the falling edge of the scanning signal of the Nth scanning line and the starting time of the falling edge of the scanning signal of the N+1th scanning line are both within the time period occupied by the third control signal.

[0031] Optionally, in some embodiments of the present application, the starting time of the falling edge of the third control signal is equal to the starting time of the falling edge of the last scanning signal when the display panel is in the second mode.

[0032] Optionally, in some embodiments of the present application, multiple first control signal lines are electrically connected to the control end of the demultiplexing unit, and the starting time of the rising edge of the control signal of the second control signal line is equal to or later than the earliest one of the starting times of the rising edge of the control signal of the multiple first control signal lines.

[0033] Optionally, in some embodiments of the present application, the starting time of the rising edge of the control signal of the second control signal line is earlier than or equal to the latest starting time of the falling edge of the control signals of the first control signal lines.

[0034] In the present application, by setting the first control signal line to normally complete two high-level and low-level switches within the time period occupied by the scanning signal of the Nth scanning line, the starting time of the falling edge of the scanning signal of the Nth scanning line and the starting time of the falling edge of the scanning signal of the N+1th scanning line are both located within the time period occupied by a control signal of the second control signal line, so that the high-level signal of the second control signal line lasts from the scanning signal period of the Nth scanning line to the scanning signal period of the N+1th scanning line, that is, during the scanning signal periods of two adjacent scanning lines, the second control signal line is in an open state, which reduces the number of high-level and low-level switching of the control signal of the second control signal line, thereby reducing the voltage drop caused by the switching of high and low levels, and thereby reducing the power consumption of the display panel during operation.

[0035] 2 to 7 , an embodiment of the present application provides a display panel, which includes a pixel array, a plurality of data lines, a plurality of scan lines, and a demultiplexing circuit 110 .

[0036] The pixel array includes a plurality of pixels arranged in an array, a plurality of data lines are arranged along a first direction X, one of the data lines is electrically connected to a column of the pixels, and the data line is configured to output a data signal to the pixels, and a plurality of scan lines Gate are arranged along a second direction Y intersecting the first direction X, one scan line Gate is electrically connected to a control terminal of a row of pixels, and the scan line Gate is configured to output a scan signal to the control terminal of the pixels.

[0037] The demultiplexing circuit 110 includes at least one data signal input terminal S1, at least one demultiplexing unit 111, at least one first control signal line MUX1 and one second control signal line MUX2. The two control terminals of the demultiplexing unit 111 are electrically connected to the first control signal line MUX1 and the second control signal line MUX2, respectively. One demultiplexing unit 111 is electrically connected to one data signal input terminal S1, and the two output terminals of the demultiplexing unit 111 are electrically connected to two data lines D1 and D2, respectively.

[0038] The first control signal line MUX1 is configured to output a control signal to control the connection between the data signal input terminal S1 and one data line D1, and the second control signal line MUX2 is configured to output a control signal to control the connection between the data signal input terminal S1 and another data line D2.

[0039] The starting time when the control signal switches from a low level to a high level is the starting time of the rising edge of the control signal, and the starting time when the control signal switches from a high level to a low level is the starting time of the falling edge of the control signal.

[0040] When the control signal of the first control signal line MUX1 is at a high level, a data line D1 electrically connected to the output end controlled by the first control signal line MUX1 in the demultiplexing unit 111 is connected to the data signal input end S1, and the demultiplexing circuit 110 outputs the data signal of the data signal input end S1 to a column of pixels, and the pixels are charged. When the control signal of the first control signal line MUX1 is at a low level, a data line D1 electrically connected to the output end controlled by the first control signal line MUX1 in the demultiplexing unit 111 is disconnected from the data signal input end S1, and the pixels electrically connected to the data line D1 are not charged. When the control signal of the second control signal line MUX2 is at a high level, a data line D1 electrically connected to the output end controlled by the first control signal line MUX1 in the demultiplexing unit 111 is connected to the data signal input end S1, and the data signal input end S1 outputs the data signal to the pixel through the data line D2, and the pixel is charged. When the control signal of the second control signal line MUX2 is at a low level, a data line D2 electrically connected to the output end controlled by the second control signal line MUX2 in the demultiplexing unit 111 is disconnected from the data signal input end S1, and the pixel electrically connected to the data line D2 is not charged.

[0041] As shown in Figure 3, the time period occupied by a control signal of the first control signal line MUX1 is within the time period occupied by the scan signal of the N-th scan line GateN, and the starting moment of the falling edge of the scan signal of the N-th scan line GateN and the starting moment of the falling edge of the scan signal of the N+1-th scan line GateN+1 are both within the time period occupied by a control signal of the second control signal line MUX2, where N is a non-zero positive integer.

[0042] That is, within the time period H occupied by a scan signal, the control signal of the first control signal line MUX1 switches from a low level to a high level, and from a high level to a low level, to periodically open and close a data line D1. The time period occupied by the control signal of the first control signal line MUX1 is T1, where T1 is less than H. The control signal of the second control signal line MUX2 switches from a low level to a high level only once, that is, the data line D2 controlled by the second control signal line MUX2 is turned on only once within at least the 2H period, which is the time period occupied by a scan signal of a scan line GateN and the time period occupied by a scan signal of the next scan line GateN+1. The data line D2 is kept in a continuously open state, thereby reducing the switching frequency of the control signal of the second control signal line MUX2 between a high level and a low level, thereby reducing power consumption.

[0043] In the present application, by setting the first control signal line MUX1 to normally complete two high-level and low-level switchings within the time period occupied by the scan signal of the Nth scan line GateN, the starting time of the falling edge of the scan signal of the Nth scan line GateN and the starting time of the falling edge of the scan signal of the N+1th scan line GateN+1 are both located within the time period occupied by a control signal of the second control signal line MUX2, so that the high-level signal of the second control signal line MUX2 lasts from the scan signal period of the Nth scan line GateN to the scan signal period of the N+1th scan line GateN+1, that is, during the scan signal periods of two adjacent scan lines Gate, the second control signal line MUX2 is in an open state, thereby reducing the number of high-level and low-level switchings of the control signal of the second control signal line MUX2 within one frame time, thereby reducing the voltage drop of the display panel caused by the high-level and low-level switching, and thereby reducing the power consumption of the display panel during operation.

[0044] Specifically, as shown in FIG1 , in the prior art, during the time period occupied by the scan signal of a scan line GateN, the first control signal line MUX1 and the second control signal line MUX2 each switch between a high level and a low level twice. As shown in FIG3 , in the present application, the second control signal line MUX2 switches between a high level and a low level only once during the time period occupied by the scan signal of a scan line GateN, and during the time period occupied by the scan signal of the next scan line GateN+1, the second control signal line MUX2 remains in a high level state, thereby reducing the voltage drop caused by switching from a high level to a low level, thereby reducing the power consumption of the display panel.

[0045] In this embodiment, the time period occupied by the scan signal of the Nth scan line GateN is the scan signal period of the Nth scan line GateN. The time period occupied by the scan signal of the N+1th scan line GateN+1 is the scan signal period of the N+1th scan line GateN+1. The time period occupied by the scan signal of the Nth scan line GateN is equal to the time period occupied by the scan signal of the N+1th scan line GateN+1.

[0046] As shown in FIG. 2 and FIG. 3 , in the first embodiment of the present application, the starting time of the rising edge of the control signal of the first control signal line MUX1 is earlier than or equal to the starting time of the rising edge of the control signal of the second control signal line MUX2 .

[0047] In this embodiment, the first control signal line MUX1 is configured to control the connection between the first data line D1 and the data signal input terminal S1 , and the second control signal line MUX2 is configured to control the connection between the second data line D2 and the data signal input terminal S1 .

[0048] Specifically, the conduction moment between the first data line D1 and the data signal input terminal S1 is prior to or equal to the conduction moment between the second data line D2 and the data signal input terminal S1. After the first data line D1 and the data signal input terminal S1 are conducted, the demultiplexing circuit 110 outputs the corresponding column pixel data signal to the first data line D1 according to the data signal input by the data signal input terminal S1. After the second data line and the second data signal input terminal S1 are conducted, the demultiplexing circuit 110 outputs the data signal to the second data line D2 according to the data signal input by the data signal input terminal S1. When the control signal of the first control signal line MUX1 and the control signal of the second control signal line MUX2 are both at a high level, the two columns of pixels electrically connected to the demultiplexing circuit 110 both receive the data signal of the first column of pixels connected to the first data line D1; when the control signal of the first control signal line MUX1 is a low level signal and the control signal of the second control signal line MUX2 is at a high level, the first data line D1 does not transmit the data signal, and the second data line D2 transmits the data signal of the second column of pixels to the second column of pixels. When the second data line D2 transmits the data signal of the second column of pixels, the data signal of the second column of pixels covers the data signal of the first column of pixels transmitted within the T1 time, thereby ensuring that the second column of pixels can be charged correctly.

[0049] This embodiment ensures that pixels electrically connected to a periodically switched data line will not be mischarged during the charging process by setting the opening time of a periodically switched data line earlier than the opening time of a continuously switched data line, thereby ensuring normal display of the display panel.

[0050] In this embodiment, within the time period H occupied by the scan signal of the Nth scan line GateN, the time period occupied by the control signal of the second control signal line MUX2 is greater than or equal to the time period occupied by the control signal of the first control signal line MUX1.

[0051] When the control signal of the first control signal line MUX1 is a low-level signal and the control signal of the second control signal line MUX2 is a high-level signal, the first data line D1 does not transmit a data signal, and the second data line D2 transmits the data signal of the second column of pixels to the second column of pixels. After the second data line D2 transmits the data signal of the second column of pixels, the data signal of the second column of pixels overwrites the data signal of the first column of pixels, thereby ensuring that the second column of pixels can be properly charged. During the time period occupied by the scan signal of the Nth scan line Gate, the time period occupied by the control signal of the second control signal line MUX2 is greater than or equal to the time period occupied by the control signal of the first control signal line MUX1, ensuring that the data signal of the second column of pixels has sufficient time to overwrite the data signal of the first column of pixels, thereby ensuring that the second column of pixels will not be incorrectly charged.

[0052] In this embodiment, during the time period H occupied by the scan signal of the Nth scan line Gate, the starting time of the falling edge of the control signal of the first control signal line MUX1 is equal to or later than the starting time of the rising edge of the control signal of the second control signal line MUX2. Since the turning-on time of the second control signal line MUX2 is earlier than or equal to the turning-off time of the first control signal line MUX1, the time required to charge the first column of pixels and the second column of pixels can be reduced, which is conducive to achieving a high refresh rate of the display panel.

[0053] In this embodiment, the starting time of the rising edge of the control signal of the first control signal line MUX1 is equal to the starting time of the rising edge of the scanning signal of the Nth scanning line GateN. At the time when each scanning line Gate is turned on, the control signal of the first control signal line MUX1 is simultaneously switched from a low level to a high level to turn on the first data line D1, thereby shortening the duration H of the scanning signal of each scanning line Gate, further improving the refresh rate of the display panel. In this application, turning on the data line D means that the data line D is connected to the data signal input terminal S1 under the control of the demultiplexing unit 111, thereby opening the data transmission channel of the pixel. Turning off the data line D means that the data line D is disconnected from the data signal input terminal S1 under the control of the demultiplexing unit 111, thereby closing the data transmission channel of the pixel.

[0054] In this embodiment, the demultiplexing unit 111 includes a first transistor M1 and a second transistor M2, the gate of the first transistor M1 is electrically connected to the first control signal line MUX1, the gate of the second transistor M2 is electrically connected to the second control signal line MUX2, one of the drain or source of the first transistor M1 is electrically connected to a data line, the source or drain of the first transistor M1 is electrically connected to the data signal input terminal S1, one of the drain or source of the second transistor M2 is electrically connected to the data line, and the other of the drain or source of the second transistor M2 is electrically connected to the data signal input terminal S1. During the time period occupied by two adjacent scanning signals, the first transistor M1 is configured to be periodically turned on and off according to the control signal of the first control signal line MUX1, and the second transistor M2 is configured to be continuously turned on according to the control signal of the second control signal line MUX2.

[0055] In this embodiment, one of the source and drain of the first transistor M1 is electrically connected to the first data line D1, and the other of the source and drain of the first transistor M1 is electrically connected to the data signal input terminal S1. One of the source and drain of the second transistor M2 is electrically connected to the second data line D2, and the other of the source and drain of the second transistor M2 is electrically connected to the data signal input terminal S1.

[0056] When the control signal of the first control signal line MUX1 is at a high level, the first transistor M1 is turned on; when the control signal of the first control signal line MUX1 is at a low level, the first transistor M1 is turned off. When the control signal of the second control signal line MUX2 is at a high level, the second transistor M2 is turned on; when the control signal of the second control signal line MUX2 is at a low level, the second transistor M2 is turned off.

[0057] In this embodiment, any two data lines D1 and D2 electrically connected to the same demultiplexing unit 111 have the same polarity.

[0058] In this embodiment, the polarities of two adjacent columns of data lines D1 and D3 are opposite, and the polarities of two adjacent data signal input terminals S1 and S2 are opposite.

[0059] In this embodiment, the display panel includes a control signal switching module 120 , and the control signal switching module 120 is electrically connected to the first control signal line MUX1 and the second control signal line MUX2 .

[0060] The control signal switching module 120 is configured to control the first control signal line MUX1 to output a first control signal, and to control the second control signal line MUX2 to output a second control signal, when the display panel is in a first mode. The time period occupied by the first control signal is within the time period occupied by a scan signal, the time period occupied by the second control signal is within the time period H occupied by a scan signal, and the total duration of the time period occupied by the first control signal and the time period occupied by the second control signal is less than or equal to the duration of the time period occupied by the scan signal. When the display panel is in the first mode, the first control signal and the second control signal are both switched between a high level and a low level twice during a scan signal period, ensuring that each column of pixels can receive the corresponding data signal to achieve accurate charging. This helps meet the high refresh rate requirements of the display panel when displaying dynamic images and improves the accuracy of pixel charging.

[0061] The control signal switching module 120 is configured to control the first control signal line MUX1 to output the first control signal, and to control the second control signal line MUX2 to output the third control signal, when the display panel is in the second mode. The starting time of the falling edge of the scan signal of the Nth scan line GateN and the starting time of the falling edge of the scan signal of the N+1th scan line GateN are both within the time period occupied by the third control signal. When the display panel is in the second mode, the first control signal remains unchanged, and the second control signal is switched to the third control signal. Because the starting time of the falling edge of the scan signal of the Nth scan line GateN and the starting time of the falling edge of the scan signal of the N+1th scan line GateN+1 are both within the time period occupied by the third control signal, the third control signal switches between high and low levels at a lower frequency than the second control signal during a frame of display. This facilitates low-power operation of the display panel and is more suitable for operating the display panel in a low-power mode when displaying static images or pure colors (red / green / blue images).

[0062] This embodiment uses the first mode and the second mode to coordinate with each other, so that the display panel can ensure normal display of the screen when displaying different screens, while effectively reducing the logical power consumption of the display panel, which is beneficial to energy saving and power saving of the display panel, and can also better ensure the service life of the display panel and extend the service life of the display panel.

[0063] In this embodiment, the starting time of the falling edge of the third control signal is equal to the starting time of the falling edge of the last scan signal when the display panel is in the second mode.

[0064] Specifically, when the display panel is in the second mode, the third control signal switches from a low level to a high level and remains at the high level until the display panel switches from the second mode to the first mode, at which point the third control signal switches from a high level to a low level. That is, when the display panel is in the second mode, the second transistor M2 controlled by the second control signal line MUX2 remains in an on state.

[0065] As shown in FIG4 and FIG5 , in the second embodiment of the present application, the second embodiment is similar to the first embodiment, and the second embodiment can be combined with the first embodiment. The difference between the second embodiment and the first embodiment is that:

[0066] The two first control signal lines MUX1 are electrically connected to the control terminals of the demultiplexing unit 111. The rising edge of the control signal of the second control signal line MUX2 starts at or after the earliest of the rising edges of the control signals of the two first control signal lines MUX1. Data transmission on the data line D1 controlled by the first control signal line MUX1 begins earlier than data transmission on the data line controlled by the second control signal line MUX2. Because the control signal of the second control signal line MUX2 is continuously high, the switching start time of the control signal of the first control signal line MUX1 from a low level to a high level is earlier than or at least equal to the switching start time of the control signal of the second control signal line MUX2 from a low level to a high level. This facilitates the data line D1 controlled by the first control signal line MUX1 to transmit the corresponding data signal first.

[0067] Specifically, during a scan signal period, the falling edge of the control signal of the first first control signal line MUX1_1 is earlier than the rising edge of the control signal of the second first control signal line MUX1_2, that is, the time periods occupied by the control signals of multiple first control signal lines MUX1 do not overlap, thereby ensuring that each data line D1 controlled by the first control signal line MUX1 can transmit the corresponding data signal, thereby avoiding charging errors in the pixel columns.

[0068] In this embodiment, the demultiplexing unit 111 also includes a third transistor M3, wherein the gates of the first transistor M1 and the third transistor M3 are electrically connected to the two first control signal lines MUX1, respectively, the output ends of the first transistor M1 and the second transistor M2 are electrically connected to the two data lines D1 and D2, respectively, and the input end of the third transistor M3 is electrically connected to the data signal input end S1.

[0069] In this embodiment, the starting time of the rising edge of the control signal of the second control signal line MUX2 is earlier than or equal to the latest starting time of the falling edge of the control signal of the two first control signal lines MUX1.

[0070] Specifically, the starting time of the rising edge of the control signal of the second control signal line MUX2 is earlier than or equal to the starting time of the falling edge of the control signal of the second first control signal line MUX1_2, so as to cancel the time required from the starting time of the falling edge of the control signal of the second control signal line to the starting time of the rising edge of the control signal of the second control signal line MUX2, which is beneficial to shorten the time required for a scanning signal and is beneficial to the high refresh rate of the display panel.

[0071] As shown in FIG6 and FIG7 , in the third embodiment of the present application, the third embodiment is similar to the second embodiment, and the third embodiment can be combined with at least one of the first embodiment and the second embodiment. The difference between the third embodiment and the second embodiment is that:

[0072] The three first control signal lines MUX1 are electrically connected to the control terminal of the demultiplexing unit 111 , and the starting time of the rising edge of the second control signal line MUX2 is equal to or later than the earliest one of the starting times of the rising edges of the control signals of the three first control signal lines MUX1 .

[0073] During a scan signal period, the falling edge of the control signal of the first first control signal line MUX1_1 occurs earlier than the rising edge of the control signal of the second first control signal line MUX1_2. The falling edge of the control signal of the second first control signal line MUX1_2 also occurs before the rising edge of the control signal of the third first control signal line MUX1_3. That is, the time periods occupied by the control signals of the three first control signals do not overlap. This ensures that the data signals transmitted by the data line D1 controlled by the three first control signal lines MUX1 do not interfere with each other, thereby preventing pixel mischarging.

[0074] In this embodiment, the demultiplexing unit 111 further includes a third transistor M3 and a fourth transistor M4, wherein the gate of the first transistor M1, the gate of the third transistor M3, and the gate of the fourth transistor M4 are electrically connected to the three first control signal lines MUX1, respectively, the output end of the first transistor M1, the output end of the second transistor M2, and the output end of the third transistor M3 are electrically connected to the three data lines D1, D2, and D3, respectively, the input end of the third transistor M3 is electrically connected to the data signal input end S1, and the input end of the fourth transistor M4 is electrically connected to the data signal input end S1.

[0075] In this embodiment, the starting time of the rising edge of the control signal of the second control signal line MUX2 is earlier than or equal to the starting time of the falling edge of the control signal of the third first control signal line MUX1_3.

[0076] As shown in FIG8 , based on the display panel 100 provided in any of the above embodiments, the present application further provides a display device, which includes the display panel 100 and a driver chip 200. The display panel 100 is the display panel 100 described in any of the above embodiments. The driver chip 200 is used to transmit data signals to data lines.

[0077] The display device can be a smartphone, tablet computer, e-book reader, smart watch, camera, game console, etc.

[0078] The display panel 100 includes a pixel array consisting of a plurality of pixels, a gate driving circuit (GOA), scan lines, and a demultiplexing circuit 110. The gate driving circuit includes a plurality of data lines arranged along a first direction X, and a plurality of scan lines arranged along a second direction Y. The first direction X and the second direction Y intersect.

[0079] Among them, one data line is electrically connected to a column of pixels. In the first direction X, multiple data lines are electrically connected to the driver chip 200 through the demultiplexing circuit 110. The demultiplexing circuit 110 is configured to control the on and off of multiple data lines and the driver chip 200. The demultiplexing circuit 110 can reduce the output channels of the driver chip 200 by multiples, thereby reducing the number of driver chips 200 and reducing costs.

[0080] In the second direction Y, the driver chip 200 is disposed above the display panel 100 or below the display panel 100. There is at least one driver chip 200. The driver chip 200 transmits data signals to the pixel columns via data lines. In some embodiments, the driver chip 200 can be bonded to the display panel 100 using a chip on film (COF).

[0081] In the second direction Y, one scan line is electrically connected to the control terminals of a row of pixels, and the scan line is configured to output scan signals to the control terminals of the pixels.

[0082] The demultiplexing circuit 110 includes at least one data signal input terminal, at least one demultiplexing unit, at least one first control signal line, and one second control signal line. The two control terminals of the demultiplexing unit are electrically connected to the first control signal line and the second control signal line, respectively. One demultiplexing unit is electrically connected to one of the data signal input terminals. The two output terminals of the demultiplexing unit are electrically connected to the two data lines, respectively.

[0083] The time period occupied by a control signal of the first control signal line is within the time period occupied by the scanning signal of the Nth scanning line GateN, and the starting moment of the falling edge of the scanning signal of the Nth scanning line GateN and the starting moment of the falling edge of the scanning signal of the N+1th scanning line GateN+1 are both within the time period occupied by a control signal of the second control signal line, where N is a non-zero positive integer.

[0084] In the present application, by setting the first control signal line MUX1 to normally complete two high-level and low-level switchings within the time period occupied by the scan signal of the Nth scan line GateN, the starting time of the falling edge of the scan signal of the Nth scan line GateN and the starting time of the falling edge of the scan signal of the N+1th scan line GateN+1 are both located within the time period occupied by one control signal of the second control signal line MUX2, so that the high-level signal of the second control signal line MUX2 lasts from the scan signal period of the Nth scan line GateN to the scan signal period of the N+1th scan line GateN+1, that is, during the scan signal periods of two adjacent scan lines Gate, the second control signal line MUX2 is in an open state, thereby reducing the number of high-level and low-level switchings of the control signal of the second control signal line MUX2 within one frame time, thereby reducing the voltage drop of the display device caused by the high-level and low-level switching, and thereby reducing the power consumption of the display device during operation.

[0085] Those skilled in the art will appreciate that modifications or equivalent substitutions may be made to the embodiments of the present application without departing from the spirit and scope of the present application, and such modifications or equivalent substitutions shall be encompassed within the scope of the present application. The various embodiments may be combined with each other but will not be described in detail here.

[0086] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A display panel, wherein, The display panel includes: a pixel array including a plurality of pixels arranged in an array; a plurality of data lines arranged along a first direction, and one of the data lines is electrically connected to one column of the pixels; a plurality of scan lines arranged along a second direction intersecting with the first direction, and one of the scan lines is electrically connected to the control ends of one row of the pixels, and the scan line is configured to output a scan signal to the control ends of the pixels; a demultiplexing circuit, the demultiplexing circuit includes at least one data signal input terminal, at least one demultiplexing unit, at least one first control signal line and one second control signal line, two control ends of the demultiplexing unit are respectively electrically connected to the first control signal line and the second control signal line, one demultiplexing unit is electrically connected to one data signal input terminal, and two output ends of the demultiplexing unit are respectively electrically connected to two of the data lines; a time period occupied by a control signal of the first control signal line is located within a time period occupied by a scan signal of the Nth scan line, and starting moments of falling edges of the scan signal of the Nth scan line and a scan signal of the (N + 1)th scan line are both located within a time period occupied by a control signal of the second control signal line, where N is a non-zero positive integer.

2. The display panel according to claim 1, wherein, A starting moment of a rising edge of the control signal of the first control signal line is earlier than or equal to a starting moment of a rising edge of the control signal of the second control signal line.

3. The display panel according to claim 2, wherein, Within a time period occupied by the scan signal of the Nth scan line, a time period occupied by the control signal of the second control signal line is greater than or equal to a time period occupied by the control signal of the first control signal line.

4. The display panel according to claim 3, wherein, Within a time period occupied by the scan signal of the Nth scan line, a starting moment of a falling edge of the control signal of the first control signal line is equal to or later than a starting moment of a rising edge of the control signal of the second control signal line.

5. The display panel according to claim 3, wherein, A starting moment of a rising edge of the control signal of the first control signal line is equal to a starting moment of a rising edge of the scan signal of the Nth scan line.

6. The display panel according to any one of claims 1 to 5, wherein, The demultiplexing unit includes a first transistor and a second transistor, a gate of the first transistor is electrically connected to the first control signal line, a gate of the second transistor is electrically connected to the second control signal line, one of a drain or a source of the first transistor is electrically connected to one of the data lines, a source or a drain of the first transistor is electrically connected to the data signal input terminal, one of a drain or a source of the second transistor is electrically connected to one of the data lines, and the other of the drain or the source of the second transistor is electrically connected to the data signal input terminal. Within time periods occupied by two adjacent scan signals, the first transistor is configured to be periodically turned on and off according to the control signal of the first control signal line, and the second transistor is configured to be continuously turned on according to the control signal of the second control signal line.

7. The display panel according to any one of claims 1 to 5, wherein, The display panel includes a control signal switching module, and the control signal switching module is electrically connected to the first control signal line and the second control signal line; The control signal switching module is configured to control the first control signal line to transmit a first control signal and control the second control signal line to transmit a second control signal when the display panel is in the first mode. Wherein, the time period occupied by the first control signal is within the time period occupied by one of the scan signals, the time period occupied by the second control signal is within the time period occupied by one of the scan signals, and the total duration of the time period occupied by the first control signal and the time period occupied by the second control signal is less than or equal to the duration of the time period occupied by one of the scan signals; The control signal switching module is configured to control the first control signal line to transmit the first control signal and control the second control signal line to transmit a third control signal when the display panel is in the second mode. Wherein, the start time of the falling edge of the scan signal of the Nth scan line and the start time of the falling edge of the scan signal of the (N + 1)th scan line are both within the time period occupied by the third control signal.

8. The display panel according to claim 7, wherein, The start time of the falling edge of the third control signal is equal to the start time of the falling edge of the last scan signal when the display panel is in the second mode.

9. The display panel according to any one of claims 1 to 5, wherein, Multiple first control signal lines are electrically connected to the control end of the demultiplexing unit, and the start time of the rising edge of the control signal of the second control signal line is equal to or later than the earliest one among the start times of the rising edges of the control signals of the multiple first control signal lines.

10. The display panel according to claim 9, wherein, The time periods occupied by the control signals of the multiple first control signal lines do not overlap.

11. The display panel according to claim 9, wherein, The start time of the rising edge of the control signal of the second control signal line is earlier than or equal to the latest one among the start times of the falling edges of the control signals of the multiple first control signal lines.

12. The display panel according to claim 9, wherein, The demultiplexing unit includes a first transistor and a third transistor. The gates of the first transistor and the third transistor are respectively electrically connected to two of the first control signal lines, and the input ends of the first transistor and the third transistor are electrically connected to the data signal input end.

13. The display panel according to claim 12, wherein, The demultiplexing unit further includes a fourth transistor. The gates of the first transistor, the third transistor, and the fourth transistor are respectively electrically connected to three of the first control signal lines, and the input end of the fourth transistor is electrically connected to the data signal input end.

14. The display panel according to any one of claims 1 to 5, wherein, The polarities of two adjacent data signal input ends are opposite.

15. The display panel according to any one of claims 1 to 5, wherein, The polarities of any two data lines electrically connected to the same demultiplexing unit are the same.

16. A display device, wherein, Comprising: A display panel, including a pixel array, multiple data lines, multiple scan lines, and a demultiplexing circuit. The pixel array includes a plurality of pixels arranged in an array; A plurality of the data lines are arranged in a first direction, and one of the data lines is electrically connected to a column of the pixels; a plurality of the scan lines are arranged in a second direction intersecting the first direction, and one of the scan lines is electrically connected to a control end of a row of the pixels, and the scan line is configured to output a scan signal to the control end of the pixel; the demultiplexing circuit includes at least one data signal input end, at least one demultiplexing unit, at least one first control signal line, and one second control signal line. Two control ends of the demultiplexing unit are respectively electrically connected to the first control signal line and the second control signal line. One demultiplexing unit is electrically connected to one data signal input end, and two output ends of the demultiplexing unit are respectively electrically connected to two of the data lines; a time period occupied by a control signal of the first control signal line is located within a time period occupied by a scan signal of the Nth scan line, and a starting moment of a falling edge of the scan signal of the Nth scan line and a starting moment of a falling edge of the scan signal of the (N + 1)th scan line are both located within a time period occupied by a control signal of the second control signal line, where N is a non-zero positive integer; and a driving chip, configured to transmit a data signal to the data line.

17. The display device according to claim 16, wherein, A starting moment of a rising edge of the control signal of the first control signal line is earlier than or equal to a starting moment of a rising edge of the control signal of the second control signal line.

18. The display device according to claim 17, wherein, Within a time period occupied by the scan signal of the Nth scan line, a time period occupied by the control signal of the second control signal line is greater than or equal to a time period occupied by the control signal of the first control signal line.

19. The display device according to claim 18, wherein, Within a time period occupied by the scan signal of the Nth scan line, a starting moment of a falling edge of the control signal of the first control signal line is equal to or later than a starting moment of a rising edge of the control signal of the second control signal line.

20. The display device according to claim 18, wherein, A starting moment of a rising edge of the control signal of the first control signal line is equal to a starting moment of a rising edge of the scan signal of the Nth scan line.

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