Task processing method and apparatus, and related device

Abstract

A task processing method and apparatus, and a related device, which relate to the technical field of computers. The method comprises: executing a first task, the first task comprising multiple subtasks, and a subtask which is being executed being a first subtask; in the process of executing the first subtask, when the priority of a second task to be executed is higher than the priority of the first task, preferentially executing the second task after the execution of the first subtask is completed, the first subtask and the second task being executed by means of the same processing unit; and after the execution of the second task is completed, executing the remaining subtasks in the first task. Thus, in the process of executing the first task, the second task having a higher priority can be inserted to be executed without needing to wait for the completion of the execution of the whole first task, so that a processing time delay of the second task having a higher priority is reduced, the requirement of an application for the processing time delay of the second task can be satisfied, and the performance of the application is optimized.

Description

Task processing method, device and related equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 27, 2023, with application number 202311832069.6 and application name “Task processing methods, devices and related equipment”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of task processing technology, and in particular to a task processing method, apparatus, and related equipment. Background Art

[0003] With the development of multi-core processor core architecture, using multiple cores to process tasks in parallel has become a mainstream task processing method.

[0004] Currently, when multiple processor cores are processing tasks, multiple tasks often require the same processor core to handle them. Because the processor core architecture typically operates in a run-to-completion mode, meaning that after a task is started, the processor core will continue to execute the first task until it completes, a second task must wait for the first task to complete before it can continue using the same processor core.

[0005] However, this approach to task processing increases the processing time of the second task and reduces its efficiency. If the second task is latency-sensitive, the execution delay may exceed the maximum latency limit the second task can tolerate, thereby affecting the operation of the upper-layer service to which the second task corresponds.

[0006] Summary of the Invention

[0007] This application provides a task processing method that enables high-priority tasks (such as latency-sensitive services) to be executed and completed first when the execution mode of the processor core architecture is run to completion, thereby meeting the low latency requirements for processing high-priority tasks. In addition, this application also provides a task processing apparatus, a computing device, a computer-readable storage medium, and a computer program product.

[0008] In the first aspect, the present application provides a task processing method, which can be executed by a corresponding task processing device. Specifically, the task processing device executes a first task, which includes multiple subtasks. For example, the task processing device can divide the first task into multiple subtasks, etc., and the subtask currently being executed is the first subtask. In the process of executing the first subtask, when a second task to be executed is detected, and the priority of the second task is higher than the priority of the first task, the task processing device will give priority to executing the second task after executing the first subtask. The first subtask and the second task are executed by the same processing unit, which can be a processor core, etc. In addition, after the second task is executed, the task processing device executes the remaining subtasks in the first task, that is, the other subtasks in the multiple subtasks included in the first task except the first subtask, such as continuing to use the processor core to execute the remaining subtasks, etc.

[0009] During the execution of a first task, the task processing device will use the processing unit to execute a higher-priority second task after completing the first subtask of the currently executing first task. That is, during the execution of the first task, the task processing device will insert the execution of the higher-priority second task without waiting for the entire first task to complete. This reduces the processing latency of the higher-priority second task, thereby meeting the application's latency requirements for the second task and optimizing application performance.

[0010] In one possible implementation, before executing a first task, the task processing device identifies the first task as a low-priority task based on its type and divides the first task into multiple subtasks. Thus, during the subsequent execution of the subtasks within the lower-priority first task, if a higher-priority task awaits execution, the higher-priority task can be started after the currently executing subtask within the first task completes, thereby reducing the processing delay for the higher-priority second task.

[0011] In one possible implementation, if a first task includes multiple task classes, the task processing device may divide the first task into multiple subtasks based on the multiple task classes included in the first task. In this case, each subtask includes at least one task class. In this way, the task processing device can implement the division of subtasks based on the task classes in the task.

[0012] In one possible implementation, if a first task includes multiple operators, the task processing device may divide the first task into multiple subtasks based on the multiple operators included in the first task. In this case, each subtask includes at least one operator. In this way, the task processing device can implement subtask division based on the operators in the task.

[0013] In one possible implementation, the first and second tasks are thread tasks within a first process task. The task processing device can then edit the first process task into a first computational graph comprising the first and second tasks based on the editing model. The first computational graph defines dependencies between different thread tasks within the first process task. For example, different nodes within the first computational graph can be used to represent different thread tasks, and directed edges between nodes can be used to indicate dependencies between different thread tasks. These dependencies refer to the dependencies between the execution of thread tasks, allowing the task processing device to detect the currently executable second task from the first computational graph. In this way, the task processing device can sequentially process each thread task through the computational graph, ensuring the smooth execution of the thread tasks.

[0014] In one possible implementation, when an application starts, the runtime scheduler (i.e., the task processing device) can request processor resources from memory and use these processor resources as user-mode resources. These processor resources include multiple cores. Therefore, when a first process task starts, the runtime scheduler can intercept the resource request for the first process task and allocate the user-mode resources to the first process task. In this way, when executing the various thread tasks within the first process task using user-mode resources, there is no need to switch from user mode to kernel mode, effectively reducing the overhead associated with switching from user mode to kernel mode and back again.

[0015] In one possible implementation, before executing the second task, the task processing device obtains a resource scheduling result, and the resource scheduling result indicates that multiple subtasks are to be executed by the first processor core. Then, after completing the second task, when the task processing device schedules the corresponding hardware resources to execute the remaining subtasks in the first task, it may specifically use the first processor core to execute the remaining subtasks in the first task based on the resource scheduling result. In this way, even if a second task with a higher execution priority is inserted, the task processing device will continue to use the first processor core to execute the remaining subtasks in the first task based on the previously set resource scheduling result, without having to re-schedule new hardware resources for the remaining subtasks. This can effectively reduce the overhead of resource scheduling, thereby improving the utilization of hardware resources.

[0016] In a possible implementation, the application includes multiple programming models, such as a first programming model and a second programming model. Then, the application can edit different process tasks into multiple thread tasks through different programming models.

[0017] In the second aspect, the present application provides a task processing device, an execution module, used to execute a first task, the first task includes multiple subtasks, and the subtask being executed is the first subtask; a detection module, used to detect that the priority of the second task to be executed is higher than the priority of the first task; the execution module is also used to detect that the priority of the second task to be executed is higher than the priority of the first task, and after executing the first subtask, execute the second task, and the first subtask and the second task are executed by the same processing unit; after the execution of the second task is completed, execute the remaining subtasks in the first task.

[0018] In a possible implementation, the task processing device further includes: an identification module for identifying the first task as a low-priority task based on the type of the first task before executing the first task; and a division module for dividing the first task into a plurality of subtasks.

[0019] In a possible implementation, the first task includes multiple task classes; the division module is configured to divide the first task into multiple subtasks according to the multiple task classes, and each of the multiple subtasks includes at least one task class.

[0020] In a possible implementation, the first task includes multiple operators; the division module is configured to divide the first task into multiple subtasks according to the multiple operators, and each of the multiple subtasks includes at least one operator.

[0021] In one possible embodiment, the first task and the second task are thread tasks in a first process task, and the task processing device also includes: an editing module, used to edit the first process task into a first computational graph including the first task and the second task according to an editing model, wherein the first computational graph sets the dependency relationship between different thread tasks in the first process task; and a detection module, used to detect the second task from the first computational graph.

[0022] In one possible embodiment, the task processing device can be a runtime scheduler, which also includes: an application module, which is used to apply for processor resources from the kernel when the application is started, and use the processor resources as user-state resources, and the processor resources include multiple cores; an interception module, which is used to intercept the resource application request of the first process when the first process task is started, and allocate the user-state resources to the first process task.

[0023] In one possible embodiment, the task processing device also includes: an acquisition module, which is used to obtain a resource scheduling result before executing the second task, and the resource scheduling result indicates that multiple subtasks are executed by the first processor core; then, an execution module, which is used to use the first processor core to execute the remaining subtasks in the first task according to the resource scheduling result after the second task is completed.

[0024] In a possible implementation, the application includes multiple programming models, such as a first programming model and a second programming model. Then, the application can edit different process tasks into multiple thread tasks through different programming models.

[0025] In a third aspect, the present application provides a computing device comprising a processor and a memory. The processor and the memory communicate with each other. The processor is configured to execute instructions stored in the memory so that the computing device performs a task processing method as described in the first aspect or any one of the implementations of the first aspect. It should be noted that the memory may be integrated into the processor or may be independent of the processor. The computing device may further comprise a bus. The processor is connected to the memory via the bus. The memory may comprise a readable memory and a random access memory.

[0026] In a fourth aspect, the present application provides a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is executed on a computing device, the computing device executes the operating steps of the task processing method described in the first aspect or any implementation of the first aspect.

[0027] In a fifth aspect, the present application provides a computer program product comprising instructions, which, when executed on a computing device, enables the computing device to execute the operating steps of the task processing method described in the first aspect or any one of the implementations of the first aspect.

[0028] Based on the implementation methods provided in the above aspects, this application can also be further combined to provide more implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic diagram of the structure of an exemplary data processing system provided by the present application;

[0030] FIG2 is a flowchart of a task processing method provided by this application;

[0031] FIG3 is a schematic diagram of execution dependencies between multiple thread tasks provided by this application;

[0032] FIG4 is a schematic diagram showing that the execution delay of the second task provided by the present application is reduced;

[0033] FIG5 is a schematic diagram of the structure of a task processing device provided by the present application;

[0034] FIG6 is a schematic diagram of the hardware structure of a computing device provided in this application. DETAILED DESCRIPTION

[0035] The terms "first," "second," and so on, in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate and are merely used to describe the manner in which objects with the same attributes are distinguished in the embodiments of this application.

[0036] The technical solution in this application will be described below in conjunction with the drawings provided in this application.

[0037] 1 , which shows a schematic diagram of the structure of a data processing system. As shown in FIG1 , the data processing system 10 includes an application layer 101 , a hardware layer 102 , and a task processing device 200 .

[0038] The application layer 101 includes at least one application, such as an image recognition application, and is described in FIG1 using application 1 as an example. Furthermore, application 1 may include at least one programming model, and FIG1 uses programming models 1 to 3 as an example. Exemplarily, the programming model may be a message passing interface (MPI) model, a shared memory parallel programming (OpenMP) model, a SYCL model (a high-level programming model for the open computing language (OpenCL)), or other types of programming models.

[0039] The hardware layer 102 includes multiple processor cores, each of which can execute thread tasks. Furthermore, the multiple processor cores can be used to execute multiple thread tasks in parallel. The multiple processor cores in the hardware layer 102 can be identical, or they can be different, such as some processor cores being large cores with higher processing performance, while others being small cores with lower processing performance.

[0040] Furthermore, the hardware layer 102 may also include other devices, such as a network interface controller (NIC), memory, accelerator, or other types of devices, as shown in FIG1 . For example, the memory may be a direct memory access (DMA) device. The accelerator may be a graphics processing unit (GPU), for example.

[0041] The task processing device 200 is used to schedule the processor cores (and other hardware) in the hardware layer 102 to execute thread tasks. For example, the task processing device 200 can be implemented in software. For example, the task processing device 200 can be specifically referred to as a runtime scheduler, and the runtime scheduler can run on the processor cores.

[0042] During the execution of application 1, at least one task, such as a data search task, may be generated based on user operations on application 1. For each task, the programming model can edit the task into one or more process tasks. These process tasks may have dependencies, such as the execution of process task A within the multiple process tasks depending on the execution result of process task B (i.e., process task B must be executed first). The programming model can then generate multiple computation graphs 1 based on the dependencies between these multiple process tasks. Each node in the computation graphs 1 represents a process task, and directed edges between different nodes in the computation graphs 1 indicate the dependencies between different process tasks. Next, for each process task, the orchestration model can edit the process task into multiple thread tasks. These thread tasks have dependencies, such as the execution of thread task A within the multiple thread tasks depending on the execution of thread task B first. Based on the dependencies between these multiple thread tasks, the programming model can generate computation graph 2. In actual application scenarios, each process task may correspond to a computation graph 2. In this way, the programming model can use computation graphs 1 and 2 to orchestrate process tasks and thread tasks.

[0043] Based on the programming model's orchestration results for process tasks and thread tasks (e.g., the aforementioned computational graphs 1 and 2), the task processing device can schedule multiple processor cores in the hardware layer 102 to execute the multiple thread tasks included in each process task in parallel. The data processing system 10 processes thread tasks based on a run-to-completion execution model, meaning that once a thread task begins execution, it continues executing until completion, and will not be interrupted by other thread tasks during its execution. Accordingly, resources used by the thread task during execution are not preempted by other thread tasks.

[0044] However, while the processor core is executing the lower-priority thread task, other higher-priority thread tasks are often waiting to be executed. In this case, the second thread task needs to wait until the processor core completes the first thread task before it can begin executing the second thread task. This causes the second thread task to be in the waiting state for a long time, resulting in a longer overall execution delay for the higher-priority thread task, affecting the service operation in the application layer 101, such as service response timeouts.

[0045] To this end, the task processing device 200 provided in the present application can control hardware resources such as processor cores in the hardware layer 102 to intersperse the execution of other tasks with higher priorities during the execution of tasks.

[0046] Specifically, for the thread first task with a lower priority, the task processing device 200 will split the thread first task into multiple subtasks before execution, and use the processor core in the hardware layer 102 to execute the first subtask of the multiple subtasks. In the process of executing the first subtask, there may be a thread second task with a higher priority that is currently waiting for execution. Then, when the task processing device 200 detects that the priority of the thread second task to be executed is higher than the priority of the thread first task, and the thread second task can also use the processor core to execute the thread second task, the task processing device 200 will give priority to using the processor core to execute the thread second task after completing the execution of the first subtask. After the thread second task is executed, the task processing device 200 will continue to execute the remaining subtasks in the first task (such as the second subtask, the third subtask, etc. obtained by splitting the thread first task).

[0047] Because the first thread task is split into multiple subtasks, during the execution of the first thread task, the task processing device 200 can execute the second thread task with a higher priority, which is issued by the application layer 101, after the first subtask of the currently executing first thread task is completed. That is, during the execution of the first thread task, the task processing device 200 will insert the second thread task with a higher priority, so that the second thread task does not need to wait for the entire first thread task to be completed before it can be executed. This reduces the processing delay of the second thread task with a higher priority, thereby meeting the processing delay requirements of the services in the application layer 101 for the second thread task, and optimizing the performance of the applications in the application layer 101.

[0048] In actual applications, when scheduling multiple processor cores in the hardware layer 102 to execute multiple thread tasks in parallel, the task processing device 200 can accelerate the processing of high-priority thread tasks through the above process, thereby completing the processing of the multiple thread tasks included in a process task. Furthermore, once the multiple thread tasks included in all process tasks have been processed in the above manner, the task generated by application 1 can be completed.

[0049] It is worth noting that the data processing system 10 shown in FIG1 is merely an example and is not intended to be limiting. For example, in actual application scenarios, the data processing system 10 also includes components such as the kernel of an operating system (not shown in FIG1 ). For another example, in other data processing systems, the application layer 101 may include a larger number of applications, and the types and numbers of programming models included in different applications may vary; or the hardware layer 102 may also include other types or quantities of hardware.

[0050] For ease of understanding, an embodiment of the task processing method provided in this application is described below with reference to the accompanying drawings.

[0051] Referring to FIG. 2 , FIG. 2 is a flow chart illustrating a task processing method provided in an embodiment of the present application. This method can be applied to the data processing system 10 shown in FIG. 1 , or can be applied to other applicable data processing systems. For ease of explanation, this embodiment is described using the data processing system 10 shown in FIG. 1 as an example.

[0052] The task processing method shown in FIG2 may specifically include:

[0053] S201: The task processing apparatus 200 obtains a first task to be executed.

[0054] In this embodiment, after a programming model (such as programming model 1) compiles multiple thread tasks and the corresponding computational graphs for each process task, the programming model can determine the first task that can currently be executed based on the dependencies between the different thread tasks indicated by the computational graph. The first task can be one of the multiple thread tasks. For example, the computational graph generated by the programming model can be shown in Figure 3. Figure 3 includes multiple nodes, each of which indicates a thread task; directed edges between different nodes indicate the execution dependencies between different thread tasks. For example, the directed edge between node 1 and node 3 indicates that the execution of the thread task identified by node 3 depends on the thread task identified by node 1 being executed first. Furthermore, the tasks identified by different nodes have different execution priorities. For example, in Figure 3, the thread tasks indicated by nodes 3 and 8 have a higher execution priority (higher than the execution priority of the thread tasks indicated by the remaining nodes). In this embodiment, the first task that can currently be executed as described in step S201 can be the lower-priority tasks indicated by nodes 4, 6, and 9.

[0055] Then, the programming model sends the first task to the kernel of the operating system through a first type of interface to request the kernel of the operating system to schedule resources for the first task to execute the first task. The first type of interface is the interface for the programming model to send thread tasks to the outside.

[0056] Accordingly, the task processing device 200 can continuously monitor the first type of interface (which can be one or more). Furthermore, when the programming model outputs a first task through the first type of interface, the task processing device 200 can intercept the first task sent by the programming model 1 to the kernel, so that the task processing device 200 can subsequently schedule resources for the first task, such as scheduling a processing unit to execute the first task. The scheduled processing unit can be a processor core in the hardware layer 102, and can also include other hardware such as an accelerator card and a network card.

[0057] Alternatively, after the programming model has programmed multiple thread tasks and generated a computation graph, the task processing device 200 can detect the currently executable thread task based on the dependencies between the different thread tasks indicated by the computation graph, i.e., detect the currently executable thread task that does not depend on other thread tasks to be executed first. Assuming that the currently executable thread task is detected to be the first task, the task processing device 200 schedules processor core 1 to execute the task for the first task.

[0058] In actual application, before the task processing device 200 obtains the first task, the task processing device 200 (or the runtime scheduler) may also pre-create user-mode resources based on the hardware in the hardware layer 102 to process the first task in the user mode. The created user-mode resources may be, for example, user-mode threads.

[0059] In a specific implementation, when application 1 is started, the programming model can request the operating system kernel through a second type of interface to create processor resources for executing tasks. The processor resources include multiple processor cores (or simply cores). Accordingly, the task processing device 200 can continuously monitor the second type of interface, and when the programming model outputs a request for processor resources through multiple second type interfaces, the task processing device 200 can intercept the request, request processor resources from the memory, and use the requested processor resources as user-mode resources. User-mode resources refer to processor resources used in user mode. For example, the task processing device 200 can create multiple user-mode threads based on the number of requested processor resources (i.e., multiple processor cores). User-mode threads, also known as user-level threads, are threads implemented in user programs without the support of the operating system kernel, and thread creation is completed in user space. Each user-mode thread can be responsible for scheduling a processor core and can be used to execute a thread task. In this case, the number of user-mode threads created by the task processing device 200 for each programming model can match the number of multiple processor cores in the hardware layer 102. For example, assuming that the hardware layer 102 includes 32 processor cores, the task processing device 200 can create 32 user-mode threads for each programming model from programming model 1 to programming model 3, resulting in a total of 96 user-mode threads. In this way, after the task processing device 200 creates multiple user-mode threads corresponding to a processor resource, the processor resource can be implemented as a user-mode resource.

[0060] In actual application, when the task processing device 200 starts running, it can first manage all hardware in the hardware layer 102, including the processor cores and the devices used by the processor cores (such as network cards, accelerators, DMA, etc.), to determine the hardware resources included in the hardware layer 102. The task processing device 200 can then notify each programming model of the hardware resource information included in the hardware layer 102 (such as the number of processor cores included in the hardware layer 102). In this way, each programming model can apply for the corresponding processor resources based on this hardware resource information, such as applying for the 32 processor cores included in the hardware layer 102.

[0061] After completing the creation of user-mode resources, when the first process task is started, that is, when the multiple thread tasks included in the first process task begin execution, the programming model can send a resource request to the kernel via the third type of interface to request the corresponding processor resources to execute the multiple thread tasks included in the first process task. Accordingly, the task processing device 200 can intercept the resource request and allocate user-mode resources to the first process task, that is, allocate the user-mode resources to the various thread tasks included in the first process task.

[0062] The following description will be made by taking the processing of the first task among multiple thread tasks and the allocation of user-mode resources as an example.

[0063] S202 : The task processing apparatus 200 splits the first task into multiple subtasks, where the multiple subtasks include a first subtask and a second subtask.

[0064] In this embodiment, before executing the first task using the allocated user-mode resources, the task processing apparatus 200 may first obtain the execution priority of the first task.

[0065] Among them, the priority of the execution of the first task can be specified by the technician / user. For example, the technician / user can define that the task issued by the OpenMP model has a lower priority to be executed, and define that the task issued by the SYCL model has a higher priority to be executed, etc. The first task (thread task) generated by the programming model can include priority information. For example, the first task can include a priority. When the priority is "high" or "1", it is used to indicate that the first task is executed with a higher priority, and when the priority is "low" or "0", it is used to indicate that the first task is executed with a lower priority.

[0066] Alternatively, the priority of the first task can be obtained through analysis by the task processing device 200. For example, the first task can include its type. When the type of the first task indicates that the first task is a data computing type or a data storage type task, the task processing device 200 can determine that the first task is executed with a lower priority. When the type of the first task indicates that the first task is a data movement type task (such as data backup, data migration, etc.), the task processing device 200 can determine that the first task is executed with a higher priority.

[0067] Therefore, after acquiring the first task, the task processing device 200 may further determine the priority of the first task to be executed. The priority may be identified by a corresponding value, mark, etc. For ease of understanding, this embodiment is described by taking the first task as a task with a lower priority as an example.

[0068] After determining that the first task is a task with a lower priority, the task processing apparatus 200 may split the first task into multiple subtasks, and the priorities of the multiple subtasks obtained by splitting are consistent with the execution priority of the first task.

[0069] As an example of implementing the first method of splitting the first task, when the programming model generates the first task based on the task class (task_base), the first task can include multiple task classes. Thus, the task processing device 200 can treat each task class as a subtask within the first task, thereby splitting the first task. A task class refers to a class defined for a task, and different classes can include different task contents.

[0070] As an example of implementing the second method of splitting the first task, the task processing device 200 can divide the execution logic of the first task into blocks, with each block of execution tasks serving as a subtask of the first task, thereby splitting the first task into multiple subtasks. For example, the first task may include multiple operators, each of which can be a block of execution logic. Thus, the task processing device 200 can split the first task into multiple subtasks at the operator granularity, with each subtask including at least one operator.

[0071] In actual application, the task processing device 200 may also use other methods to split the first task into multiple subtasks, and this is not limited.

[0072] The multiple subtasks corresponding to the first task can be executed in parallel. For example, the task processing device 200 can split the first task into subtask A, subtask B, and subtask C. The task processing device 200 can use multiple processor cores to execute subtask A and subtask B in parallel. After subtask A and subtask B are completed, subtask C can be executed using one processor core.

[0073] Alternatively, the multiple subtasks corresponding to the first task can be executed serially. For example, the task processing device 200 can split the first task into subtask a, subtask b, and subtask c, and the task processing device 200 uses one processor core to execute subtask a, subtask b, and subtask c in sequence.

[0074] For ease of explanation, in this embodiment, the multiple subtasks obtained by splitting the first task include a first subtask and a second subtask. The execution order of the first subtask is before the execution order of the second subtask, such as the execution of the second subtask depends on the execution result of the first subtask.

[0075] S203: The task processing apparatus 200 utilizes the processing unit to execute the first subtask in the first task.

[0076] After splitting the first task with a lower priority into multiple subtasks, the task processing device 200 can use the allocated user-state resources to execute the first subtask among the multiple subtasks. In this embodiment, the user-state resources allocated to the first subtask may include a processing unit, which includes a processor core. Furthermore, the processing unit may also include other hardware in the hardware layer 102, such as an accelerator such as a GPU. In a specific implementation, a user-state thread may run on the processing unit, and the processing unit may execute the first subtask based on the program logic indicated by the user-state thread.

[0077] S204 : During the execution of the first subtask, the task processing apparatus 200 obtains a second task to be executed.

[0078] For example, the task processing device 200 can obtain the second task output by the programming model by monitoring and intercepting the first type of interface. Alternatively, the task processing device can detect the currently executable second task from a computation graph generated by the programming model that indicates the execution dependencies between different thread tasks, and the like. This embodiment is not limited to this.

[0079] In actual applications, while the processor core (processing unit) in the hardware layer 102 is executing the first subtask, there may be other tasks that can also be started. These other tasks are the second tasks described in step S203. For example, if, during the execution of the first subtask, other tasks that the second task depends on are completed by other processor cores, the second task can be in an executable state and can be acquired by the task processing device 200.

[0080] S205 : The task processing device 200 detects whether the priority of the second task is higher than the priority of the first task. If not, the process proceeds to step S206 ; if yes, the process proceeds to step S207 .

[0081] In a specific implementation, the second task may carry priority indication information, so that the task processing device 200 can determine the priority of the second task based on the indication information. Alternatively, after obtaining the second task, the task processing device 200 can determine the priority of the second task based on the type of the second task. The implementation method for the task processing device 200 to obtain the priority of the second task can be found in the above description of obtaining the priority of the first task, and is not repeated here.

[0082] Then, the task processing device 200 can compare the priority of the second task with the priority of the first task to be executed, and determine whether the priority of the second task to be executed is higher than the priority of the first task currently being executed. If not, the task processing device 200 can wait for the first task to be completed before scheduling hardware resources to execute the second task, that is, executing step S206. If so, the task processing device 200 can insert the second task with a higher execution priority during the execution of the first task by executing step S207. In this embodiment, the priority of the second task is set to be higher than the priority of each subtask in the first task, and the execution of the second task requires the use of the same processing unit as the first subtask.

[0083] S206 : When it is detected that the priority of the second task is lower than the priority of the first task, the task processing device 200 waits for all subtasks in the first task to be completed before using the processing unit to execute the second task.

[0084] S207 : When it is detected that the priority of the second task is higher than the priority of the first task, the task processing device 200 uses the processing unit to preferentially execute the second task after executing the first subtask.

[0085] S208 : After the second task is completed, the task processing apparatus 200 executes the remaining subtasks in the first task.

[0086] That is, when the priority of the second task is higher, the remaining subtasks in the first task except the first subtask can be started after the second task is completed.

[0087] In a specific implementation, assuming the processing unit is a processor core, the task processing device 200 can monitor whether the processor core has completed the first subtask. If the first subtask has not been completed, the second task is placed in a waiting state until the task processing device 200 determines that the first subtask has been completed. At this point, the task processing device 200 can schedule the second task to the processor core, so that the processor core can begin executing the second task.

[0088] After completing the second task, the task processing device 200 uses the hardware resources in the hardware layer 102 to execute the remaining subtasks in the first task. For example, the task processing device 200 can call the processor core to continue executing the second subtask, the third subtask, and other remaining subtasks in the first task.

[0089] As an implementation example, the task processing device 200 can execute the various subtasks included in the first task based on the static scheduling strategy. In specific implementation, before the task processing device 200 executes the second task, the task processing device 200 can obtain the resource scheduling result corresponding to the first task. The resource scheduling result is used to indicate the processor core used to execute the multiple subtasks in the first task. In this embodiment, the first subtask and the second subtask are executed by the same processor unit as an example. The resource scheduling result can be the result generated by the task scheduling device 200 after splitting the first task and performing resource scheduling for the various subtasks in the first task.

[0090] In this way, after completing the execution of the second task, the task processing device 200 can continue to use the processing unit indicated by the resource scheduling result to execute the second subtask in the first task. That is, before and after inserting the execution of the second task, the hardware resources set for executing the second subtask remain unchanged. In this way, during the execution of the first task, even if the second task is interspersed, the task processing device 200 still continues to use processor core 1 to execute the remaining subtasks in the first task based on the previously set resource scheduling result, without having to reschedule hardware resources for the remaining subtasks. This can effectively reduce the overhead of resource scheduling, thereby improving the utilization of hardware resources.

[0091] Furthermore, when the data processing system 10 executes tasks in the run-to-completion mode, by splitting the first task into multiple subtasks, the execution of the second task with a higher priority can be interspersed during the execution of the first task. This allows the second task to be executed without waiting for the entire first task to be completed, thereby effectively reducing the overall execution delay of the second task and improving the execution efficiency of the second task. As shown in FIG3 , the second task can be executed at time T1, without having to wait until time T2, thereby shortening the execution delay of the second task by (T2-T1).

[0092] When the second task can be executed and completed first, the operation performance of the service in the application layer 101 corresponding to the second task can also be improved, such as the response delay of the service can be reduced, and the performance of application 1 can be optimized.

[0093] In actual application, the task processing device 200 can use processor resources to execute multiple thread tasks included in each process task based on the above method, so as to ensure that in the process of executing multiple thread tasks, the delay of thread tasks with higher priority waiting to be executed can be reduced, thereby improving the overall execution efficiency of the multiple threads, that is, improving the execution efficiency of the process task.

[0094] The process of the task processing device 200 executing a task is described by taking the example of the task processing device 200 obtaining the second task included in the same process task during the process of executing the first task. In other embodiments, programming models 1 to 3 in application 1 can all send multiple thread tasks to be executed through the first type of interface. Then, the task processing device 200 can intercept the multiple thread tasks, and the task processing device 200 can schedule the processor core to execute the thread task A with a lower priority issued by programming model 1, and in the process of executing the thread task A, obtain the thread task B with a higher priority issued by programming model 2. Then, the task processing device 200 can refer to the method described in the above embodiment, and after completing the execution of some subtasks in thread task A, give priority to executing thread task B, and after completing the execution of thread task B, continue to execute the remaining subtasks in thread task A, so as to improve the efficiency of the execution of thread task B. Its specific implementation method can be found in the above description of the execution of the first task and the second task, which will not be repeated here.

[0095] In addition, the processor resources allocated to the thread tasks by the task processing device 200 are user-state resources. This allows the same processor core to complete the switching in user state when switching to execute thread tasks generated by different programming models based on different time slices. For example, the user-state thread a required to execute thread task A generated by programming model 1 can be switched to the user-state thread b required to execute thread task B generated by programming model 2 on the processor core. This allows the processor core to switch the executed thread from user-state thread A to user-state thread B without having to execute the process of switching from user state to kernel state and then from kernel state to user state, thereby effectively reducing the overhead of thread switching.

[0096] In actual application, when the task processing device 200 obtains multiple thread tasks to be executed at the same time, if the task with a lower priority to be executed has not started execution, the task processing device 200 can determine the task with a higher priority among the multiple thread tasks that can be executed at present based on the execution dependency between the tasks, and preferentially allocate a processing unit to the task with a higher priority so that the task with a higher priority is executed first. After the thread task with a higher priority is executed, the task processing device 200 re-schedules the processing unit to start executing the thread task with a lower priority. If the thread task with a lower priority is executed before the thread task with a higher priority, the task processing device 200 can instruct to suspend the execution of the remaining subtasks of the thread task after the execution of some subtasks included in the thread task with a lower priority is completed, and preferentially schedule the processing unit to the task with a higher priority. After the task with a higher priority is executed, the task processing device 200 uses the processing unit to continue to execute the remaining unexecuted subtasks of the thread task with a lower priority.

[0097] It should be noted that the method embodiment shown in FIG2 is merely an example. Based on the method flow shown in FIG2 , the process of the task processing device 200 utilizing the hardware resources in the hardware layer 102 to execute tasks may also adopt the following embodiments.

[0098] Example 1: In the method embodiment shown in FIG2 , the first and second tasks acquired by task processing device 200 are thread tasks generated and sent by the same programming model. In other possible embodiments, multiple programming models in application 1 can each send multiple thread tasks with different priorities. In this case, task processing device 200 can follow the above method and prioritize the execution of higher-priority thread tasks.

[0099] Example 2: The method embodiment shown in FIG2 uses the example of the task processing device 200 interspersing the execution of a single, higher-priority second task during the execution of a first task as an example. In other possible embodiments, the task processing device 200 may simultaneously receive multiple, higher-priority tasks to be executed. For example, if the second and third tasks are received simultaneously, and the execution of the second and third tasks requires the use of the processing units used during the execution of the first subtask, then after the first subtask is completed, the task processing device 200 may schedule the processor core to prioritize the execution of the higher-priority second task. After the second task is completed, the processor core will continue to execute the higher-priority third task. Furthermore, after the third task is also completed, the task processing device instructs the processor core to continue executing the remaining unexecuted subtasks of the first task. In this way, while executing the lower-priority first task, the task processing device 200 can intersperse the execution of multiple, higher-priority thread tasks, namely the second and third tasks, thereby reducing the waiting execution latency of the data processing system 10 for multiple, higher-priority thread tasks.

[0100] Example 3: In addition to giving priority to executing thread tasks with higher priorities, the task processing device 200 can also execute multiple thread tasks with lower priorities in parallel. Furthermore, when the multiple thread tasks are issued by different programming models, the thread task processing device 200 can also instruct the processor core to execute different thread tasks assigned to the processor core in different time slices based on the time slice granularity. For example, assuming that the thread tasks assigned to the processor core include thread task x issued by programming model 1 and thread task y issued by programming model 2, the task processing device 200 can schedule the processor core to execute thread task x in time slice 1; when time slice 1 ends, even if thread task x has not been completed, the processor core will stop executing thread task x and start executing thread task y in the adjacent time slice 2 (that is, the next time slice of time slice 1). Similarly, after time slice 2 ends, regardless of whether thread task y has completed execution, the processor core will stop executing thread task y and resume executing thread task x in the immediately following time slice 3 (the time slice after time slice 2). Similarly, within a period of time (including multiple time slices), a single processor core can concurrently execute thread tasks issued by different programming models.

[0101] In addition, for multiple thread tasks issued by multiple thread models, the thread task processing device 200 can not only instruct the processor core to execute thread tasks issued by different programming models at the granularity of time slices, but also supports the execution of thread tasks at other granularities. For example, the task processing device 200 can support the processor core to execute each thread task at the granularity of thread tasks. That is, within a period of time, the processor core will start to execute a thread task issued by programming model 2 only after completing the execution of a thread task issued by programming model 1. For another example, the thread task processing device 200 can support the processor core to execute thread tasks issued by different programming models at a user-defined granularity, and there is no limitation on this.

[0102] It is worth noting that other reasonable step combinations that can be thought of by those skilled in the art based on the above description also fall within the scope of protection of this application. Secondly, those skilled in the art should also be familiar with that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by this application.

[0103] The task processing method provided in the embodiment of the present application is introduced above with reference to FIG. 1 to FIG. 4 . Next, the structure of the task processing apparatus and computing device provided in the embodiment of the present application is introduced with reference to the accompanying drawings.

[0104] 5 , which shows a schematic structural diagram of a task processing device, the task processing device 500 includes:

[0105] An execution module 501 is configured to execute a first task, where the first task includes multiple subtasks, and the subtask being executed is the first subtask;

[0106] A detection module 502 is configured to detect that the priority of the second task to be executed is higher than the priority of the first task;

[0107] The execution module 501 is also used to detect that the priority of the second task to be executed is higher than the priority of the first task. After executing the first subtask, it executes the second task, and the first subtask and the second task are executed by the same processing unit; after the second task is completed, the remaining subtasks in the first task are executed.

[0108] In a possible implementation, the task processing device 500 further includes:

[0109] an identification module 503, configured to identify the first task as a low-priority task according to the type of the first task before executing the first task;

[0110] The division module 504 is configured to divide the first task into a plurality of subtasks.

[0111] In one possible implementation, the first task includes multiple task classes;

[0112] The division module 504 is configured to divide the first task into a plurality of subtasks according to a plurality of task classes, wherein each of the plurality of subtasks includes at least one task class.

[0113] In one possible implementation, the first task includes a plurality of operators;

[0114] The division module 504 is configured to divide the first task into a plurality of subtasks according to the plurality of operators, where each of the plurality of subtasks includes at least one operator.

[0115] In a possible implementation, the first task and the second task are thread tasks in the first process task, and the task processing device 500 further includes:

[0116] An editing module 505 is configured to edit the first process task into a first computation graph including the first task and the second task according to the editing model, wherein the first computation graph sets dependencies between different thread tasks in the first process task;

[0117] The detection module 502 is configured to detect the second task from the first computation graph.

[0118] In a possible implementation, the task processing device 500 may be a runtime scheduler, and the task processing device 500 further includes:

[0119] An application module 506 is used to apply for processor resources from the kernel when the application starts, and use the processor resources as user-mode resources. The processor resources include multiple cores.

[0120] The interception module 507 is used to intercept the resource application request of the first process when the first process task is started, and allocate user-mode resources to the first process task.

[0121] In a possible implementation, the task processing device 500 further includes:

[0122] An acquisition module 508 is configured to acquire a resource scheduling result before executing the second task, where the resource scheduling result indicates that the plurality of subtasks are to be executed by the first processor core;

[0123] Then, the execution module 501 is configured to execute the remaining subtasks of the first task using the first processor core according to the resource scheduling result after the second task is completed.

[0124] In a possible implementation, the application includes multiple programming models, such as a first programming model and a second programming model. Then, the application can edit different process tasks into multiple thread tasks through different programming models.

[0125] Since the task processing device 500 shown in Figure 5 corresponds to the task processing device 200 in the embodiment shown in Figure 2 above, the specific implementation method of the task processing device 500 shown in Figure 5 and its technical effects can be found in the relevant description of the embodiment shown in Figure 2 above, and will not be repeated here.

[0126] FIG6 is a schematic diagram of the hardware structure of a computing device 600 provided in the present application. The computing device 600 can, for example, implement the task processing apparatus 200 in the embodiment shown in FIG2 .

[0127] As shown in Figure 6, the computing device 600 includes a processor 601, a memory 602, and a communication interface 603. The processor 601, the memory 602, and the communication interface 603 communicate via a bus 604, and may also communicate via other means such as wireless transmission. The memory 602 is used to store instructions, and the processor 601 is used to execute the instructions stored in the memory 602. Furthermore, the computing device 600 may also include a memory unit 605, and the memory unit 605 may be connected to the processor 601, the storage medium 602, and the communication interface 603 via a bus 604. The memory 602 stores program code, and the processor 601 may use the program code stored in the memory 602 to perform the following operations:

[0128] Executing a first task, where the first task includes multiple subtasks, and the subtask being executed is the first subtask;

[0129] When it is detected that the priority of the second task to be executed is higher than the priority of the first task, the second task is executed after the first subtask is executed, and the first subtask and the second task are executed by the same processing unit;

[0130] After the second task is completed, the remaining subtasks in the first task are executed.

[0131] It should be understood that in this embodiment, the processor 601 may be a CPU, or may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete device components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0132] The memory 602 may include a read-only memory and a random access memory, and provides instructions and data to the processor 601. The memory 602 may also include a nonvolatile random access memory.

[0133] The memory 602 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0134] The communication interface 603 is used to communicate with other devices connected to the computing device 600. In addition to the data bus, the bus 604 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are labeled as bus 604 in the figure.

[0135] It should be understood that the computing device 600 according to the embodiment of the present application may correspond to the task processing device 500 in the embodiment of the present application, and may correspond to executing the method executed by the task processing device 200 in the method shown in Figure 2 in the embodiment of the present application. The above-mentioned and other operations and / or functions implemented by the computing device 600 are respectively for implementing the process of the corresponding method in Figure 2. For the sake of brevity, they will not be repeated here.

[0136] The present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by a computing device, or a data storage device such as a data center that contains one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to execute the above-mentioned task processing method.

[0137] The present application also provides a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the computer program product fully or partially generates the process or function described in the present application.

[0138] The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, or data center to another website, computer, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0139] The computer program product may be a software installation package. When any of the aforementioned task processing methods is required, the computer program product may be downloaded and executed on a computing device.

[0140] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0141] The terms used in the above embodiments are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification of this application and the appended claims, the singular expressions "a", "an", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless the context clearly indicates otherwise. It should also be understood that in the embodiments of the present application, "one or more" refers to one, two or more; the character " / " generally indicates that the objects before and after are in an "or" relationship. In the embodiments of the present application. "Simultaneously" refers to the same time period, including the situation at the same moment.

[0142] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0143] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A task processing method, characterized in that, The method includes: Performing a first task, where the first task includes multiple subtasks, and the subtask being executed is the first subtask; When it is detected that the priority of a second task to be executed is higher than the priority of the first task, after the first subtask is executed, the second task is executed, and the first subtask and the second task are executed by the same processing unit; After the second task is executed, the remaining subtasks in the first task are executed.

2. The method according to claim 1, characterized in that, The method further includes: Before executing the first task, identifying the first task as a low-priority task according to the type of the first task; Dividing the first task into the multiple subtasks.

3. The method according to claim 2, wherein The first task includes multiple task classes, and the dividing the first task into the multiple subtasks includes: Dividing the first task into the multiple subtasks according to the multiple task classes, where each subtask in the multiple subtasks includes at least one task class.

4. The method according to claim 2, wherein The first task includes multiple operators, and the dividing the first task into the multiple subtasks includes: Dividing the first task into the multiple subtasks according to the multiple operators, where each subtask in the multiple subtasks includes at least one operator.

5. The method according to any one of claims 1 to 4, characterized in that, The first task and the second task are thread tasks in a first process task, and the method further includes: Editing the first process task into a first computation graph including the first task and the second task according to an editing model, where the dependency relationship between different thread tasks in the first process task is set in the first computation graph; Detecting the second task from the first computation graph.

6. The method according to any one of claims 1 to 5, characterized in that, The method includes: When the application starts, the runtime scheduler applies to the kernel for processor resources and takes the processor resources as user-mode resources, where the processor resources include multiple cores; When the first process task starts, the runtime scheduler intercepts the resource application request for the first process task and allocates the user-mode resources to the first process task.

7. The method according to any one of claims 1 to 6, characterized in that The method further includes: Before executing the second task, obtaining a resource scheduling result, where the resource scheduling result indicates that the multiple subtasks are executed by a first processor core; Then, the executing the remaining subtasks in the first task after the second task is executed includes: After the second task is executed, according to the resource scheduling result, using the first processor core to execute the remaining subtasks in the first task.

8. A task processing device, characterized in that, The apparatus includes: An execution module for executing a first task, where the first task includes multiple subtasks, and the subtask being executed is the first subtask; A detection module for detecting that the priority of a second task to be executed is higher than the priority of the first task; The execution module is further configured to, when it is detected that the priority of the second task to be executed is higher than the priority of the first task, execute the second task after the first subtask is executed, where the first subtask and the second task are executed by the same processing unit; and execute the remaining subtasks in the first task after the second task is executed.

9. The device according to claim 8, wherein The apparatus further includes: An identification module, configured to identify, before executing the first task, the first task as a low-priority task according to the type of the first task; A division module, configured to divide the first task into the multiple subtasks.

10. The device according to claim 9, characterized in that, The first task includes multiple task classes; The division module is configured to divide the first task into the multiple subtasks according to the multiple task classes, and each subtask of the multiple subtasks includes at least one task class.

11. The device according to claim 9, characterized in that, The first task includes multiple operators; The division module is configured to divide the first task into the multiple subtasks according to the multiple operators, and the multiple subtasks Each subtask of them includes at least one operator.

12. The device according to any one of claims 8 to 11, characterized in that, The first task and the second task are thread tasks in a first process task, and the apparatus further includes: An editing module, configured to edit the first process task into a first computation graph including the first task and the second task according to an editing model, and dependencies between different thread tasks in the first process task are set in the first computation graph; A detection module, configured to detect the second task from the first computation graph.

13. The device according to any one of claims 8 to 12, characterized in that, The apparatus further includes: An application module, configured to, when the application starts, a runtime scheduler applies to the kernel for processor resources and uses the processor resources as user-mode resources, and the processor resources include multiple cores; An interception module, configured to, when the first process task starts, the runtime scheduler intercepts a resource application request of the first process and allocates the user-mode resources to the first process task.

14. The device according to any one of claims 8 to 13, characterized in that, The apparatus further includes: An acquisition module, configured to acquire a resource scheduling result before executing the second task, where the resource scheduling result indicates that the multiple subtasks are executed by a first processor core; Then, an execution module, configured to, after the second task is executed, execute the remaining subtasks in the first task by using the first processor core according to the resource scheduling result.

15. A computing device, characterized in that, Including a processor and a memory; The processor is configured to execute instructions stored in the memory, so that the computing device executes the steps of the method according to any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that, Including instructions, when running on a computing device, enabling the computing device to execute the steps of the method according to any one of claims 1 to 7.

17. A computer program product comprising instructions, characterized in that, When running on at least one computing device, enabling the at least one computing device to execute the method according to any one of claims 1 to 7.

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