Semiconductor device, electronic apparatus and semiconductor device manufacturing method

Abstract

The present application relates to the technical field of semiconductors. Provided in the embodiments of the present application are a semiconductor device, an electronic apparatus and a semiconductor device manufacturing method. The semiconductor device comprises a substrate, a fin structure and a gate; the fin structure is arranged on the substrate, and the fin structure comprises conductive parts and channel parts which are alternately arranged in a first direction; the channel parts comprise a plurality of spaced channel layers which are stacked in the direction away from the substrate; the gate is arranged surrounding the surface of each channel layer among the plurality of channel layers; at least two channel layers among the plurality of channel layers have different sizes in the first direction, the first direction being parallel to the substrate. The semiconductor device can achieve the purpose of uniform electrical properties of the fin structure at different positions by means of a simple structural configuration, thus effectively improving the reliability of the semiconductor device.

Description

Semiconductor device, electronic device, and method for manufacturing semiconductor device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 28, 2023, with application number 202311847458.6 and application name “Semiconductor devices, electronic devices and methods for preparing semiconductor devices”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, an electronic device, and a method for manufacturing a semiconductor device. Background Art

[0003] In advanced process technologies, the transistors of integrated circuits mostly use Fin Field-Effect Transistors (FinFETs). However, as process precision reaches below 5nm, FinFETs will also face problems such as increased electrostatic coupling, parasitic capacitance, and increased off-state leakage.

[0004] At present, a new transistor architecture has been introduced in the field, namely the Gate All Around Field-Effect Transistor (GAA FET). GAA FET is a non-planar transistor. Compared with planar transistors of the same area, it has a larger effective gate width (Weff), higher channel density and performance, and a larger driving switching current per unit area of ​​the transistor. In addition, the gate of GAAFET is set around its multi-layer channel layer (such as nanowires / nanosheets), which can enhance the control of the current in the channel layer, facilitate the depletion of majority carriers in the channel layer, reduce the short channel effect, and thus improve the response speed of the transistor.

[0005] However, due to process errors and other reasons, there are differences between different channel layers. For example, the doping concentration may be different, which leads to electrical non-uniformity at different locations of the GAA FET, greatly reducing the reliability of the device.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a semiconductor device, an electronic device, and a method for manufacturing a semiconductor device, with the aim of achieving uniform electrical properties at different positions of a GAA FET through a simple structural design, thereby effectively improving the reliability of the semiconductor device.

[0008] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0009] In a first aspect, a semiconductor device is provided. The semiconductor device includes a substrate, a fin structure, and a gate.

[0010] The fin structure is provided on a substrate and includes a conductive portion and a channel portion alternately arranged along a first direction. The channel portion includes multiple channel layers stacked and spaced apart in a direction away from the substrate. A gate is provided around the surface of each channel layer in the multiple channel layers. At least two of the multiple channel layers have different dimensions in the first direction; the first direction is parallel to the substrate.

[0011] In the semiconductor device provided in the embodiments of the present application, by setting a multi-layer channel layer, at least two channel layers have different dimensions (i.e., lengths) in a first direction, the electrical performance of the multi-layer channel layers is made relatively uniform. That is, by controlling the length of the channel layer, the electrical performance of the channel layer is regulated. For example, by setting a smaller length corresponding to the channel layer with a smaller saturation current in the multi-layer channel layer, the saturation current of the multi-layer channel layer is made closer to the same, thereby optimizing the uniformity of the electrical performance of the semiconductor device, improving the reliability of the semiconductor device, and facilitating the continued development of technology nodes.

[0012] Compared with the technical means of regulating electrical properties by doping concentration in related technologies, the regulation of electrical properties by the length of the channel layer in the embodiment of the present application is relatively simple. The length of the channel layer can be changed only by controlling the etching position, and the degree of refinement is high, the error is small, and the effect of achieving uniformity of electrical properties of semiconductor devices is better.

[0013] The embodiment of the present application adds a control means (i.e., length control) for regulating the electrical performance of semiconductor devices. The means of regulating the electrical performance of the device by the length of the channel layer can be combined with the means of regulating the electrical performance of the device by the doping concentration of the channel layer, thereby regulating the uniformity of the electrical performance of the semiconductor device from multiple dimensions, further optimizing the control effect on the uniformity of the electrical performance of the semiconductor device, and further improving the reliability of the semiconductor device.

[0014] In addition, in the embodiment of the present application, by designing the length of the channel layer differently, the stress on the multi-layer channel layer as a whole can be dispersed, avoiding the situation where the channel layer bends under the action of stress due to the relatively concentrated stress when the length of the multi-layer channel layer is exactly the same, thereby improving the structural stability of the semiconductor device.

[0015] In a possible implementation of the first aspect, two channel layers with different sizes in the first direction have the same saturation current, thereby ensuring that the electrical performance of the semiconductor device at different channel layer locations is substantially the same, thereby improving the reliability of the semiconductor device.

[0016] In a possible implementation of the first aspect, among the multiple channel layers, a channel layer with a lower doping concentration has a smaller dimension in the first direction. That is, the length of the channel layer can be set based on the doping concentration of the channel layer. For example, after detecting a pattern of changes in the doping concentration of the channel layer, the length of the channel layer can be adaptively and regularly set to compensate for differences in electrical properties caused by differences in doping concentration.

[0017] In a possible implementation of the first aspect, two channel layers having different dimensions in the first direction have the same width-to-length ratio. The width-to-length ratio is the ratio of the dimension of the channel layer in the second direction to the dimension in the first direction. The second direction is parallel to the substrate and perpendicular to the first direction. In other words, by controlling the length of the channel layers, the width-to-length ratios of different channel layers can be made the same, thereby ensuring that the saturation currents corresponding to the different channel layers are the same. This improves the uniformity of the electrical performance of the semiconductor device at different locations, thereby optimizing the reliability of the semiconductor device.

[0018] In a possible implementation of the first aspect, among the multiple channel layers, a channel layer with a smaller dimension in the second direction also has a smaller dimension in the first direction. This allows the multiple channel layers to maintain a substantially uniform width-to-length ratio, ensuring that the saturation currents corresponding to different channel layers are the same. This improves the uniformity of the electrical performance of the semiconductor device at different locations, thereby optimizing the reliability of the semiconductor device.

[0019] In a possible implementation of the first aspect, the dimensions of the multi-layer channel layer in the second direction and in the first direction gradually decrease as they move away from the substrate. This ensures uniform electrical performance of the semiconductor device while avoiding the difficulty of etching the fin structure due to a high aspect ratio, thereby reducing the difficulty of manufacturing the semiconductor device.

[0020] In a possible implementation of the first aspect, two side surfaces of the channel portion that are disposed opposite each other in the first direction are inclined, and on the same side, side surfaces of different channel layers are located in the same plane. Thus, during the etching process, only a single etching cut at an inclined angle can be performed to achieve the goal of gradually decreasing the length of the multi-layer channel layer as it moves away from the substrate.

[0021] In a possible implementation of the first aspect, two side surfaces of the channel portion that are opposite to each other in the first direction are arranged in a stepped manner.

[0022] In a possible implementation manner of the first aspect, a size of the conductive portion in the first direction gradually increases in a direction away from the substrate.

[0023] By setting the length of the conductive part to gradually increase in the direction away from the substrate, on the one hand, the conductive part can adapt to the trend of the length of the multi-layer channel layer gradually decreasing, thereby facilitating the conductive part (source and / or drain) to always maintain contact with the channel layer, ensuring the smooth opening and closing of the semiconductor device. On the other hand, the length of the end of the conductive part away from the substrate is larger, so that the area of ​​its top is larger, thereby making the process window larger when setting the contact structure on the top of the conductive part, thereby reducing the difficulty of preparing the contact structure and improving the electrical connection performance between the conductive part and the contact structure.

[0024] In a possible implementation of the first aspect, at least two portions of the gate have different sizes in the first direction, and the larger the size of the channel layer in the first direction, the larger the size of the portion of the gate corresponding to the channel layer surrounding the channel layer in the first direction.

[0025] That is, the size of the gate in the first direction changes with the size of the channel layer it surrounds in the first direction, so that the gate can completely surround the channel layer, thereby ensuring control of the channel in the channel layer while avoiding the problem that the size of the gate in the first direction is too large, which increases the difficulty of preparing the conductive part, or causes the distance between the conductive part and the channel layer to be too large, resulting in a decrease in channel transmission efficiency.

[0026] In a possible implementation of the first aspect, the dimensions of the multilayer channel layer in the first direction gradually decrease in a direction away from the substrate, and two side surfaces of the multilayer channel layer that are opposite to each other in the first direction are arranged in a stepped manner. Two side surfaces of the gate that are opposite to each other in the first direction are arranged in a stepped manner, and the stepped side surfaces of the gate match the shape of the stepped side surfaces of the multilayer channel layer.

[0027] In a possible implementation of the first aspect, the semiconductor device further includes a spacer layer, the spacer layer being disposed on two side surfaces of the gate that are opposite each other in the first direction. Where the two side surfaces of the gate that are opposite each other in the first direction are arranged in a stepped configuration, a surface of the spacer layer is arranged in a stepped configuration, and the stepped surface of the spacer layer matches the shape of the stepped side surfaces of the gate.

[0028] In a second aspect, a method for preparing a semiconductor device is provided, the method comprising:

[0029] A fin structure is formed on a substrate; the fin structure includes a sacrificial layer and a channel layer alternately stacked in a direction away from the substrate. A dummy gate is formed; the dummy gate is arranged across the fin structure, and at least two portions of the dummy gate arranged in a direction away from the substrate have different sizes in a first direction; the first direction is parallel to the substrate; the portion of the fin structure covered by the dummy gate is a channel portion, which includes a multilayer channel layer, and the channel layer is a portion of the semiconductor layer covered by the dummy gate; at least two channel layers in the multilayer channel layer have different sizes in the first direction. The portion of the fin structure not covered by the dummy gate is removed and replaced with a conductive portion; the conductive portion and the channel portion are alternately arranged in the first direction. The dummy gate and the sacrificial layer are removed and replaced with a gate; the gate surrounds the surface of each channel layer in the multilayer channel layer.

[0030] The preparation method provided in the embodiment of the present application can prepare a semiconductor device with at least two channel layers of different lengths. That is, the preparation method provided in the embodiment of the present application can effectively regulate the electrical properties corresponding to multiple channel layers in the semiconductor device by changing the length of the channel layer, so that the electrical properties corresponding to the multiple channel layers are more uniform, thereby improving the reliability of the semiconductor device.

[0031] In addition, in semiconductor devices with a high aspect ratio, compared with the fact that the lengths of the multi-layer channel layers are exactly the same, the design of different lengths of the multi-layer channel layers in the embodiment of the present application is conducive to filling materials at deeper locations. For example, it is conducive to filling the gate at the surface of the channel layer closest to the substrate, avoiding the formation of voids or uneven filling problems at this location, and avoiding affecting the DC performance of the semiconductor device.

[0032] In a third aspect, an integrated circuit is provided, comprising an electronic device and the semiconductor device provided by any one of the embodiments in the first aspect, wherein the electronic device is electrically connected to the semiconductor device.

[0033] In a fourth aspect, an electronic device is provided, comprising a circuit board and the integrated circuit provided in the embodiment of the third aspect, wherein the integrated circuit is provided on the circuit board and electrically connected to the circuit board.

[0034] The technical effects brought about by the integrated circuit in the third aspect and the electronic device in the fourth aspect can be referred to the technical effects brought about by the design method of the semiconductor device in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0036] FIG2 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0037] FIG3 is a cross-sectional view taken along the section line AA′ in FIG2 ;

[0038] FIG4 is a cross-sectional view along the section line BB' in FIG2;

[0039] FIG5 is another cross-sectional view along the section line BB' in FIG2;

[0040] FIG6 is another cross-sectional view along the section line BB' in FIG2;

[0041] FIG7 is another cross-sectional view along the section line BB' in FIG2;

[0042] FIG8 is another cross-sectional view of a semiconductor device provided in an embodiment of the present application;

[0043] FIG9 is a side view taken along the direction C in FIG2 ;

[0044] FIG10 is a flow chart of the preparation of a semiconductor device according to an embodiment of the present application;

[0045] 11 to 18 are schematic structural diagrams corresponding to various steps of manufacturing a semiconductor device. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0047] In the description of this application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first," "second," etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the terms "coupled," "connected," and their derivatives may be used. The terms "coupled" and "connected" should be understood broadly. For example, "connected" can mean a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediary. The embodiments disclosed herein are not necessarily limited to the contents herein.

[0051] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0052] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0053] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0054] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0055] In addition, the scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art will know that with the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0056] The embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk maker, a robot vacuum), an unmanned aerial vehicle (UAV), a radar, an aerospace equipment, an on-board device, a vehicle, or other different types of user devices or terminal devices; the electronic device may also be a network device such as a base station. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic device.

[0057] FIG1 is a schematic diagram of the structure of an electronic device exemplarily provided in an embodiment of the present application. As shown in FIG1 , the electronic device 1000 includes an integrated circuit 100 and a circuit board 200 , on which the integrated circuit 100 may be disposed.

[0058] Exemplarily, the circuit board 200 may be a printed circuit board (PCB).

[0059] It will be understood that the structure of the electronic device 1000 shown in FIG1 does not constitute a specific limitation on the electronic device 1000. The electronic device 1000 may include more or fewer components than those shown in FIG1 , or may combine some of the components shown in FIG1 , or may have a different arrangement of components than that shown in FIG1 .

[0060] The embodiment of the present application also provides an integrated circuit 100 .

[0061] For example, as shown in FIG1 , the integrated circuit 100 may include a logic circuit 101 , an analog circuit 102 , a storage circuit 103 , an input / output circuit 104 , and the like.

[0062] It should be understood that the integrated circuit 100 includes but is not limited to a logic circuit 101, an analog circuit 102, a storage circuit 103 and an input / output circuit 104. For example, in addition to the aforementioned four circuits, the integrated circuit 100 may also include circuits of other types or functions, or force dividers.

[0063] Furthermore, the integrated circuit 100 may include one or more of a logic circuit 101 , an analog circuit 102 , a memory circuit 103 , and an input-output circuit 104 .

[0064] Based on this, the number of logic circuits 101, analog circuits 102, memory circuits 103, and input / output circuits 104 included in the integrated circuit 100 can be set as needed. The integrated circuit 100 may include one or more logic circuits 101. The integrated circuit 100 may also include one or more analog circuits 102. The integrated circuit 100 may also include one or more memory circuits 103. The integrated circuit 100 may also include one or more input / output circuits 104.

[0065] 1 , an integrated circuit 100 may include a semiconductor device 10 and some electronic devices 20 . The electronic devices 20 are electrically connected to the semiconductor device 10 .

[0066] For example, referring to FIG. 1 , the semiconductor device 10 and the electronic device 20 may be integrated into a logic circuit 101 . The semiconductor device 10 and the electronic device 20 in the logic circuit 101 cooperate with each other to implement functions such as “AND”, “OR”, and “NOT” in the logic circuit 101 .

[0067] For example, the electronic device 20 may be a resistor, a capacitor, or other electronic device.

[0068] For example, the semiconductor device 10 and the electronic device 20 may also be provided in other circuits, for example, in the storage circuit 103 , and this application does not impose any specific limitation on this.

[0069] The present invention also provides a semiconductor device 10. FIG2 is a schematic structural diagram of the semiconductor device 10 provided in the present invention. FIG3 is a cross-sectional view along the section line AA' in FIG2, and FIG4 is a cross-sectional view along the section line BB' in FIG2.

[0070] In some embodiments, as shown in FIG. 2 , FIG. 3 and FIG. 4 , the semiconductor device 10 includes a substrate 1 , a fin structure 2 and a gate 3 .

[0071] Exemplarily, the material of substrate 1 can be a semiconductor material. For example, it can be one of bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), and silicon germanium-on-insulator (SGOI). The present embodiment of the present application does not limit the material of substrate 1.

[0072] Exemplarily, at least a portion or the entirety of the substrate 1 may be doped, for example, may be P-type doped or N-type doped.

[0073] 2 , 3 and 4 , the fin structure 2 is disposed on a substrate 1 .

[0074] Exemplarily, referring to FIG. 2 , FIG. 3 and FIG. 4 , the fin structure 2 extends along a first direction X, that is, the length extension direction of the fin structure 2 is the first direction X.

[0075] The first direction X is parallel to the substrate 1 .

[0076] 4 , the fin structure 2 includes conductive portions 22 and channel portions 21A alternately arranged along a first direction X.

[0077] 3 and 4 , the channel portion 21A includes a plurality of channel layers 21 . The plurality of channel layers 21 are stacked and spaced apart in a direction away from the substrate 1 .

[0078] The multilayer channel layer 21 includes a semiconductor material to form a metal oxide semiconductor field effect transistor, for example, a gate-all-around transistor (GAA FET). The channel layer 21 is a region of the transistor for forming a channel.

[0079] For example, the channel layer 21 may be a nanowire (NW) or a nanosheet (NS).

[0080] It can be understood that the semiconductor device 10 may include a plurality of fin structures 2 arranged along the second direction Y, and a plurality of transistors may be formed on one fin structure 2, each transistor including a channel portion 21A (i.e., a multilayer channel layer 21). Figures 2, 3, and 4 only illustrate the example that the semiconductor device 10 includes one fin structure 2, and one fin structure 2 corresponds to forming one transistor, and do not limit the number of fin structures 2 in the semiconductor device 10 and the number of transistors formed.

[0081] 2 and 4 , the fin structure 2 may include a plurality of conductive portions 22 .

[0082] For example, referring to FIG4 , a conductive portion 22 may be provided on each of two sides of a channel portion 21A (i.e., a multilayer channel layer 21) that are oppositely disposed along the first direction X. For example, referring to FIG2 and FIG4 , a transistor may have two conductive portions 22, with each of two sides of the channel portion 21A (i.e., a multilayer channel layer 21) that are oppositely disposed along the first direction X having a conductive portion 22 provided thereon. It will be appreciated that a transistor may further include multiple channel portions 21A and multiple conductive portions 22, and the embodiments of the present application do not limit the number of channel portions 21A and conductive portions 22 in the transistor.

[0083] The conductive portion 22 is used to form the source and drain of the transistor in the semiconductor device 10. For example, referring to FIG4 , two conductive portions 22 disposed on either side of the channel portion 21A (i.e., the multilayer channel layer 21) along the first direction X serve as the source and drain of the transistor in the semiconductor device 10, respectively.

[0084] The multilayer channel layer 21 in the channel portion 21A is used as the channel region of the transistor in the semiconductor device 10. Referring to Figure 4, in the multilayer channel layer 21, the two side surfaces of each channel layer 21 that are opposite to each other along the first direction X are in contact with the conductive portion 22, so that after a channel is formed in the multilayer channel layer 21 under the control of the gate 3, conduction between the two conductive portions 22 on both sides of the channel layer 21 (i.e., between the source and the drain) can be achieved.

[0085] Exemplarily, the doping type of the conductive portion 22 is different from the doping type of the channel layer 21 .

[0086] Exemplarily, the doping concentration of the conductive portion 22 is greater than the doping concentration of the channel layer 21 .

[0087] For example, the conductive portion 22 may be formed by using an epitaxial growth method and an etching process.

[0088] For example, the conductive portion 22 may be P-type doped or N-type doped by selecting the epitaxial material and the type of doped atoms.

[0089] Exemplarily, the material of the conductive portion 22 may be a germanium-silicon mixture, for example.

[0090] Exemplarily, the conductive portion 22 is doped with a high concentration, thereby improving the conductivity of the conductive portion 22 (ie, the source and the drain).

[0091] For example, the shape of the conductive portion 22 can be customized. For example, the conductive portion 22 can be in the shape of a quadrangular pyramid. Alternatively, as shown in FIG. 2 , the conductive portion 22 can be in the shape of a rectangular parallelepiped. Alternatively, the conductive portion 22 can be in an irregular shape, which is not limited herein.

[0092] For example, referring to FIG. 4 , the size of the conductive portion 22 in the thickness direction of the substrate 1 (ie, the third direction Z) may be smaller than the size of the fin structure 2 in the thickness direction of the substrate 1 .

[0093] For example, referring to Figures 2, 3, and 4, the fin structure 2 may further include a well structure 23. As shown in Figures 3 and 4, at least a portion of the well structure 23 is located between the substrate 1 and the conductive portion 22. The sum of the dimensions of the conductive portion 22 and the well structure 23 in the thickness direction of the substrate 1 (i.e., the third direction Z) is approximately equal to the dimension of the fin structure 2 in the thickness direction of the substrate 1.

[0094] Exemplarily, the well structure 23 and the conductive portion 22 have different doping concentrations. For example, the doping concentration of the well structure 23 is lower than the doping concentration of the conductive portion 22 .

[0095] Exemplarily, referring to FIG. 4 , at least a portion of the well structure 23 is also located between the substrate 1 and the channel layer 21 .

[0096] Exemplarily, the well structure 23 may be integrally formed with the channel layer 21 , that is, the well structure 23 and the channel layer 21 may have the same doping concentration and doping type.

[0097] Exemplarily, the well structure 23 may also be integrally formed with the substrate 1 .

[0098] 2 , 3 and 4 , the gate 3 in the semiconductor device 10 is disposed across the fin structure 2 and surrounds the surface of each channel layer 21 in the multi-layer channel layer 21 .

[0099] For example, referring to Figure 3, at least part of the gate 3 is stacked with the channel layer 21 in the third direction Z, so that at least part of the gate 3 is arranged above and below the channel layer 21 (taking the orientation in Figure 3 as an example), and referring to Figure 3, part of the gate 3 is also arranged on two side surfaces of the channel layer 21 that are opposite to each other along the second direction Y.

[0100] It can be understood that, referring to FIG. 4 , two side surfaces of the channel layer 21 that are opposite to each other along the first direction X are used to contact the conductive portion 22 , and therefore no gate 3 is disposed thereon.

[0101] The gate 3 is used to control the formation of a channel in the channel layer 21, thereby controlling the conduction between the two conductive parts 22 located on both sides of the channel layer 21, or controlling no channel to be formed in the channel layer 21, so that the two conductive parts 22 located on both sides of the channel layer 21 are disconnected. That is, the gate 3 is used to control the opening and closing of the transistor in the semiconductor device 10.

[0102] By having the gate 3 surround the surface of each channel layer 21 in the multi-layer channel layer 21 , the control capability of the gate 3 over the channel in the channel layer 21 can be effectively improved, thereby improving the electrical performance of the semiconductor device 10 .

[0103] For example, referring to Figures 2, 3 and 4, the semiconductor device 10 also includes a gate oxide layer 5, which is arranged between the gate 3 and the channel layer 21 to achieve electrical insulation between the gate 3 and the channel layer 21, thereby facilitating the gate 3 to control the channel in the channel layer 21.

[0104] For example, referring to FIG. 2 and FIG. 3 , the semiconductor device 10 may further include a shallow trench isolation layer 4. The shallow trench isolation layer 4 is disposed on the substrate 1 and is located on opposite sides of the fin structure 2 along the second direction Y. The surface of the shallow trench isolation layer 4 away from the substrate 1 is closer to the substrate 1 than the surface of the fin structure 2 away from the substrate 1.

[0105] That is, referring to Figure 2, the shallow trench isolation layer 4 is only arranged around the portion of the fin structure 2 close to the substrate 1. For example, referring to Figure 2, the shallow trench isolation layer 4 is arranged on two side surfaces of the well structure 23 that are opposite to each other along the second direction Y, thereby facilitating the isolation between two adjacent fin structures 2 (not shown in the figure).

[0106] Exemplarily, the material of the shallow trench isolation layer 4 is an insulating material. For example, the material of the shallow trench isolation layer 4 may include a binary or multinary compound composed of elements such as silicon (Si), carbon (C), nitrogen (N), and oxygen (O).

[0107] Referring to Figure 4, in the semiconductor device 10, at least two of the multilayer channel layers 21 have different dimensions d1 in the first direction X, that is, in the multilayer channel layers 21 stacked in a direction away from the substrate 1 in the same transistor, at least two of the channel layers 21 have different lengths.

[0108] Exemplarily, the lengths of the multilayer channel layers 21 are all different, or some of the multilayer channel layers 21 have the same length, while the remaining channel layers 21 have longer lengths, or the remaining channel layers 21 have shorter lengths, or at least one channel layer 21 among the remaining channel layers 21 has a longer length, while at least one channel layer 21 has a shorter length.

[0109] With the rapid development of semiconductor technology, the integration of GAA FETs (such as the aforementioned semiconductor device 10) is becoming increasingly higher, and the degree of refinement of the various internal structures is also gradually increasing. This has led to significant challenges to the various performance characteristics of GAA FETs. For example, in highly integrated devices, due to the high aspect ratio, the process difficulty in etching or doping the device is relatively high, which can easily lead to large performance differences between structures at different depths (such as the channel layer 21), affecting the uniformity of the entire device. For example, when doping the multi-layer channel layer 21, the doping concentration of the channel layer 21 at a deeper depth (closer to the substrate 1) may be different from the doping concentration of the channel layer 21 at a shallower depth, resulting in poor electrical uniformity at different depths of the semiconductor device 10, affecting the reliability of the semiconductor device 10.

[0110] In order to ensure the continued advancement of Moore's Law, the improvement of various performances of GAA FET, such as the uniformity of electrical performance, has become inevitable. In related technologies, in order to ensure that the electrical performance corresponding to each channel layer (such as the conductivity of the channel) is close to the same, efforts are usually made to improve the refinement of the doping process, so as to ensure that the channel layers of different layers in the multi-layer channel layer have the same doping concentration as much as possible. However, due to the high integration of the device, the refinement of the doping process cannot be improved indefinitely. The current GAA FET still has process errors that lead to different doping concentrations in different channel layers, affecting the uniformity of the electrical performance of the GAA FET. In addition, there are other factors besides doping concentration that will also cause different electrical properties of different channel layers, which also affect the uniformity of the electrical performance of the GAA FET.

[0111] In the semiconductor device 10 provided in the embodiment of the present application, by providing a multi-layer channel layer 21, at least two layers of the channel layer 21 have different dimensions d1 (i.e., length) in the first direction X, the electrical properties of the multi-layer channel layer 21 can be made more uniform. That is, by controlling the length of the channel layer 21, the electrical properties of the channel layer 21 can be regulated. For example, by providing a smaller length corresponding to the channel layer 21 with a smaller saturation current among the multi-layer channel layer 21, the saturation current corresponding to the multi-layer channel layer 21 is made closer to the same, thereby optimizing the uniformity of the electrical properties of the semiconductor device 10, improving the reliability of the semiconductor device 10, and facilitating the continued development of technology nodes.

[0112] Compared with the technical means of regulating electrical properties by doping concentration in related technologies, the regulation of electrical properties by the length of the channel layer 21 in the embodiment of the present application is relatively simple. The length change of the channel layer 21 can be achieved only by controlling the etching position, and the degree of refinement is high, the error is small, and the effect of achieving uniformity of the electrical properties of the semiconductor device 10 is better.

[0113] The embodiment of the present application adds a control means (i.e., length control) for controlling the electrical performance of the semiconductor device 10. The means of controlling the electrical performance of the device by the length of the channel layer 21 can be combined with other control means, such as the means of controlling the electrical performance of the device by the doping concentration of the channel layer 21, so as to control the uniformity of the electrical performance of the semiconductor device 10 from multiple dimensions, further optimize the control effect on the uniformity of the electrical performance of the semiconductor device 10, and further improve the reliability of the semiconductor device 10.

[0114] In addition, in the embodiment of the present application, by designing the length of the channel layer 21 differently, the stress on the multi-layer channel layer 21 as a whole can be dispersed, thereby avoiding the situation where the channel layer 21 bends under the action of stress due to the relatively concentrated stress when the lengths of the multi-layer channel layer 21 are exactly the same, thereby improving the structural stability of the semiconductor device 10.

[0115] In some embodiments, the saturation currents corresponding to the multiple channel layers 21 are the same. For example, the saturation currents corresponding to the two channel layers 21 with different dimensions d1 in the first direction X are also the same, thereby ensuring that the electrical performance of the semiconductor device 10 at different locations of the channel layers 21 is roughly the same, thereby improving the reliability of the semiconductor device 10.

[0116] Under certain conditions, the current in a circuit reaches its maximum value and no longer increases with increasing voltage. This maximum current is called the saturation current. This saturation current is an important indicator of the semiconductor device 10. In a transistor, the magnitude of the saturation current is directly related to the electrical performance and operating state of the semiconductor device 10.

[0117] In the transistor I D -V DS (I D is the saturation current, V DS In the saturation region of the curve (where d is the source-drain voltage difference), the relationship between the ideal saturation current and the length of the channel layer 21 (i.e., the dimension d1 in the first direction X) is:

[0118] Wherein, W is the width of the channel layer 21 (ie, the dimension d2 of the channel layer 21 in the second direction Y), L is the length of the channel layer 21 (ie, the dimension d1 of the channel layer 21 in the first direction X), μ n is the carrier mobility, C ox is the capacitance between the gate 3 and the channel layer 21, V GS is the operating voltage applied by gate 3, V T is the threshold voltage.

[0119] It can be seen from this formula that the longer the length of the channel layer 21, the smaller the corresponding saturation current. When the electrical properties corresponding to different channel layers 21 of the semiconductor device 10 are uneven, by controlling the length change of the channel layer 21, the size of the saturation current can be effectively adjusted, so that the electrical properties corresponding to the multi-layer channel layer 21 are close to each other, thereby improving the electrical uniformity and reliability of the semiconductor device 10.

[0120] In some embodiments, among the multi-layer channel layers 21, the channel layers 21 with lower doping concentrations have correspondingly smaller dimensions d1 (i.e., length) in the first direction X. That is, the length of the channel layers 21 can be set according to the doping concentration of the channel layers 21. For example, after obtaining a variation pattern of the doping concentration of the channel layers 21, the length of the channel layers 21 can be adaptively and regularly set to compensate for electrical differences caused by differences in doping concentrations.

[0121] For example, channel layers 21 of different depths are set to correspond to different doping concentrations to ensure that each channel layer 21 can reach an accurate doping state. Then, in the multi-layer channel layer 21, the channel layer 21 with a smaller doping concentration has a smaller length. Thus, by combining the control means of doping concentration and length, the electrical performance of the multi-layer channel layer 21 is made close to uniform, thereby improving the reliability of the semiconductor device 10.

[0122] The doping concentration of the channel layer 21 is closely related to the resistance of the channel layer 21 . It is understandable that the greater the doping concentration, the greater the concentration of carriers that can be formed in the channel layer 21 , that is, the smaller the resistance of the channel layer 21 .

[0123] The relationship between the resistance and length of the channel layer 21 is:

[0124] Wherein, R is resistance, ρ is resistivity, L is length (i.e., dimension d1 of the channel layer 21 in the first direction X), CD is width (i.e., dimension of the channel layer 21 in the second direction Y), s is thickness (i.e., dimension of the channel layer 21 in the third direction Z), and CD×s is the cross-sectional area of ​​the channel layer 21 parallel to the second direction Y.

[0125] According to the resistance formula, when the resistivity ρ and the cross-sectional area CD×s of the channel layer 21 are constant, the longer the length L of the channel layer 21 is, the larger the corresponding resistance R is.

[0126] In summary, among the multi-layer channel layers 21, if the doping concentration of one channel layer 21 is relatively low, its corresponding resistance is relatively high, resulting in a relatively low current transmitted in the channel layer 21. To maintain a consistent current transmitted in the multi-layer channel layers 21, it is necessary to reduce the resistance of the channel layer 21 with the relatively low doping concentration. As can be seen from the above resistance R formula, the length of the channel layer 21 is proportional to the resistance. Therefore, the resistance in the channel layer 21 can be reduced by reducing the length of the channel layer 21. In other words, to maintain consistent electrical properties of the multi-layer channel layers 21, the length of the channel layer 21 with the relatively low doping concentration can be reduced.

[0127] The following can also be achieved through the threshold voltage V T The mutual variation between the doping concentration and the length of the channel layer 21 is characterized.

[0128] The aforementioned saturation current I D In the formula, the threshold voltage V T It is determined by the material properties and process parameters. It is closely related to the doping concentration of the channel layer 21. The threshold voltage V T It can be expressed by the following formula:

[0129] Among them, Q SD (max) is the maximum value of the space charge density per unit area of ​​the depletion layer, Q' SS is the charge per unit area, Φ ms is the metal-semiconductor work function difference, Φ f is the barrier height.

[0130] Where, the barrier height Φ f It can be:

[0131] The space charge density per unit area of ​​the channel layer 21 is Q SD The maximum value of Q can be: SD (max) = eN a x dT ;

[0132] Among them, x dT It can be:

[0133] In the above formulas, Na is the doping concentration of the channel layer 21. It can be seen from the above formulas that the doping concentration Na is related to the barrier height Φ f It is directly proportional to the doping concentration Na and the maximum value of the space charge density per unit area Q SD (max) is directly proportional.

[0134] By substituting the above formulas into the saturation current I D By converting the formula, we can get the length of the channel layer 21 (L1 and L2) and the barrier height Φ f and the maximum value of the space charge density per unit area Q SD The relationship between (max) is:

[0135] From the above formula, we can know that the length L of the channel layer 21 (including L1 and L2) is related to the barrier height Φ f (including Φ f,1 and Φ f,2 ) is proportional to the length L of the channel layer 21 and the maximum value Q of the space charge density per unit area. SD (max) are directly proportional to each other.

[0136] In summary, at the saturation current I D Under the same conditions, the smaller the doping concentration Na of the channel layer 21 is, the greater the barrier height Φ f The smaller the value, the maximum value of the space charge density per unit area Q SD The smaller (max) is, the smaller the length L of the corresponding channel layer 21 is. That is, the doping concentration Na of the channel layer 21 is proportional to the length L of the channel layer 21 .

[0137] That is, by configuring the multi-layer channel layer 21 such that the length of the channel layer 21 with a lower doping concentration is also shorter, the saturation current of the multi-layer channel layer 21 can be ensured to be close to uniform. Specifically, if the doping concentrations of different channel layers 21 in the semiconductor device 10 vary, resulting in different electrical properties, the length of the channel layer 21 can be adjusted accordingly based on the variation in the doping concentration of the channel layer 21, thereby effectively controlling the electrical properties of the multi-layer channel layer 21 to be close to uniform, thereby improving the electrical uniformity and reliability of the semiconductor device 10.

[0138] In some embodiments, the width-to-length ratios of the multiple channel layers 21 are the same.

[0139] The width-to-length ratio of the channel layer 21 is the ratio of a dimension d2 of the channel layer 21 in the second direction Y to a dimension d1 of the channel layer 21 in the first direction X.

[0140] For example, the width-to-length ratios of two channel layers 21 with different dimensions d1 in the first direction X are the same, that is, the width-to-length ratios of different channel layers 21 can be made the same by controlling the length of the channel layer 21, thereby making the saturation currents corresponding to different channel layers 21 the same, thereby improving the uniformity of the electrical performance of the semiconductor device 10 at different positions, and thus optimizing the reliability of the semiconductor device 10.

[0141] For example, the smaller the dimension d2 (ie, width) of the channel layer 21 in the second direction Y, the smaller the dimension d1 (ie, length) thereof in the first direction X, so that different channel layers 21 can have substantially the same width-to-length ratio.

[0142] As the integration of the semiconductor device 10 gradually increases, the aspect ratio of the fin structure 2 in the semiconductor device 10 (the ratio of the size of the fin structure 2 in the third direction Z to the size d2 of the fin structure 2 in the second direction Y) gradually increases. In the etching process, the closer to the substrate 1 (that is, the deeper the depth), the lighter the etching degree of the fin structure 2, resulting in the size d2 (that is, the width) of the fin structure 2 in the second direction Y being roughly narrow at the top and wide at the bottom (taking the orientation in Figure 3 as an example), that is, along the direction away from the substrate 1, the width of the channel layer 21 can be gradually reduced (as shown in Figure 3).

[0143] In some embodiments, as shown in Figure 3, the length of the multilayer channel layer 21 (i.e., the dimension d1 in the first direction X) is also gradually reduced along the direction away from the substrate 1, so that the multilayer channel layer 21 can be kept with approximately the same width-to-length ratio, so that the saturation current corresponding to different channel layers 21 is the same, thereby improving the uniformity of the electrical performance of the semiconductor device 10 at different positions, thereby optimizing the reliability of the semiconductor device 10.

[0144] In addition, by setting the length of the multi-layer channel layer 21 to gradually decrease in the direction away from the substrate 1, the problem of greater etching difficulty caused by a high aspect ratio can be avoided, thereby reducing the difficulty of preparing the semiconductor device 10.

[0145] In some embodiments, as shown in Figure 4, the two side surfaces of the channel portion 21A that are relatively arranged in the first direction X (such as the left side surface and the right side surface in Figure 4) are inclined, that is, the two side surfaces of the multilayer channel layer 21 that are relatively arranged in the first direction X (such as the left side surface and the right side surface in Figure 4) are inclined, and on the same side (for example, on the left side or on the right side), the side surfaces of different channel layers 21 are roughly located in the same plane, so that during the etching preparation process, only one etching cut with an inclined angle can be performed to achieve the purpose of gradually reducing the length of the multilayer channel layer 21 in the direction away from the substrate 1.

[0146] It can be understood that, referring to Figure 4, the two side surfaces of the multilayer channel layer 21 that are relatively arranged in the first direction X gradually approach each other in the direction away from the substrate 1, that is, the two side surfaces are inclined in the direction of approaching each other, so that the dimension d1 of the multilayer channel layer 21 in the first direction X gradually decreases in the direction away from the substrate 1.

[0147] In some embodiments, as shown in Figure 5, the two side surfaces of the channel portion 21A that are relatively arranged in the first direction X (such as the left side surface and the right side surface in Figure 5) are arranged in a stepped manner, that is, the two side surfaces of the multilayer channel layer 21 that are relatively arranged in the first direction X (such as the left side surface and the right side surface in Figure 5) are arranged in a stepped manner, which can also achieve the purpose of gradually reducing the length of the multilayer channel layer 21 in the direction away from the substrate 1.

[0148] Exemplarily, referring to FIG. 5 , the steps formed on the side surfaces of the multilayer channel layer 21 gradually rise in a direction away from the substrate 1 , so that the size of the multilayer channel layer 21 in the first direction X gradually decreases in a direction away from the substrate 1 .

[0149] Exemplarily, the dimension d1 of the multilayer channel layer 21 in the first direction X may vary continuously. For example, referring to FIG. 5 , the dimension d1 of the multilayer channel layer 21 in the first direction X decreases gradually along a direction away from the substrate 1 .

[0150] Or illustratively, the dimension d1 of the multilayer channel layer 21 in the first direction X may also change in stages. For example, referring to FIG6 , along the direction away from the substrate 1 , the length of each channel layer 21 may decrease once, or the length of every two channel layers 21 may decrease once. The change pattern of the length of the channel layer 21 may depend on factors such as the doping concentration or width of the channel layer 21 , and the application embodiment does not limit this.

[0151] In some embodiments, referring to FIG7 , the length of one of the channel layers 21 can also be varied, thereby achieving precise control of the channel layer 221. For example, referring to FIG7 , among the multiple channel layers 21, only one of the channel layers 21 can be set to have a relatively short length. For example, only one or more channel layers 21 with a low doping concentration can be set to have a short length. That is, the length of the target channel layer 21 (e.g., the channel layer 21 with a large doping concentration error) can be specifically set, thereby correcting the channel layer 21 with a large electrical performance defect and improving the uniformity of the electrical performance of the semiconductor device 10 as a whole.

[0152] It can be understood that the aforementioned multiple embodiments can be combined with each other. For example, in some embodiments, the electrical properties of the channel layer 21 can be regulated by comprehensively considering multiple factors affecting the saturation current of the channel layer 21, such as the width, doping concentration, and length of the channel layer 21, so that the electrical properties of the multi-layer channel layer 21 are close to each other, thereby improving the reliability of the semiconductor device 10.

[0153] FIG. 8 is a cross-sectional view showing a case where the semiconductor device 10 includes a plurality of transistors T. FIG.

[0154] In some embodiments, as shown in Figures 4 and 8, the dimension d3 of the conductive portion 22 in the first direction X gradually increases in the direction away from the substrate 1, that is, the length of the conductive portion 22 gradually increases. For example, referring to Figure 4, the length of the conductive portion 22 is roughly narrow at the bottom and wide at the top (taking the orientation in Figure 4 as an example).

[0155] By setting the length of the conductive portion 22 to gradually increase in the direction away from the substrate 1, on the one hand, the conductive portion 22 can adapt to the trend of the length of the multilayer channel layer 21 (i.e., the dimension d1 in the first direction X) gradually decreasing, thereby facilitating the conductive portion 22 (source and / or drain) to always maintain contact with the channel layer 21, ensuring the smooth opening and closing of the semiconductor device 10. On the other hand, the length of the end of the conductive portion 22 away from the substrate 1 is larger, so that the area of ​​its top is larger, thereby making the process window larger when setting the contact structure 6 (see Figure 8) on the top of the conductive portion 22, thereby reducing the difficulty of preparing the contact structure 6 and improving the electrical connection performance between the conductive portion 22 and the contact structure 6.

[0156] Exemplarily, referring to FIG. 8 , the semiconductor device 10 may further include a contact structure 6 , which is disposed on the fin structure 2 and at least covers the upper surface of the conductive portion 22 , thereby achieving external connection of the conductive portion 22 and transmitting electrical signals to the conductive portion 22 .

[0157] It is understandable that the two side surfaces of the conductive portion 22 that are opposite to each other in the first direction X can also be arranged in an inclined or stepped manner (see FIG8 ), so that the conductive portion 22 matches the structure of the multiple channel layers 21 that are arranged in an inclined or stepped manner.

[0158] FIG. 9 is a side view of the semiconductor device 10 taken along the line C in FIG. 2 .

[0159] In some embodiments, as shown in FIG9 , at least two portions of the gate 3 have different dimensions d4 in the first direction X, and the larger the dimension d1 (see FIG4 ) of the channel layer 21 in the first direction X, the larger the dimension d4 of the corresponding portion of the gate 3 surrounding the channel layer 21 in the first direction X.

[0160] That is, the dimension d4 of the gate 3 in the first direction X changes with the dimension d1 of the channel layer 21 it surrounds in the first direction X, so that the gate 3 can completely surround the channel layer 21, thereby ensuring control of the channel in the channel layer 21 while avoiding the problem that the dimension of the gate 3 in the first direction X is too large, which increases the difficulty of preparing the conductive part 22, or causes the distance between the conductive part 22 and the channel layer 21 to be too large, resulting in a decrease in channel transmission efficiency.

[0161] Exemplarily, the shapes of the two side surfaces of the gate 3 that are opposite to each other along the first direction X are similar to the shapes of the two side surfaces of the multilayer channel layer 21 that are opposite to each other along the first direction X. For example, when the two side surfaces of the multilayer channel layer 21 that are opposite to each other along the first direction X are inclined, the two side surfaces of the gate 3 that are opposite to each other along the first direction X are also inclined. Or, for example, referring to FIG. 9 , when the two side surfaces of the multilayer channel layer 21 that are opposite to each other along the first direction X are stepped, the two side surfaces of the gate 3 that are opposite to each other along the first direction X are also stepped.

[0162] Exemplarily, the variation pattern of the dimension d4 of the gate 3 in the first direction X corresponds to the variation pattern of the dimension d1 of the channel layer 21 surrounded by the gate 3 in the first direction X.

[0163] For example, referring to Figure 9, the two side surfaces of the gate 3 that are opposite to each other along the first direction X are stepped, and the stepped side surfaces of the gate 3 match the shape of the stepped side surfaces of the multilayer channel layer 21. For example, along the direction away from the substrate 1, the steps of the stepped side surfaces of the gate 3 gradually increase, thereby corresponding to the design that the length of the multilayer channel layer 21 (the dimension d1 in the first direction X) gradually decreases along the direction away from the substrate 1.

[0164] In some embodiments, as shown in FIG. 9 , the semiconductor device 10 may further include a spacer layer 7 .

[0165] The spacer layer 7 extends along the second direction Y. Referring to FIG. 9 , the spacer layer 7 is disposed on two opposite side surfaces of the gate 3 along the first direction X. The spacer layer 7 can protect the gate 3 from external damage.

[0166] For example, it is understood that the surface of the spacer layer 7 (the surface extending along the second direction Y) can also be arranged in an inclined or stepped manner, and the stepped surface of the spacer layer 7 matches the shape of the stepped side surface of the gate 3. The specific arrangement of the spacer layer 7 is the same as the arrangement of the two side surfaces of the gate 3 arranged opposite to each other along the first direction X, and will not be repeated here.

[0167] In some embodiments, it can be understood that an inclined or stepped shape can be formed on only one of the two side surfaces of the multilayer channel layer 21 that are oppositely arranged along the first direction X, that is, the length of the channel layer 21 can be changed on only one side (for example, the left side or the right side in Figure 4), or the length can be changed on both sides. The drawings provided in the embodiments of the present application only illustrate the example of length changes on both sides and do not constitute a limitation to this.

[0168] The uniformity of the electrical performance of the semiconductor device 10 obtained in the above embodiment will be analyzed below:

[0169] In related technologies, in a semiconductor device with three channel layers, the variance of the resistance of the three channel layers can reach 22.3%, and the variance of the electric power of the three channel layers can reach 20.1%, indicating that the electrical performance differences between the three channel layers are large.

[0170] In the embodiment of the present application, by adjusting the length of the three-layer channel layer 21, the difference in electrical performance between the three-layer channel layer can be effectively reduced. For details, see Table 1, Table 2 and Table 3.

[0171] Table 1

[0172] Referring to Table 1, the embodiment of the present application can effectively reduce the resistance variance of the three-layer channel layer 21 to 7.6% and the electric power variance to 7.4% by setting L1=L3>L2 (that is, the length of the first channel layer is the same as the length of the third channel layer and is greater than the length of the second channel layer). Compared with the related art, the difference in electrical performance between the three-layer channel layers 21 is effectively reduced.

[0173] Table 2

[0174] Referring to Table 2, the embodiment of the present application reduces the resistance variance and the electric power variance of the three-layer channel layer 21 to 2.8% by setting L1<L2=L3. Compared with the related art, the difference in electrical performance between the three-layer channel layer 21 is also further reduced.

[0175] Table 3

[0176] Referring to Table 3, the embodiment of the present application reduces the resistance variance and the electric power variance of the three-layer channel layer 21 to 0.7% by setting L1<L2<L3 (that is, the length of the multi-layer channel layer 21 gradually decreases in the direction away from the substrate 1). That is, there is almost no difference in the electrical performance between the three-layer channel layer 21, and the reliability of the semiconductor device 10 is significantly improved.

[0177] Similarly, in the related art, in a semiconductor device with five channel layers, the variance of the resistance of the five channel layers can reach 20.8%, and the variance of the electric power of the three channel layers can reach 16.5%, indicating that the difference in electrical performance between the five channel layers is also large.

[0178] Table 4 is an example of adjusting the length of the five-layer channel layer 21 provided in this application.

[0179] Table 4

[0180] Referring to Table 4, the embodiment of the present application reduces the resistance variance of the three-layer channel layer 21 to 4.0% and the electrical power variance to 4.1% by setting L1 = L2 < L3 = L4 = L5, thereby reducing the difference in electrical performance between the five-layer channel layer 21. In other words, in a semiconductor device 10 having three or more channel layers 21, the uniformity of the electrical performance of the multiple channel layers 21 can still be controlled by varying the length of the channel layer 21.

[0181] It can be understood that in the embodiments corresponding to the aforementioned multiple tables of the present application, except for the length difference, other parameters are exactly the same as the parameters in the related art, for example, the resistivity, width, thickness, etc. are all the same, so as to highlight the impact of length changes on electrical performance.

[0182] The embodiment of the present application further provides a method for manufacturing a semiconductor device 10. FIG10 is a flowchart of the manufacturing method, and FIG11 to FIG18 are schematic diagrams of the structures corresponding to the steps in the manufacturing process of the semiconductor device 10.

[0183] In some embodiments, as shown in FIG10 , the preparation method includes the following preparation steps S1 to S4:

[0184] S1: As shown in FIG11 , a fin structure 2 is formed on a substrate 1 .

[0185] Exemplarily, step S1 may include: alternately stacking sacrificial layers 2A and semiconductor layers 2B on a substrate 1. Cutting the sacrificial layers 2A and semiconductor layers 2B to form a plurality of fin structures 2 spaced apart from each other. The plurality of fin structures 2 are arranged along a second direction Y, with each fin structure 2 extending along a first direction X.

[0186] It can be understood that the fin structure 2 formed in step S1 includes sacrificial layers 2A and semiconductor layers 2B alternately stacked in a direction away from the substrate 1 .

[0187] That is, the fin structure 2 includes a plurality of stacked and spaced semiconductor layers 2B, and adjacent semiconductor layers 2B are spaced apart by sacrificial layers 2A.

[0188] Exemplarily, as shown in FIG. 11 , step S1 may further include: forming a shallow trench isolation layer 4 on the substrate 1 .

[0189] For example, a shallow trench isolation material that completely surrounds the fin structure 2 may be first deposited, and then the shallow trench isolation material may be etched back in a direction toward the substrate 1 to form a shallow trench isolation layer 4, thereby exposing at least a portion of the fin structure 2. The unexposed portion of the fin structure 2 (i.e., the portion surrounded by the shallow trench isolation layer 4) serves as the well structure 23. By controlling the etch-back time, the height of the exposed portion of the fin structure 2 may be controlled.

[0190] S2: As shown in FIG12 , a dummy gate 3A is formed.

[0191] 12 , the dummy gate 3A is disposed across the fin structure 2 . For example, the dummy gate 3A is disposed across a portion of the fin structure 2 located on a side of the shallow trench isolation layer 4 away from the substrate 1 .

[0192] FIG13 is a side view along the direction D in FIG12 .

[0193] Referring to Figure 13, at least two parts of the virtual gate 3A arranged in a direction away from the substrate 1 have different sizes d5 in the first direction X. For example, the parts of the virtual gate 3A covering different semiconductor layers 2B have different sizes d5 in the first direction X, which facilitates cutting at least two semiconductor layers 2B in the multi-layer semiconductor layer 2B into different lengths in subsequent process steps, that is, forming channel layers 21 with different lengths.

[0194] For example, referring to Figure 13, in the direction away from the substrate 1, the dimension d5 of the virtual gate 3A in the first direction X gradually decreases, thereby facilitating that the length of the multilayer channel layer 21 formed in the subsequent process steps (the dimension d1 along the first direction X) gradually decreases in the direction away from the substrate 1.

[0195] For example, during the process of forming the dummy gate 3A, the dummy gate 3A may be etched at a certain tilt angle, so that two side surfaces of the dummy gate 3A that are opposite to each other along the first direction X are tilted.

[0196] Alternatively, by way of example, during the formation of the dummy gate 3A, the etching time at different positions of the dummy gate 3A may be controlled so that two side surfaces of the dummy gate 3A that are opposite to each other along the first direction X are formed in a stepped shape. For example, along the directions in which the two side surfaces diverge from each other, the etching time is gradually increased and the etching degree is gradually deepened, so that the two side surfaces form steps that gradually rise in a direction away from the substrate 1.

[0197] 13 , the portion of the fin structure 2 covered by the dummy gate 3A serves as the channel portion 21A. That is, the portion of the fin structure 2 covered by the dummy gate 3A can serve as the channel portion 21A.

[0198] Referring to FIG. 13 , the channel portion 21A includes a multilayer channel layer 21. The channel layer 21 is the portion of the semiconductor layer 2B covered by the dummy gate 3A. Specifically, the portion of the semiconductor layer 2B covered by the dummy gate 3A serves as the channel layer 21 in the channel portion 21A. The portion of the semiconductor layer 2B not covered by the dummy gate 3A will be removed in subsequent processing steps.

[0199] 16 , among the multiple channel layers 21 of a channel portion 21A, at least two channel layers 21 have different sizes d1 in the first direction X.

[0200] Exemplarily, as shown in FIG14 , after forming the dummy gate 3A, the manufacturing method may further include:

[0201] S21: Referring to FIG14 , forming a spacer layer 7. The spacer layer 7 is disposed on two opposite side surfaces of the dummy gate 3A along the first direction X.

[0202] It can be understood that the shape of the surface of the sidewall layer 7 (the surface extending along the second direction Y) depends on the shapes of the two side surfaces of the virtual gate 3A that are opposite to each other along the first direction X. For example, referring to Figure 14, when the two side surfaces of the virtual gate 3A that are opposite to each other along the first direction X are stepped, the surface of the sidewall layer 7 is also stepped.

[0203] S3 : Referring to FIG. 15 and FIG. 16 , the portion of the fin structure 2 not covered by the dummy gate 3A is removed (see FIG. 15 , the portions of the fin structure 2 located on the left and right sides of the dummy gate 3A are removed), and replaced with the conductive portion 22 (see FIG. 16 ).

[0204] For example, an in-situ multi-step etching process may be used to remove portions of the fin structure 2 located on both sides of the dummy gate 3A, so as to be compatible with the existing GAA FET manufacturing process without the need to design a special corresponding manufacturing process.

[0205] For example, referring to Figure 15, the portions of the fin structure 2 located on both sides of the virtual gate 3A can be removed with the surface of the spacer layer 7 as the boundary, so that in the portion of the fin structure 2 covered by the virtual gate 3A and the spacer layer 7, the dimension d1 (see Figure 16) of the multilayer channel layer 21 in the first direction X can be the same as the change in the surface of the spacer layer 7.

[0206] For example, referring to FIG16 , after step S3 , at least two of the multi-layer channel layers 21 covered by the dummy gate 3A have different dimensions d1 in the first direction X. For example, referring to FIG16 , the dimensions d1 of the multi-layer channel layers 21 in the first direction X gradually decrease in a direction away from the substrate 1 .

[0207] Exemplarily, referring to FIG. 16 , a dimension d3 of the conductive portion 22 in the first direction X gradually increases in a direction away from the substrate 1 , thereby matching the length variation of the multi-layer channel layer 21 .

[0208] S4 : Referring to FIG. 17 and FIG. 18 , the dummy gate 3A and the sacrificial layer 2A (see FIG. 17 ) are removed and replaced with the gate 3 .

[0209] 18 , the gate electrode 3 is formed to surround the surface of each channel layer 21 in the multi-layer channel layer 21 .

[0210] For example, it can be understood that after removing the virtual gate 3A and the sacrificial layer 2A, and before filling the gate material to form the gate 3, the preparation method may also include: depositing a gate oxide layer 5 on the sidewalls of the sidewall layer 7 and the surface of the channel layer 21, so as to facilitate electrical insulation between the subsequently formed gate 3 and the channel layer 21, and to facilitate electrical insulation between the gate 3 and the conductive part 22.

[0211] For example, referring to FIG18 , the gate 3 replaces the virtual gate 3A and the sacrificial layer 2A. The shapes of the two side surfaces of the gate 3 that are opposite to each other along the first direction X depend on the shapes of the two side surfaces of the virtual gate 3A that are opposite to each other along the first direction X. For example, referring to FIG18 , the two side surfaces of the gate 3 that are opposite to each other along the first direction X may be stepped, thereby matching the length of the channel layer 21 surrounded by the gate 3.

[0212] The preparation method provided in the embodiment of the present application can prepare a semiconductor device 10 in which at least two channel layers 21 have different lengths (dimension d1 along the first direction X). That is, the preparation method provided in the embodiment of the present application can effectively regulate the electrical properties corresponding to multiple channel layers 21 in the semiconductor device 10 by changing the length of the channel layer 21, so that the electrical properties corresponding to the multiple channel layers 21 are more uniform, thereby improving the reliability of the semiconductor device 10.

[0213] In addition, in the semiconductor device 10 with a high aspect ratio, the length of the multilayer channel layer 21 is exactly the same, and the design of different lengths of the multilayer channel layer 21 in the embodiment of the present application is conducive to filling materials at deeper positions. For example, it is conducive to filling the gate 3 on the surface of the channel layer 21 closest to the substrate 1, avoiding the formation of voids or uneven filling problems at this position, and avoiding affecting the DC performance of the semiconductor device 10.

[0214] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this disclosure should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; a fin structure disposed on the substrate, the fin structure comprising a conductive portion and a channel portion alternately disposed along a first direction; the channel portion comprising a plurality of channel layers, the plurality of channel layers being stacked and spaced apart in a direction away from the substrate; a gate electrode, surrounding and arranged on a surface of each channel layer in the multi-layer channel layer; At least two channel layers in the multi-layer channel layer have different sizes in the first direction; and the first direction is parallel to the substrate.

2. The semiconductor device according to claim 1, wherein The two channel layers having different sizes in the first direction correspond to the same saturation current.

3. The semiconductor device according to claim 1 or 2, wherein: In the multi-layer channel layer, the channel layer with a lower doping concentration has a smaller size in the first direction.

4. The semiconductor device according to any one of claims 1 to 3, wherein The two channel layers having different sizes in the first direction have the same width-to-length ratio; the width-to-length ratio is the ratio of the size of the channel layer in the second direction to the size of the channel layer in the first direction; The second direction is parallel to the substrate and perpendicular to the first direction.

5. The semiconductor device according to any one of claims 1 to 4, wherein: Among the multiple channel layers, a channel layer with a smaller size in the second direction also has a smaller size in the first direction.

6. The semiconductor device according to any one of claims 1 to 5, wherein: Along the direction away from the substrate, the dimensions of the multi-layer channel layer in the second direction and in the first direction gradually decrease.

7. The semiconductor device according to claim 6, wherein: Two side surfaces of the channel portion that are opposite to each other in the first direction are inclined, and on the same side, side surfaces of different channel layers are located in the same plane.

8. The semiconductor device according to claim 6, wherein: Two side surfaces of the channel portion that are opposite to each other in the first direction are arranged in a stepped shape.

9. The semiconductor device according to any one of claims 6 to 8, wherein: Along the direction away from the substrate, the size of the conductive portion in the first direction gradually increases.

10. The semiconductor device according to any one of claims 1 to 9, wherein: At least two portions of the gate have different sizes in the first direction, and the larger the size of the channel layer in the first direction, the larger the size of the corresponding portion of the gate surrounding the channel layer in the first direction.

11. The semiconductor device according to claim 10, wherein: Along the direction away from the substrate, the size of the multilayer channel layer in the first direction gradually decreases, and two side surfaces of the multilayer channel layer opposite to each other in the first direction are arranged in a stepped manner; Two side surfaces of the gate that are opposite to each other in the first direction are arranged in a stepped shape, and the stepped side surfaces of the gate match the shapes of the stepped side surfaces of the multi-layer channel layer.

12. The semiconductor device according to claim 11, wherein Also includes: A spacer layer is provided on two side surfaces of the gate that are opposite to each other in the first direction. The surface of the spacer layer is arranged in a stepped shape, and the stepped surface of the spacer layer matches the shape of the stepped side surfaces of the gate.

13. A method for preparing a semiconductor device, characterized in that: include: forming a fin structure on a substrate; the fin structure comprising a sacrificial layer and a semiconductor layer alternately stacked in a direction away from the substrate; forming a virtual gate; The dummy gate is arranged across the fin structure, and at least two portions of the dummy gate arranged in a direction away from the substrate have different sizes in a first direction; the first direction is parallel to the substrate; the portion of the fin structure covered by the dummy gate is a channel portion, the channel portion includes a multi-layer channel layer, and the channel layer is the portion of the semiconductor layer covered by the dummy gate; among the multi-layer channel layer, at least two channel layers have different sizes in the first direction; removing a portion of the fin structure not covered by the dummy gate and replacing it with a conductive portion; the conductive portion and the channel portion are alternately arranged along the first direction; The dummy gate and the sacrificial layer are removed and replaced with a gate; the gate is arranged around the surface of each channel layer in the multi-layer channel layer.

14. An integrated circuit, characterized in that: include: The semiconductor device according to any one of claims 1 to 12; An electronic device is electrically connected to the semiconductor device.

15. An electronic device, characterized in that: include: The integrated circuit according to claim 14; A circuit board, on which the integrated circuit is arranged.

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