Repair method for memory, and circuit

Abstract

Provided in the embodiments of the present disclosure are a repair method for a memory, and a circuit. The repair method comprises: a memory receiving a repair instruction sent from the outside, wherein the repair instruction carries a failed address, and the failed address is a storage unit address of a failed storage unit; performing broadcasting on a fuse array, and sequentially determining whether the currently broadcast fuse address is a target fuse address until at least one target fuse address is found, wherein the target fuse address is a fuse address that is mapped to a target redundant address, and the target redundant address is a redundant address capable of repairing the failed address; and writing the failed address into a first target fuse address that has not been used among the at least one target fuse address, so as to access the target redundant address when an access request for the failed address is received. By means of the solution in the embodiments of the present disclosure, a failed storage unit address can be repaired by using a redundant address, which has a mapping relationship with a fuse address, in a memory.

Description

Memory repair method and circuit

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 29, 2023, with application number 202311871414.7 and application name “Memory Repair Method and Circuit”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present disclosure relate to the field of semiconductor technology, and are related to, but not limited to, a memory repair method and circuit. Background Art

[0003] Memory failures can occur during production and use. For example, DRAM (Dynamic Random Access Memory) can experience WL (Word Line) failures, BL (Bit Line) failures, or memory cell failures during production and use. After the memory is packaged, failed addresses can be repaired using Post Package Repair (PPR). However, the number of redundant addresses designated for PPR repair in memory is very limited and may not meet actual repair needs.

[0004] Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a memory repair method and circuit.

[0006] In a first aspect, an embodiment of the present disclosure provides a method for repairing a memory, wherein the memory includes a memory array and a fuse array, the memory array including a plurality of memory cells and a plurality of redundant cells, the memory cells having memory cell addresses, the redundant cells having redundant addresses, the fuse array including a plurality of fuse cells, and the fuse cells having fuse addresses; wherein at least some of the fuse addresses are mapped one-to-one with preset redundant addresses; the repair method includes:

[0007] The memory receives a patch instruction sent from the outside, wherein the patch instruction carries a failure address, and the failure address is a storage unit address of a failed storage unit;

[0008] Broadcasting the fuse array, and sequentially determining whether the currently broadcast fuse address is a target fuse address, until at least one target fuse address is found; wherein the target fuse address is the fuse address that maps the target redundant address; and the target redundant address is the redundant address that can repair the failed address;

[0009] The failed address is written into a first unused target fuse address among the at least one target fuse address, so as to access the target redundant address when an access request for the failed address is received.

[0010] In some embodiments, broadcasting the fuse array and sequentially determining whether the currently broadcast fuse address is the target fuse address specifically includes:

[0011] Determining whether the currently broadcast fuse address is a fuse address mapped to a redundant address in the same memory bank or memory bank group as the failed address;

[0012] If yes, the currently broadcast fuse address is determined as the first fuse address;

[0013] If not, continue reading the next address;

[0014] determining whether the first fuse address is unused;

[0015] If yes, determining the first fuse address as the target fuse address;

[0016] If not, continue reading the next address.

[0017] In some embodiments, determining whether the currently broadcast fuse address is a fuse address mapped to a redundant address in the same memory bank or memory bank group as the failed address specifically includes:

[0018] Determining whether the currently broadcast fuse address is a fuse address mapped to the first root redundant address in the same memory bank or memory bank group as the failed address;

[0019] Determining whether the currently broadcast fuse address is the fuse address mapped to the last redundant address in the same memory bank or memory bank group as the failed address;

[0020] Determining the currently broadcast fuse address as the first fuse address includes determining fuse addresses between the fuse address mapped by the first root redundant address and the fuse address mapped by the last root redundant address in the same memory bank or memory bank group as the failed address as the first fuse address.

[0021] In some embodiments, broadcasting the fuse array specifically includes:

[0022] By counting the region address, row address and column address of the fuse array respectively, the current read fuse address is determined;

[0023] The determining whether the currently read fuse address is a fuse address mapped to the first root redundant address in the same memory bank or memory bank group as the failed address specifically includes:

[0024] Determine whether the count values ​​of the region address, the row address, and the column address of the currently read fuse address are the region address, the row address, and the column address of the fuse address mapped by the first root redundant address; if so, pull the first target address indication signal high;

[0025] The determining whether the currently read fuse address is the fuse address mapped to the last redundant address in the same memory bank or memory bank group as the failed address specifically includes:

[0026] It is determined whether the count values ​​of the region address, row address and column address of the currently read fuse address are the region address, row address and column address of the fuse address mapped by the last redundant address; if so, the first target address indication signal is pulled low.

[0027] In some embodiments, the method further comprises:

[0028] If the currently read fuse address maps to the last redundant address and the current first fuse address is not an unused fuse address, the value of the resource register of the current memory bank or memory bank group is updated to the first value indicating no available redundant address, and the repair operation is terminated.

[0029] In a second aspect, an embodiment of the present disclosure further provides a patch circuit for a memory, wherein the memory includes a memory array and a fuse array, the memory array includes a plurality of memory cells and a plurality of redundant cells, the memory cells have memory cell addresses, the redundant cells have redundant addresses, the fuse array includes a plurality of fuse cells, and the fuse cells have fuse addresses; wherein at least some of the fuse addresses are mapped one-to-one with preset redundant addresses; the patch circuit includes:

[0030] An instruction receiving unit, configured to receive a patch instruction sent from an external source, wherein the patch instruction carries a failure address indicating an address of a failed storage unit;

[0031] an address broadcasting unit connected to the fuse array and the instruction receiving unit, and configured to broadcast the fuse array;

[0032] an address search unit connected to the address broadcast unit, configured to sequentially receive the fuse addresses broadcasted by the address broadcast unit and determine whether the currently broadcast fuse address is a target fuse address, until at least one target fuse address is found; wherein the target fuse address is the fuse address mapped to the target redundant address; and the target redundant address is the redundant address capable of repairing the failed address;

[0033] The address writing unit is connected to the fuse array and the address search unit, and is used for decoding a first unused target fuse address among the at least one target fuse address, and writing the failed address to the fuse unit corresponding to the target fuse address.

[0034] In some embodiments, the address lookup unit includes:

[0035] an address matching circuit connected to the address broadcast unit, sequentially receiving fuse addresses broadcasted by the address broadcast unit, and configured to match a fuse address mapped by a first root redundant address of at least one memory bank or memory bank group, and a fuse address mapped by a last root redundant address of at least one memory bank or memory bank group, based on the fuse addresses broadcasted by the address broadcast unit;

[0036] an indication signal generating unit connected to the address matching circuit, configured to output a high-level signal when the broadcast fuse address matches the fuse address mapped by the first redundant address, and output a low-level signal when the broadcast fuse address matches the fuse address mapped by the last redundant address;

[0037] A search output unit is connected to the fuse array and the address broadcast unit, and is used to read the flag information of the fuse address according to the fuse address broadcast by the address broadcast unit, and output the fuse address when the flag information indicates that the fuse address is not used.

[0038] In some embodiments, the address matching circuit includes:

[0039] a first matching circuit, configured to determine whether the broadcast fuse address matches the fuse address mapped to the first root redundant address, and to output a first matching signal to the indication signal generating unit when a match is found;

[0040] a second matching circuit, configured to determine whether the broadcast fuse address matches the fuse address mapped to the last redundant address, and to output a second matching signal to the indication signal generating unit when a match occurs;

[0041] The indication signal generating unit includes a first latch, which outputs the high-level signal when receiving the first matching signal and outputs the low-level signal when receiving the second matching signal.

[0042] In some embodiments, the search output unit includes: a first AND gate, a first input terminal of which is connected to the output terminal of the first latch, and a second input terminal of which is used to receive the flag bit information;

[0043] a first trigger, whose signal input terminal is connected to the output terminal of the first AND gate, and whose clock input terminal is used to receive the broadcast clock signal;

[0044] a second trigger, whose signal input terminal is connected to the first power supply terminal, and whose clock input terminal is connected to the output terminal of the first trigger;

[0045] a second latch, whose signal input end is connected to the address broadcast unit and is used to sequentially receive the broadcasted fuse addresses, and whose clock input end is connected to the output end of the second flip-flop;

[0046] The second latch outputs the target fuse address when the first latch outputs the high level signal and the flag information indicates that the flag is not used.

[0047] In a second aspect, an embodiment of the present disclosure further provides a memory, including:

[0048] A storage array; wherein the storage array comprises a plurality of storage cells and a plurality of redundant cells, the storage cells having storage cell addresses, and the redundant cells having redundant addresses;

[0049] Peripheral circuit; wherein the peripheral circuit includes a fuse array, the fuse array includes a plurality of fuse units, the fuse units have fuse addresses, and the repair circuit provided by any of the above embodiments.

[0050] In the disclosed embodiments, a method of broadcasting the fuse array is used to search for redundant addresses that are mapped one-to-one with the fuse addresses. The method then searches for redundant addresses that can be used to patch failed addresses, and then finds the first available redundant address for each patch. This fully utilizes the numerous redundant address lines within the memory for post-packaging patching of failed addresses, thereby meeting more patching needs while reducing the waste of redundant address resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] FIG1 is a schematic diagram of a memory provided by an embodiment of the present disclosure;

[0052] FIG2 is a flowchart of a memory repair method according to an embodiment of the present disclosure;

[0053] FIG3 is a second flowchart of a memory repair method provided by an embodiment of the present disclosure;

[0054] FIG4 is a schematic structural diagram of a memory repair circuit provided by an embodiment of the present disclosure;

[0055] FIG5 is a schematic diagram of a partial structure of a repair circuit provided in an embodiment of the present disclosure;

[0056] FIG6 is a schematic diagram of an address matching circuit and a signal generating unit in a patch circuit provided by an embodiment of the present disclosure;

[0057] FIG7 is a schematic structural diagram of a search output unit in a patch circuit according to an embodiment of the present disclosure;

[0058] FIG8 is a schematic diagram of various signal waveforms of a patching circuit provided by an embodiment of the present disclosure;

[0059] FIG9 is a schematic structural diagram of a repair circuit of another memory provided by an embodiment of the present disclosure;

[0060] FIG10 is a schematic diagram of another memory provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in a variety of different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. The terms used herein in the specification of this disclosure are intended only to describe specific embodiments and are not intended to limit this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0063] An embodiment of the present disclosure provides a method for repairing a memory. As shown in FIG1 , the memory 100 includes a memory array 110 and a fuse array 120. The memory array 110 includes a plurality of memory cells and a plurality of redundant cells. The memory cells have memory cell addresses 111, and the redundant cells have redundant addresses 112. The fuse array 120 includes a plurality of fuse cells, each having a fuse address 121. At least some of the fuse addresses 121 are mapped one-to-one with preset redundant addresses 112. As shown in FIG2 , the repair method includes:

[0064] S101: The memory receives a patch instruction sent from an external source, wherein the patch instruction carries a failure address, and the failure address is a storage unit address of a failed storage unit;

[0065] S102, broadcasting the fuse array, and sequentially determining whether the currently broadcast fuse address is a target fuse address, until at least one target fuse address is found; wherein the target fuse address is the fuse address that maps the target redundant address; and the target redundant address is the redundant address that can repair the failed address;

[0066] S103: Write the failed address into a first unused target fuse address among the at least one target fuse address, so as to access the target redundant address when an access request for the failed address is received.

[0067] In the disclosed embodiments, the memory cells in the memory are used to store data, but the memory cells may fail, resulting in an inability to store data normally, or storing erroneous data. The failure may be a failure of a single memory cell, for example, a failure of a transistor in the memory cell, or a failure caused by leakage of a storage capacitor; it may also be a WL failure or a BL failure. The redundant memory cell has the same structure as the memory cell, but does not participate in the reading and writing of data by the normal memory cell, that is, the redundant cell is not accessed under normal circumstances, and can only participate in the storage and reading and writing of data in place of the normal memory cell in the event of a failure.

[0068] The aforementioned memory cell addresses may include row addresses, column addresses, addresses of memory banks, and addresses of memory bank groups. Redundant addresses also include row addresses, column addresses, addresses of memory banks, and addresses of memory bank groups. If a memory cell fails, the aforementioned row addresses, column addresses, addresses of memory banks, and addresses of memory bank groups are required to locate the memory cell. If a WL fails, only the row address and memory bank or memory bank group are required to locate the memory cell. If a BL fails, only the column address and memory bank or memory bank group are required to locate the BL. If the aforementioned repair operation is performed within a memory bank, then only the row address or column address is required to locate the WL and BL failures.

[0069] In an embodiment of the present disclosure, the memory further includes a fuse array comprising a large number of one-time programmable (OTP) fuse cells. Multiple fuse cells can be used as a group to store addresses (such as failed storage cell addresses), trimming parameters, and other parameters. A fuse address can be used to locate a group of fuse cells. Therefore, if the group of fuse cells stores address data (the address data contains multiple bits), the fuse address can be used to locate the address data stored in the group of fuse cells.

[0070] In an embodiment of the present disclosure, some of the multiple fuse addresses in the fuse array may be mapped one-to-one with redundant addresses, that is, each fuse address corresponds to a redundant address, and this mapping relationship may be a fixed setting in the memory. For example, it is implemented by a fixed decoding method of a local register and an address decoder. Specifically, a local register is provided in the memory and is connected to the address decoder. The local register can store multiple addresses in sequence, which correspond to the part of the fuse array used for mapping with redundant addresses. That is, the address information stored in the fuse array will be stored in the corresponding position of the local register when it is read out. Each address stored in the local register is decoded to its corresponding redundant address when it is transmitted to the address decoder. In this way, a one-to-one mapping of the fuse address and the redundant address is achieved.

[0071] To make it easier to understand, here are some examples:

[0072] The fuse array includes 128 addresses, fuse[127:0], of which fuse[127:64], i.e., the 64th to 127th fuse addresses, are used for one-to-one mapping with the redundant address rwl[63:0]. When reading the fuse array fuse[127:64], the read content will be stored in the above-mentioned local register. The content stored in the local register is decoded by the address decoder and decoded to the fixed redundant address rwl[63:0] in sequence. Therefore, if the failure address fail[63:0] is stored in the fuse array fuse[127:64], when accessing the failure address, the address decoder decodes the part of the local register that stores the failure address, thereby decoding it to a fixed redundant address to replace the failure address. For example, accessing the failure address fail0, which is stored in the fuse array fuse64, is read out to the first address of the local register and decoded to the corresponding first redundant address rwl0, thus achieving the replacement of fail0 to rwl0.

[0073] In the disclosed embodiment, the memory can perform PPR to patch the failed address, and the memory receives a patch instruction sent from the outside to obtain the failed address to be patched. The above-mentioned failed address can be the storage cell address of the failed storage cell, including the row address, column address, and address of the storage body or storage body group used to locate the storage cell. In some embodiments, the failed address can also be the row address of the failed WL or the column address of the failed BL. In some embodiments, the patching of the storage cell can also be achieved by replacing the row or column where the storage cell is located with a redundant row or redundant column.

[0074] During the memory manufacturing process, many redundant addresses are set up. These redundant addresses are generally used for testing and repairing before shipment. However, after shipment, the PPR (Pre-printed Position Regulator) typically uses only one or a few fixed redundant addresses. This results in a large number of PPRs being unused after the memory leaves the factory, resulting in a waste of resources.

[0075] Because redundant addresses in the memory are mapped one-to-one to some fuse addresses in the fuse array, the disclosed embodiment employs a broadcast method for the fuse array, sequentially scanning each fuse address in the fuse array and reading the contents stored therein to determine whether the fuse address is an available fuse address that can be used to store a failed address as the target fuse address. The failed address is then written into the available fuse address. Utilizing the mapping relationship between fuse addresses and redundant addresses, the failed address is directly decoded into a redundant address when accessed, thereby implementing a repair. Here, the target redundant address mapped to the target fuse address is a redundant address that can be used to repair the failed address.

[0076] In the disclosed embodiment, considering that the target fuse address may have been used in the previous PPR, that is, other failed addresses have been stored, when writing the failed address this time, it should be confirmed that the target fuse address written is an unused target fuse address among the at least one target fuse address. Since the broadcast process reads the fuse addresses sequentially, it is possible to confirm whether each fuse address is the target fuse address and whether it has been used. If the first unused target fuse address is read, the failed address to be repaired can be written into the target fuse address.

[0077] In this way, the failed address can be written into the next target fuse address during the next PPR. In this way, each fuse address can be accessed in a polling manner through broadcasting, so that its corresponding redundant address has a chance to be used in the PPR, thereby reducing the waste of redundant address resources.

[0078] In some embodiments, as shown in FIG3 , in step S102 , broadcasting the fuse array and sequentially determining whether the currently broadcast fuse address is the target fuse address specifically includes:

[0079] S11, determining whether the currently broadcast fuse address is a fuse address mapped to a redundant address in the same memory bank or memory bank group as the failed address;

[0080] S12, if yes, determine the currently broadcast fuse address as the first fuse address; if no, continue to read the next address;

[0081] S13, determining whether the first fuse address is unused;

[0082] S14: If yes, determine the first fuse address as the target fuse address; if no, continue to read the next address.

[0083] Since the fuse array in the memory can have multiple uses, some of them are mapped to redundant addresses and used to repair failed addresses; some can be used for other purposes, such as storing adjustment parameters. Therefore, in the repair process involved in the embodiment of the present disclosure, it is necessary to find the fuse address mapped to the target redundant address that can be used to repair the failed address by broadcasting. In addition, for the same storage body / same storage body group repair method, since the repair of the failed address requires the use of a redundant address in the same storage body or storage body group as the failed address, in order to find the target fuse address, it is also necessary to confirm whether the currently broadcasted fuse address is the fuse address mapped to the redundant address in the same storage body or storage body group as the failed address. If so, it is defined as the first fuse address. It is also necessary to further determine whether it is not used. If it is not used, it can be determined as the target fuse address. If it has been used, then the first fuse address cannot be used to repair the failed address, and it is necessary to continue reading the next address.

[0084] In some embodiments, the step S11 of determining whether the currently broadcast fuse address is a fuse address mapped to a redundant address in the same memory bank or memory bank group as the failed address specifically includes:

[0085] S21, determining whether the currently broadcast fuse address is a fuse address mapped to the first root redundant address in the same memory bank or memory bank group as the failed address;

[0086] S22, determining whether the currently broadcast fuse address is the fuse address mapped to the last redundant address in the same memory bank or memory bank group as the failed address;

[0087] The above step S12 specifically includes: S23, determining the fuse addresses between the fuse address mapped by the first redundant address and the fuse address mapped by the last redundant address in the same memory bank or memory bank group as the failed address as the first fuse address.

[0088] Considering that the portion of the fuse array that is mapped one-to-one with the redundant addresses of the same memory bank or memory bank group is generally continuous, and the first redundant address in the memory bank or memory bank group is mapped to the first fuse address in this portion of continuous fuse addresses in the fuse array, when searching for the target fuse address, it is only necessary to find the fuse address mapped to the first redundant address, that is, the first fuse address in this portion of continuous fuse addresses, and then find the fuse address mapped to the last redundant address, that is, the last fuse address in this portion of continuous fuse addresses. The fuse addresses between the two are all the above-mentioned first fuse address, that is, the fuse address that is mapped one-to-one with the redundant address in the same memory bank or memory bank group as the failed address.

[0089] Therefore, during the broadcast process, each fuse address is sequentially determined to determine whether it is the fuse address mapped to the first redundant address and whether it is the fuse address mapped to the last redundant address. Once the fuse addresses mapped to the first redundant address and the last redundant address are found, the fuse addresses between the two can be directly determined as the first fuse address, eliminating the need to determine the correspondence between each redundant address and a fuse address. Of course, in other embodiments, if the mapping relationship between redundant addresses and fuse addresses is unordered, it is necessary to determine whether each fuse address corresponds to a redundant address.

[0090] In some embodiments, broadcasting the fuse array specifically includes:

[0091] By counting the region address, row address and column address of the fuse array respectively, the current read fuse address is determined;

[0092] The determining whether the currently read fuse address is a fuse address mapped to the first root redundant address in the same memory bank or memory bank group as the failed address specifically includes:

[0093] Determine whether the count values ​​of the region address, the row address, and the column address of the currently read fuse address are the region address, the row address, and the column address of the fuse address mapped by the first root redundant address; if so, pull the first target address indication signal high;

[0094] The determining whether the currently read fuse address is the fuse address mapped to the last redundant address in the same memory bank or memory bank group as the failed address specifically includes:

[0095] It is determined whether the count values ​​of the region address, row address and column address of the currently read fuse address are the region address, row address and column address of the fuse address mapped by the last redundant address; if so, the first target address indication signal is pulled low.

[0096] In the embodiment of the present disclosure, an address counter can be used to broadcast the fuse array. Specifically, the address counter can count the column address, row address, and region address respectively. Each count outputs the count value as the address to the fuse array to read the corresponding fuse address. It can be understood that during the counting process, the address counter can increment the column address in sequence according to the jump of the broadcast clock. The column address, row address, and region address can all be represented by multi-bit binary numbers. When the column address is all 1, the row address increases by one bit and the column address is cleared. When the row address is all 1, the region address increases by one bit and the row address is cleared. In this way, the broadcast of the entire fuse array can be achieved.

[0097] The above-mentioned step of determining whether the fuse address is the fuse address mapped to the first or last redundant address can be implemented by a matching circuit, which can be a circuit structured in the form of a comparator or a lookup table. The input end of this circuit can receive the address output by the address counter during the broadcast process, including the aforementioned region address, row address, and column address. This circuit generally outputs a low-level signal, i.e., a logic 0. When the input address matches the fuse address mapped to the first redundant address, the output signal is pulled high, setting the output to 1. When the input address matches the fuse address mapped to the last redundant address, the output signal is pulled low, setting the output to 0. In this embodiment, the first target address indication signal is active high. In other embodiments, an active low-level first target address indication signal can also be used. For such a signal, the circuit generally outputs a high-level signal, i.e., a logic 1. When the input address matches the fuse address mapped to the first redundant address, the output signal is pulled low, setting the output to 0. When the input address matches the fuse address mapped by the last redundant address, the output signal is pulled high, so that the output is set to 1.

[0098] It is understood that since the fuse addresses between the fuse address mapped by the first redundant address and the fuse address mapped by the last redundant address are mapped consecutively, during the broadcasting process of outputting the fuse addresses between them, neither the fuse address mapped by the first redundant address nor the fuse address mapped by the last redundant address will be matched. Therefore, the signal output by the above-mentioned circuit will not be changed. Since the output is already pulled high when the first redundant address is matched, the circuit will maintain the output of the high-level signal during this period.

[0099] That is, during the broadcast process, when the first fuse address is matched, the matching circuit will continue to output a high-level signal until it matches the first fuse address corresponding to the last redundant address, after which it will switch to outputting a low-level signal. Thus, when the signal output by the matching circuit, i.e., the first target address indication signal, is 1, it indicates that the currently broadcast fuse address is the first fuse address. While the first target indication signal is 1, it can be further determined whether the broadcast fuse address has been used, thereby determining the target fuse address.

[0100] In some embodiments, the method further comprises:

[0101] If the currently read fuse address maps to the last redundant address and the current first fuse address is not an unused fuse address, the value of the resource register of the current memory bank or memory bank group is updated to the first value indicating no available redundant address, and the repair operation is terminated.

[0102] The value stored in the resource register indicates whether the current memory bank or memory bank group has any redundant addresses available for patching failed addresses. When the value is the first value, it indicates that the current memory bank or memory bank group has no available redundant addresses. That is, the redundant addresses of the current memory bank or memory bank group have been used up. Accordingly, the fuse addresses that are mapped one-to-one with the redundant addresses are already stored with other failed addresses. Therefore, patching the failed addresses is unavailable at this point, and the patching operation is terminated.

[0103] Accordingly, when the current storage body or storage body group still has available redundant addresses, the value stored in its resource register may be a second value that is different from the first value. Therefore, in the subsequent patching process, the value of the resource register can be directly detected to determine whether the patching operation can still be performed. If it is detected that the value stored therein is the first value, there is no need to start the detection, that is, there is no need to start the above-mentioned broadcasting and other operations. It can be understood that in the embodiment of the present disclosure, after receiving the patching instruction sent externally, the above-mentioned method may also include: detecting the value stored in the resource register of the storage body or storage body group where the failed address is located. If it is the first value, the patching is terminated and the information of the patching failure can be fed back; if it is the second value, the step of broadcasting the fuse array can continue.

[0104] The fuse address may include multiple fuse units for storing failed addresses and may also include at least one flag bit for indicating whether the fuse address has been used. Therefore, whether the fuse address has been used can be determined by detecting the flag bit of the fuse address.

[0105] FIG4 is a schematic diagram of a patch circuit 200 for a memory provided in an embodiment of the present disclosure. The memory 100 includes a memory array 110 and a fuse array 120. The patch circuit 200 and the fuse array 120 are located in a peripheral circuit of the memory 100. The memory array 110 includes a plurality of memory cells and a plurality of redundant cells. The memory cells have memory cell addresses 111, and the redundant cells have redundant addresses 112. The fuse array 120 includes a plurality of fuse cells, each having a fuse address 121. At least some of the fuse addresses 121 are mapped one-to-one with preset redundant addresses 112. As shown in FIG4 and FIG9 , the patch circuit 200 includes:

[0106] An instruction receiving unit 210 is configured to receive a patch instruction 211 sent from an external source, wherein the patch instruction carries a failure address 113 indicating an address of a failed storage unit;

[0107] An address broadcasting unit 220 connected to the fuse array 120 and the instruction receiving unit 210 and configured to broadcast the fuse array 120;

[0108] The address search unit 230 is connected to the address broadcast unit 220 and is configured to sequentially receive the fuse addresses 121 broadcasted by the address broadcast unit 220 and determine whether the currently broadcast fuse address 121 is a target fuse address until at least one target fuse address is found; wherein the target fuse address is the fuse address 121 mapped to the target redundant address; and the target redundant address is the redundant address 112 that can repair the failed address 113;

[0109] The address writing unit 240 is connected to the fuse array 120 and the address lookup unit 230 , and is configured to decode a first unused target fuse address among the at least one target fuse address and write the failure address 113 to the fuse unit corresponding to the target fuse address.

[0110] In the disclosed embodiments, the memory cells in the memory are used to read and write data, but the memory cells may fail, resulting in inability to read and write data normally. The failure may be a failure of a single memory cell, for example, a failure of the memory cell's transistor, or a failure caused by leakage of the storage capacitor; it may also be a WL failure or a BL failure. The redundant memory cells have the same structure as the memory cells, but do not participate in the reading and writing of data of the normal memory cells. That is, the redundant cells are not accessed under normal circumstances, and can only participate in the reading and writing of data in place of the normal memory cells in the event of a failure.

[0111] The above-mentioned memory cell addresses may include row addresses, column addresses, addresses of memory banks and memory bank groups, etc. Redundant addresses also include row addresses, column addresses, addresses of memory banks and memory bank groups, etc. If a memory cell fails, the above-mentioned row addresses, column addresses, addresses of memory banks and memory bank groups are needed to locate the memory cell. If a WL fails, only the row address and the memory bank or memory bank group are needed to locate the memory cell. If a BL fails, the column address and the memory bank and memory bank group are needed to locate the BL. For failed memory cells, a redundant cell row can be used to replace the memory cells in the row to achieve redundant row repair, or a redundant cell column can be used to replace the memory cells in the column to achieve redundant column repair. If the above-mentioned repair operation is performed inside the memory bank, then only the row address or column address is needed to locate the failure of WL and BL.

[0112] In an embodiment of the present disclosure, the memory further includes a fuse array comprising a large number of one-time editable fuse units. A group of fuse units can be used to store parameters such as addresses. A fuse address can be used to locate a group of fuse units. Therefore, if a group of fuse units stores address data, the fuse address can be used to locate the address data stored in the group of fuse units.

[0113] In an embodiment of the present disclosure, some of the multiple fuse addresses in the fuse array may be mapped one-to-one with redundant addresses, that is, each fuse address corresponds to a redundant address, and this mapping relationship may be a fixed setting in the memory. For example, it is implemented by a fixed decoding method of a local register and an address decoder. Specifically, a local register is provided in the memory and is connected to the address decoder. The local register can store multiple addresses in sequence, which correspond to the part of the fuse array used for mapping with redundant addresses. That is, the address information stored in the fuse array will be stored in the corresponding position of the local register when it is read out. Each address stored in the local register is decoded to its corresponding redundant address when it is transmitted to the address decoder. In this way, a one-to-one mapping of the fuse address and the redundant address is achieved.

[0114] In the disclosed embodiments, the memory can perform PPR to patch failed addresses. The memory receives externally sent patch instructions to obtain the failed address to be patched. The failed address can be the memory cell address of the failed memory cell, including the row address, column address, and address of the memory bank or memory bank group used to locate the memory cell. In some embodiments, the failed address can also be the row address of a failed WL or the column address of a failed BL.

[0115] During the memory manufacturing process, many redundant addresses are set up. These redundant addresses are generally used for testing and repairing before shipment. However, after shipment, the PPR (Pre-printed Position Regulator) typically uses only one or a few fixed redundant addresses. This results in a large number of PPRs being unused after the memory leaves the factory, resulting in a waste of resources.

[0116] Because redundant addresses in the memory are mapped one-to-one to some fuse addresses in the fuse array, the disclosed embodiment employs a broadcast method for the fuse array, sequentially scanning each fuse address in the fuse array and reading the contents stored therein to determine whether the fuse address is an available fuse address that can be used to store a failed address as the target fuse address. The failed address is then written into the available fuse address. Utilizing the mapping relationship between fuse addresses and redundant addresses, the failed address is directly decoded into a redundant address when accessed, thereby implementing a repair. Here, the target redundant address mapped to the target fuse address is a redundant address that can be used to repair the failed address.

[0117] In the disclosed embodiment, considering that the target fuse address may have been used in the previous PPR, that is, other failed addresses have been stored, when writing the failed address this time, it should be confirmed that the target fuse address written is an unused target fuse address among the at least one target fuse address. Since the broadcast process reads the fuse addresses sequentially, it is possible to confirm whether each fuse address is the target fuse address and whether it has been used. If the first unused target fuse address is read, the failed address to be repaired can be written into the target fuse address.

[0118] In this way, the failed address can be written into the next target fuse address during the next PPR. In this way, each fuse address can be accessed in a polling manner through broadcasting, so that its corresponding redundant address has a chance to be used in the PPR, thereby reducing the waste of redundant address resources.

[0119] In the embodiment of the present disclosure, the instruction receiving unit 210 may include a pin for receiving instructions. The instruction receiving unit 110 may also include an instruction decoding unit for decoding received instructions into recognizable patch instructions, and an address decoding unit for decoding received addresses.

[0120] In the disclosed embodiment, the address broadcast unit 220 broadcasts fuse addresses sequentially through polling, allowing each fuse address in the fuse array 120 to be read sequentially. The address broadcast unit 220 can be implemented using a counter, which counts the addresses and sequentially outputs the fuse addresses to the fuse array 120 so that the contents stored in the corresponding fuse addresses can be read. During the reading process, the address broadcast unit 220 also sequentially outputs the fuse addresses 121 to the address lookup unit 230. The address lookup unit 230 then determines whether the received fuse address is the target fuse address mapped to the redundant address based on the received fuse address.

[0121] Because the address broadcast unit 220 broadcasts fuse addresses sequentially, the address writing unit 240 can write the failed address to the first unused target fuse address when the address lookup unit 230 finds the target fuse address, and then terminate the address broadcast. In this way, the failed address to be repaired is written into the fuse address mapped to a redundant address. When the memory receives an access request for the failed address, the failed address can be decoded into the corresponding redundant address based on the mapping relationship between the fuse address and the redundant address, thereby replacing the failed address with the redundant address.

[0122] In some embodiments, as shown in FIG5 , the address broadcast unit 220 includes: a region address counter 221 , a row address counter 222 , and a column address counter 223 ;

[0123] The area address counter 221 is connected to the row address counter 222 and is used to update the count value when the row address counter 222 counts to the last bit;

[0124] The row address counter 222 is connected to the column address counter 223 and is used to update the count value when the column address counter 223 counts to the last bit;

[0125] An input terminal of the column address counter 223 is used to receive an address broadcast clock signal clk. The column address counter 223 is used to update a count value when the address broadcast clock signal clk changes.

[0126] The address broadcast unit 220 can count the column address, row address and region address in sequence to generate address count values, each of which corresponds to a fuse unit address addr. In this way, by broadcasting the address count values, the fuse addresses in the fuse array can be read sequentially.

[0127] In some embodiments, as shown in FIG5 , the address lookup unit 230 includes:

[0128] an address matching circuit 231 connected to the address broadcast unit 220, sequentially receiving the fuse address addr broadcasted by the address broadcast unit 220, and configured to match the fuse address mapped by the first root redundant address of at least one memory bank or memory bank group, and the fuse address mapped by the last root redundant address of at least one memory bank or memory bank group, according to the fuse address addr broadcasted by the address broadcast unit 220;

[0129] an indication signal generating unit 232, connected to the address matching circuit 231, configured to output a high-level signal when the broadcast fuse address matches the fuse address mapped by the first redundant address, and output a low-level signal when the broadcast fuse address matches the fuse address mapped by the last redundant address;

[0130] The search output unit 233 is connected to the fuse array 120 and the address broadcast unit 220, and is used to read the flag information of the fuse address according to the fuse address broadcast by the address broadcast unit 220, and output the fuse address when the flag information indicates that the fuse address is not used.

[0131] In some embodiments, the flag bit of the fuse address includes 1 bit; wherein, when the flag bit is a first value (for example, "0"), it indicates that the first fuse address is not used; when the flag bit is a second value (for example, "1"), it indicates that the first fuse address has been used.

[0132] In other embodiments, the flag bit includes at least two bits; wherein, when at least two bits of the flag bit obtain a first value (for example, "0") after a first operation (for example, an AND operation, an OR operation, an XOR operation, etc.), it indicates that the first fuse address is not used; when at least two bits of the flag bit obtain a second value (for example, "1") after a first operation, it indicates that the first fuse address has been used.

[0133] The above-mentioned flag information is the value of the flag or the value of the flag after the above-mentioned first operation. For a fuse address, it can include several bits for storing addresses, and can also include one or at least two bits for the above-mentioned flag. Exemplarily, a fuse address includes 17 bits, of which 16 bits are used to store addresses and the other 1 bit is a flag. It is understandable that when the fuse address has not been used, the flag information of the fuse address should be the initial value, used to indicate that the fuse address has not yet stored an address; when the fuse address is written into the address, the flag information should also be modified to a value indicating that it has been used.

[0134] In this way, the above-mentioned search output unit 233 can determine whether the target fuse address has been used by detecting the flag information of each target fuse address. When the first unused target fuse address is found, the fuse address can be output so that the address burning unit 240 burns the failed address to the fuse address.

[0135] In some embodiments, as shown in FIG5 , the address matching circuit 231 includes:

[0136] a first matching circuit 231a, configured to determine whether the broadcast fuse address matches the fuse address mapped by the first root redundant address, and to output a first match signal 1st RWL to the indication signal generating unit when a match occurs;

[0137] a second matching circuit 231b, configured to determine whether the broadcast fuse address matches the fuse address mapped by the last redundant address, and to output a second match signal last RWL to the indication signal generating unit when a match occurs;

[0138] The indication signal generating unit 232 includes a first latch, whose output signal is the indication signal 232s. The first latch outputs the high-level signal upon receiving the first match signal and outputs the low-level signal upon receiving the second match signal. For example, the indication signal generating unit 232 can be an RS latch.

[0139] In some embodiments, as shown in FIG6 , the address lookup unit 230 further includes a resource check unit 234 connected to the address matching circuit 231 and configured to receive a second match signal, Last RWL, when the last redundant address is matched. Furthermore, upon receiving the second match signal, Last RWL, the resource check unit 234 detects the flag information of the current fuse address to determine whether the fuse address has been used. If the fuse address has been used, this indicates that the current memory bank or memory bank group no longer has any available redundant cells and corresponding fuse cells. At this point, the patching process can be terminated, and the value of the redundant resource register of the current memory bank or memory bank group is updated to indicate that no redundant addresses are available.

[0140] It should be noted that the patch circuit in the disclosed embodiment can configure the aforementioned first matching circuit 231a and second matching circuit 231b for each memory bank or memory bank group. For example, the first matching circuit 231a and second matching circuit 231b corresponding to the first memory bank bank0 and the i-th memory bank banki shown in FIG5 . In other words, each first matching circuit 231a and second matching circuit 231b is specific to a memory bank or memory bank group. This is because the fuse array in the memory can be used to store any failed addresses of all memory banks or memory bank groups, while the redundant addresses are distributed across each memory bank or memory bank group. In other words, the fuse array can include fuse addresses in different segments for mapping the redundant addresses of different memory banks or memory bank groups.

[0141] Furthermore, when broadcasting fuse addresses, all fuse addresses are broadcasted sequentially in a round-robin manner. Therefore, during the address matching process, it is necessary to determine to which memory bank or memory bank group the redundant address of each fuse address is mapped. Therefore, the address matching circuit 231 includes multiple first matching circuits 231a for matching fuse addresses mapped to the first redundant addresses of multiple different memory banks or memory bank groups; and multiple second matching circuits 231b for matching fuse addresses mapped to the last redundant addresses of multiple different memory banks or memory bank groups.

[0142] Exemplarily, each first matching circuit 231a and second matching circuit 231b includes a first-stage NAND gate and a second-stage NOR gate. The first-stage NAND gate may include multiple NAND gates, and the input of the second-stage NOR gate is connected to the outputs of all the first-stage NAND gates. The multiple inputs of the first-stage NAND gate can be used to receive the row address, column address, and region address after or after inversion, identification information of the memory bank or memory bank group to which the fuse address is mapped, and other required identification information, so that only when a fixed address value (e.g., the fuse address value corresponding to the first redundant address or the fuse address value corresponding to the last redundant address) is input, the inputs of the first-stage NAND gate are all 1. The information after the above operation will only output a logic 1 at a fixed address value. In this way, by setting the logical operation, the first matching circuit will only output a logic 1 when it matches the fuse address mapped to the first redundant word line of a specified memory bank or memory bank group, and the second matching circuit will only output a logic 1 when it matches the fuse address mapped to the last redundant word line.

[0143] For example, as shown in FIG6 , the first-stage NAND gate includes a three-input NAND gate NAND1 and a two-input NAND gate NAND2. The input of NAND1 is used to receive the activation signal Bank i (i can be the counting sequence number of any memory bank or memory bank group) of the currently broadcast memory bank or memory bank group, the column address X Addr, and the column address Y Addr, or the inverted signals of the above signals (i.e., the dotted position in FIG6 can be connected to an inverter). The input of NAND2 is used to receive the region address S Addr or its inverted signal (i.e., the dotted position in FIG6 can be connected to an inverter) and the address clock signal clk. The output signals of both are input to the NOR gate NOR. When all input signals match the predetermined signal (i.e., when the currently broadcast fuse address matches the preset fuse address), the NOR gate NOR will output a logic 1, i.e., a high-level signal as the first match signal 1st RWL or the second match signal last RWL, and provide it to the indication signal generation unit 232.

[0144] Thus, when the address matching circuit fails to match the fuse address of the first redundant address mapping or the fuse address of the last redundant address mapping, it maintains the output logic 0, that is, outputs a low-level signal. When the fuse address of the first redundant address mapping is matched, the circuit outputs a logic 1 as the first match signal 1st RWL, which is provided to the indication signal generation unit 232, thereby pulling the output signal of the indication signal generation unit 232 high. When the fuse address of the last redundant address mapping is matched, the circuit outputs a logic 1 again as the second match signal last RWL, which is provided to the indication signal generation unit 232, thereby pulling the output signal of the indication signal generation unit 232 low.

[0145] In some embodiments, as shown in FIG7 , the search output unit 233 includes: a first AND gate AND, a first input terminal of which is connected to the output terminal of the first latch LATCH1 , and a second input terminal for receiving the flag bit information;

[0146] a first flip-flop FF1, whose signal input terminal is connected to the output terminal of the first AND gate AND1, and whose clock input terminal is used to receive the broadcast clock signal;

[0147] A second flip-flop FF2, whose signal input terminal is connected to the first power supply terminal VCC, and whose clock input terminal is connected to the output terminal of the first flip-flop FF1;

[0148] A second latch LATCH2, whose signal input terminal is connected to the address broadcast unit 220, is used to sequentially receive the currently broadcasted fuse address Fuse addr i[n:0], and whose clock input terminal is connected to the output terminal of the second flip-flop FF2;

[0149] The second latch LATCH2 outputs the target fuse address when the first latch LATCH1 outputs the high level signal and the flag bit information indicates that the flag bit is not used.

[0150] Among them, when the flag information (Fuse used bit) is "1", it means that the fuse address currently broadcast has not been used, and the flag information is directly input into the first AND gate AND; when the flag information (Fuse used bit) is "0", it means that the fuse address currently broadcast has not been used, and the flag signal is inverted and then input into the first AND gate AND.

[0151] The signal waveforms of the above circuit are shown in Figure 8. Since the period during which the first latch LATCH1 outputs a high level indicates that the currently broadcast fuse address is the target fuse address mapped to the target redundant address, when the flag information (Fuse used bit) is "1," indicating that the currently broadcast fuse address has not been used, this flag information is directly input into the first AND gate AND. When the flag information (Fuse used bit) is "0," indicating that the currently broadcast fuse address has not been used, this flag information is inverted and then input into the first AND gate AND. Therefore, the Fuse used bit of the unused fuse is 1 at the input of the first AND gate AND. Therefore, when the first AND gate AND outputs a high level signal, it indicates that the currently broadcast fuse address is a fuse address that can be used to repair a failed address. The output signal of the first AND gate AND is transmitted to the first flip-flop FF1, whose output signal serves as the clock signal for the second flip-flop FF2. It can be understood that when the first AND gate AND outputs a high level signal, it correspondingly triggers the second flip-flop FF2 to output a high level signal. Because the output signal of the first flip-flop serves as the clock signal for the second flip-flop FF2, after the first flip-flop FF1 outputs a high-level signal, the output signal of the second flip-flop FF2 will transition to a high-level signal and remain high. Thus, the output signal of the second flip-flop FF2 serves as the clock signal for the second latch LATCH2. Only when the output signal transitions will the currently broadcast fuse address—that is, the first fuse address that can be used to repair a failed address—be output.

[0152] It should be noted that the second latch LATCH2 can also be implemented by a trigger.

[0153] In some embodiments, as shown in FIG9 , the patching circuit further includes:

[0154] a local register 250 comprising a plurality of address registers 251, each address register 251 being sequentially mapped one-to-one with the redundant address, the local register 250 being configured to store address data stored in at least a portion of the fuse addresses in the fuse array that are mapped one-to-one with the redundant address;

[0155] The address decoding unit 260 is connected to the local register 250 and is used to receive the address to be accessed and access the mapped redundant address when the address to be accessed is consistent with the failed address stored in the local register, and access the address to be accessed when the address to be accessed is inconsistent with the failed address.

[0156] In the embodiment of the present disclosure, the address stored in the fuse array can be read out to the local register 250 by broadcasting the fuse array. The local register and the redundant address have a one-to-one mapping relationship, that is, when the address decoder 260 decodes the address stored in the specified position in the local register, no matter which storage unit the address actually points to, the address decoder 260 decodes it as a fixed redundant address. In other words, the local register is mapped one-to-one with the fuse address in the fuse array, and one-to-one with the redundant address. Therefore, when the fuse address stores a failed address, the failed address can be read into the corresponding local register 250 and stored by broadcasting. When a command to access the failed address is received, the address decoder 260 decodes the redundant address mapped by the local register 250 storing the failed address; when the address to be accessed is not a failed address, the address decoder performs normal decoding.

[0157] The present disclosure also provides a memory, as shown in FIG10 , wherein the memory 300 includes:

[0158] Storage array 310; wherein the storage array includes a plurality of storage units and a plurality of redundant units, the storage units have storage unit addresses, and the redundant units have redundant addresses;

[0159] The peripheral circuit 320 includes a fuse array 321 , wherein the fuse array includes a plurality of fuse units, and the fuse units have fuse addresses; the repair circuit 200 provided by any of the above embodiments.

[0160] It should be understood that “some embodiments”, “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0161] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0162] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A repair method for a memory (100), characterized in that, The memory includes a storage array (110) and a fuse array (120). The storage array includes a plurality of storage units and a plurality of redundant units. The storage units have storage unit addresses (111), and the redundant units have redundant addresses (112). The fuse array (120) includes a plurality of fuse units, and the fuse units have fuse addresses (121); wherein at least part of the fuse addresses (121) are mapped one-to-one with preset redundant addresses (112); the repair method includes: (S101) The memory receives a repair instruction sent externally. The repair instruction carries a failure address, and the failure address is the storage unit address of a failed storage unit. (S102) Broadcast the fuse array, and sequentially determine whether the currently broadcast fuse address is a target fuse address until at least one target fuse address is found; wherein the target fuse address is the fuse address mapped to the target redundant address; the target redundant address is the redundant address that can repair the failure address. (S103) Write the failure address into the first unused target fuse address among the at least one target fuse addresses, so as to access the target redundant address when an access request for the failure address is received.

2. The repair method according to claim 1, characterized in that, The broadcasting of the fuse array and sequentially determining whether the currently broadcast fuse address is a target fuse address specifically includes: (S11) Determine whether the currently broadcast fuse address is a fuse address mapped to a redundant address in the same bank or bank group as the failure address. (S12) If so, determine the currently broadcast fuse address as the first fuse address. If not, continue to read the next address. (S13) Determine whether the first fuse address is unused. (S14) If so, determine the first fuse address as the target fuse address. If not, continue to read the next address.

3. The repair method according to claim 2, characterized in that, The determination of whether the currently broadcast fuse address is a fuse address mapped to a redundant address in the same bank or bank group as the failure address specifically includes: Determine whether the currently broadcast fuse address is a fuse address mapped to the first redundant address in the same bank or bank group as the failure address. Determine whether the currently broadcast fuse address is a fuse address mapped to the last redundant address in the same bank or bank group as the failure address. The determination of the currently broadcast fuse address as the first fuse address includes: determining all fuse addresses between the fuse address mapped to the first redundant address and the fuse address mapped to the last redundant address in the same bank or bank group as the failure address as the first fuse address.

4. The repair method according to claim 3, wherein the broadcasting of the fuse array specifically includes: Determine the currently read fuse address by counting the region address, row address, and column address of the fuse array respectively. Determining whether the currently read fuse address is the fuse address mapped by the first redundant address in the same memory bank or memory bank group as the failure address specifically includes: Determining whether the count values of the region address, row address, and column address of the currently read fuse address are the region address, row address, and column address of the fuse address mapped by the first redundant address. If so, raising the first target address indication signal; Determining whether the currently read fuse address is the fuse address mapped by the last redundant address in the same memory bank or memory bank group as the failure address specifically includes: Determining whether the count values of the region address, row address, and column address of the currently read fuse address are the region address, row address, and column address of the fuse address mapped by the last redundant address. If so, lowering the first target address indication signal.

5. The patching method according to claim 3 or 4, characterized in that, The method further includes: If the currently read fuse address maps to the last redundant address and the current first fuse address is not an unused fuse address, updating the value of the resource register of the current memory bank or memory bank group to a first value indicating no available redundant address and ending the repair operation.

6. A repair circuit (200) for a memory, characterized in that, The memory (100) includes a memory array (110) and a fuse array (120). The memory array includes a plurality of memory cells and a plurality of redundant cells. The memory cells have memory cell addresses (111), and the redundant cells have redundant addresses (112). The fuse array includes a plurality of fuse cells, and the fuse cells have fuse addresses (121); wherein, at least some of the fuse addresses (121) are mapped one-to-one with preset redundant addresses (112); the repair circuit (200) includes: An instruction receiving unit (210) for receiving a repair instruction (211) externally transmitted, and the repair instruction carries a failure address (113) for indicating the failed memory cell address; An address broadcasting unit (220) connected to the fuse array (120) and the instruction receiving unit (210) for broadcasting to the fuse array (120); An address searching unit (230) connected to the address broadcasting unit (220) for sequentially receiving the fuse addresses (121) broadcast by the address broadcasting unit (220) and determining whether the currently broadcast fuse address (121) is a target fuse address until at least one target fuse address is found; wherein, the target fuse address is the fuse address mapping the target redundant address; the target redundant address is the redundant address (112) that can repair the failure address (113); An address programming unit (240) connected to the fuse array (120) and the address searching unit (230) for decoding the first unused target fuse address among the at least one target fuse addresses and programming the failure address (113) into the fuse cell corresponding to the target fuse address. The address searching unit (230) includes:

7. The repair circuit according to claim 6, characterized in that, ​ An address matching circuit (231), connected to the address broadcasting unit (220), sequentially receives the fuse addresses (addr) broadcast by the address broadcasting unit (220), and is used to match the fuse addresses mapped by the first redundant address of at least one memory bank or memory bank group according to the fuse addresses (addr) broadcast by the address broadcasting unit (220), and to match the fuse addresses mapped by the last redundant address of at least one memory bank or memory bank group; An indication signal generating unit (232), connected to the address matching circuit (231), is used to output a high-level signal when the broadcast fuse address matches the fuse address mapped by the first redundant address, and to output a low-level signal when the broadcast fuse address matches the fuse address mapped by the last redundant address; A lookup output unit (233), connected to the fuse array (120) and the address broadcasting unit (220), is used to read the flag bit information of the fuse address according to the fuse address broadcast by the address broadcasting unit (220), and to output the fuse address when the flag bit information indicates that the fuse address is not in use.

8. The repair circuit according to claim 7, characterized in that The address matching circuit includes: A first matching circuit (231a), used to determine whether the broadcast fuse address matches the fuse address mapped by the first redundant address, and used to output a first matching signal (1st RWL) to the indication signal generating unit when they match; A second matching circuit (231b), used to determine whether the broadcast fuse address matches the fuse address mapped by the last redundant address, and used to output a second matching signal (last RWL) to the indication signal generating unit when they match; The indication signal generating unit (232) includes a first latch, and the first latch outputs the high-level signal when receiving the first matching signal, and outputs the low-level signal when receiving the second matching signal.

9. The repair circuit according to claim 8, wherein, The lookup output unit (233) includes: a first AND gate, whose first input terminal is connected to the output terminal of the first latch (LATCH1), and whose second input terminal is used to receive the flag bit information; A first flip-flop (FF1), whose signal input terminal is connected to the output terminal of the first AND gate (AND1), and whose clock input terminal is used to receive the broadcast clock signal of the broadcast; A second flip-flop (FF2), whose signal input terminal is connected to the first power supply terminal (VCC), and whose clock input terminal is connected to the output terminal of the first flip-flop (FF1); A second latch (LATCH2), whose signal input terminal is connected to the address broadcasting unit (220), is used to sequentially receive the broadcast fuse addresses (Fuse addr i[n:0]), and whose clock input terminal is connected to the output terminal of the second flip-flop (FF2); The second latch (LATCH2) outputs the target fuse address when the first latch (LATCH1) outputs the high-level signal and the flag bit information indicates that the flag bit is not in use.

10. A memory (300), characterized in that, Including: A storage array (310); wherein the storage array includes a plurality of storage units and a plurality of redundant units, the storage units have storage unit addresses, and the redundant units have redundant addresses; A peripheral circuit (320); wherein the peripheral circuit includes a fuse array (321), the fuse array includes a plurality of fuse units, the fuse units have fuse addresses, and a repair circuit (200) according to any one of claims 6 to 9.

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