Multi-host and multi-compute express link memory device system and application device thereof

Abstract

The embodiments of the present application relate to the technical field of computer systems and storage. Provided are a multi-host and multi-compute express link memory device system and an application device thereof. The method comprises: in response to a memory allocation request, determining a target express link memory device on the basis of selection popularity, generating a configuration instruction, and accessing the target express link memory device to a host according to the configuration instruction; in response to the access of the target express link memory device, acquiring device parameter information of compute express link memory devices; on the basis of the device parameter information, determining an address space; allocating a target memory slice on the basis of memory requirements of the memory allocation request, and, on the basis of a host identity identifier and the target memory slice, updating memory management information and generating a memory allocation success message; reading the memory allocation success message, and enabling the address space corresponding to the target memory slice; and, on the basis of the address space, managing the target compute express link memory device. The present application can ensure the secure use of compute express link memories among multiple hosts.

Description

A multi-host and multi-computing fast link memory device system and its application device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 29, 2023, with application number 202311862782.5, and entitled “A multi-host and multi-computing fast-link memory device system and its application device,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer systems and storage technology, and in particular to a multi-host and multi-computing fast link memory device system, an electronic device, and a computer storage medium. Background Art

[0004] Compute Express Link (CXL) is a new interconnect technology standard for processors, memory expansion, and accelerators. It maintains coherency between the CPU (central processing unit) memory space and the memory of connected devices. While CXL 3.0 currently supports multiple hosts sharing the same CXL memory device, reliable and secure management methods for multi-host CXL memory sharing are still lacking.

[0005] Summary of the Invention

[0006] In view of the above problems, embodiments of the present application are proposed to provide a multi-host and multi-computing fast link memory device system, an electronic device and a computer storage medium that overcome the above problems or at least partially solve the above problems.

[0007] To solve the above problems, in a first aspect of the present application, an embodiment of the present application discloses a multi-host and multi-computing fast-link memory device system, in which any computing fast-link memory device in the system is connected to multiple hosts through a data center manager, any computing fast-link memory device is divided into multiple memory slices based on a preset size, and a single memory slice of any computing fast-link memory device is allocated to one host for use at the same time. The host is provided with a host identity, and the computing fast-link memory device stores memory management information, which records the correspondence between the memory slices and the multiple hosts;

[0008] The host determines, in response to the memory allocation request, a selection heat of any computing fast link memory device, determines a target computing fast link memory device from any computing fast link memory device based on the selection heat, generates a configuration instruction, the configuration instruction corresponds to the target computing fast link memory device, and sends the configuration instruction to the data center manager;

[0009] The data center manager connects the target computing fast link memory device to the host according to the configuration instructions;

[0010] The host obtains device parameter information of the computing fast link memory device in response to access of the target computing fast link memory device;

[0011] The host determines the address space based on the device parameter information;

[0012] The host sends a memory allocation request to the target compute fast link memory device;

[0013] The target computing fast link memory device allocates a target memory slice based on the memory requirement of the memory allocation request, updates memory management information based on the host identity and the target memory slice, and generates a memory allocation success message;

[0014] The host reads the memory allocation success message and enables the address space corresponding to the target memory slice;

[0015] The host computes fast links to memory devices based on the address space management target.

[0016] Optionally, the system further includes:

[0017] The host determines, in response to the memory access request, an access address of the memory access request;

[0018] The host determines whether the access address belongs to the target memory slice of the target computing fast link memory device, and determines the validity of the access address;

[0019] The host performs access control based on the validity of the access address.

[0020] Optionally, the step of performing access control based on the validity of the access address includes:

[0021] When the access address belongs to the target computing fast link memory device and does not correspond to the target memory slice, an access exception message is generated; the access exception message indicates that the target computing fast link memory device is not authorized to be accessed;

[0022] When the access address corresponds to the target memory slice, a memory access request is sent to the target computing fast link memory device to access the target computing fast link memory device.

[0023] Optionally, the system further includes:

[0024] The host determines, in response to the memory release request, an address space corresponding to the target memory slice;

[0025] The host sends the address space corresponding to the target memory slice to the target computing fast link memory device;

[0026] The target computing quickly links the memory device to release the target memory slice and generates a release success message.

[0027] Optionally, the system further includes:

[0028] The host updates the memory management information according to the release success information, and determines that the allocation state corresponding to the target memory slice is an allocatable state.

[0029] Optionally, the system further includes:

[0030] The host sets the address space corresponding to the target memory slice to a disabled state based on the release success information.

[0031] Optionally, in response to the memory allocation request, determining the selection heat of any computing fast link memory device, and determining a target computing fast link memory device from any computing fast link memory device according to the selection heat includes:

[0032] In response to a memory allocation request, receiving unallocated memory information and access latency information of a computing fast link memory device provided by a data center manager;

[0033] Filtering computing fast link memory devices provided by the data center manager according to the unallocated memory information and the access delay information to generate a first computing fast link memory device set, where the computing fast link memory devices in the first computing fast link memory device set meet the unallocated memory information and the access delay information;

[0034] A target computing fast link memory device is determined from the first computing fast link memory device set according to the selection heat.

[0035] Optionally, the step of screening computing fast link memory devices provided by the data center manager based on the unallocated memory information and the access latency information to generate a first computing fast link memory device set includes:

[0036] Filtering computing fast link memory devices provided by the data center manager according to the unallocated memory information to generate a second computing fast link memory device set, wherein computing fast link memory devices in the second computing fast link memory device set satisfy the unallocated memory information;

[0037] The second computing fast link memory device set is screened according to the access delay information to generate a first computing fast link memory device set.

[0038] Optionally, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat includes:

[0039] Calculating selection heat values ​​of computing fast link memory devices in the first computing fast link memory device set based on a selection heat calculation formula;

[0040] sorting the computing fast link memory devices in the first computing fast link memory device set based on descending order of selection heat values;

[0041] The first compute quick link memory device is determined as the target compute quick link memory device.

[0042] Optionally, select the heat calculation formula as:

[0043] M ava The unallocated memory size of the fast link memory device to be calculated, M req The requested memory size for the memory allocation request, D max Calculate the maximum access delay in the fast link memory device set for the first time; D cur is the access delay of the fast link memory device to be calculated; ε is the preset impact factor.

[0044] Optionally, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat further includes:

[0045] Memory utilization is determined based on unallocated memory, which is the ratio of allocated memory size to the total memory size of the Quick Link Memory device.

[0046] Optionally, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat further includes:

[0047] The preset impact factor is determined based on memory utilization. The preset impact factor formula is:

[0048] Optionally, the system includes:

[0049] The host sends a configuration request to the data center manager to obtain device information of the computing fast link bus;

[0050] The host creates a directed graph based on the device information;

[0051] The host determines and calculates access delay information of the fast link memory device based on the directed graph.

[0052] Optionally, the host device has a first key, the target computing quick link memory device has a second public key, and the system further includes:

[0053] The host generates a re-encryption key based on the first key and the second public key;

[0054] The host sends the re-encryption key to the target compute Quick Link memory device.

[0055] Optionally, the host device further has a first public key, and the system further includes:

[0056] In response to the information transmission request, the host encrypts the first secret key using the first public key to generate a key ciphertext;

[0057] The host packages the key ciphertext and the ciphertext information to generate first encrypted information;

[0058] The host sends the first encrypted information to the target computing quick link memory device;

[0059] The target computing quick link memory device decrypts the first encrypted information based on the re-encryption key.

[0060] Optionally, the system further includes:

[0061] The host receives the second encrypted information sent by the target computing quick link memory device;

[0062] The host decrypts the second encrypted information based on the first key.

[0063] Optionally, the system further includes:

[0064] The host initializes the first public key and the first secret key.

[0065] Optionally, the system further includes:

[0066] The computing fast link memory device receives a memory allocation request;

[0067] The computing fast link memory device performs memory allocation based on the memory allocation request, updates memory management information based on the host identity, and generates a memory allocation success message;

[0068] The Compute Quick Link memory device sends a memory allocation success message to the host.

[0069] Optionally, the system further includes:

[0070] When receiving a host access request, the computing fast link memory device verifies a target access memory of the host access request;

[0071] The computing fast link memory device determines, based on the memory management information, whether the target access memory belongs to the host corresponding to the host access request;

[0072] The computing fast link memory device responds to the host access request when the target access memory belongs to the host corresponding to the host access request;

[0073] The computing fast link memory device rejects the host access request when the target access memory does not belong to the host corresponding to the host access request.

[0074] In the second aspect of the present application, an embodiment of the present application discloses an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, the multi-host and multi-computing fast-link memory device system as above is implemented.

[0075] In the third aspect of the present application, an embodiment of the present application discloses a computer non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the multi-host and multi-computing fast link memory device system as described above is implemented.

[0076] The embodiments of the present application include the following advantages:

[0077] In an embodiment of the present application, a host determines the selection popularity of any computing quick link memory device in response to a memory allocation request, and determines a target computing quick link memory device from any computing quick link memory device based on the selection popularity, generates a configuration instruction, and the configuration instruction corresponds to the target computing quick link memory device; sends the configuration instruction to a data center manager; the data center manager connects the target computing quick link memory device to the host based on the configuration instruction; the host obtains device parameter information of the computing quick link memory device in response to the connection of the target computing quick link memory device; the host determines an address space based on the device parameter information; the host sends a memory allocation request to the target computing quick link memory device; the target computing quick link memory device allocates a target memory slice based on the memory requirement of the memory allocation request, updates memory management information based on the host identity and the target memory slice, and generates a memory allocation success message; the host reads the memory allocation success message and enables the address space corresponding to the target memory slice; the host manages the target computing quick link memory device based on the address space; by setting a secure access mechanism based on the device information of the computing quick link memory device and the memory address of the host device, the target computing quick link memory device processes the host-based forwarding request, which can ensure the safe and orderly use of computing quick link memory between hosts. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] FIG1 is a flowchart of the execution steps of an embodiment of a multi-host and multi-computing fast link memory device system of the present application;

[0079] FIG2 is a schematic diagram of the interaction between a host device and a computing fast link memory device in an embodiment of a multi-host and multi-computing fast link memory device system of the present application;

[0080] FIG3 is a schematic diagram of a fast link memory device of an embodiment of a multi-host and multi-computing fast link memory device system of the present application;

[0081] FIG4 is a structural block diagram of an electronic device provided in an embodiment of the present application;

[0082] FIG5 is a structural block diagram of a storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0083] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0084] Referring to Figure 1, a flowchart of the execution steps of an embodiment of a multi-host and multi-computing fast-link memory device system of the present application is shown. In the system, any computing fast-link memory device is connected to multiple hosts through a data center manager. Any computing fast-link memory device is divided into multiple memory slices based on a preset size. A single memory slice of any computing fast-link memory device is allocated to one host for use at the same time. The host is provided with a host identity. The computing fast-link memory device stores memory management information. The memory management information records the correspondence between the memory slices and multiple hosts.

[0085] In an embodiment of the present application, a host device can be connected to at least one computing express link memory device. The computing express link memory device is a CXL memory device. For a schematic diagram of the connection between the computing express link memory device and the host device, please refer to Figure 2. A CXL memory device can provide multiple CXL ports. Through the CXL Fabric (switch), each port of the CXL memory device is connected to a host. The CXL memory device acts as a logical memory device of the host device and exposes the memory capacity of the entire device. Multiple hosts can access the CXL memory device as needed. For a single CXL memory device, as shown in Figure 3, the CXL memory device includes the following CXL interface unit, address mapping unit, access permission unit, memory controller, DRAM (memory), communication unit, memory management unit and usage monitoring and alarm unit. The CXL address mapping unit converts the memory address into the physical address of the DRAM, and the access permission unit verifies the legitimacy of the access. The memory controller provides functions such as memory error checking, management and isolation. The communication unit is responsible for managing network communications. The memory management unit mainly stores memory management information and is responsible for the management of the proxy re-encryption key, the device private key and the host public key. The memory management information records the host ID (identity identifier) ​​of the host to which each piece of memory belongs. The utilization monitoring and alarm unit is used to monitor the memory utilization and display the memory utilization of the current device. When the utilization rate of a certain CXL memory in the system exceeds 85%, an alarm will be issued to remind the administrator to increase the memory to avoid reducing the system performance due to lack of system memory. Among them, the memory management information of the CXL memory device is represented by an array. Each member of the array records the host ID to which the corresponding memory space belongs. The size of each memory piece can be configured according to demand, such as 1G (bytes). After the CXL memory device is powered on, the device will be initialized and the memory management information array will be cleared.

[0086] The following steps can be performed to quickly link multiple hosts and multiple computing devices to a memory device system:

[0087] Step 101: In response to a memory allocation request, the host determines the selection popularity of any computing quick link memory device, determines a target computing quick link memory device from any computing quick link memory device based on the selection popularity, generates a configuration instruction corresponding to the target computing quick link memory device, and sends the configuration instruction to a data center manager.

[0088] When the host is powered on or a new CXL memory device is connected to the CXL Fabric network, there will be an access signal for the computing fast link memory device, such as a CXL hot-swap signal. In response to the access signal of the computing fast link memory device, the device information of the computing fast link memory device can be obtained. The device information includes but is not limited to device model, memory size and other device-related information, and the device information can be saved in the CXL device information table. For example, in a Linux (operating) system, each CXL memory device can be regarded as a NUMA (memory) node without a CPU (central processing unit), and the relevant information can be recorded in the pg_data_t (structure) structure, and also in the node linked list pgdat_litst (structure). Determine the selection heat of each computing fast link memory device, and determine the target computing fast link memory device from all computing fast link memory devices based on the selection heat, and generate configuration instructions. Among them, the configuration instructions correspond to the target computing fast link memory device

[0089] The generated configuration instructions can then be sent to the data center manager.

[0090] Step 102: The data center manager connects the target computing quick link memory device to the host according to the configuration instruction;

[0091] Sending the configuration instruction to the data center manager After receiving the configuration instruction, the data center manager can connect the target computing fast link memory device to the host based on the configuration instruction, so that the host can subsequently call the computing fast link memory device for use.

[0092] Step 103: In response to the access of the target computing fast link memory device, the host obtains device parameter information of the computing fast link memory device;

[0093] When the target computing fast link memory device is connected to the host, device parameter information of the computing fast link memory device can be obtained.

[0094] Step 104: The host determines the address space based on the device information;

[0095] The host determines the address space based on the device parameter information, and the host can allocate the address space to the computing fast link memory device for use.

[0096] Step 105: The host sends a memory allocation request to the target computing quick link memory device;

[0097] The host may send the memory allocation request to the target computing quick link memory device in response to the memory allocation request, so as to perform memory allocation management in the target computing quick link memory device.

[0098] Step 106: The target computing fast link memory device allocates a target memory slice based on the memory requirement of the memory allocation request, updates memory management information based on the host identity and the target memory slice, and generates a memory allocation success message;

[0099] The target computing quick link memory device can allocate a target memory slice based on the memory requirement size of the memory allocation request, the size of the target memory slice is not less than the memory requirement size of the memory allocation request, based on the host identity and the target memory slice, update the memory management information, and generate a memory allocation success message.

[0100] Step 107: The host reads the memory allocation success message and enables the address space corresponding to the target memory slice.

[0101] The host device reads the memory allocation success message, enables the address space, and activates the address space corresponding to the target memory slice so that the address space can be used by the virtual machine deployed thereon.

[0102] In step 108 , the host calculates a fast link memory device based on the address space management target.

[0103] The host can manage the target computing fast link memory device based on the address space by performing operations such as writing or releasing in the address space.

[0104] In summary, when a host device discovers that it needs to apply for CXL memory allocation to run a new virtual machine, it first determines the target CXL memory device and its node ID, and then sends a request to the target CXL memory device through the management network. The request information includes the host ID and the size of the requested memory. The target CXL memory device allocates sufficient memory based on the request, updates the CXL memory management information, saves the ID of the host to which the newly allocated memory slice belongs, and finally sends a successful allocation message to the host, which includes the allocated memory location. After receiving the message, the host notifies the Linux Kenel memory management unit, first setting the status of the corresponding range of memory to enable. The hypervisor then uses the numa_alloc_onnode() function to allocate memory on the specified node, that is, allocates memory on the target CXL memory device, and finally uses this memory as all or part of the memory of the virtual machine.

[0105] In some embodiments of the present application, the system also includes: the host determines the access address of the memory access request in response to the memory access request; the host determines whether the access address belongs to the target memory slice of the target computing quick link memory device, and determines the validity of the access address; the host performs access control based on the validity of the access address.

[0106] In an embodiment of the present application, when access to a target computing quick link memory device is required, the access address of the memory access request can be determined in response to the memory access request, and then it is determined whether the access address belongs to the target memory slice of the target computing quick link memory device to determine the validity of the access address; the host performs access control based on the validity of the access address to control whether the memory access request is allowed.

[0107] In some embodiments of the present application, the system also includes: the step of performing access control based on the validity of the access address includes: generating access exception information when the access address belongs to the target computing quick link memory device and does not correspond to the target memory slice; the access exception information indicates that there is no permission to access the target computing quick link memory device; when the access address corresponds to the target memory slice, sending a memory access request to the target computing quick link memory device to access the target computing quick link memory device.

[0108] When a virtual machine application on a host device accesses the memory of a CXL device, the host device responds to the memory access request, determines the access address of the memory access request, and generates access exception information when the access address does not belong to the address space. When the access address belongs to the address space, the memory access request can be sent to the target computing fast link memory device to access the target computing fast link memory device to obtain data. Specifically, the memory access request can be forwarded to the CXL memory device. When the CXL memory device receives the access request, its access permission unit will check whether the memory range has been allocated. If the memory address has been allocated, the data will be returned normally. If the memory address has not been allocated, a memory access failure will be returned. The host will generate a memory access exception, which will be handled by the exception handler.

[0109] In some embodiments of the present application, the system also includes: the host determines the address space corresponding to the target memory slice in response to the memory release request; the host sends the address space corresponding to the target memory slice to the target computing quick link memory device; the target computing quick link memory device is also used to release the target memory slice and generate a release success message.

[0110] When a host device needs to release memory from a target CXL device (for example, when a virtual machine stops running), it sends a memory release request to the target CXL device via the management network. The message includes the location and size of the memory to be released. Upon receiving the message, the target CXL memory device modifies its memory management information, clears the host ID of the corresponding memory slice, and then responds to the host confirming the successful memory release. Upon receiving the successful release message, the host sets the memory status of the corresponding address space range to disabled.

[0111] In some embodiments of the present application, the system further includes: the host updates the memory management information according to the release success information, and determines that the allocation state corresponding to the target memory slice is an allocatable state.

[0112] After the release is successful, the memory management information can be updated according to the release success information, and the allocation state corresponding to the target memory slice can be determined as an allocatable state, so that the target memory slice can be allocated to other hosts again.

[0113] In some embodiments of the present application, the system further includes: the host setting the address space corresponding to the target memory slice to a disabled state based on the release success information.

[0114] After releasing the corresponding memory, the address space corresponding to the target memory slice may be set to a disabled state to prevent the host from processing the address space corresponding to the target memory slice, which may cause data loss.

[0115] In some embodiments of the present application, in response to a memory allocation request, determining the selection heat of any computing quick link memory device, and determining the target computing quick link memory device from any computing quick link memory device based on the selection heat includes the following steps: in response to the memory allocation request, receiving the unallocated memory information and access delay information of the computing quick link memory device provided by the data center manager; based on the unallocated memory information and access delay information, screening the computing quick link memory devices provided by the data center manager to generate a first computing quick link memory device set, wherein the computing quick link memory devices in the first computing quick link memory device set meet the unallocated memory information and access delay information.

[0116] During memory allocation, since the host stores device information for CXL memory devices, it sends selection information to the CXL memory devices via the management network. In response to the memory allocation request, the host receives unallocated memory information and access delay information for the compute fast link memory devices provided by the data center manager. Based on the unallocated memory information and access delay information, the host filters the compute fast link memory devices provided by the data center manager to generate a first compute fast link memory device set. The compute fast link memory devices in the first compute fast link memory device set satisfy the unallocated memory information and access delay information. A target compute fast link memory device is determined from the first compute fast link memory device set based on the selection popularity. This allows the target compute fast link memory device to be selected based on availability.

[0117] Furthermore, based on the unallocated memory information and the access delay information, the computing quick link memory devices provided by the data center manager are screened to generate a first computing quick link memory device set, including the steps of: based on the unallocated memory information, screening the computing quick link memory devices provided by the data center manager to generate a second computing quick link memory device set, wherein the computing quick link memory devices in the second computing quick link memory device set meet the unallocated memory information; and screening the second computing quick link memory device set based on the access delay information to generate a first computing quick link memory device set.

[0118] Furthermore, the step of determining the target computing quick link memory device from the first computing quick link memory device set based on the selection heat includes: calculating the selection heat value of the computing quick link memory device in the first computing quick link memory device set based on the selection heat calculation formula; sorting the computing quick link memory devices in the first computing quick link memory device set based on descending order of the selection heat value; and determining the first-place computing quick link memory device as the target computing quick link memory device.

[0119] The heat data corresponding to the latency parameter and the remaining memory information can be calculated according to a preset heat calculation formula. Then, the computing fast link memory devices are sorted in descending order based on the size of the heat data, and the first computing fast link memory device, that is, the computing fast link memory device with the largest heat data, is selected as the target computing fast link memory device. The heat calculation formula can be:

[0120] M ava The unallocated memory size of the fast link memory device to be calculated, M req The requested memory size for the memory allocation request, D max Calculate the maximum access delay in the fast link memory device set for the first time; D cur is the access delay of the fast link memory device to be calculated; ε is the preset impact factor.

[0121] In some embodiments of the present application, the step of determining a target computing quick link memory device from a first computing quick link memory device set based on selection heat also includes: determining memory utilization based on unallocated memory, where the memory utilization is the ratio of the allocated memory size to the total memory size of the quick link memory device.

[0122] Specifically, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat further includes:

[0123] The preset impact factor is determined based on memory utilization. The preset impact factor formula is:

[0124] Furthermore, before calculating heat data, the memory occupancy rate can be determined based on the remaining memory information to determine whether the memory occupancy rate is too high. When the memory occupancy rate is less than a preset usage threshold, the fast link memory device can be considered as a candidate. In response to the memory occupancy rate being less than the preset usage threshold, the heat data calculation step based on the heat calculation formula, latency parameters, and remaining memory information can be executed for further screening.

[0125] In addition, in response to the memory occupancy rate being not less than a preset usage threshold, the heat data is determined to be zero.

[0126] When the memory occupancy rate is not less than the preset usage threshold, that is, the usage rate of the computing fast link memory device is high and it is not suitable as a candidate. The heat data can be determined to be zero to make it the computing fast link memory device with the lowest heat.

[0127] In some embodiments of the present application, the system includes: the host sends a configuration request to the data center manager to obtain device information of the computing fast link bus; the host establishes a directed graph based on the device information; the host determines the access delay information of the computing fast link memory device based on the directed graph.

[0128] In an embodiment of the present application, a host can obtain device information for the Compute Express Link bus by sending a configuration request to a data center manager; a directed graph is then constructed based on the device information; and access latency information for Compute Express Link memory devices is determined based on the directed graph. Specifically, a command is sent from the management network to a CXL Switch in the CXL Fabric network to obtain information such as its configuration, ports, and port connections, thereby constructing a directed graph. The access latency from the host to each CXL memory device is calculated using signal latency as an edge weight.

[0129] In some embodiments of the present application, the system further includes: the host initializing the first public key and the first secret key.

[0130] The host device can use the PKI (Public Key Infrastructure) system to initialize the public key and private key, and store its own private key inside the device. The public key of the host device is the first public key, and the private key of the host device is the first private key.

[0131] In addition, the CXL memory device may also utilize a PKI (Public Key Infrastructure) system to initialize a public key and a private key, wherein the public key of the CXL memory device is the second public key, and the private key of the CXL memory device is the second private key.

[0132] In some embodiments of the present application, the system further includes: the host generates a re-encryption key based on the first key and the second public key; and the host sends the re-encryption key to the target computing quick link memory device.

[0133] The host selects one or more CXL memory devices as candidate application memory devices, obtains the second public key of the CXL memory device from the PKI system, uses the second public key of the CXL memory device and the first private key of the host device to generate one or more proxy re-encryption keys, and then sends the proxy re-encryption keys to the corresponding CXL memory device; the CXL memory device records the proxy re-encryption key and the corresponding host ID; then the CXL memory device obtains the host's public key from the PKI system, and internally records the host's first public key and the corresponding host ID.

[0134] In some embodiments of the present application, the system further comprises: the host, in response to the request to send information, encrypting the first key using the first public key to generate a key ciphertext; the host packaging the key ciphertext and the ciphertext information to generate first encrypted information; the host sending the first encrypted information to the target computing fast link memory device;

[0135] The target computing quick link memory device decrypts the first encrypted information based on the re-encryption key.

[0136] When a host sends data to a target CXL memory device, it first randomly generates an AES / DES key and encrypts it using the AES or DES algorithm. This key is then encrypted with the host's public key. The data ciphertext and key ciphertext are then packaged in a specified format and sent over the management network to the target CXL memory device. Because the data is encrypted using the host's public key, only devices with the host's private key or the proxy re-encryption key can decrypt it. Devices without the proxy re-encryption key and the host cannot decrypt the data, thus ensuring the security of the data sent by the host. Upon receiving the ciphertext, the target CXL memory device converts it using the proxy re-encryption key, decrypts the symmetric key ciphertext using its own private key, and then decrypts the data ciphertext using the symmetric key. Using proxy re-encryption technology when sending data from the host allows multiple devices with the proxy re-encryption key to receive messages simultaneously, thus avoiding point-to-point data transmission that consumes management bus bandwidth while ensuring data security.

[0137] In some embodiments of the present application, the system further includes: the host receiving second encrypted information sent by the target computing quick link memory device; and the host decrypting the second encrypted information based on the first key.

[0138] CXL memory devices send data to hosts in two ways: broadcast, in which data is received by all devices on the management network and is sent in plaintext; and data is sent to a specific host. In this case, a randomly generated AES / DES key is first encrypted using the AES or DES algorithm. This key is then encrypted with the target host's public key. The data ciphertext and key ciphertext are then packaged in a specified format and sent to the target host via the management network. Upon receiving the data, the target host decrypts the key ciphertext using its private key, and then uses the same key to decrypt the data ciphertext. CXL memory devices combine symmetric and asymmetric encryption algorithms when sending data to hosts, effectively ensuring data communication security.

[0139] In an embodiment of the present application, a host determines the selection popularity of any computing quick link memory device in response to a memory allocation request, and determines a target computing quick link memory device from any computing quick link memory device based on the selection popularity, generates a configuration instruction, and the configuration instruction corresponds to the target computing quick link memory device; sends the configuration instruction to a data center manager; the data center manager connects the target computing quick link memory device to the host based on the configuration instruction; the host obtains device parameter information of the computing quick link memory device in response to the connection of the target computing quick link memory device; the host determines an address space based on the device parameter information; the host sends a memory allocation request to the target computing quick link memory device; the target computing quick link memory device allocates a target memory slice based on the memory requirement of the memory allocation request, updates memory management information based on the host identity and the target memory slice, and generates a memory allocation success message; the host reads the memory allocation success message and enables the address space corresponding to the target memory slice; the host manages the target computing quick link memory device based on the address space; by setting a secure access mechanism based on the device information of the computing quick link memory device and the memory address of the host device, the target computing quick link memory device processes the host-based forwarding request, which can ensure the safe and orderly use of computing quick link memory between hosts.

[0140] The embodiment of the present application may also include a computing fast link memory management method, involving a multi-host and multi-computing fast link memory device architecture, any computing fast link memory device supports sharing by multiple hosts, the computing fast link memory device is managed by slicing according to a preset size, the memory slice of the computing fast link memory device is allocated to at most one host for use at the same time, the host has a host identity identifier, the computing fast link memory device stores memory management information, the memory management information records the correspondence between the memory slice and multiple hosts; the host is used to respond to a memory allocation request, determine the target computing fast link memory device based on the selection heat, generate a configuration instruction, the configuration instruction corresponds to the target computing fast link memory device; send the configuration instruction to the data center manager, the data center manager is used to connect the target computing fast link memory device to the host; in response to the connection of the target computing fast link memory device, obtain the device information of the computing fast link memory device; based on the device information, determine the address space, the address space is used to allocate to the computing fast link memory device for use; send a memory allocation request, the implementation of the above process can refer to the above embodiment, and will not be repeated here. The method is applied to computing fast link memory devices. The computing fast link memory management method can specifically include the following steps:

[0141] Step S1, calculating a fast link memory device to receive a memory allocation request;

[0142] In the embodiment of the present application, the computing fast link memory device is a target computing fast link memory device for processing a request, and can receive a memory allocation request sent by a host device and trigger an allocation task on its own physical memory.

[0143] Step S2, calculating the fast link memory device to perform memory allocation based on the memory allocation request, updating memory management information based on the host identity, and generating a memory allocation success message;

[0144] Memory allocation can be performed based on a memory allocation request, a memory disk corresponding to the memory allocation request can be determined, and the memory disk and host identity can be recorded in an array corresponding to the host's own memory management information to update the memory management information and generate a memory allocation success message. The memory allocation success message is then fed back to the host device.

[0145] Step S3, the calculation fast link memory device sends a memory allocation success message to the host device; the host is also used to read the memory allocation success message and enable the address space corresponding to the target memory slice.

[0146] A memory allocation success message can be sent to the host device so that the host device can use the allocated memory in the compute fast link memory device. The host device can read the memory allocation success message, determine that the memory allocation is successful, enable the address space, enable the address space corresponding to the target memory slice, and manage the target compute fast link memory device based on the address space to respond to various processing requirements.

[0147] In some embodiments of the present application, the system also includes: when the computing quick link memory device receives a host access request, checking the target access memory of the host access request; the computing quick link memory device determines whether the target access memory belongs to the host corresponding to the host access request based on memory management information; when the computing quick link memory device belongs to the host corresponding to the host access request, the computing quick link memory device responds to the host access request; when the computing quick link memory does not belong to the host corresponding to the host access request, the computing quick link memory device rejects the host access request.

[0148] The computing fast link memory device establishes a secure access mechanism with the host device to prevent errors during host access and improve the security of using the computing fast link memory device.

[0149] An embodiment of the present application may include a computing fast link memory management method, involving a multi-host and multi-computing fast link memory device architecture, wherein any computing fast link memory device supports sharing by multiple hosts, the computing fast link memory device is managed by slicing according to a preset size, a memory slice of the computing fast link memory device is allocated to at most one host at a time, a host corresponding to a host identity, the computing fast link memory device stores memory management information, and the memory management information records a correspondence between the memory slice and multiple hosts; the method includes:

[0150] The host determines, in response to the memory allocation request, a target computing fast link memory device according to the selection heat, and generates a configuration instruction, the configuration instruction corresponding to the target computing fast link memory device;

[0151] The host sends a configuration instruction to the data center manager, which is used to connect the target computing fast link memory device to the host;

[0152] The host obtains device information of the computing fast link memory device in response to access of the target computing fast link memory device;

[0153] Determine the address space based on the device information, and allocate the address space to the computing fast link memory device for use;

[0154] The host sends a memory allocation request to the compute fast link memory device;

[0155] The computing fast link memory device receives a memory allocation request;

[0156] The computing fast link memory device performs memory allocation based on the memory allocation request, updates memory management information based on the host identity, and generates a memory allocation success message;

[0157] The computing fast link memory device sends a memory allocation success message to the host device

[0158] The host reads the memory allocation success message and enables the address space corresponding to the target memory slice.

[0159] Optionally, the method further comprises:

[0160] Fast link memory devices based on address space management target calculation.

[0161] Optionally, the method further comprises:

[0162] In response to a memory access request, determining an access address of the memory access request;

[0163] Determining whether the access address belongs to the target memory slice of the target computing fast link memory device to determine the validity of the access address;

[0164] Access control is performed based on the validity of the access address.

[0165] Optionally, the step of performing access control based on the validity of the access address includes:

[0166] When the access address belongs to the target computing fast link memory device and does not correspond to the target memory slice, an access exception message is generated; the access exception message indicates that the target computing fast link memory device is not authorized to be accessed;

[0167] When the access address corresponds to the target memory slice, a memory access request is sent to the target computing fast link memory device to access the target computing fast link memory device.

[0168] Optionally, the method further comprises:

[0169] In response to the memory release request, determining an address space corresponding to the target memory slice;

[0170] The address space corresponding to the target memory slice is sent to the target computing fast link memory device, and the target computing fast link memory device is also used to release the target memory slice and generate release success information.

[0171] Optionally, the method further comprises:

[0172] According to the release success information, the memory management information is updated to determine that the allocation state corresponding to the target memory slice is an allocatable state.

[0173] Optionally, the method further comprises:

[0174] The address space corresponding to the target memory slice is set to a disabled state based on the release success information.

[0175] Optionally, in response to the memory allocation request, the step of determining a target computing fast link memory device according to the selection heat includes:

[0176] In response to a memory allocation request, receiving unallocated memory information and access latency information of a computing fast link memory device provided by a data center manager;

[0177] Filtering computing fast link memory devices provided by the data center manager according to the unallocated memory information and the access delay information to generate a first computing fast link memory device set, where the computing fast link memory devices in the first computing fast link memory device set meet the unallocated memory information and the access delay information;

[0178] A target computing fast link memory device is determined from the first computing fast link memory device set according to the selection heat.

[0179] Optionally, the step of screening computing fast link memory devices provided by the data center manager based on the unallocated memory information and the access latency information to generate a first computing fast link memory device set includes:

[0180] Filtering computing fast link memory devices provided by the data center manager according to the unallocated memory information to generate a second computing fast link memory device set, wherein computing fast link memory devices in the second computing fast link memory device set satisfy the unallocated memory information;

[0181] The second computing fast link memory device set is screened according to the access delay information to generate a first computing fast link memory device set.

[0182] Optionally, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat includes:

[0183] Calculating selection heat values ​​of computing fast link memory devices in the first computing fast link memory device set based on a selection heat calculation formula;

[0184] sorting the computing fast link memory devices in the first computing fast link memory device set based on descending order of selection heat values;

[0185] The first compute quick link memory device is determined as the target compute quick link memory device.

[0186] Optionally, select the heat calculation formula as:

[0187] M ava The unallocated memory size of the fast link memory device to be calculated, M req The requested memory size for the memory allocation request, D max Calculate the maximum access delay in the fast link memory device set for the first time; D cur is the access delay of the fast link memory device to be calculated; ε is the preset impact factor.

[0188] Optionally, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat further includes:

[0189] Memory utilization is determined based on unallocated memory, which is the ratio of allocated memory size to the total memory size of the Quick Link Memory device.

[0190] Optionally, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat further includes:

[0191] The preset impact factor is determined based on memory utilization. The preset impact factor formula is:

[0192] Optionally, the method comprises:

[0193] Send a configuration request to the Data Center Manager to obtain device information for the Compute Quick Link bus

[0194] Establish a directed graph based on device information;

[0195] The access delay information of the fast-link memory device is determined and calculated based on the directed graph.

[0196] Optionally, the host device has a first key, the target computing quick link memory device has a second public key, and the method further includes:

[0197] Generate a re-encryption key based on the first key and the second public key;

[0198] Send the re-encryption key to the target compute fast link memory device.

[0199] Optionally, the host device further has a first public key, and the method further includes:

[0200] In response to the information transmission request, encrypting the first secret key using the first public key to generate a secret key ciphertext;

[0201] Packing the key ciphertext and the ciphertext information to generate first encrypted information;

[0202] The first encrypted information is sent to a target computing fast link memory device, where the target computing fast link memory device is further configured to decrypt the first encrypted information based on a re-encryption key.

[0203] Optionally, the method further comprises:

[0204] receiving second encrypted information sent by the target computing quick link memory device;

[0205] The second encrypted information is decrypted based on the first key.

[0206] Optionally, the method further comprises:

[0207] Initialize a first public key and a first secret key.

[0208] Optionally, the method further comprises:

[0209] When receiving a host access request, the computing fast link memory device verifies a target access memory of the host access request;

[0210] The computing fast link memory device determines, based on the memory management information, whether the target access memory belongs to the host corresponding to the host access request;

[0211] The computing fast link memory device responds to the host access request when the target access memory belongs to the host corresponding to the host access request;

[0212] The computing fast link memory device denies a host access request when a target access memory does not belong to a host corresponding to the host access request.

[0213] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0214] 4 , an embodiment of the present application further provides an electronic device, including:

[0215] Processor 401 and storage medium 402, storage medium 402 stores a computer program executable by processor 401, when the electronic device is running, processor 401 executes the computer program to execute a multi-host and multi-computing fast link memory device system as any of the embodiments of the present application.

[0216] Multi-host and multi-computing fast-link memory device system, including:

[0217] Any computing fast link memory device in the system is connected to multiple hosts through a data center manager. Any computing fast link memory device is divided into multiple memory slices based on a preset size. A single memory slice of any computing fast link memory device is allocated to one host for use at the same time. The host is provided with a host identity. The computing fast link memory device stores memory management information. The memory management information records the correspondence between the memory slices and the multiple hosts.

[0218] The host determines, in response to the memory allocation request, a selection heat of any computing fast link memory device, determines a target computing fast link memory device from any computing fast link memory device based on the selection heat, generates a configuration instruction, the configuration instruction corresponds to the target computing fast link memory device, and sends the configuration instruction to the data center manager;

[0219] The data center manager connects the target computing fast link memory device to the host according to the configuration instructions;

[0220] The host obtains device parameter information of the computing fast link memory device in response to access of the target computing fast link memory device;

[0221] The host determines the address space based on the device parameter information;

[0222] The host sends a memory allocation request to the target compute fast link memory device;

[0223] The target computing fast link memory device allocates a target memory slice based on the memory requirement of the memory allocation request, updates memory management information based on the host identity and the target memory slice, and generates a memory allocation success message;

[0224] The host reads the memory allocation success message and enables the address space corresponding to the target memory slice;

[0225] The host computes fast links to memory devices based on the address space management target.

[0226] Optionally, the system further includes:

[0227] The host determines, in response to the memory access request, an access address of the memory access request;

[0228] The host determines whether the access address belongs to the target memory slice of the target computing fast link memory device, and determines the validity of the access address;

[0229] The host performs access control based on the validity of the access address.

[0230] Optionally, the step of performing access control based on the validity of the access address includes:

[0231] When the access address belongs to the target computing fast link memory device and does not correspond to the target memory slice, an access exception message is generated; the access exception message indicates that the target computing fast link memory device is not authorized to be accessed;

[0232] When the access address corresponds to the target memory slice, a memory access request is sent to the target computing fast link memory device to access the target computing fast link memory device.

[0233] Optionally, the system further includes:

[0234] The host determines, in response to the memory release request, an address space corresponding to the target memory slice;

[0235] The host sends the address space corresponding to the target memory slice to the target computing fast link memory device;

[0236] The target computing quickly links the memory device to release the target memory slice and generates a release success message.

[0237] Optionally, the system further includes:

[0238] The host updates the memory management information according to the release success information, and determines that the allocation state corresponding to the target memory slice is an allocatable state.

[0239] Optionally, the system further includes:

[0240] The host sets the address space corresponding to the target memory slice to a disabled state based on the release success information.

[0241] Optionally, in response to the memory allocation request, determining the selection heat of any computing fast link memory device, and determining a target computing fast link memory device from any computing fast link memory device according to the selection heat includes:

[0242] In response to a memory allocation request, receiving unallocated memory information and access latency information of a computing fast link memory device provided by a data center manager;

[0243] Filtering computing fast link memory devices provided by the data center manager according to the unallocated memory information and the access delay information to generate a first computing fast link memory device set, where the computing fast link memory devices in the first computing fast link memory device set meet the unallocated memory information and the access delay information;

[0244] A target computing fast link memory device is determined from the first computing fast link memory device set according to the selection heat.

[0245] Optionally, the step of screening computing fast link memory devices provided by the data center manager based on the unallocated memory information and the access latency information to generate a first computing fast link memory device set includes:

[0246] Filtering computing fast link memory devices provided by the data center manager according to the unallocated memory information to generate a second computing fast link memory device set, wherein computing fast link memory devices in the second computing fast link memory device set satisfy the unallocated memory information;

[0247] The second computing fast link memory device set is screened according to the access delay information to generate a first computing fast link memory device set.

[0248] Optionally, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat includes:

[0249] Calculating selection heat values ​​of computing fast link memory devices in the first computing fast link memory device set based on a selection heat calculation formula;

[0250] sorting the computing fast link memory devices in the first computing fast link memory device set based on descending order of selection heat values;

[0251] The first compute quick link memory device is determined as the target compute quick link memory device.

[0252] Optionally, select the heat calculation formula as:

[0253] M ava The unallocated memory size of the fast link memory device to be calculated, M req The requested memory size for the memory allocation request, D max Calculate the maximum access delay in the fast link memory device set for the first time; D cur is the access delay of the fast link memory device to be calculated; ε is the preset impact factor.

[0254] Optionally, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat further includes:

[0255] Memory utilization is determined based on unallocated memory, which is the ratio of allocated memory size to the total memory size of the Quick Link Memory device.

[0256] Optionally, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat further includes:

[0257] The preset impact factor is determined based on memory utilization. The preset impact factor formula is:

[0258] Optionally, the system includes:

[0259] The host sends a configuration request to the data center manager to obtain device information of the computing fast link bus;

[0260] The host creates a directed graph based on the device information;

[0261] The host determines and calculates access delay information of the fast link memory device based on the directed graph.

[0262] Optionally, the host device has a first key, the target computing quick link memory device has a second public key, and the system further includes:

[0263] The host generates a re-encryption key based on the first key and the second public key;

[0264] The host sends the re-encryption key to the target compute Quick Link memory device.

[0265] Optionally, the host device further has a first public key, and the system further includes:

[0266] In response to the information transmission request, the host encrypts the first secret key using the first public key to generate a key ciphertext;

[0267] The host packages the key ciphertext and the ciphertext information to generate first encrypted information;

[0268] The host sends the first encrypted information to the target computing quick link memory device;

[0269] The target computing quick link memory device decrypts the first encrypted information based on the re-encryption key.

[0270] Optionally, the system further includes:

[0271] The host receives the second encrypted information sent by the target computing quick link memory device;

[0272] The host decrypts the second encrypted information based on the first key.

[0273] Optionally, the system further includes:

[0274] The host initializes the first public key and the first secret key.

[0275] Optionally, the system further includes:

[0276] The computing fast link memory device receives a memory allocation request;

[0277] The computing fast link memory device performs memory allocation based on the memory allocation request, updates memory management information based on the host identity, and generates a memory allocation success message;

[0278] The Compute Quick Link memory device sends a memory allocation success message to the host.

[0279] Optionally, the system further includes:

[0280] When receiving a host access request, the computing fast link memory device verifies a target access memory of the host access request;

[0281] The computing fast link memory device determines, based on the memory management information, whether the target access memory belongs to the host corresponding to the host access request;

[0282] The computing fast link memory device responds to the host access request when the target access memory belongs to the host corresponding to the host access request;

[0283] The computing fast link memory device rejects the host access request when the target access memory does not belong to the host corresponding to the host access request.

[0284] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage. Alternatively, the memory may be at least one storage device located away from the processor.

[0285] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0286] 5 , an embodiment of the present application further provides a computer non-volatile readable storage medium 501 , on which a computer program is stored. When the computer program is executed by a processor, a multi-host and multi-computing fast link memory device system such as any one of the embodiments of the present application is executed.

[0287] A multi-host and multi-computing fast-link memory device system includes: any computing fast-link memory device in the system is connected to multiple hosts via a data center manager, any computing fast-link memory device is divided into multiple memory slices based on preset sizes, a single memory slice of any computing fast-link memory device is allocated to one host for use at the same time, the host is provided with a host identity, and the computing fast-link memory device stores memory management information, the memory management information recording the correspondence between the memory slices and the multiple hosts;

[0288] The host determines, in response to the memory allocation request, a selection heat of any computing fast link memory device, determines a target computing fast link memory device from any computing fast link memory device based on the selection heat, generates a configuration instruction, the configuration instruction corresponds to the target computing fast link memory device, and sends the configuration instruction to the data center manager;

[0289] The data center manager connects the target computing fast link memory device to the host according to the configuration instructions;

[0290] The host obtains device parameter information of the computing fast link memory device in response to access of the target computing fast link memory device;

[0291] The host determines the address space based on the device parameter information;

[0292] The host sends a memory allocation request to the target compute fast link memory device;

[0293] The target computing fast link memory device allocates a target memory slice based on the memory requirement of the memory allocation request, updates memory management information based on the host identity and the target memory slice, and generates a memory allocation success message;

[0294] The host reads the memory allocation success message and enables the address space corresponding to the target memory slice;

[0295] The host computes fast links to memory devices based on the address space management target.

[0296] Optionally, the system further includes:

[0297] The host determines, in response to the memory access request, an access address of the memory access request;

[0298] The host determines whether the access address belongs to the target memory slice of the target computing fast link memory device, and determines the validity of the access address;

[0299] The host performs access control based on the validity of the access address.

[0300] Optionally, the step of performing access control based on the validity of the access address includes:

[0301] When the access address belongs to the target computing fast link memory device and does not correspond to the target memory slice, an access exception message is generated; the access exception message indicates that the target computing fast link memory device is not authorized to be accessed;

[0302] When the access address corresponds to the target memory slice, a memory access request is sent to the target computing fast link memory device to access the target computing fast link memory device.

[0303] Optionally, the system further includes:

[0304] The host determines, in response to the memory release request, an address space corresponding to the target memory slice;

[0305] The host sends the address space corresponding to the target memory slice to the target computing fast link memory device;

[0306] The target computing quickly links the memory device to release the target memory slice and generates a release success message.

[0307] Optionally, the system further includes:

[0308] The host updates the memory management information according to the release success information, and determines that the allocation state corresponding to the target memory slice is an allocatable state.

[0309] Optionally, the system further includes:

[0310] The host sets the address space corresponding to the target memory slice to a disabled state based on the release success information.

[0311] Optionally, in response to the memory allocation request, determining the selection heat of any computing fast link memory device, and determining a target computing fast link memory device from any computing fast link memory device according to the selection heat includes:

[0312] In response to a memory allocation request, receiving unallocated memory information and access latency information of a computing fast link memory device provided by a data center manager;

[0313] Filtering computing fast link memory devices provided by the data center manager according to the unallocated memory information and the access delay information to generate a first computing fast link memory device set, where the computing fast link memory devices in the first computing fast link memory device set meet the unallocated memory information and the access delay information;

[0314] A target computing fast link memory device is determined from the first computing fast link memory device set according to the selection heat.

[0315] Optionally, the step of screening computing fast link memory devices provided by the data center manager based on the unallocated memory information and the access latency information to generate a first computing fast link memory device set includes:

[0316] Filtering computing fast link memory devices provided by the data center manager according to the unallocated memory information to generate a second computing fast link memory device set, wherein computing fast link memory devices in the second computing fast link memory device set satisfy the unallocated memory information;

[0317] The second computing fast link memory device set is screened according to the access delay information to generate a first computing fast link memory device set.

[0318] Optionally, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat includes:

[0319] Calculating selection heat values ​​of computing fast link memory devices in the first computing fast link memory device set based on a selection heat calculation formula;

[0320] sorting the computing fast link memory devices in the first computing fast link memory device set based on descending order of selection heat values;

[0321] The first compute quick link memory device is determined as the target compute quick link memory device.

[0322] Optionally, select the heat calculation formula as:

[0323] M ava The unallocated memory size of the fast link memory device to be calculated, M req The requested memory size for the memory allocation request, D max Calculate the maximum access delay in the fast link memory device set for the first time; D cur is the access delay of the fast link memory device to be calculated; ε is the preset impact factor.

[0324] Optionally, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat further includes:

[0325] Memory utilization is determined based on unallocated memory, which is the ratio of allocated memory size to the total memory size of the Quick Link Memory device.

[0326] Optionally, the step of determining a target computing fast link memory device from the first computing fast link memory device set according to the selection heat further includes:

[0327] The preset impact factor is determined based on memory utilization. The preset impact factor formula is:

[0328] Optionally, the system includes:

[0329] The host sends a configuration request to the data center manager to obtain device information of the computing fast link bus;

[0330] The host creates a directed graph based on the device information;

[0331] The host determines and calculates access delay information of the fast link memory device based on the directed graph.

[0332] Optionally, the host device has a first key, the target computing quick link memory device has a second public key, and the system further includes:

[0333] The host generates a re-encryption key based on the first key and the second public key;

[0334] The host sends the re-encryption key to the target compute Quick Link memory device.

[0335] Optionally, the host device further has a first public key, and the system further includes:

[0336] In response to the information transmission request, the host encrypts the first secret key using the first public key to generate a key ciphertext;

[0337] The host packages the key ciphertext and the ciphertext information to generate first encrypted information;

[0338] The host sends the first encrypted information to the target computing quick link memory device;

[0339] The target computing quick link memory device decrypts the first encrypted information based on the re-encryption key.

[0340] Optionally, the system further includes:

[0341] The host receives the second encrypted information sent by the target computing quick link memory device;

[0342] The host decrypts the second encrypted information based on the first key.

[0343] Optionally, the system further includes:

[0344] The host initializes the first public key and the first secret key.

[0345] Optionally, the system further includes:

[0346] The computing fast link memory device receives a memory allocation request;

[0347] The computing fast link memory device performs memory allocation based on the memory allocation request, updates memory management information based on the host identity, and generates a memory allocation success message;

[0348] The Compute Quick Link memory device sends a memory allocation success message to the host.

[0349] Optionally, the system further includes:

[0350] When receiving a host access request, the computing fast link memory device verifies a target access memory of the host access request;

[0351] The computing fast link memory device determines, based on the memory management information, whether the target access memory belongs to the host corresponding to the host access request;

[0352] The computing fast link memory device responds to the host access request when the target access memory belongs to the host corresponding to the host access request;

[0353] The computing fast link memory device rejects the host access request when the target access memory does not belong to the host corresponding to the host access request.

[0354] Some embodiments in this specification are described in a progressive manner. Some embodiments focus on the differences from other embodiments, and the same or similar parts between some embodiments can be referred to each other.

[0355] Those skilled in the art will appreciate that some embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0356] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, terminal device (system), and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flow chart and / or block diagram and the combination of the process and / or box in the flow chart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device produce a device for realizing the function specified in one process or multiple processes and / or one box or multiple boxes of the flow chart.

[0357] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0358] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0359] Although some preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0360] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0361] The above is a detailed introduction to a multi-host and multi-computing fast-link memory device system, an electronic device and a computer storage medium provided by the present application. Some embodiments are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A multi-host and multi-compute fast link memory device system, characterized in that, Any computing quick link memory device in the system is connected to multiple hosts through a data center manager; In response to a memory allocation request, the host determines the selection popularity of any computing quick link memory device, and determines a target computing quick link memory device from any computing quick link memory device according to the selection popularity, and generates a configuration instruction, where the configuration instruction corresponds to the target computing quick link memory device; Send the configuration instruction to the data center manager; The data center manager connects the target computing quick link memory device to the host according to the configuration instruction; In response to the access of the target computing quick link memory device, the host obtains the device parameter information of the target computing quick link memory device; The host determines an address space according to the device parameter information; The host manages the target computing quick link memory device based on the address space.

2. The system according to claim 1, wherein Any computing quick link memory device forms a plurality of memory slices based on a preset size, and a single memory slice of any computing quick link memory device is allocated to one host for use at the same time. The host is provided with a host identity identifier, and the computing quick link memory device stores memory management information, and the memory management information records the corresponding relationship between the memory slice and the plurality of hosts. The system further includes: The host sends the memory allocation request to the target computing quick link memory device; The target computing quick link memory device allocates a target memory slice based on the memory requirement of the memory allocation request, updates the memory management information based on the host identity identifier and the target memory slice, and generates a memory allocation success message; The host reads the memory allocation success message and enables the address space corresponding to the target memory slice.

3. The system according to claim 1, characterized in that, The system further includes: In response to a memory access request, the host determines the access address of the memory access request; The host determines the validity of the access address by determining whether the access address belongs to the target memory slice of the target computing quick link memory device; The host performs access control based on the validity of the access address.

4. The system according to claim 3, characterized in that, The step of performing access control based on the validity of the access address includes: When the access address belongs to the target computing quick link memory device and does not correspond to the target memory slice, generate an access exception information; the access exception information indicates that there is no permission to access the target computing quick link memory device; When the access address corresponds to the target memory slice, send the memory access request to the target computing quick link memory device to access the target computing quick link memory device.

5. The system according to claim 2, wherein The system further includes: In response to a memory release request, the host determines the address space corresponding to the target memory slice; The host sends the address space corresponding to the target memory slice to the target computing quick link memory device; The target computing quick link memory device releases the target memory slice and generates a release success message.

6. The system according to claim 5, wherein The system further includes: Based on the successful release information, the host updates the memory management information and determines that the allocation status of the target memory slice is the allocable status.

7. The system according to claim 6, wherein The system further includes: Based on the successful release information, the host sets the address space corresponding to the target memory slice to the disabled state.

8. The system according to claim 1, characterized in that, The step of determining the selection popularity of any Compute Express Link memory device in response to a memory allocation request and determining a target Compute Express Link memory device from any Compute Express Link memory device according to the selection popularity includes: In response to a memory allocation request, receiving the unallocated memory information and access latency information of the Compute Express Link memory device provided by the data center manager; According to the unallocated memory information and the access latency information, filtering the Compute Express Link memory devices provided by the data center manager to generate a first set of Compute Express Link memory devices, and the Compute Express Link memory devices in the first set of Compute Express Link memory devices meet the unallocated memory information and the access latency information; Determining the target Compute Express Link memory device from the first set of Compute Express Link memory devices according to the selection popularity.

9. The system according to claim 8, wherein, The step of filtering the Compute Express Link memory devices provided by the data center manager according to the unallocated memory information and the access latency information to generate a first set of Compute Express Link memory devices includes: Filtering the Compute Express Link memory devices provided by the data center manager according to the unallocated memory information to generate a second set of Compute Express Link memory devices, and the Compute Express Link memory devices in the second set of Compute Express Link memory devices meet the unallocated memory information; Filtering the second set of Compute Express Link memory devices according to the access latency information to generate the first set of Compute Express Link memory devices.

10. The system according to claim 8, wherein The step of determining the target Compute Express Link memory device from the first set of Compute Express Link memory devices according to the selection popularity includes: Calculating the selection popularity values of the Compute Express Link memory devices in the first set of Compute Express Link memory devices based on a selection popularity calculation formula; Sorting the Compute Express Link memory devices in the first set of Compute Express Link memory devices in descending order based on the selection popularity values; Determining the Compute Express Link memory device ranked first as the target Compute Express Link memory device.

11. The system according to claim 10, wherein The selection popularity calculation formula is as follows: M ava M is the memory size not allocated for the fast link memory device to be calculated req D is the requested memory size of the memory allocation request max D is the maximum access latency in the first set of calculated fast link memory devices cur ε is the access latency of the fast link memory device to be calculated; ε is a preset influence factor 12. The system according to claim 11, wherein, The step of determining the target Compute Express Link memory device from the first set of Compute Express Link memory devices according to the selection popularity further includes: Determining the memory utilization rate according to the unallocated memory, where the memory utilization rate is the ratio of the size of the allocated memory to the total memory size of the Compute Express Link memory device.

13. The system according to claim 11, wherein The step of determining the target Compute Express Link memory device from the first set of Compute Express Link memory devices according to the selection popularity further includes: Determine the preset influence factor according to the memory utilization rate, and the formula of the preset influence factor is:

14. The system according to claim 1, wherein The system includes: The host sends a configuration request to the data center manager to obtain the device information of the Compute Express Link bus; The host establishes a directed graph based on the device information; The host determines the access latency information of the Compute Express Link memory device according to the directed graph.

15. The system according to claim 1, wherein The host device has a first secret key, and the target Compute Express Link memory device has a second public key. The system further includes: The host generates a re-encryption key according to the first secret key and the second public key. The host sends the re-encryption key to the target Compute Express Link memory device.

16. The system according to claim 15, wherein The host device further has a first public key. The system further includes: In response to the information sending request, the host encrypts the first secret key with the first public key to generate a key ciphertext. The host packs the key ciphertext and the ciphertext information to generate a first encrypted information. The host sends the first encrypted information to the target Compute Express Link memory device. The target Compute Express Link memory device decrypts the first encrypted information based on the re-encryption key.

17. The system according to claim 16, wherein, The system further includes: The host receives the second encrypted information sent by the target Compute Express Link memory device. The host decrypts the second encrypted information based on the first secret key.

18. The system according to claim 16, wherein The system further includes: The host initializes the first public key and the first secret key.

19. The system according to claim 2, wherein The system further includes: The Compute Express Link memory device receives the memory allocation request. The Compute Express Link memory device performs memory allocation based on the memory allocation request, updates the memory management information based on the host identity identifier, and generates a memory allocation success message. The Compute Express Link memory device sends the memory allocation success message to the host.

20. The system according to claim 2, wherein The system further includes: When receiving a host access request, the Compute Express Link memory device verifies the target access memory of the host access request. The Compute Express Link memory device determines whether the target access memory belongs to the host corresponding to the host access request according to the memory management information. When the target access memory belongs to the host corresponding to the host access request, the Compute Express Link memory device responds to the host access request. When the target access memory does not belong to the host corresponding to the host access request, the Compute Express Link memory device rejects the host access request.

21. An electronic device, characterized in that, Comprising a processor, a memory, and a computer program stored on the memory and capable of running on the processor, where when the computer program is executed by the processor, it implements the multi-host and multi-Compute Express Link memory device system according to any one of claims 1 to 20.

22. A computer non-volatile readable storage medium, characterized in that, A computer program is stored on the computer non-volatile readable storage medium, and when the computer program is executed by a processor, it implements the multi-host and multi-Compute Express Link memory device system according to any one of claims 1 to 20.

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