Data storage system and method, and server

Abstract

The present application relates to the technical field of computers. Disclosed are a data storage system and method, and a server. The system comprises: a local CPU and a local FPGA accelerator card connected to the local CPU by means of a PCIe interface, wherein the local CPU is connected to several local hard disks by means of the PCIe interface; the local FPGA accelerator card is connected to several local expanded hard disks; and the local FPGA accelerator card is configured to establish network communication between the local CPU and a remote CPU, and receive and process local data sent by the local CPU and remote data sent by the remote CPU, such that the local CPU and the remote CPU share expanded hard disks. In the system provided in the present solution, the local FPGA accelerator card can be connected to the local expanded hard disks, so as to realize the expansion of the local hard disks, and the local FPGA accelerator card can also replace a network interface card, so as to establish the network communication between the local CPU and the remote CPU, thereby improving the performance of a server.

Description

Data storage system, method and server

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 28, 2023, with application number 2023118395014 and application name “A Data Storage System, Method and Server”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present application relate to the field of computer technology, and more specifically, to a data storage system, method, and server. Background Art

[0004] At present, servers have put forward higher requirements on the capacity and response speed of data storage systems in scenarios facing large-scale high-speed computing and data exchange. Large-capacity, fast-response storage structures play a vital role in reducing the overall energy consumption and cost of server systems. Therefore, the use of local hard disks is crucial.

[0005] In related technologies, a PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) switch is usually added to the server to carry more local hard drives in the server. At the same time, network cards and switches are used to establish network connections between servers to achieve storage space sharing between servers.

[0006] However, the number of PCIe switches available is limited by the number of PCIe ports on a server, and network cards require CPU (Central Processing Unit) resources, hindering server performance. Therefore, a data storage system that can both expand local hard drives and interconnect servers is urgently needed to improve server performance.

[0007] Summary of the Invention

[0008] The present application provides a data storage system, method and server to solve the defects of related technologies such as the inability to guarantee server performance.

[0009] The present application provides a data storage system, comprising: a local CPU and a local FPGA (Field Programmable Gate Array) accelerator card connected to the local CPU via a PCIe interface;

[0010] The local CPU is connected to several local hard disks through the PCIe interface;

[0011] The local FPGA accelerator card is connected to several local expansion hard drives;

[0012] The local FPGA accelerator card is configured to establish network communication between the local CPU and the remote CPU, and receive and process local data sent by the local CPU and remote data sent by the remote CPU, so that the local CPU and the remote CPU share the extended hard disk.

[0013] In an optional embodiment, the local FPGA accelerator card is connected to the remote FPGA accelerator card via an optical switch to establish network communication between the local CPU and the remote CPU;

[0014] The remote FPGA and the remote CPU are connected via a PCIe interface.

[0015] In an optional embodiment, the local FPGA accelerator card includes: an optical fiber module;

[0016] The optical switch is connected to the transceiver pins of the local FPGA accelerator card through an optical fiber module;

[0017] The local CPU is connected to the transceiver pins of the local FPGA accelerator card through the PCIe interface;

[0018] The optical switch is configured to forward remote data sent by the remote CPU.

[0019] In an optional embodiment, the local FPGA accelerator card is configured to:

[0020] According to the communication protocol type of the optical fiber module, the data format of the received remote data is converted so that the data format of the remote data is the same as that of the local data.

[0021] In an optional embodiment, the local FPGA accelerator card includes: a primary logic component and a secondary logic component;

[0022] The primary logic component is configured to perform a first logical decomposition on the local data sent by the local CPU and / or the remote data forwarded by the optical switch to obtain primary logic data;

[0023] The secondary logic component is configured to perform secondary logic decomposition on the primary logic data to obtain a corresponding number of sub-data to be stored.

[0024] In an optional embodiment, the local FPGA accelerator card includes: a hard disk connector;

[0025] The hard disk connector is configured to store the sub-data to be stored in the corresponding local expansion hard disk;

[0026] The sub-data to be stored is obtained by logically decomposing local data and remote data, and the number of data channels of the sub-data to be stored is the same as that of the local extended hard disk.

[0027] In an optional implementation, the data decomposition logic of the primary logic component and the secondary logic component is determined according to the application requirements of the local CPU and the remote CPU for the local extended hard disk.

[0028] In an optional implementation, the local FPGA accelerator card communicates with the host BMC (Baseboard Management Controller) based on a complex programmable logic device to obtain the application requirements of the local CPU for the local expansion hard disk.

[0029] In an optional embodiment, the secondary logic component includes a first logic component and a second logic component, and the local FPGA accelerator card is connected to 8 local expansion hard disks via a PCIe interface;

[0030] When the local CPU's application requirements for local expansion hard disks require all local expansion hard disks, the local FPGA accelerator card transceiver transmits local data to the first-level logic component;

[0031] The first-level logic component is configured to perform a first logic decomposition on the local data sent by the local CPU to obtain a first path of local data and a second path of local data; the first-level logic data includes the first path of local data and the second path of local data;

[0032] Inputting a first path of local data into a first logic component, the first logic component being configured to decompose the first path of local data into four paths of sub-data to be stored;

[0033] The local second path of data is input to the second logic component, and the second logic component is configured to decompose the local second path of data into four paths of sub-data to be stored.

[0034] In an optional embodiment, the secondary logic component includes a first logic component and a second logic component, and the local FPGA accelerator card is connected to 8 local expansion hard disks via a PCIe interface;

[0035] When the local CPU has no application demand for the local expansion hard disk, it indicates that the remote CPU's application demand for the local expansion hard disk is that all local expansion hard disks are required;

[0036] The local FPGA accelerator card transceiver transmits the remote data to the first-level logic component, which is configured to decompose the remote data into a first-channel remote data and a second-channel remote data; the first-level logic data includes the first-channel remote data and the second-channel remote data;

[0037] Inputting the remote first data path into the first logic component, the first logic component is configured to decompose the remote first data path into 4 sub-data paths to be stored;

[0038] The remote second-path data is input to the second logic component, and the second logic component is configured to decompose the remote second-path data into 4 paths of sub-data to be stored.

[0039] In an optional embodiment, the secondary logic component includes a first logic component and a second logic component, and the local FPGA accelerator card is connected to 8 local expansion hard disks via a PCIe interface;

[0040] When the local CPU's application demand for the local expansion hard disk is one local expansion hard disk, it indicates that the remote CPU's application demand for the local expansion hard disk is seven local expansion hard disks.

[0041] The local FPGA accelerator card transceiver directly transmits the local data to the first logic component, and the first logic component is configured to decompose the local data into one channel of sub-data to be stored;

[0042] The local FPGA acceleration card transceiver splits and transmits the remote data to the first logic component and the second logic component. The first logic component is configured to decompose the obtained remote data into three sub-data to be stored, and the second logic component is configured to decompose the obtained remote data into four sub-data to be stored.

[0043] In an optional embodiment, the secondary logic component includes a first logic component and a second logic component, and the local FPGA accelerator card is connected to 8 local expansion hard disks via a PCIe interface;

[0044] When the local CPU's application demand for local expansion hard disks is 7 local expansion hard disks, it indicates that the remote CPU's application demand for local expansion hard disks is 1 local expansion hard disk.

[0045] The local FPGA accelerator card transceiver directly transmits the remote data to the second logic component, and the second logic component is configured to decompose the remote data into one channel of sub-data to be stored;

[0046] The local FPGA acceleration card transceiver splits and transmits the local data to the first logic component and the second logic component. The first logic component is configured to decompose the obtained local data into 4 sub-data to be stored, and the second logic component is configured to decompose the obtained local data into 3 sub-data to be stored.

[0047] In an optional embodiment, when the application requirement of the local CPU for the local expansion hard disk is that four local expansion hard disks are required, it is represented that the application requirement of the remote CPU for the local expansion hard disk is that four local expansion hard disks are required;

[0048] The local FPGA accelerator card transceiver transmits local data and remote data to the first-level logic components;

[0049] The first-level logic component is configured to decompose local data into local first-level logic data and decompose remote data into remote first-level logic data;

[0050] The first logic component is configured to decompose the local primary logic data into four paths of sub-data to be stored;

[0051] The second logic component is configured to decompose the remote primary logic data into 4 paths of sub-data to be stored.

[0052] In an optional embodiment, when the application requirement of the local CPU for the local expansion hard disk is that 5 local expansion hard disks are required, it is represented that the application requirement of the remote CPU for the local expansion hard disk is that 3 local expansion hard disks are required;

[0053] The local FPGA accelerator card transceiver directly transmits the remote data to the second logic component, and the second logic component is configured to decompose the remote data into three sub-data to be stored;

[0054] The local FPGA acceleration card transceiver splits and transmits the local data to the first logic component and the second logic component. The first logic component is configured to decompose the obtained local data into 4 sub-data to be stored, and the second logic component is configured to decompose the obtained local data into 1 sub-data to be stored.

[0055] In an optional embodiment, the secondary logic component includes a first logic component and a second logic component, and the local FPGA accelerator card is connected to 8 local expansion hard disks via a PCIe interface;

[0056] When the local CPU's application requirement for local expansion hard disks is 6 local expansion hard disks, it indicates that the remote CPU's application requirement for local expansion hard disks is 2 local expansion hard disks.

[0057] The local FPGA acceleration card transceiver splits and transmits the local data to the first logic component and the second logic component. The first logic component is configured to decompose the local data into 4 sub-data to be stored; the second logic component is configured to decompose the obtained local data into 2 sub-data to be stored.

[0058] The local FPGA accelerator card transceiver directly transmits the remote data to the second logic component, and the second logic component is configured to decompose the obtained remote data into two paths of sub-data to be stored.

[0059] In an optional embodiment, the secondary logic component includes a first logic component and a second logic component, and the local FPGA accelerator card is connected to 8 local expansion hard disks via a PCIe interface;

[0060] When the local CPU's application requirement for local expansion hard disks is 2 local expansion hard disks, it indicates that the remote CPU's application requirement for local expansion hard disks is 6 local expansion hard disks.

[0061] The local FPGA acceleration card transceiver splits and transmits the remote data to the first logic component and the second logic component. The first logic component is configured to decompose the remote data into two paths of sub-data to be stored; the second logic component is configured to decompose the obtained remote data into four paths of sub-data to be stored.

[0062] The local FPGA accelerator card transceiver directly transmits the local data to the first logic component, and the first logic component is configured to decompose the obtained local data into two paths of sub-data to be stored. In an optional embodiment, the local FPGA accelerator card includes:

[0063] Complex programmable logic devices are configured to control and manage power and monitor the entire board status of the local FPGA accelerator card;

[0064] Sends the entire board status information to the host BMC.

[0065] In an optional embodiment, the local FPGA acceleration card includes: a plurality of memory slots configured to connect to local expansion memory to expand the memory resources of the server.

[0066] The present application provides a data storage method, comprising:

[0067] Get the data to be stored;

[0068] Save the data to be stored to the local hard disk, local extended hard disk or remote extended hard disk;

[0069] Among them, the local hard disk is connected to the local CPU through the PCIe interface, the local extended hard disk is connected to the local FPGA acceleration card, the local FPGA acceleration card is connected to the local CPU through the PCIe interface, and the remote FPGA acceleration card connected to the remote CPU is provided with a remote extended hard disk. The local CPU and the remote CPU establish network communication through the local FPGA acceleration card and the remote FPGA acceleration card, so that the local CPU and the remote CPU share the extended hard disk.

[0070] The present application provides a server, including: a data storage system designed as described in the above embodiment.

[0071] The technical solution of this application has the following advantages:

[0072] The present application provides a data storage system, method and server, which includes: a local CPU and a local FPGA accelerator card connected to the local CPU via a PCIe interface; the local CPU is connected to several local hard disks via a PCIe interface; the local FPGA accelerator card is connected to several local extended hard disks; the local FPGA accelerator card is configured to establish network communication between the local CPU and the remote CPU, and receive and process local data sent by the local CPU and remote data sent by the remote CPU, so that the local CPU and the remote CPU share the extended hard disk. In the system provided by the above scheme, the local FPGA accelerator card can not only connect to the local extended hard disk to achieve the expansion of the local hard disk, but also replace the network card to establish network communication between the local CPU and the remote CPU, thereby improving the performance of the server. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0074] FIG1 is a schematic structural diagram of an exemplary data storage system provided in an embodiment of the present application;

[0075] FIG2 is a schematic diagram of the structure of another exemplary data storage system provided in an embodiment of the present application;

[0076] FIG3 is a schematic diagram of the structure of a local FPGA acceleration card provided in an embodiment of the present application;

[0077] FIG4 is a schematic diagram of the structure of another local FPGA acceleration card provided in an embodiment of the present application;

[0078] FIG5 is a schematic diagram of a flow chart of a data storage method provided in an embodiment of the present application;

[0079] FIG6 is a schematic diagram of the structure of the server provided in an embodiment of the present application.

[0080] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0081] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0082] In addition, the terms "first," "second," etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. In the description of the following embodiments, "plurality" means more than two, unless otherwise explicitly defined.

[0083] In the related art, it is common to add a PCIe switch to the server to carry more local hard disks in the server, and at the same time, a network connection between the servers is established using a network card and a switch to realize storage space sharing between the servers. However, since the addition of PCIe switches is limited by the number of PCIe interfaces of the server, and the network card needs to occupy the CPU resources of the server, it is not conducive to ensuring the performance of the server. In response to the above problems, an embodiment of the present application provides a data storage system, method and server, which includes: a local CPU and a local FPGA acceleration card connected to the local CPU through a PCIe interface; the local CPU is connected to several local hard disks through a PCIe interface; the local FPGA acceleration card is connected to several local extended hard disks; the local FPGA acceleration card is configured to establish network communication between the local CPU and the remote CPU, and receive and process local data sent by the local CPU and remote data sent by the remote CPU, so that the local CPU and the remote CPU share the extended hard disk. In the system provided by the above scheme, the local FPGA acceleration card can not only connect to the local extended hard disk to realize the expansion of the local hard disk, but can also replace the network card to establish network communication between the local CPU and the remote CPU, thereby improving the performance of the server.

[0084] The following embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. The following describes the embodiments of the present application in conjunction with the accompanying drawings.

[0085] The present invention provides a data storage system configured to expand a local hard disk of a server and interconnect servers. The data storage system includes: a local CPU and a local FPGA accelerator card connected to the local CPU via a PCIe interface;

[0086] Among them, the local CPU is connected to several local hard disks through the PCIe interface; the local FPGA accelerator card is connected to several local extended hard disks; the local FPGA accelerator card is configured to establish network communication between the local CPU and the remote CPU, and receive and process local data sent by the local CPU and remote data sent by the remote CPU, so that the local CPU and the remote CPU share the extended hard disk.

[0087] It should be noted that, as shown in FIG1 , which is a structural diagram of an exemplary data storage system provided in an embodiment of the present application, the structures of the local CPU and the remote CPU are basically the same. Taking the local CPU as an example, it includes 4 PCIe x16 interfaces, of which 3 PCIe x16 interfaces are connected to 4 local hard disks (NVMe SSD (Non-Volatile Memory Express Solid State Drive, non-volatile memory host controller interface specification solid state drive)), 1 PCIe x16 interface is connected to the local FPGA accelerator card, and the local CPU also includes several memory slots (such as DDR (Double Data Rate Synchronous Dynamic Random Access Memory, double rate synchronous dynamic random access memory) -CHA / B, DDR-CHC / D, DDR-CHE / F and DDR-CHG / H), each memory slot can be plugged with 4 memory sticks (DIMM (Dual-Inline-Memory-Modules, dual inline memory modules)), the local CPU also includes several PCIe x8 interfaces, which are configured to connect to Raid cards and other cards, and the local CPU also includes DMI (Direct Media Interface, direct media interface) and UPI (Universal Peripherals Interface, universal external interface) interface.

[0088] Optionally, the local FPGA acceleration card provided in the embodiment of the present application can be configured with a network card function, which can act as a network card to establish a network connection between the local CPU and the remote CPU, and receive and process local data sent by the local CPU and remote data sent by the remote CPU to realize the sharing of the local extended hard disk and the remote extended hard disk.

[0089] Optionally, in one embodiment, the local FPGA acceleration card is connected to the remote FPGA acceleration card via an optical switch to establish network communication between the local CPU and the remote CPU.

[0090] The remote FPGA and the remote CPU are connected via a PCIe interface.

[0091] For example, as shown in FIG2 , which is a schematic diagram of the structure of another exemplary data storage system provided in an embodiment of the present application, the local CPU is connected to several local hard disks and a local FPGA accelerator card via a PCIe interface, and the local FPGA accelerator card is connected to several local extended hard disks. The remote CPU is connected to several remote hard disks and a remote FPGA accelerator card via a PCIe interface, and the remote FPGA accelerator card is connected to several remote extended hard disks. The local FPGA accelerator card and the remote FPGA accelerator card are connected via an optical switch to achieve network communication, thereby achieving sharing of local extended hard disks and remote extended hard disks.

[0092] Optionally, in one embodiment, the local FPGA acceleration card includes: an optical fiber module.

[0093] The optical switch is connected to the transceiver pins of the local FPGA accelerator card via an optical fiber module, and the local CPU is connected to the transceiver pins of the local FPGA accelerator card via a PCIe interface. The optical switch is configured to forward remote data sent by the remote CPU.

[0094] Optionally, the remote data sent by the remote CPU is forwarded through the optical switch, and the optical switch sends the remote data to the transceiver pin of the local FPGA acceleration card through the optical fiber module (QSFP (Quad Small Form-factor Pluggable, four-channel SFP interface) 28) of the local FPGA acceleration card. The local data sent by the local CPU enters the transceiver pin of the local FPGA acceleration card through the Goldfinger PCIe x16 connected to the PCIe x16 interface of the local CPU, so as to enter the local FPGA acceleration card.

[0095] Optionally, in one embodiment, to ensure that the logic components in the local FPGA acceleration card can adapt to remote data of different protocol types, the local FPGA acceleration card is configured to convert the data format of the received remote data according to the communication protocol type of the optical fiber module so that the data format of the remote data is the same as that of the local data.

[0096] Optionally, the format of remote data received by the optical fiber module QSFP28 can be in various forms, mainly depending on the protocol used for optical port communication. Common protocols include Ethernet, Fibre Channel, InfiniBand (a high-performance computer network communication standard), and Synchronous Optical Fiber Protocol, etc., and different protocol data are parsed. Among them, the main difference between the local data received through the PCIe interface and the remote data received by the QSFP28 is the different packet headers. For example, the packet header includes information such as the protocol type and address. Therefore, the remote data received by the QSFP28 can be converted into PCIe data in the local FPGA accelerator card to make the remote data and the local data have the same data format.

[0097] On the basis of the above embodiments, in order to make the FPGA accelerator better suitable for various application scenarios and improve the performance of the server, as shown in Figure 3, a structural diagram of a local FPGA acceleration card provided in an embodiment of the present application is provided. As an implementable method, in one embodiment, the local FPGA acceleration card includes: a primary logic component and a secondary logic component.

[0098] Among them, the first-level logic component is configured to perform a first logical decomposition on the local data sent by the local CPU and / or the remote data forwarded by the optical switch to obtain first-level logical data; the second-level logic component is configured to perform a second-level logical decomposition on the first-level logical data to obtain a corresponding number of sub-data to be stored.

[0099] It should be noted that since the local data and remote data directly received by the local FPGA accelerator card are all in x16 structure, and the local expansion hard disks it connects to are all in x4 structure, in order to adapt to the local expansion hard disk, the local FPGA accelerator card needs to logically decompose the local data and remote data based on the first-level logic components and the second-level logic components to convert them into several x4-structured sub-data to be stored.

[0100] Optionally, after receiving local data (PCIe x16_0) and remote data (QSFP28 x16_1), the local FPGA accelerator card transceiver sends them to the first-level logic component (Switch_0) to perform a first logical decomposition based on the first-level logic component (Switch_0) to obtain two paths of first-level logic data (such as x16_2 and x16_3), and then performs a second-level logical decomposition on the two paths of first-level logic data based on the second-level logic component to obtain sub-data to be stored (x4) corresponding to the number of local extended hard disks.

[0101] Optionally, in one embodiment, the local FPGA acceleration card includes: a hard disk connector (MCIO CONN (Modular Connector Input Output Connector, a multi-channel input / output connector) x16).

[0102] Among them, the hard disk connector is configured to store the sub-data to be stored in the corresponding local expansion hard disk. The sub-data to be stored is obtained by logically decomposing local data and remote data. The sub-data to be stored has the same number of data channels as the local expansion hard disk. The hard disk connector is connected to the NVMe SSD hard disk (local expansion hard disk) through a dedicated cable.

[0103] Optionally, as shown in Figure 3, the secondary logic component of the local FPGA acceleration card provided in an embodiment of the present application includes a first logic component (Switch_1) and a second logic component (Switch_2). The first logic component and the second logic component are both provided with corresponding hard disk connectors, that is, the local FPGA acceleration card is provided with two hard disk connectors, and each hard disk connector is provided with a local expansion hard disk fixedly connected thereto. The two hard disk connectors are respectively configured to decompose the first logic component and the second logic component to obtain sub-data to be stored and store them in the corresponding local expansion hard disks.

[0104] Optionally, in one embodiment, the data decomposition logic of the primary logic component and the secondary logic component is determined according to application requirements of the local CPU and the remote CPU for the local extended hard disk.

[0105] It should be noted that the data decomposition logic of the primary logic component and the secondary logic component can also be determined according to the business requirements of the server.

[0106] Optionally, in one embodiment, the local FPGA accelerator card communicates with the host BMC based on a complex programmable logic device (CPLD) to obtain the application requirements of the local CPU for the local extended hard disk.

[0107] The application demand of the local CPU for the local expansion hard disk may be mainly expressed as the application quantity demand for the local expansion hard disk.

[0108] Optionally, for the internal logic part of the local FPGA acceleration card, the CPLD of the local FPGA acceleration card first communicates with the BMC of the CPU to obtain the hard disk storage space required by the local CPU, and then the CPLD communicates with the FPGA card in the local FPGA acceleration card to confirm the storage information to determine the application requirements of the local CPU for the local extended hard disk.

[0109] Optionally, in one embodiment, taking the example of a local FPGA acceleration card connecting 8 local expansion hard disks through a PCIe interface, when the application requirement of the local CPU for the local expansion hard disk is that all local expansion hard disks are required, the local FPGA acceleration card transceiver transmits the local data to the first-level logic component; the first-level logic component is configured to perform a first logical decomposition on the local data sent by the local CPU to obtain a local first-path data and a local second-path data; the first-level logic data includes the local first-path data and the local second-path data; the local first-path data is input into the first logic component, and the first logic component is configured to decompose the local first-path data into 4-path sub-data to be stored; the local second-path data is input into the second logic component, and the second logic component is configured to decompose the local second-path data into 4-path sub-data to be stored.

[0110] Optionally, when the local CPU's application requirement for the local extended hard disk requires all local extended hard disks, it indicates that the current local extended hard disk is not shared with the remote CPU, that is, the local FPGA acceleration card transceiver only receives local data, and then transmits the received local data to the first-level logic component to first perform a first-level logical decomposition on the local data to obtain local first-path data and local second-path data, and then decompose the local first-path data and local second-path data into sub-data to be stored based on the first logic component and the second logic component respectively.

[0111] Optionally, in one embodiment, when the local CPU has no application demand for the local extended hard disk, the application demand of the remote CPU for the local extended hard disk is characterized as requiring all local extended hard disks; the local FPGA acceleration card transceiver transmits the remote data to the first-level logic component, and the first-level logic component is configured to decompose the remote data into remote first-path data and remote second-path data; the first-level logic data includes remote first-path data and remote second-path data; the remote first-path data is input into the first logic component, and the first logic component is configured to decompose the remote first-path data into 4-path sub-data to be stored; the remote second-path data is input into the second logic component, and the second logic component is configured to decompose the remote second-path data into 4-path sub-data to be stored.

[0112] Optionally, when the local CPU has no application requirements for the local extended hard disk, all local extended hard disks representing the local FPGA acceleration card can be used as shared extended hard disks of the remote CPU. At this time, the local FPGA acceleration card transceiver only receives remote data, and then transmits the received remote data to the first-level logic component to first perform a first-level logical decomposition on the remote data to obtain remote first-path data and remote second-path data, and then decompose the remote first-path data and remote second-path data into sub-data to be stored based on the first logic component and the second logic component respectively.

[0113] Optionally, as shown in Figure 3, when the local CPU needs the eight SSDs (Solid State Disks) connected to the local FPGA accelerator card, PCIe x16_0 serves as the host of logical Switch_0 and transmits data downward to x16_2 and x16_3. Then x16_2 and x16_3 serve as the hosts of logical Switch_1 and logical Switch_2, respectively, and transparently transmit data downward to the four x4s. When the local CPU does not need the eight SSDs connected to the local FPGA accelerator card, QSFP X16_1 serves as the host of logical Switch_0 and transmits data downward to x16_2 and x16_3. Then x16_2 and x16_3 serve as the hosts of logical Switch_1 and logical Switch_2, respectively, and transparently transmit data downward to the four x4s.

[0114] Optionally, in one embodiment, when the local CPU's application requirement for the local extended hard disk is that one local extended hard disk is required, the remote CPU's application requirement for the local extended hard disk is that seven local extended hard disks are required; the local FPGA acceleration card transceiver directly transmits the local data to the first logic component, and the first logic component is configured to decompose the local data into one path of sub-data to be stored; the local FPGA acceleration card transceiver splits and transmits the remote data to the first logic component and the second logic component, and the first logic component is configured to decompose the obtained remote data into three paths of sub-data to be stored, and the second logic component is configured to decompose the obtained remote data into four paths of sub-data to be stored.

[0115] Accordingly, in one embodiment, when the local CPU's application requirement for the local expansion hard disk is that 7 local expansion hard disks are required, the remote CPU's application requirement for the local expansion hard disk is that 1 local expansion hard disk is required; the local FPGA acceleration card transceiver directly transmits the remote data to the second logic component, and the second logic component is configured to decompose the remote data into 1 path of sub-data to be stored; the local FPGA acceleration card transceiver splits and transmits the local data to the first logic component and the second logic component, the first logic component is configured to decompose the obtained local data into 4 paths of sub-data to be stored, and the second logic component is configured to decompose the obtained local data into 3 paths of sub-data to be stored.

[0116] Optionally, when there is a large gap between the application requirements of the local CPU and the remote CPU for the local extended hard disk, in order to improve the data decomposition efficiency, the local data and the remote data can be directly transferred to the secondary logical component, that is, the data can be directly decomposed based on the first logical component and the second logical component to quickly convert them into sub-data to be stored.

[0117] Optionally, in one embodiment, when the local CPU's application requirement for the local extended hard disk is that 4 local extended hard disks are required, it is characterized that the remote CPU's application requirement for the local extended hard disk is that 4 local extended hard disks are required; the local FPGA acceleration card transceiver transmits local data and remote data to the first-level logic component; the first-level logic component is configured to decompose the local data into local first-level logic data (x16_2) and decompose the remote data into remote first-level logic data (x16_3); the first logic component is configured to decompose the local first-level logic data into 4-way sub-data to be stored; the second logic component is configured to decompose the remote first-level logic data into 4-way sub-data to be stored.

[0118] Optionally, when the local CPU needs four SSDs connected to the local FPGA accelerator card, PCIe x16_0 and QSFPX16_1 simultaneously serve as the host of logical Switch_0, transmitting data to x16_2 and x16_3 respectively. Then, x16_2 and x16_3 serve as the host of logical Switch_1 and logical Switch_2 respectively, transparently transmitting data to four x4 ports respectively.

[0119] Optionally, in one embodiment, when the local CPU's application requirement for the local expansion hard disk is that 5 local expansion hard disks are required, the remote CPU's application requirement for the local expansion hard disk is characterized as that 3 local expansion hard disks are required; the local FPGA acceleration card transceiver directly transmits the remote data to the second logic component, and the second logic component is configured to decompose the remote data into 3 sub-data to be stored; the local FPGA acceleration card transceiver splits and transmits the local data to the first logic component and the second logic component, the first logic component is configured to decompose the obtained local data into 4 sub-data to be stored, and the second logic component is configured to decompose the obtained local data into 1 sub-data to be stored.

[0120] Optionally, in one embodiment, the secondary logic component includes a first logic component and a second logic component, and the local FPGA acceleration card is connected to 8 local expansion hard disks via a PCIe interface;

[0121] When the local CPU's application requirement for local expansion hard disks is 6 local expansion hard disks, it indicates that the remote CPU's application requirement for local expansion hard disks is 2 local expansion hard disks.

[0122] The local FPGA acceleration card transceiver splits and transmits the local data to the first logic component and the second logic component. The first logic component is configured to decompose the local data into 4 sub-data to be stored; the second logic component is configured to decompose the obtained local data into 2 sub-data to be stored.

[0123] The local FPGA accelerator card transceiver directly transmits the remote data to the second logic component, and the second logic component is configured to decompose the obtained remote data into two paths of sub-data to be stored.

[0124] Optionally, in one embodiment, the secondary logic component includes a first logic component and a second logic component, and the local FPGA acceleration card is connected to 8 local expansion hard disks via a PCIe interface;

[0125] When the local CPU's application requirement for local expansion hard disks is two local expansion hard disks, it indicates that the remote CPU's application requirement for local expansion hard disks is six local expansion hard disks.

[0126] The local FPGA acceleration card transceiver splits and transmits the remote data to the first logic component and the second logic component. The first logic component is configured to decompose the remote data into two paths of sub-data to be stored; the second logic component is configured to decompose the obtained remote data into four paths of sub-data to be stored.

[0127] The local FPGA acceleration card transceiver directly transmits the local data to the first logic component, and the first logic component is configured to decompose the obtained local data into two paths of sub-data to be stored.

[0128] For example, as shown in Table 1, the data decomposition logic used by the local FPGA accelerator card to meet different application requirements is as follows:

[0129] Table 1

[0130] PCIe x16_0 represents local data, hereinafter referred to as x16_0. The corresponding number represents the number of local expansion hard drives required by the local CPU. QSFP28 x16_1 represents remote data, hereinafter referred to as x16_1. The corresponding number represents the number of local expansion hard drives required by the remote CPU. Switch_0 represents the primary logic component, Switch_1 represents the first logic component, and Switch_2 represents the second logic component. Up represents input, also known as upstream; Down represents output, also known as downstream. x4 represents sub-data to be stored. x16_2 and x16_3 represent the primary logical data decomposed from the primary logic component.

[0131] It should be noted that when the local CPU or remote CPU needs to read data from the local extended hard disk, the transmission path for reading the data is similar to the data storage path provided in the above embodiment. The read data passes through the secondary logic component and the primary logic component in turn for data restoration, and is finally transmitted to the local CPU through the PCIe x16 interface, or transmitted to the optical switch through the optical fiber module.

[0132] It should be noted that Switch_0 is encapsulated with a logical IP (Internet Protocol) core, that is, one channel of x16 data enters the logical core and outputs two channels of x16 data. The UP of Switch0 is 32 pairs of differential pins (16 pairs of RX receiving and 16 pairs of TX sending), and the down of Switch0 is 2 channels of X16, each channel of X16 is the same as the UP, and then enters Switch1 and Switch2 respectively. This decomposition logic actually decomposes the x16 data obtained at the entrance into 8 x4 data (sub-data to be stored) at the exit through logic, so that the local and remote NVMe SSDs can be flexibly configured to make full and reasonable use of hard disk resources. On the basis of the above embodiment, as shown in Figure 4, which is a structural schematic diagram of another local FPGA acceleration card provided in an embodiment of the present application, as an implementable method, in one embodiment, the local FPGA acceleration card includes: a complex programmable logic device, which is configured to control and manage the power supply.

[0133] Among them, the complex programmable logic device is also configured to monitor the entire board status information of the local FPGA accelerator card and send the entire board status information to the host BMC.

[0134] It's important to note that the CPLD is responsible for controlling power sequencing and GPIO (General-Purpose Input / Output) communication. It also acts as the FPGA accelerator's Baseboard Management (BMC), managing and monitoring board power consumption, temperature, and alarms. This information communicates with the CPU board via the SMBUS (System Management Bus) in the PCIe x16 connector. The CPLD communicates with the FPGA primarily through I2C and GPIO, obtaining information about the current FPGA status and the source and decomposition of data entering the FPGA.

[0135] Optionally, in one embodiment, the local FPGA acceleration card includes: a plurality of memory slots (DDR4 / 5), which are configured to connect to local expansion memory to expand the memory resources of the server.

[0136] It should be noted that the local FPGA acceleration card provided in the embodiment of the present application is a standard x16 PCIe card that supports 4-way DDR4 / DDR5 and 2-way QSFP-DD. The complex programmable logic device (CPLD) controls and manages the power supply and acts as the BMC function of the local FPGA acceleration card to manage and monitor the power consumption, temperature, alarm and other status information of the entire board. At the same time, it communicates with the host BMC of the host side (local CPU) through SMBUS to send the status information of the entire board to the host BMC. The local FPGA acceleration card is connected to the PCIe Slot of the local CPU via PCIe GEN5 x16, and then the two MCIO connectors of the local FPGA acceleration card are output to connect to 8 NVMe SSDs (local expansion hard drives).

[0137] In one embodiment, the local FPGA acceleration card includes: a whole-board status indicator light (LED).

[0138] The board status indicator is configured to report the status of the local FPGA accelerator card in different lighting modes, such as a solid red light if the temperature is too high and a solid yellow light if the power consumption is too high.

[0139] Optionally, in one embodiment, the local FPGA accelerator card includes: a clock generator and flash memory. As shown in FIG4 , the local FPGA accelerator card also includes functional components such as a clock buffer CLK Buffer, Other IC, JTAG, and FAN CONN.

[0140] Flash memory and a clock generator are essential components on the FPGA board. Flash memory is a standard, essential FPGA peripheral component to ensure proper FPGA operation. The clock generator generates a clock that is fed to the Compute Express Link (CXL) memory expansion board (memory module slot), a device interconnect technology standard, via the CXL memory expansion board (memory module slot). This signal is essential for the CXL memory to operate.

[0141] It should be noted that the local FPGA acceleration card is based on the FPGA card, and functional components such as a clock generator and flash memory are added to the FPGA card to build a local FPGA acceleration card. The components to be added can be set according to actual needs, and this embodiment of the application does not limit it.

[0142] An embodiment of the present application provides a data storage system comprising: a local CPU and a local FPGA accelerator card connected to the local CPU via a PCIe interface; the local CPU connected to several local hard drives via the PCIe interface; the local FPGA accelerator card connected to several local expansion hard drives; and the local FPGA accelerator card configured to establish network communication between the local CPU and a remote CPU, so that the local CPU and the remote CPU can share the expansion hard drive. In the system provided by the above solution, the local FPGA accelerator card can not only connect to the local expansion hard drive to expand the local hard drive, but can also replace the network card to establish network communication between the local CPU and the remote CPU, thereby improving server performance. The FPGA accelerator card can flexibly implement NVMe SSD expansion and hard drive sharing of the remote CPU. This not only simplifies expansion but also facilitates NVMe SSD expansion allocation, allowing the local CPU and the remote CPU to efficiently and reasonably use the locally expanded NVMe SSD. The number of expansion SSDs that can be implemented can vary with different FPGA resources and can be allocated on demand. In addition, the local expansion hard drive is relative to the currently mounted CPU. The remote CPU also has its own local NVMe SSD, which can also be shared with the remote CPU.

[0143] The embodiment of the present application provides a data storage method for data storage. The execution subject of the embodiment of the present application is an electronic device, such as a server, a desktop computer, a laptop computer, a tablet computer, and other electronic devices that can be used for data storage.

[0144] FIG5 is a flow chart of a data storage method according to an embodiment of the present application. The method includes:

[0145] Step 701, obtaining data to be stored;

[0146] Step 702: Save the data to be stored to the local hard disk, the local extended hard disk, or the remote extended hard disk.

[0147] Among them, the local hard disk is connected to the local CPU through the PCIe interface, the local extended hard disk is connected to the local FPGA acceleration card, the local FPGA acceleration card is connected to the local CPU through the PCIe interface, and the remote FPGA acceleration card connected to the remote CPU is provided with a remote extended hard disk. The local CPU and the remote CPU establish network communication through the local FPGA acceleration card and the remote FPGA acceleration card, so that the local CPU and the remote CPU share the extended hard disk.

[0148] Regarding the data storage method in this embodiment, the specific implementation of each step has been described in detail in the embodiment of the system and will not be elaborated here.

[0149] The data storage method provided in the embodiment of the present application is applied to the data storage system provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0150] An embodiment of the present application provides a server configured to execute the data storage method provided in the above embodiment.

[0151] As shown in Figure 6, it is a schematic diagram of the structure of the server provided in the embodiment of the present application. The server includes the data storage system provided in the above embodiment.

[0152] The server provided in the embodiment of the present application is applied to the data storage method provided in the above embodiment to store data in the data storage system. Its implementation method and principle are the same and will not be repeated here.

[0153] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the system can be divided into different functional modules to complete all or part of the functions described above.

[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data storage system, characterized in that, including: a local central processing unit (CPU) and a local field programmable gate array (FPGA) acceleration card connected to the local CPU through a Peripheral Component Interconnect Express (PCIe) interface of a high-speed serial computer expansion bus standard; the local CPU is connected to a plurality of local hard disks through a PCIe interface; the local FPGA acceleration card is connected to a plurality of local extended hard disks; the local FPGA acceleration card is configured to establish network communication between the local CPU and a remote CPU, and receive and process local data sent by the local CPU and remote data sent by the remote CPU, so that the local CPU and the remote CPU share the extended hard disks.

2. The system according to claim 1, wherein the local FPGA acceleration card is connected to a remote FPGA acceleration card through an optical switch to establish network communication between the local CPU and the remote CPU; wherein, the remote FPGA and the remote CPU are connected through a PCIe interface.

3. The system according to claim 1, wherein the local FPGA acceleration card includes: an optical fiber module; the optical switch is connected to the transceiver pins of the local FPGA acceleration card through the optical fiber module; the local CPU is connected to the transceiver pins of the local FPGA acceleration card through a PCIe interface; wherein, the optical switch is configured to forward remote data sent by the remote CPU.

4. The system according to claim 3, wherein the local FPGA acceleration card is configured to: perform data format conversion on the received remote data according to the communication protocol type of the optical fiber module, so that the data format of the remote data is the same as that of the local data.

5. The system according to claim 1, wherein the local FPGA acceleration card includes: a hard disk connector; the hard disk connector is configured to store the sub-data to be stored into the corresponding local extended hard disk; wherein, the sub-data to be stored is obtained by logically decomposing the local data and the remote data, and the number of data channels of the sub-data to be stored is the same as that of the local extended hard disk.

6. The system according to claim 1, characterized in that the local FPGA acceleration card includes: a first-level logic component and a second-level logic component; the first-level logic component is configured to perform a first logical decomposition on the local data sent by the local CPU and / or the remote data forwarded by the optical switch to obtain first-level logical data; the second-level logic component is configured to perform a second logical decomposition on the first-level logical data to obtain a corresponding number of sub-data to be stored.

7. The system according to claim 6, wherein the data decomposition logics of the first-level logic component and the second-level logic component are determined according to the application requirements of the local CPU and the remote CPU for the local extended hard disks.

8. The system according to claim 7, characterized in that, the local FPGA acceleration card communicates with a baseboard management controller (BMC) based on a complex programmable logic device to obtain the application requirements of the local CPU for the local extended hard disks.

9. The system according to claim 7, wherein the second-level logic component includes a first logic component and a second logic component, and the local FPGA acceleration card is connected to 8 local extended hard disks through the PCIe interface; when the application requirement of the local CPU for the local extended hard disks is to require all the local extended hard disks, the local FPGA acceleration card transceiver transmits the local data to the first-level logic component; The first-level logic component is configured to perform a first logical decomposition on the local data sent by the local CPU to obtain local first-path data and local second-path data; the first-level logical data includes the local first-path data and the local second-path data; Input the local first-path data into the first logical component, and the first logical component is configured to decompose the local first-path data into 4 sub-data to be stored; Input the local second-path data into the second logical component, and the second logical component is configured to decompose the local second-path data into 4 sub-data to be stored.

10. The system according to claim 7, characterized in that, The second-level logic component includes a first logical component and a second logical component, and the local FPGA acceleration card is connected to 8 local extended hard disks through the PCIe interface; When the local CPU has no application requirement for the local extended hard disk, it represents that the remote CPU's application requirement for the local extended hard disk is to require all the local extended hard disks; The local FPGA acceleration card transceiver transmits the remote data to the first-level logic component, and the first-level logic component is configured to decompose the remote data into remote first-path data and remote second-path data; the first-level logical data includes the remote first-path data and the remote second-path data; Input the remote first-path data into the first logical component, and the first logical component is configured to decompose the remote first-path data into 4 sub-data to be stored; Input the remote second-path data into the second logical component, and the second logical component is configured to decompose the remote second-path data into 4 sub-data to be stored.

11. The system according to claim 7, wherein The second-level logic component includes a first logical component and a second logical component, and the local FPGA acceleration card is connected to 8 local extended hard disks through the PCIe interface; When the local CPU's application requirement for the local extended hard disk is to require 1 local extended hard disk, it represents that the remote CPU's application requirement for the local extended hard disk is to require 7 local extended hard disks; The local FPGA acceleration card transceiver directly transmits the local data to the first logical component, and the first logical component is configured to decompose the local data into 1 sub-data to be stored; The local FPGA acceleration card transceiver splits and transmits the remote data to the first logical component and the second logical component. The first logical component is configured to decompose the obtained remote data into 3 sub-data to be stored, and the second logical component is configured to decompose the obtained remote data into 4 sub-data to be stored.

12. The system according to claim 7, wherein The second-level logic component includes a first logical component and a second logical component, and the local FPGA acceleration card is connected to 8 local extended hard disks through the PCIe interface; When the local CPU's application requirement for the local extended hard disk is to require 7 local extended hard disks, it represents that the remote CPU's application requirement for the local extended hard disk is to require 1 local extended hard disk; The local FPGA acceleration card transceiver directly transmits the remote data to the second logical component, and the second logical component is configured to decompose the remote data into 1 sub-data to be stored. The local FPGA acceleration card transceiver splits and transmits the local data to the first logic component and the second logic component. The first logic component is configured to decompose the obtained local data into 4 sub-data to be stored, and the second logic component is configured to decompose the obtained local data into 3 sub-data to be stored.

13. The system according to claim 7, wherein The secondary logic component includes a first logic component and a second logic component. The local FPGA acceleration card is connected to 8 local expansion hard disks through the PCIe interface. When the application requirement of the local CPU for the local expansion hard disk is 4 of the local expansion hard disks, it represents that the application requirement of the remote CPU for the local expansion hard disk is 4 of the local expansion hard disks. The local FPGA acceleration card transceiver transmits the local data and the remote data to the primary logic component. The primary logic component is configured to decompose the local data into local primary logic data and decompose the remote data into remote primary logic data. The first logic component is configured to decompose the local primary logic data into 4 sub-data to be stored. The second logic component is configured to decompose the remote primary logic data into 4 sub-data to be stored.

14. The system according to claim 7, characterized in that The secondary logic component includes a first logic component and a second logic component. The local FPGA acceleration card is connected to 8 local expansion hard disks through the PCIe interface. When the application requirement of the local CPU for the local expansion hard disk is 5 of the local expansion hard disks, it represents that the application requirement of the remote CPU for the local expansion hard disk is 3 of the local expansion hard disks. The local FPGA acceleration card transceiver directly transmits the remote data to the second logic component. The second logic component is configured to decompose the remote data into 3 sub-data to be stored. The local FPGA acceleration card transceiver splits and transmits the local data to the first logic component and the second logic component. The first logic component is configured to decompose the obtained local data into 4 sub-data to be stored, and the second logic component is configured to decompose the obtained local data into 1 sub-data to be stored.

15. The system according to claim 7, characterized in that The secondary logic component includes a first logic component and a second logic component. The local FPGA acceleration card is connected to 8 local expansion hard disks through the PCIe interface. When the application requirement of the local CPU for the local expansion hard disk is 6 of the local expansion hard disks, it represents that the application requirement of the remote CPU for the local expansion hard disk is 2 of the local expansion hard disks. The local FPGA acceleration card transceiver splits and transmits the local data to the first logic component and the second logic component. The first logic component is configured to decompose the local data into 4 sub-data to be stored. The second logic component is configured to decompose the obtained local data into 2 sub-data to be stored. The local FPGA acceleration card transceiver directly transmits the remote data to the second logic component. The second logic component is configured to decompose the obtained remote data into 2 sub-data to be stored.

16. The system according to claim 7, characterized in that, The secondary logic component includes a first logic component and a second logic component. The local FPGA acceleration card is connected to 8 local expansion hard disks through the PCIe interface; When the application requirement of the local CPU for the local expansion hard disk is 2 local expansion hard disks, it represents that the application requirement of the remote CPU for the local expansion hard disk is 6 local expansion hard disks; The transceiver of the local FPGA acceleration card splits and transmits the remote data to the first logic component and the second logic component. The first logic component is configured to decompose the remote data into 2 sub-data to be stored; the second logic component is configured to decompose the obtained remote data into 4 sub-data to be stored; The transceiver of the local FPGA acceleration card directly transmits the local data to the first logic component, and the first logic component is configured to decompose the obtained local data into 2 sub-data to be stored.

17. The system according to claim 1, wherein The local FPGA acceleration card includes: A complex programmable logic device, configured to control and manage the power supply and monitor the overall board status information of the local FPGA acceleration card; Send the overall board status information to the host BMC.

18. The system according to claim 1, wherein The local FPGA acceleration card includes: a plurality of memory module slots, configured to connect to the local extended memory to expand the memory resources of the server.

19. A data storage method, characterized in that, Includes: Obtain the data to be stored; Save the data to be stored to the local hard disk, local expansion hard disk or remote expansion hard disk; Wherein, the local hard disk is connected to the local CPU through the PCIe interface, the local expansion hard disk is connected to the local FPGA acceleration card, the local FPGA acceleration card is connected to the local CPU through the PCIe interface, a remote expansion hard disk is provided on the remote FPGA acceleration card connected to the remote CPU, and the local CPU and the remote CPU establish network communication through the local FPGA acceleration card and the remote FPGA acceleration card so that the local CPU and the remote CPU share the expansion hard disk.

20. A server, characterized in that, Includes: The data storage system according to any one of claims 1 to 18.

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