Chip packaging structure, single board and network device

Abstract

The embodiments of the present application relate to the technical field of semiconductor devices. Provided are a chip packaging structure, a single board and a network device, which are used for improving the sealing reliability of chip packaging structures and preventing leakage of cooling liquids. The chip packaging structure comprises a packaging substrate, a heat dissipation cover, a chip and a sealing structure. The heat dissipation cover covers the packaging substrate, and the heat dissipation cover and the packaging substrate enclose a heat dissipation cavity. The chip is located in the heat dissipation cavity, and the chip is arranged on the packaging substrate. At least part of the sealing structure is located in the heat dissipation cavity. The sealing structure is arranged on the packaging substrate. The sealing structure is arranged around the periphery of the chip, and is connected to the chip. The sealing structure is further sealingly connected to the heat dissipation cover, and the part of the sealing structure sealingly connected to the heat dissipation cover is a metallic material or an inorganic non-metallic material.

Description

Chip packaging structure, single board and network equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 29, 2023, with application number 202311862481.2 and application name “A chip packaging structure, single board and network device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor device technology, and in particular to a chip packaging structure, a single board, and a network device. Background Art

[0003] As network equipment becomes increasingly multifunctional, the integration level and assembly density of chips continue to increase. While chips have powerful functions, they also lead to a sharp increase in chip power consumption and heat generation.

[0004] Currently, conventional air cooling technology can no longer meet the heat dissipation requirements of chips. Therefore, jet liquid cooling is gradually becoming more widely used. However, the current jet liquid cooling method has a high risk of coolant leakage and poor reliability of the heat dissipation module.

[0005] Summary of the Invention

[0006] The purpose of this application is to provide a chip packaging structure, a single board and a network device, which are used to improve the sealing reliability of the chip packaging structure and prevent coolant leakage.

[0007] According to a first aspect of an embodiment of the present application, a chip packaging structure is provided, which includes a packaging substrate, a heat dissipation cover, a chip and a sealing structure. The heat dissipation cover is provided on the packaging substrate, and the heat dissipation cover and the packaging substrate enclose a heat dissipation cavity. The chip is located in the heat dissipation cavity, and the chip is provided on the packaging substrate. At least a portion of the sealing structure is located in the heat dissipation cavity. The sealing structure is provided on the packaging substrate. The sealing structure is provided around the periphery of the chip and the sealing structure is connected to the chip. The sealing structure is also sealed to the heat dissipation cover, and the portion where the sealing structure is sealed to the heat dissipation cover is a metal material or an inorganic non-metallic material.

[0008] As can be seen from the above, the heat dissipation cover and the packaging substrate enclose a heat dissipation cavity, and the chip is located in the heat dissipation cavity. By passing the coolant into the heat dissipation cavity, the coolant can absorb and take away the heat emitted by the chip, thereby completing the heat dissipation work of the chip. In the related art, the heat dissipation cover is bonded to the organic polymer on the side of the chip. However, during the operation of the chip, the temperature of the coolant around the chip is generally higher than room temperature. In a warm coolant environment, the organic polymer will age and produce deformation or surface cracking. When the connection between the organic polymer and the heat dissipation cover is deformed or cracked, a gap will be generated between the organic polymer and the heat dissipation cover, thereby reducing the sealing performance of the connection between the heat dissipation cover and the organic polymer, and causing the coolant to leak at this location. The connection between the sealing structure and the heat dissipation cover of the chip packaging structure provided in the embodiment of the present application is made of metal material or inorganic non-metallic material. In a warm coolant environment, both metal materials and inorganic non-metallic materials are not easy to age, thereby avoiding deformation or surface cracking of the part where the sealing structure and the heat dissipation cover are sealed due to material aging. This prevents a gap from forming between the sealing structure and the heat dissipation cover, thereby preventing the coolant from leaking from between the sealing structure and the heat dissipation cover. This improves the sealing reliability of the chip packaging structure and prevents coolant leakage.

[0009] In some embodiments of the present application, the sealing structure includes a first annular structure and a second annular structure. The first annular structure is sealed to the heat dissipation cover and is made of a metal material or an inorganic non-metallic material. The second annular structure is located within the hollow area of ​​the first annular structure, and the chip is located within the hollow area of ​​the second annular structure, i.e., the first annular structure, the second annular structure, and the chip are nested in sequence. The second annular structure is connected to the chip on the side facing the chip, and connected to the first annular structure on the side facing away from the chip. The first annular structure is made of a metal material or an inorganic non-metallic material. The first annular structure is not susceptible to aging, preventing deformation or surface cracking due to material aging, which could cause a gap between the sealing structure and the heat dissipation cover, thereby allowing coolant to leak through the gap. This ensures the sealing performance of the connection between the first annular structure and the heat dissipation cover and prevents coolant leakage. In addition, the second annular structure is connected to the chip on the side facing the chip, and the second annular structure is connected to the first annular structure on the side facing away from the chip, thereby ensuring the relative fixation of the first annular structure, the second annular structure, and the chip, and ensuring the stability of the connection between the sealing structure and the chip.

[0010] In some embodiments of the present application, the chip packaging structure further includes a sealing ring. The sealing ring is disposed between the first annular structure and the heat dissipation cover. The first annular structure is sealed to the heat dissipation cover via the sealing ring. The sealing ring disposed between the first annular structure and the heat dissipation cover ensures a seal between the first annular structure and the heat dissipation cover, preventing coolant leakage between the first annular structure and the heat dissipation cover.

[0011] In some embodiments of the present application, the first annular structure includes a first annular portion and a first extension portion. The first annular portion is arranged on the packaging substrate and is connected to the packaging substrate. The side of the first annular portion facing the chip is connected to the second annular structure. The first annular portion is also sealed to the heat dissipation cover. The first extension portion is arranged on the packaging substrate and is located on the side of the first annular portion facing away from the chip. The first extension portion is connected to the packaging substrate. The side of the first extension portion facing the chip is connected to the first annular portion. The first annular portion is connected to the first extension portion, and the first annular portion and the first extension portion are both connected to the packaging substrate, thereby increasing the connection area between the first annular structure and the packaging substrate, and improving the connection reliability between the first annular structure and the packaging substrate.

[0012] In some embodiments of the present application, the second annular structure includes a second annular portion and a second extension portion. The second annular portion is arranged on the packaging substrate and connected to the packaging substrate. The side of the second annular portion facing away from the chip is connected to the first annular structure, and the side of the second annular portion facing the chip is connected to the chip. The second extension portion is located on the side of the second annular portion facing away from the packaging substrate, and the second extension portion is connected to the first annular structure. The second annular portion is connected to the second extension portion, and both the second annular portion and the second extension portion are connected to the first annular structure, thereby increasing the connection area between the second annular structure and the first annular structure and improving the connection reliability between the second annular structure and the first annular structure.

[0013] In some embodiments of the present application, a heat dissipation cover includes a top cover and a side portion. The side portion is located on the side of the top cover facing the package substrate and is connected to the top cover. The inner sidewall of the side portion is connected to a sealing structure. During operation, the hydraulic pressure in the heat dissipation chamber is high, and the coolant exerts a force on the top cover and the side portion. In related art, the connection between the heat dissipation cover and other structures is parallel to the surface of the chip facing away from the package substrate. When the heat dissipation cover is subjected to a force perpendicular to the surface of the chip facing the heat dissipation chamber due to the hydraulic pressure in the heat dissipation chamber, only the connection force at the connection counteracts the force generated by the hydraulic pressure, which can easily create a gap and lead to coolant leakage. In contrast, in the chip packaging structure provided in the embodiments of the present application, the inner sidewall of the side portion is connected to the sealing structure. In this case, the connection between the heat dissipation cover and the sealing structure is located on the inner sidewall of the side portion. When the heat dissipation cover is subjected to a force perpendicular to the surface of the chip facing the heat dissipation chamber due to the hydraulic pressure in the heat dissipation chamber, the connection force at the connection between the inner sidewall of the side portion and the sealing structure and the friction between the inner sidewall of the heat dissipation cover and the sealing structure prevent the heat dissipation cover and the sealing structure from separating and creating a gap, thereby preventing coolant leakage. When the heat dissipation cover is subjected to a force parallel to the surface of the chip facing the heat dissipation cavity due to the hydraulic pressure of the heat dissipation cavity, the forces between the inner side walls in the symmetrical side positions are in opposite directions and thus offset each other, preventing the heat dissipation cover from detaching from the sealing structure due to excessive force and creating a gap, thereby avoiding coolant leakage.

[0014] In some embodiments of the present application, the chip packaging structure further includes a waterproof layer. This waterproof layer is located within the heat dissipation cavity and on the side of the chip facing away from the packaging substrate. The waterproof layer covers at least the connection between the sealing structure and the chip. This waterproof layer prevents direct contact between the sealing structure and the chip and the coolant, thereby preventing aging of the portion of the sealing structure facing the chip, which could affect the sealing performance due to material aging. This improves the sealing reliability of the chip packaging structure and prevents coolant leakage.

[0015] In some embodiments of the present application, the waterproof layer covers the chip surface facing away from the package substrate, and the waterproof layer also covers the sealing structure surface facing away from the package substrate. In this case, the waterproof layer can prevent the entire sealing structure from coming into direct contact with the coolant, further preventing aging of the sealing structure and thus affecting its sealing performance. Furthermore, the waterproof layer can prevent moisture within the heat dissipation cavity from penetrating the sealing structure or the chip and entering the package substrate, thereby affecting the normal operation of the circuits arranged on the package substrate.

[0016] In some embodiments of the present application, the waterproof layer comprises at least one of a metal plating layer or an inorganic coating. For example, the waterproof layer comprises at least one of a copper plating layer, a nickel plating layer, a chromium plating layer, a glassy coating, a ceramic coating, a metal-ceramic coating, or an intermetallic compound coating. Both the metal plating layer and the inorganic coating are resistant to aging, ensuring the waterproof layer's aging resistance when immersed in a warm coolant, and preventing degradation of the waterproof layer's waterproof performance due to aging.

[0017] In some embodiments of the present application, the thickness of the waterproof layer is 5μm to 100μm. Exemplarily, the thickness of the waterproof layer is 5μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, etc. The thickness of the waterproof layer is greater than or equal to 5μm, which can ensure the rigidity of the waterproof layer and prevent the coolant from entering the side of the waterproof layer facing the packaging substrate due to the rupture of the waterproof layer, thereby preventing the part of the sealing structure facing the chip from being in direct contact with the coolant and aging, thereby affecting the sealing performance. In addition, the thickness of the waterproof layer is less than or equal to 100μm. At this time, while ensuring the rigidity of the waterproof layer, the cost of the waterproof layer can be reduced.

[0018] In some embodiments of the present application, the chip packaging structure further includes a fixed plate. The fixed plate is arranged on the side of the packaging substrate facing away from the chip, and the fixed plate is connected to the packaging substrate, and the heat dissipation cover is connected to the fixed plate. The packaging substrate and the heat dissipation cover are both connected to the fixed plate. The fixed plate can support the packaging substrate and the heat dissipation cover, thereby ensuring the structural stability of the chip packaging structure. In the related art, the heat dissipation cover is connected to the organic polymer on the peripheral side of the chip, and the organic polymer is adhered to the packaging substrate and fixedly connected to the chip. During normal operation, after the heat dissipation cover is subjected to hydraulic force, a large force will be generated on the packaging substrate and the chip through the organic polymer. When the force is large, it may affect the working performance of the packaging substrate and the chip. In the chip packaging structure provided in the embodiment of the present application, after the heat dissipation cover is connected to the fixed plate, the force of the connection acts directly on the fixed plate. At this time, it is possible to avoid a large force acting on the packaging substrate and the chip, thereby improving the reliability of the chip packaging structure.

[0019] In some embodiments of the present application, the heat dissipation cover is provided with ejection holes and return holes that communicate with the heat dissipation cavity. Coolant enters the heat dissipation cavity through the ejection holes. After absorbing heat, the coolant flows out of the heat dissipation cavity through the return holes, thereby dissipating heat from the chip.

[0020] In some embodiments of the present application, the distance h between the outlet end of the jet hole facing the chip and the chip is h; where 0 < h ≤ 1 mm. For example, the distance h between the outlet end of the jet hole facing the chip and the chip is 0.1 mm, 0.2 mm, 0.4 mm, 0.6 mm, 0.8 mm, 1 mm, etc. The distance h between the outlet end of the jet hole facing the chip and the chip is greater than 0, ensuring that after the coolant flows from the jet hole into the heat dissipation cavity, it can flow through the gap between the heat dissipation cover and the chip to the return hole and finally flow out of the heat dissipation cavity. In addition, the coolant flowing out of the jet hole will produce a flow rate change under the action of gravity. When the distance h between the outlet end of the jet hole facing the chip and the chip is less than or equal to 1 mm, the flow rate of the coolant flowing out of the jet hole changes little. Therefore, the coolant flow rate will not be too high due to the action of gravity, which will cause a large impact force on the chip and cause chip damage. Alternatively, the coolant flow rate will not be too low due to the action of gravity, and the injected coolant will not be able to directly impact the chip, affecting the chip's heat dissipation effect.

[0021] According to the second aspect of the embodiments of the present application, a single board is provided, which includes the above-mentioned chip packaging structure and liquid circuit system. The liquid circuit system is connected to the heat dissipation cover of the chip packaging structure, and the liquid circuit system is connected to the heat dissipation cavity. The above-mentioned single board has the same technical effect as the chip packaging structure provided by the aforementioned embodiment, which will not be repeated here. In addition, the liquid circuit system is used to inject coolant into the heat dissipation cavity. After the coolant absorbs the heat emitted by the chip in the heat dissipation cavity, it flows back to the liquid circuit system. The refluxed coolant is cooled in the liquid circuit system and is injected into the heat dissipation cavity again. This cycle continuously absorbs and takes away the heat emitted by the chip to complete the heat dissipation of the chip.

[0022] In a third aspect of the embodiments of the present application, a network device is provided, comprising the above-mentioned single board and a cabinet, wherein the single board is disposed in the cabinet and connected to the cabinet. The above-mentioned network device has the same technical effects as the single board provided in the above-mentioned embodiments, and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a schematic diagram of the structure of a communication system provided in an embodiment of the present application;

[0024] FIG2 is a schematic diagram of the structure of a single board provided in an embodiment of the present application;

[0025] FIG3 is a schematic structural diagram of a first chip packaging structure provided in an embodiment of the present application;

[0026] FIG4 is a schematic structural diagram of a second chip packaging structure provided in an embodiment of the present application;

[0027] FIG5 is a schematic structural diagram of a third chip packaging structure provided in an embodiment of the present application;

[0028] FIG6 is a schematic structural diagram of a fourth chip packaging structure provided in an embodiment of the present application;

[0029] FIG7 is a schematic structural diagram of a fifth chip packaging structure provided in an embodiment of the present application;

[0030] FIG8 is a schematic structural diagram of a sixth chip packaging structure provided in an embodiment of the present application;

[0031] FIG9 is a schematic structural diagram of a seventh chip packaging structure provided in an embodiment of the present application.

[0032] Figure numerals: 01-communication system; 02-network device; 03-first access device; 04-second access device; 10-single board; 20-cabinet; 11-chip packaging structure; 111-heat dissipation cavity; 112-chip; 12-fluid system; 1201-cooling liquid tank; 1202-first liquid flow channel; 1203-second liquid flow channel; 1204-hydraulic pump; 1205-side return flow channel; 1206-side valve; 1207-first flow meter; 1208-visual mirror; 1209-second flow meter; 1210-stop valve; 1211-flow valve; 1 212-Pressure protector; 1213-Filter; 1214-Preheater; 1215-Refrigerator; 113-Packaging substrate; 114-Heat dissipation cover; 115-Sealing structure; A-Section where the sealing structure and heat dissipation cover are sealed; 1151-First annular structure; 1152-Second annular structure; 116-Sealing ring; 11511-First annular portion; 11512-First extension; 11521-Second annular portion; 11522-Second extension; 1141-Top cover; 1142-Side portion; 1143-Jet hole; 1144-Return hole. 117-Fixed plate; 118-Connector; 119-Circuit board; 120-Waterproof layer. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0034] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0035] In this application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed mechanical connection, a detachable mechanical connection, or an integrated connection; or, "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0036] In the embodiments of this application, words such as "exemplarily" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplarily" is intended to present the relevant concepts in a concrete manner.

[0037] In the drawings of the embodiments of the present application, components are represented by guide lines with arrows; parts are represented by guide lines only; hollow structures such as cavities and openings are represented by guide lines with wavy lines.

[0038] An embodiment of the present application provides a communication system 01, as shown in Figure 1. Communication system 01 may include a network device 02 and a first access device 03 connected to network device 02. Network device 02 may be a data center, a server, an optical access central office device, a switch, or the like. First access device 03 may send signals to network device 02, which then processes or stores the received signals. Alternatively, network device 02 may send signals to first access device 03, thereby enabling signal exchange between network device 02 and first access device 03.

[0039] Continuing with Figure 1 , the communication system 01 may also include multiple second access devices 04 connected to the network device 02. Similar to the first receiving device 03 described above, the second access devices 04 and the network device 02 can also exchange signals. For example, the network device 02 may receive a signal from the first access device 03, process and distribute the signal, and then transmit the signal to different second access devices 04. Alternatively, the network device 02 may receive a signal from a second access device 04 and transmit the signal to the first access device 03.

[0040] Continuing with FIG1 , network device 02 includes a board 10 and a cabinet 20. Board 10 is disposed within and connected to cabinet 20. Cabinet 20 protects board 10 and also provides power to board 10 to ensure normal operation.

[0041] The above embodiment, as shown in FIG1 , takes as an example a communication system 01 including one network device 02, one first access device 03, and two second access devices 04, and one network device 02 including one cabinet 20 and five boards 10. In other embodiments of the present application, the number of network devices 02, first access devices 03, and second access devices 04 can be other numbers, and the number of cabinets 20 and boards 10 included in one network device 02 can also be other numbers.

[0042] Based on this, since the chip generates heat due to working power consumption during operation, which in turn causes an increase in circuit delay and affects the normal working performance of the chip, in order to dissipate heat from the chip, in some embodiments of the present application, as shown in FIG2 , the above-mentioned single board 10 may include a chip packaging structure 11 and a liquid circuit system 12. The chip packaging structure 11 has a heat dissipation cavity 111 and a chip 112 disposed in the heat dissipation cavity 111. The liquid circuit system 12 is connected to the heat dissipation cavity 111 of the chip packaging structure 11. The liquid circuit system 12 is used to inject coolant into the heat dissipation cavity 111 of the chip packaging structure 11. After the coolant absorbs the heat dissipated by the chip 112, it flows back into the liquid circuit system 12. After the returned coolant is cooled in the liquid circuit system 12, it is injected into the heat dissipation cavity 111 again. This cycle continuously absorbs and takes away the heat dissipated by the chip 112 to complete the heat dissipation of the chip 112.

[0043] The above embodiment, as shown in FIG2 , takes a single board 10 as an example, including one chip packaging structure 11 and one fluid path system 12. In other embodiments of the present application, the number of chip packaging structures 11 and fluid path systems 12 can be other numbers, and one fluid path system 12 can also be connected to the heat dissipation cavities 111 of multiple chip packaging structures 11.

[0044] Continuing with FIG. 2 , the fluid system 12 may include a coolant tank 1201, a first fluid channel 1202, a second fluid channel 1203, and a hydraulic pump 1204 disposed on the first fluid channel 1202. One end of the first fluid channel 1202 communicates with the water tank, while the other end of the first fluid channel 1202 communicates with the heat dissipation cavity 111 of the chip package structure 11. The hydraulic pump 1204 provides circulation power, causing the coolant to circulate between the first fluid channel 1202, the heat dissipation cavity 111, the second fluid channel 1203, and the coolant tank 1201, thereby dissipating heat from the chip package structure 11.

[0045] 2 , the fluid system 12 may further include a side return channel 1205 and a side valve 1206 disposed on the side return channel 1205. One end of the side return channel 1205 is in communication with the first liquid channel 1202, and the other end of the side return channel 1205 is in communication with the coolant tank 1201. When the first liquid channel 1202 is blocked, the side valve 1206 opens, allowing the coolant to flow directly back to the coolant tank 1201. This prevents the hydraulic pressure within the first liquid channel 1202 from continuously increasing when the first liquid channel 1202 is blocked, which could lead to leakage in the first liquid channel 1202.

[0046] Continuing with FIG. 2 , the fluid circuit system 12 may further include a first flow meter 1207 and a sight glass 1208 disposed on the first fluid channel 1202. The first flow meter 1207 monitors the coolant flow rate in the first fluid channel 1202. The sight glass 1208 allows for observation of normal coolant flow within the first fluid channel 1202. The fluid circuit system 12 may further include a second flow meter 1209 disposed on the second fluid channel 1203. The second flow meter 1209 monitors the coolant flow rate in the second fluid channel 1203.

[0047] Continuing with FIG. 2 , the fluid circuit system 12 may further include a shutoff valve 1210 disposed on the first fluid channel 1202. The shutoff valve 1210 can control the opening and closing of the first fluid channel 1202. The fluid circuit system 12 may further include a flow valve 1211 disposed on the first fluid channel 1202. The flow valve 1211 regulates the flow of coolant from the first fluid channel 1202 into the heat dissipation cavity 111, thereby ensuring that the coolant flow into the heat dissipation cavity 111 meets the heat dissipation requirements of the chip 112.

[0048] Continuing with FIG. 2 , the fluid system 12 may further include a pressure protector 1212 in communication with the portion of the first fluid channel 1202 proximal to the chip package structure 11. The pressure protector 1212 can compensate for or reduce the pressure of the coolant within the first fluid channel 1202, thereby ensuring a relatively constant hydraulic pressure flowing to the chip package structure 11. This ensures that the coolant flow rate and volume meet the heat dissipation requirements of the chip 112 while preventing damage to the chip package structure 11 caused by excessive hydraulic pressure.

[0049] 2 , the liquid circuit system 12 may further include a filter 1213 disposed on the first liquid flow channel 1202. Impurities mixed in the circulating coolant are filtered through the filter 1213 to prevent the impurities from entering the heat dissipation cavity 111, thereby preventing the impurities from being deposited in the heat dissipation cavity 111 and affecting the heat dissipation effect.

[0050] Continuing with FIG2 , the fluid system 12 may also include a preheater 1214 disposed on the first fluid channel 1202. When the board is operating at a relatively low temperature, the liquid within the fluid system 12 may freeze. In this case, the preheater 1214 preheats the coolant to prevent freezing and ensure that the coolant can flow to the heat dissipation cavity 111 for heat dissipation.

[0051] 2 , the liquid circuit system 12 may further include a refrigerator 1215 disposed on the second liquid flow channel 1203. When the coolant absorbs heat and flows through the second liquid flow channel 1203 to the refrigerator 1215, the refrigerator 1215 can cool the coolant, thereby lowering the temperature of the coolant that flows again through the coolant tank 1201 and the first liquid flow channel 1202 to the heat dissipation cavity 111, thereby improving the heat dissipation effect.

[0052] The structure of the chip packaging structure 11 is described in detail below with examples. In some embodiments of the present application, the chip packaging structure 11 may include a packaging substrate 113, a heat dissipation cover 114 disposed on the packaging substrate 113, and a chip 112 as shown in FIG3 . The heat dissipation cover 114 and the packaging substrate 113 enclose a heat dissipation cavity 111. The chip 112 is located in the heat dissipation cavity 111, and the liquid path system 12 (as shown in FIG2 ) passes the coolant into the heat dissipation cavity 111. After absorbing the heat dissipated by the chip 112, the coolant flows back to the liquid path system 12, thereby completing the heat dissipation of the chip 112.

[0053] In related technologies, the heat sink cover is bonded to the organic polymer surrounding the chip. However, during chip operation, the temperature of the coolant surrounding the chip is generally higher than room temperature. In a warm coolant environment, the organic polymer ages, deforming or cracking. Deformation or cracking at the connection between the organic polymer and the heat sink cover creates a gap between the organic polymer and the heat sink cover, which in turn degrades the sealing performance of the connection between the heat sink cover and the organic polymer, leading to coolant leakage at this location.

[0054] To address the above-mentioned issues, as further shown in FIG3 , the chip package structure 11 may further include a sealing structure 115 disposed on the package substrate 113. At least a portion of the sealing structure 115 is located within the heat dissipation cavity 111. The sealing structure 115 is disposed around the periphery of the chip 112 and is connected to the chip 112. The sealing structure 115 is also sealed to the heat dissipation cover 114, and the portion A where the sealing structure 115 and the heat dissipation cover 114 are sealed is made of a metal material or an inorganic non-metallic material. Both metal and inorganic non-metallic materials are not susceptible to aging, thus preventing deformation or surface cracking of the portion where the sealing structure 115 and the heat dissipation cover 114 are sealed. This prevents the formation of gaps between the sealing structure 115 and the heat dissipation cover 114, ensuring the sealing performance of the connection between the heat dissipation cover 114 and the sealing structure 115. This prevents coolant from leaking between the sealing structure 115 and the heat dissipation cover 114. This improves the sealing reliability of the chip package structure 11 and prevents coolant leakage.

[0055] As can be seen from the above, the portion A where the sealing structure 115 is sealed and connected to the heat dissipation cover 114 is made of a metal material or an inorganic non-metallic material. The portion of the sealing structure 115 that is sealed and connected to the heat dissipation cover 114 is described below by way of example. In some embodiments of the present application, as shown in FIG4 , the sealing structure 115 may include a first annular structure 1151. The first annular structure 1151 is sealed and connected to the heat dissipation cover 114 so that the coolant cannot pass through the connection between the first annular structure 1151 and the heat dissipation cover 114. In addition, the first annular structure 1151 is made of a metal material or an inorganic non-metallic material. At this point, the first annular structure 1151 is not prone to aging, thus avoiding deformation or surface cracking due to material aging, which would cause a gap between the sealing structure 115 and the heat dissipation cover 114, thereby causing the coolant to leak from the gap. This is to achieve the purpose of improving the sealing reliability of the chip packaging structure 11 and preventing coolant leakage.

[0056] Continuing with FIG4 , the sealing structure 115 may further include a second annular structure 1152. The second annular structure 1152 is located within the hollow region of the first annular structure 1151, and the chip 112 is located within the hollow region of the second annular structure 1152. The side of the second annular structure 1152 facing the chip 112 is connected to the chip 112, and the side of the second annular structure 1152 facing away from the chip 112 is connected to the first annular structure 1151. That is, the first annular structure 1151, the second annular structure 1152, and the chip 112 are nested in sequence, and the first annular structure 1151, the second annular structure 1152, and the chip 112 are relatively fixed to ensure the connection stability between the first annular structure 1151, the second annular structure 1152, and the chip 112.

[0057] Exemplarily, the second annular structure 1152 shown in FIG4 is an injection molded structure. In some embodiments of the present application, the first annular structure 1151 and the chip 112 can be respectively arranged on the packaging substrate 113. Then, the second annular structure 1152 is injection-molded between the first annular structure 1151 and the chip 112, so that the first annular structure 1151 and the second annular structure 1152 can be connected as an integral structural member. At this time, the second annular structure 1152 can fill the gap between the first annular structure 1151 and the chip 112 to ensure that there is no gap between the second annular structure 1152 and the chip 112, and between the first annular structure 1151 and the second annular structure 1152. To ensure the sealing performance between the first annular structure 1151, the second annular structure 1152 and the chip 112, to prevent leakage of the coolant.

[0058] Furthermore, in order to ensure the sealing performance between the first annular structure 1151 and the second annular structure 1152, and between the second annular structure 1152 and the chip 112. In some embodiments of the present application, a glue layer (not shown in the figure) can be set between the first annular structure 1151 and the second annular structure 1152 as shown in Figure 4 by dispensing glue. A glue layer can also be set between the second annular structure 1152 and the chip 112 by dispensing glue. Thereby achieving the purpose of preventing the leakage of the coolant. In addition, a glue layer (not shown in the figure) can also be set between the first annular structure 1151 and the packaging substrate 113. Ensure that the first annular structure 1151 and the packaging substrate 113 are relatively fixed.

[0059] On this basis, to ensure the sealing performance between the first annular structure 1151 and the heat dissipation cover 114, as shown in FIG4 , the chip package structure 11 may further include a sealing ring 116. The sealing ring 116 is disposed between the first annular structure 1151 and the heat dissipation cover 114. In this case, the first annular structure 1151 can be sealed to the heat dissipation cover 114 via the sealing ring 116, ensuring the sealing performance between the first annular structure 1151 and the heat dissipation cover 114 and preventing the coolant from leaking from between the first annular structure 1151 and the heat dissipation cover 114.

[0060] In the above embodiment, as shown in FIG4 , a sealed connection between the first annular structure 1151 and the heat dissipation cover 114 is achieved by disposing a single sealing ring 116 between the first annular structure 1151 and the heat dissipation cover 114. In other embodiments of the present application, a sealed connection between the first annular structure 1151 and the heat dissipation cover 114 can also be achieved by disposing multiple sealing rings 116 between the first annular structure 1151 and the heat dissipation cover 114. Alternatively, a sealed connection between the first annular structure 1151 and the heat dissipation cover 114 can also be achieved by applying a sealant between the first annular structure 1151 and the heat dissipation cover 114.

[0061] Furthermore, as shown in FIG5 , the first annular structure 1151 may include a first annular portion 11511 and a first extension portion 11512 . The first annular portion 11511 is connected to the second annular structure 1152 on the side facing the chip 112 . This ensures that the first annular structure 1151 and the second annular structure 1152 are connected. The first annular portion 11511 is also sealed to the heat dissipation cover 114 , ensuring that coolant does not leak between the first annular portion 11511 and the heat dissipation cover 114 . Furthermore, the first annular portion 11511 and the first extension portion 11512 are both disposed on the package substrate 113 . The first extension portion 11512 is located on the side of the first annular portion 11511 away from the chip 112. The first annular portion 11511 is connected to the first extension portion 11512, and the first annular portion 11511 and the first extension portion 11512 are both connected to the packaging substrate 113, thereby increasing the connection area between the first annular structure 1151 and the packaging substrate 113, and improving the connection reliability between the first annular structure 1151 and the packaging substrate 113.

[0062] Continuing with FIG. 5 , in some embodiments of the present application, the first annular portion 11511 and the first extension portion 11512 may be an integral structural member. For example, during the production process of the first annular portion 11511 and the first extension portion 11512, the first annular portion 11511 and the first extension portion 11512 may be simultaneously molded in a single mold to form the interconnected, integral first annular portion 11511 and the first extension portion 11512. An integral structural member provides greater structural stability, ensuring a stable internal structure of the first annular structure 1151.

[0063] Continuing with FIG5 , the second annular structure 1152 may include a second annular portion 11521 and a second extension portion 11522. The second annular portion 11521 is disposed on the package substrate 113 and connected to the package substrate 113. The side of the second annular portion 11521 facing away from the chip 112 is connected to the first annular structure 1151, while the side of the second annular portion 11521 facing toward the chip 112 is connected to the chip 112. The second extension portion 11522 is located on the side of the second annular portion 11521 facing away from the package substrate 113 and is connected to the first annular structure 1151. In this case, both the second annular portion 11521 and the second extension portion 11522 are connected to the first annular structure 1151, thereby increasing the connection area between the second annular structure 1152 and the first annular structure 1151 and improving the connection reliability between the second annular structure 1152 and the first annular structure 1151.

[0064] Continuing with FIG. 5 , in some embodiments of the present application, the second annular portion 11521 and the second extension portion 11522 may be integrally molded components. The first annular structure 1151 and the chip 112 may be separately disposed on the package substrate 113. Then, the second annular portion 11521 and the second extension portion 11522 are formed by injection molding between the first annular structure 1151 and the chip 112 in a single operation. This ensures that there is no gap between the first annular structure 1151, the second annular portion 11521, the second extension portion 11522, and the chip 112. This ensures sealing performance between the first annular structure 1151, the second annular portion 11521, the second extension portion 11522, and the chip 112, preventing coolant leakage.

[0065] In related art, the connection between the heat dissipation cover 114 and other structures is parallel to the surface of the chip 112 facing away from the packaging substrate 113. During operation, the hydraulic pressure in the heat dissipation chamber 111 is high, and the coolant will exert a force on the top cover 1141 and the side 1142. When the heat dissipation cover 114 is subjected to a force perpendicular to the surface of the chip 112 toward the heat dissipation chamber 111 due to the hydraulic pressure of the heat dissipation chamber 111, only the connection force at the connection can counteract the force generated by the hydraulic pressure. In this case, the connection force at the connection is less than the force generated by the hydraulic pressure, which can easily cause a gap in the connection and lead to coolant leakage.

[0066] In order to solve the above-mentioned problem, as shown in Figure 5, the above-mentioned heat dissipation cover 114 may include a top cover 1141 and a side portion 1142. The side portion 1142 is located on the side of the top cover 1141 facing the packaging substrate 113 and is connected to the top cover 1141. The inner side wall of the side portion 1142 is connected to the sealing structure 115. At this time, the connection position between the heat dissipation cover 114 and the sealing structure 115 is located on the inner side wall of the side portion 1142. When the heat dissipation cover 114 is subjected to a force perpendicular to the surface of the chip 112 facing the heat dissipation cavity 111 due to the hydraulic pressure of the heat dissipation cavity 111, the connection force at the connection between the inner side wall of the side portion 1142 and the sealing structure 115 and the friction force between the inner side wall of the heat dissipation cover 114 and the sealing structure 115 can prevent the heat dissipation cover 114 and the sealing structure 115 from detaching and generating a gap, thereby preventing the coolant from leaking. When the heat dissipation cover 114 is subjected to a force parallel to the surface of the chip 112 toward the heat dissipation cavity 111 due to the hydraulic pressure of the heat dissipation cavity 111, the forces between the inner walls of the side portions 1142 in symmetrical positions are in opposite directions and thus offset each other, thereby preventing the heat dissipation cover 114 and the sealing structure 115 from detaching due to excessive force and creating a gap, thereby avoiding coolant leakage.

[0067] Continuing with FIG5 , the top cover 1141 of the heat dissipation cover 114 is provided with an ejection hole 1143 and a return hole 1144 that communicate with the heat dissipation cavity 111. The fluid circuit system 12 (shown in FIG2 ) directs coolant into the heat dissipation cavity 111 through the ejection hole 1143. After absorbing heat, the coolant then flows back into the fluid circuit system 12 through the return hole 1144, completing the heat dissipation process for the chip 112.

[0068] Furthermore, as shown in FIG5 , the distance h between the outlet end of the jet hole 1143 facing the chip 112 and the chip 112 is, where 0<h≤1mm. For example, the distance h between the outlet end of the jet hole 1143 facing the chip 112 and the chip 112 is 0.1mm, 0.2mm, 0.4mm, 0.6mm, 0.8mm, 1mm, etc. The distance h between the outlet end of the jet hole 1143 facing the chip 112 and the chip 112 is greater than 0, ensuring that after the coolant flows from the jet hole 1143 into the heat dissipation cavity 111, it can flow through the gap between the heat dissipation cover 114 and the chip 112 to the return hole 1144, and finally flow out of the heat dissipation cavity 111.

[0069] In addition, the coolant ejected from the jet hole 1143 will produce a flow velocity change under the action of gravity. When the flow direction of the coolant ejected from the jet hole 1143 is toward the ground, the flow velocity of the coolant will gradually increase. At this time, if h>1mm, the flow velocity of the coolant will increase significantly, which will in turn have a greater impact on the chip 112, which may cause damage to the chip 112. When the flow direction of the coolant ejected from the jet hole 1143 is away from the ground, the flow velocity of the coolant will gradually decrease. At this time, if h>1mm, the flow velocity of the coolant will decrease significantly, and it may not be able to directly impact the chip 112, affecting the heat dissipation effect of the chip 112. When the flow direction of the coolant ejected from the jet hole 1143 is parallel to the ground, the flow direction of the coolant will gradually change toward the ground. If h>1mm, the flow direction of the coolant will change significantly, resulting in the coolant being unable to directly impact the part of the chip 112 away from the ground, resulting in poor heat dissipation effect of the part of the chip 112 away from the ground and uneven heat dissipation of the chip 112.

[0070] Therefore, when the distance h from the outlet end of the jet hole 1143 toward the chip 112 to the chip 112 is less than or equal to 1 mm, the flow rate of the coolant flowing out of the jet hole 1143 changes little. Therefore, the coolant flow rate will not be too high due to the effect of gravity, which will cause a large impact force on the chip 112. This prevents the chip 112 from being damaged due to excessive impact force. Alternatively, the coolant flow rate will not be too low due to the effect of gravity, and the injected coolant cannot directly impact the chip 112. This ensures the heat dissipation effect of the chip 112. Alternatively, the coolant flow direction will not change too much due to the effect of gravity. This prevents the part of the chip 112 that is away from the ground from being impacted by the coolant, ensuring uniform heat dissipation of all parts of the chip 112.

[0071] In some embodiments of the present application, as shown in Figure 5, the chip packaging structure 11 may further include a fixing plate 117. The fixing plate 117 is arranged on the side of the packaging substrate 113 facing away from the chip 112, and the fixing plate 117 is connected to the packaging substrate 113, and the heat dissipation cover 114 is connected to the fixing plate 117. The packaging substrate 113 and the heat dissipation cover 114 are both connected to the fixing plate 117. The fixing plate 117 can support the packaging substrate 113 and the heat dissipation cover 114, thereby ensuring the structural stability of the chip packaging structure 11. In addition, the sealing structure 115 can be connected to the packaging substrate 113, the packaging substrate 113 is connected to the fixing plate 117, and the fixing plate 117 is connected to the heat dissipation cover 114, thereby ensuring that the sealing structure 115 can be connected to the heat dissipation cover 114. At the same time, after the heat dissipation cover 114 is connected to the fixing plate 117, a force is generated on the heat dissipation cover 114 to approach the fixing plate 117, thereby causing the sealing ring 116 between the heat dissipation cover 114 and the sealing structure 115 to be in a compressed state to ensure the sealing performance between the heat dissipation cover 114 and the sealing structure 115.

[0072] In the related art, the heat dissipation cover 114 is connected to the organic polymer on the side of the chip 112, and the organic polymer is bonded to the packaging substrate 113 and fixedly connected to the chip 112. In normal operation, after the heat dissipation cover 114 is subjected to hydraulic force, it will generate a large force on the packaging substrate 113 and the chip 112 through the organic polymer. When the force is large, it may affect the working performance of the packaging substrate 113 and the chip 112. In the chip packaging structure 11 provided in the embodiment of the present application, after the heat dissipation cover 114 is connected to the fixing plate 117, the connection force directly acts on the fixing plate 117. This avoids generating a large force on the packaging substrate 113 and the chip 112, and improves the reliability of the chip packaging structure 11.

[0073] For example, as shown in FIG5 , the chip package structure 11 may further include a connector 118. The heat dissipation cover 114 is connected to the fixing plate 117 via the connector 118. In some embodiments of the present application, the connector 118 is a screw or bolt. The screw or bolt passes through a connection hole provided in the fixing plate 117 and is threadedly connected to a threaded hole provided in the heat dissipation cover 114. Alternatively, the connector 118 is a pin. The pin passes through a connection hole provided in the fixing plate 117 and is interference-fitted with a pin hole provided in the heat dissipation cover 114.

[0074] Alternatively, in other embodiments of the present application, the heat dissipation cover 114 and the fixing plate 117 in Figure 5 can also be connected by bolts (not shown in the figure) and nuts (not shown in the figure), and the bolts pass through the connection holes opened on the fixing plate 117 and the through holes (not shown in the figure) opened on the heat dissipation cover 114 in sequence and are threadedly connected to the nuts arranged on the side of the heat dissipation cover 114 away from the fixing plate 117.

[0075] Of course, as shown in FIG. 5 , the sealing structure 115 and the heat dissipation cover 114 may also be directly bonded to ensure that the sealing structure 115 and the heat dissipation cover 114 are relatively fixed.

[0076] Furthermore, as shown in FIG. 5 , in some embodiments of the present application, the chip package structure 11 further includes a circuit board 119. The fixing plate 117, the circuit board 119, and the package substrate 113 are stacked in sequence. The circuit board 119 is electrically connected to the chip 112 and to other components on the board. The circuit board 119 can transmit signals between the chip 112 and other components.

[0077] In related art, chip 112 is bonded to an organic polymer disposed around the chip 112. Direct contact with the coolant causes the organic polymer to age, resulting in deformation or surface cracking. Deformation or cracking at the connection between the organic polymer and chip 112 can create a gap between the organic polymer and chip 112, degrading the sealing performance of the connection between the chip 112 and the organic polymer, which can lead to coolant leakage at this location.

[0078] To address the above issues, as shown in FIG6 , the chip package structure 11 may further include a waterproof layer 120 located within the heat dissipation cavity 111. The waterproof layer 120 is located on the side of the chip 112 facing away from the package substrate 113. The waterproof layer 120 covers at least the connection between the sealing structure 115 and the chip 112. In this case, the waterproof layer 120 prevents the connection between the sealing structure 115 and the chip 112 from direct contact with the coolant, thereby preventing aging of the portion of the sealing structure 115 facing the chip 112, which in turn prevents the sealing performance of this portion from being affected by material aging. This improves the sealing reliability of the chip package structure 11 and prevents coolant leakage.

[0079] Furthermore, as shown in FIG7 , the waterproof layer 120 may also cover the connection between the first annular structure 1151 and the second annular structure 1152. In this case, the waterproof layer 120 can also prevent the coolant from entering the connection between the first annular structure 1151 and the second annular structure 1152, further improving the sealing performance of the connection between the first annular structure 1151 and the second annular structure 1152 and preventing coolant leakage.

[0080] On this basis, as shown in FIG8 , a waterproof layer 120 can cover the surface of the chip 112 facing away from the package substrate 113. In this case, the waterproof layer 120 can prevent moisture in the heat dissipation cavity 111 from penetrating the chip 112 and entering the package substrate 113, thereby affecting the normal operation of the circuits arranged on the package substrate 113.

[0081] In some embodiments of the present application, as further shown in FIG8 , waterproof layer 120 may also cover the surface of second annular structure 1152. When second annular structure 1152 is made of an organic material, waterproof layer 120 can prevent the entire second annular structure 1152 from coming into direct contact with the coolant, further preventing aging of second annular structure 1152 that could affect sealing performance. Furthermore, waterproof layer 120 can prevent moisture within heat dissipation cavity 111 from penetrating second annular structure 1152 and entering packaging substrate 113, potentially impacting the proper operation of the circuitry arranged thereon.

[0082] In other embodiments of the present application, as shown in Figure 9, the waterproof layer 120 can cover the side surface of the sealing structure 115 facing away from the packaging substrate 113. The side surface of the sealing structure 115 facing away from the packaging substrate 113 refers to all other surfaces of the sealing structure 115 except the side surface of the sealing structure 115 facing the packaging substrate 113 and the side end face of the sealing structure 115 facing the chip 112. At this time, the waterproof layer 120 can achieve the same technical effect as the embodiment shown in Figure 8. In addition, during the packaging process, after the sealing structure 115 and the chip 112 are assembled onto the packaging substrate 113, the waterproof layer 120 can be plated or coated on the side surface of the assembly structure of the sealing structure 115 and the chip 112 facing away from the packaging substrate 113 at one time, so as to facilitate the plating or coating of the waterproof layer 120.

[0083] In any of the embodiments shown in Figures 6, 7, 8, or 9, the waterproof layer 120 may include at least one of a metal plating layer or an inorganic coating layer. For example, the waterproof layer 120 includes at least one of a copper plating layer, a nickel plating layer, a chromium plating layer, a glassy coating, a ceramic coating, a metal-ceramic coating, or an intermetallic compound coating. Both the metal plating layer and the inorganic coating layer are resistant to aging, ensuring the waterproof layer 120's aging resistance when immersed in warm coolant, and preventing degradation of the waterproof layer 120's waterproof performance due to aging.

[0084] 6, 7, 8 or 9, the chip packaging structure 11 is taken as an example to include one waterproof layer 120. In other embodiments of the present application, the number of waterproof layers 120 can be other numbers.

[0085] Furthermore, in any of the embodiments shown in Figures 6, 7, 8, or 9, the thickness of the waterproof layer 120 can be between 5 μm and 100 μm. Exemplary thicknesses include 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, and 100 μm. A thickness of 5 μm or greater ensures the rigidity of the waterproof layer 120 and prevents cracks in the waterproof layer 120, which could lead to coolant entering the side of the waterproof layer 120 facing the package substrate 113. This, in turn, prevents the portion of the sealing structure 115 facing the chip 112 from coming into direct contact with the coolant and causing degradation, which could compromise sealing performance. Alternatively, the thickness of the waterproof layer 120 is less than or equal to 100 μm. This ensures the rigidity of the waterproof layer 120 while reducing its cost.

[0086] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip packaging structure, characterized in that, Comprising: An encapsulation substrate; A heat dissipation cover, covering the encapsulation substrate, and a heat dissipation cavity is defined between the heat dissipation cover and the encapsulation substrate; A chip, located in the heat dissipation cavity, and the chip is disposed on the encapsulation substrate; A sealing structure, at least a part of which is located in the heat dissipation cavity, and the sealing structure is disposed on the encapsulation substrate; the sealing structure is disposed around the periphery of the chip and is connected to the chip; the sealing structure is also hermetically connected to the heat dissipation cover, and the part of the sealing structure hermetically connected to the heat dissipation cover is made of a metal material or an inorganic non-metallic material.

2. The chip packaging structure according to claim 1, wherein The sealing structure includes: A first annular structure, hermetically connected to the heat dissipation cover, and the first annular structure is made of a metal material or an inorganic non-metallic material; A second annular structure, located in the hollow region of the first annular structure, and the chip is located in the hollow region of the second annular structure; the side of the second annular structure facing the chip is connected to the chip, and the side of the second annular structure facing away from the chip is connected to the first annular structure.

3. The chip packaging structure according to claim 2, characterized in that, The chip packaging structure further includes: A sealing ring, disposed between the first annular structure and the heat dissipation cover, and the first annular structure is hermetically connected to the heat dissipation cover through the sealing ring.

4. The chip packaging structure according to claim 2, wherein, The first annular structure includes: A first annular portion, disposed on the encapsulation substrate and connected to the encapsulation substrate; the side of the first annular portion facing the chip is connected to the second annular structure; the first annular portion is also hermetically connected to the heat dissipation cover; A first extension portion, disposed on the encapsulation substrate and located on the side of the first annular portion facing away from the chip, and the first extension portion is connected to the encapsulation substrate; the side of the first extension portion facing the chip is connected to the first annular portion.

5. The chip packaging structure according to claim 2, wherein, The second annular structure includes: A second annular portion, disposed on the encapsulation substrate and connected to the encapsulation substrate; the side of the second annular portion facing away from the chip is connected to the first annular structure, and the side of the second annular portion facing the chip is connected to the chip; A second extension portion, located on the side of the second annular portion facing away from the encapsulation substrate, and the second extension portion is connected to the first annular structure.

6. The chip packaging structure according to any one of claims 1-5, characterized in that The heat dissipation cover includes: A top cover; A side portion, located on the side of the top cover facing the encapsulation substrate and connected to the top cover; the inner side wall of the side portion is connected to the sealing structure.

7. The chip package structure according to any one of claims 1-5, characterized in that, The chip packaging structure further includes: A waterproof layer, located in the heat dissipation cavity, on the side of the chip facing away from the encapsulation substrate, and the waterproof layer at least covers the connection portion between the sealing structure and the chip.

8. The chip packaging structure according to claim 7, characterized in that The waterproof layer covers the surface of the side of the chip facing away from the encapsulation substrate, and the waterproof layer also covers the surface of the side of the sealing structure facing away from the encapsulation substrate.

9. The chip packaging structure according to claim 7, wherein The waterproof layer includes at least one of a metal coating or an inorganic coating.

10. The chip packaging structure according to claim 7, characterized in that, The thickness of the waterproof layer is 5μm to 100μm.

11. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes: A fixing plate, the fixing plate is arranged on a side of the encapsulation substrate away from the chip, and the fixing plate is connected to the encapsulation substrate, and the heat dissipation cover is connected to the fixing plate.

12. The chip packaging structure according to claim 1, wherein, Jet holes and return holes communicating with the heat dissipation cavity are formed in the heat dissipation cover.

13. The chip packaging structure according to claim 12, wherein, The distance from the outlet end of the jet hole facing the chip to the chip is h; where 0 < h ≤ 1 mm.

14. A single board, characterized in that, Comprising: The chip packaging structure according to any one of claims 1-13; A liquid path system, connected to the heat dissipation cover of the chip packaging structure, and the liquid path system is communicated with the heat dissipation cavity.

15. A network device, characterized in that, Comprising: The single board according to claim 14; A cabinet, the single board is arranged in the cabinet and connected to the cabinet.

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