Memory

Abstract

Provided in the present application is a memory. The memory comprises a memory array chip and a logic circuit chip, which are bonded together. Each memory array tile corresponds to at least one row decoder, one secondary decoder and at least one sub-wordline driver, each row decoder provides a first number of main word lines, the secondary decoder provides a second number of secondary word lines, and the product of the total number of main decoding signals of all row decoders corresponding to a single memory array tile and the second number is the same as the number of word lines of a single memory array tile; the sub-wordline driver is used for driving word lines of a corresponding memory array tile on the basis of main decoding signals and secondary decoding signals, and the total number of driving ports of all sub-wordline drivers corresponding to a single memory array tile is the same as the number of word lines of the memory array tile; and the row decoder, the secondary decoder and the sub-wordline driver are all arranged in the logic circuit chip. The apparatus of the present application can reduce the delay from a row decoder to a sub-wordline driver, optimize timing and sensing slacks of a memory, and reduce the wiring difficulty of main word lines.

Description

Memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 29, 2023, with application number 202311872679.9 and application name “Memory”, and the Chinese patent application filed with the China Patent Office on August 19, 2024, with application number 202411141107.8 and application name “Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to semiconductor technology, and in particular to a memory. Background Art

[0003] A semiconductor memory device includes multiple memory array tiles (MATs), each of which includes memory cells arranged in an array. To read information from the memory, the memory cell address code corresponding to the desired information must be obtained. The corresponding memory cell row code is then read based on the memory cell address code, and the corresponding word line (WL) is activated based on the memory cell row code. Once the word line is activated, the memory cells connected to the word line are in a readable and writable state. Correspondingly, the memory is provided with a row decoder (Row Decoder or X-Decoder, abbreviated as X-DEC), a sub-decoder (FX) and a sub-wordline driver (SWD). The row decoder is used to generate a main decoding signal according to the first part of the memory cell address code and transmit it to the word line driver through the main decoding signal line (Main Word Line). The sub-decoder is used to generate a sub-decoding signal according to the second part of the memory cell address code and transmit it to the word line driver through the sub-decoding signal line. The word line driver is connected to the row decoder, the sub-decoder and the word line, and is used to drive the corresponding word line according to the main decoding signal and the sub-decoding signal.

[0004] In actual applications, since the main decoding signal line needs to be connected to the word line driver corresponding to each memory block, the main decoding signal line needs to cross the entire memory segment (Section), resulting in an excessively long wiring length. As a result, the delay of the main decoding signal output by the row decoder to each memory block is different, the timing uniformity is poor, and the performance of the memory is reduced. In addition, there are a large number of main decoding signals. For each main decoding signal, a main decoding signal line is required to transmit it from the row decoder to the word line driver. As the area of ​​semiconductor memory devices decreases and most memories use planar processes, the width and spacing of the main decoding signal lines are limited, resulting in increased difficulty in wiring the main decoding signal lines.

[0005] Summary of the Invention

[0006] The present application provides a memory for reducing the delay between a row decoder and a word line driver, optimizing the timing and sensing margin of the memory, and reducing the wiring difficulty of a main decoding signal line.

[0007] On the one hand, the present application provides a memory, comprising: a bonded memory array chip and a logic circuit chip, wherein the logic circuit chip is located above the memory array chip, and the memory array chip is provided with a plurality of memory segments arranged in an array, each memory segment including a plurality of memory blocks; wherein,

[0008] Each memory block corresponds to at least one row decoder, each row decoder providing a first number of primary decoding signal lines for transmitting primary decoding signals; each memory segment corresponds to a secondary decoder, the secondary decoder providing a second number of secondary decoding signal lines for transmitting secondary decoding signals; wherein the product of the sum of the number of primary decoding signals of all row decoders corresponding to a single memory block and the second number is equal to the number of word lines of the single memory block;

[0009] Each memory block corresponds to at least one word line driver, and the word line driver provides multiple driving ports for driving the word line of the corresponding memory block according to the primary decoding signal and the secondary decoding signal; wherein the total number of driving ports of all word line drivers corresponding to a single memory block is the same as the number of word lines of the memory block; wherein the row decoder, the secondary decoder and the word line driver are all arranged in the logic circuit chip.

[0010] In some examples, each storage block corresponds to four row decoders, and the positions corresponding to the four vertices of each storage block are respectively located in the areas where the four row decoders corresponding to the storage block are located in the projections of the logic circuit chip, and the four cross-adjacent storage blocks share the row decoders set at the positions corresponding to the central areas of the four storage blocks.

[0011] In some examples, row decoders set at positions corresponding to different vertices of a storage block correspond to different word line ranges; row decoders set at positions corresponding to the same vertex of two storage blocks separated by one storage block correspond to the same word line range.

[0012] In some examples, each memory segment includes a plurality of memory blocks sequentially arranged along a first direction.

[0013] In some examples, there are four wordline drivers for each memory block;

[0014] For the memory blocks that are not at the edge of each memory segment, each memory block is provided with two word line drivers within the projection area of ​​the logic circuit chip;

[0015] For the memory blocks at the edge of each memory segment, each memory block is provided with three word line drivers within the projection area of ​​the logic circuit chip.

[0016] In some examples, for a memory block that is not at an edge in each memory segment, each word line driver disposed in the memory block within a projection area of ​​the logic circuit chip is shared by the memory block and an adjacent memory block, and different word line drivers are shared by different adjacent memory blocks.

[0017] For the storage block at the edge of each storage segment, three word line drivers are set in the projection area of ​​the storage block of the logic circuit chip, one of which is shared by the storage block and the adjacent storage blocks of the storage block, and the remaining two word line drivers are only used to drive the word lines of the storage block.

[0018] In some examples, for a storage block that is not at the edge in each storage segment, each word line driver provided in the storage block within the projection area of ​​the logic circuit chip is located within the projection area, adjacent to one side of the projection area corresponding to the storage block that shares the word line driver.

[0019] In some examples, for memory blocks that are not at the edge in each memory segment, each word line driver is connected to main decoding signal lines of two adjacent row decoders, where the adjacent row decoders are row decoders shared by the memory block and the memory block that shares the word line driver.

[0020] In some examples, for a memory block at an edge in each memory segment, among the three word line drivers arranged in the memory block within the projection area of ​​the logic circuit chip, the word line driver shared by adjacent memory blocks is located within the projection area, adjacent to one side of the projection area corresponding to the adjacent memory block, and the remaining two word line drivers are located on the other side of the projection area.

[0021] In some examples, for the memory blocks at the edge of each memory segment, the word line driver shared by adjacent memory blocks is connected to the main decoding signal lines of the two row decoders shared by the memory block and the adjacent memory blocks; the remaining two word line drivers are connected to the main decoding signal lines of the remaining two row decoders corresponding to the memory block.

[0022] In some examples, each word line driver includes two sub-word line drivers, and the two sub-word line drivers have the same number of driving ports.

[0023] In some examples, the secondary decoding signal line is parallel to the first direction, and the primary decoding signal line is perpendicular to the first direction.

[0024] The present application provides a memory, which includes a bonded memory array chip and a logic circuit chip, wherein the logic circuit chip is located above the memory array chip, the memory block is arranged on the memory array chip, and the row decoder, sub-decoder, and word line driver are arranged on the logic circuit chip. Compared with a planar memory structure, the memory provides more circuit layout space and does not need to arrange the row decoder and word line driver outside the memory block, which can effectively reduce the length of the signal line, reduce the delay, and improve the performance of the memory. By providing at least one corresponding row decoder and at least one word line driver for each memory block, the word line of each memory block is controlled, wherein the product of the sum of the number of main decoding signals of all row decoders corresponding to a single memory block and a second number is equal to the number of word lines of the single memory block. This can effectively reduce the number of main decoding signal lines corresponding to the memory block, reduce the width and spacing restrictions on the main decoding signal lines, and reduce the difficulty of wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0026] FIG1 is a schematic diagram showing a structure of a memory;

[0027] FIG2 exemplarily shows a structural diagram of a memory provided by an embodiment of the present application;

[0028] FIG3 exemplarily shows a structural diagram of another memory provided by an embodiment of the present application;

[0029] FIG4 exemplarily shows a structural diagram of another memory provided by an embodiment of the present application;

[0030] FIG5 exemplarily shows a structural diagram of another memory provided by an embodiment of the present application;

[0031] FIG6 exemplarily shows a structural diagram of another memory provided by an embodiment of the present application;

[0032] FIG7 exemplarily shows a structural diagram of another memory provided by an embodiment of the present application;

[0033] FIG8 exemplarily shows a structural diagram of another memory provided by an embodiment of the present application;

[0034] FIG9 exemplarily shows a structural diagram of another memory provided by an embodiment of the present application;

[0035] FIG10 exemplarily shows a structural diagram of another memory provided by an embodiment of the present application.

[0036] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0037] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0038] First, let’s explain the terms involved in this application:

[0039] Wafer-on-wafer (WOW) structure: In the fabrication process of three-dimensional memory devices, two different wafers are typically bonded together to create a memory device, known as a wafer-on-wafer structure. The two wafers each contain different semiconductor structures. One wafer is called the memory array wafer, which includes the semiconductor structure of the memory cells used for storage; the other wafer is called the logic circuit wafer (CMOS wafer), also known as the complementary metal oxide semiconductor (CMOS) wafer. The logic circuit wafer includes the peripheral circuitry used to transmit signals to the memory cells. The fabricated memory array wafer and logic circuit wafer are then cut and packaged to produce memory array chips and logic circuit chips.

[0040] Memory block: Each memory block includes multiple memory cells arranged in an array, and each memory cell is connected to a word line and a bit line.

[0041] Bank: Each bank includes multiple memory segments, and each memory segment includes a row of memory blocks.

[0042] A semiconductor memory device includes multiple memory blocks, each of which includes memory cells arranged in an array. When reading information from the memory, it is necessary to obtain the memory cell address code corresponding to the information to be read, then read the corresponding memory cell row code based on the memory cell address code, and activate the corresponding word line based on the memory cell row code. After the word line is activated, the memory cells connected to the word line are in a readable and writable state. Accordingly, the memory is provided with a row decoder, a secondary decoder, and a word line driver. The row decoder is used to generate a primary decoding signal based on the first part of the memory cell address code, and the secondary decoder is used to generate a secondary decoding signal based on the second part of the memory cell address code. The word line driver is connected to the row decoder, the secondary decoder, and the word line, and is used to drive the corresponding word line based on the primary decoding signal and the secondary decoding signal.

[0043] In actual applications, the main decoding signal line needs to cross the entire storage segment and connect to each storage block. The unilateral arrangement of the row decoder causes the row decoder wiring length to be too long. Therefore, the delay of the main decoding signal output by the row decoder to each storage block is different. The word line driver corresponding to the storage block close to the row decoder and the word line driver corresponding to the storage block far away from the row decoder receive the main decoding signal. The delay difference is too large, resulting in poor timing uniformity; the number of main decoding signals is large, and for each main decoding signal, a main decoding signal line is required to transmit it from the row decoder to the word line driver. As the area of ​​semiconductor memory devices decreases, the width and spacing of the main decoding signal lines are limited, resulting in wiring difficulties.

[0044] The following specific embodiments illustrate the technical solutions of the present application. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The following embodiments of the present disclosure are described in conjunction with the accompanying drawings.

[0045] Figure 1 is a schematic diagram of the structure of an exemplary memory device. The memory device shown in Figure 1 utilizes a planar process. Each memory segment comprises multiple sequentially arranged memory blocks, each of which includes a special ECC (Error Checking and Correcting) feature whose size is half that of other memory blocks. Each memory segment is provided with a row decoder and two sub-decoders on either side, and each memory block is flanked by a wordline driver.

[0046] The row decoder generates n1 primary decoding signals based on the first portion of the memory cell address code and transmits them to each wordline driver via n1 primary decoding signal lines that pass through the memory segment. The secondary decoder generates n2 secondary decoding signals based on the second portion of the memory cell address code and transmits them to each wordline driver via n2 secondary decoding signal lines that pass through the memory segment. Each memory block corresponds to n1*n2*2 wordlines, controlled by two wordline drivers located on either side of the block.

[0047] In practical applications, the number of main decoding signals often exceeds the number of sub-decoding signals. For example, assuming a memory block size of 1kB, n1 can be 128 and n2 can be 8, requiring 128 main decoding signal lines for each memory block. This approach, however, limits the width and spacing of the main decoding signal lines, making routing difficult. Furthermore, because the row decoder is located on one side of a memory segment and needs to provide main decoding signals to each wordline driver corresponding to that segment, the worst-case transmission path from the row decoder to the wordline driver has a significant transmission delay. Furthermore, there is a significant delay difference between the optimal and worst-case transmission paths, impacting memory timing and performance.

[0048] Some aspects of the embodiments of the present disclosure relate to the above considerations. The following describes the solutions with reference to some embodiments.

[0049] A memory provided by an embodiment of the present application includes: a bonded memory array chip and a logic circuit chip, wherein the logic circuit chip is located above the memory array chip, and the memory array chip is provided with a plurality of memory segments arranged in an array, each memory segment including a plurality of memory blocks; wherein,

[0050] Each memory block corresponds to at least one row decoder, each row decoder provides a first number of primary decoding signal lines, the primary decoding signal lines being used to transmit primary decoding signals; each memory segment corresponds to a secondary decoder, the secondary decoder provides a second number of secondary decoding signal lines, the secondary decoding signal lines being used to transmit secondary decoding signals; wherein the product of the sum of the number of primary decoding signals of all row decoders corresponding to a single memory block and the second number is equal to the number of word lines of the single memory block;

[0051] Each memory block corresponds to at least one word line driver, which provides multiple drive ports for driving the word lines of the corresponding memory block according to the primary decoding signal and the secondary decoding signal; wherein the total number of drive ports of all word line drivers corresponding to a single memory block is the same as the number of word lines of the memory block; wherein the row decoder, secondary decoder and word line driver are all arranged on the logic circuit chip.

[0052] In practical applications, the memory structure provided in this embodiment can be applied to various types of memories. For example, it can be applied to dynamic random access memory (DRAM).

[0053] Specifically, the memory of this example includes a bonded memory array chip and a logic circuit chip, wherein the logic circuit chip is located above the memory array chip. The memory array chip is provided with a plurality of memory segments arranged in an array, wherein the memory segments include a plurality of memory blocks and may also be provided with some columnar capacitor (Ni-Cap) circuits. The logic circuit chip is provided with a row decoder, a sub-decoder, a word line driver, and may also be provided with a bit line sense amplifier (BLSA) and other peripheral (Peri) circuits. Compared with a planar memory structure, this structure provides more circuit layout space. There is no need to arrange the row decoder and word line driver outside the memory block. The distance between the row decoder and the word line driver, as well as the distance between the word line driver and the memory block can be shortened as needed, which is conducive to optimizing the signal transmission path from the row decoder to the word line driver and from the word line driver to the memory block word line, reducing signal transmission delay, and improving the performance of the memory.

[0054] FIG2 is a schematic diagram of the structure of a memory device according to an embodiment of the present application, which shows only a top view of the structure of a memory segment and its corresponding logic circuit. As shown in FIG2 , a memory segment includes multiple memory blocks 100, each of which corresponds to at least one row decoder 200. Each row decoder 200 provides a first number of primary decoding signal lines, through which primary decoding signals are transmitted to the word line driver 300 corresponding to the memory block. Each memory segment corresponds to a secondary decoder 400, which provides a second number of secondary decoding signal lines, through which secondary decoding signals are transmitted to the word line driver 300 corresponding to the memory block. Among them, the product of the sum of the number of primary decoding signals of all row decoders 200 corresponding to a single memory block 10 and the second number is the same as the number of word lines of a single memory block 100. Based on the sum of the primary decoding signals generated by all row decoders 200 corresponding to a single memory block 100 and the secondary decoding signals generated by the secondary decoders 400 corresponding to the single memory block 100, each word line in the memory block 100 can be controlled.

[0055] Control of the word lines of a memory block 100 is often achieved through a word line driver 300. In this example, each memory block 100 corresponds to at least one word line driver 300. Each word line driver 300 provides multiple drive ports for driving the word lines of the corresponding memory block 100 based on primary and secondary decoding signals. Different drive ports correspond to different word lines of the memory block 100. The total number of drive ports of all word line drivers 300 corresponding to a single memory block 100 is the same as the number of word lines in that memory block 100. Therefore, all word line drivers 300 corresponding to a single memory block 100 can drive all word lines of that memory block 100. By arranging that each memory block 100 corresponds to at least one row decoder 200 and at least one word line driver 300, the primary decoding signals required to control the word lines of each memory block 100 can be generated by multiple row decoders 200, and the word lines of the memory block 100 can be controlled by multiple word line drivers 300. This helps reduce the number of primary decoding signal lines and increases the flexibility of memory layout.

[0056] In this example, the memory includes a bonded memory array chip and a logic circuit chip, the logic circuit chip is located above the memory array chip, the memory block is arranged on the memory array chip, and the row decoder, sub-decoder and word line driver are arranged on the logic circuit chip, which can effectively reduce the length of the signal line, reduce the delay, and improve the performance of the memory; by providing at least one corresponding row decoder and at least one word line driver for each memory block, the control of the word line of each memory block is achieved, wherein the product of the sum of the number of main decoding signals of all row decoders corresponding to a single memory block and the second number is equal to the number of word lines of the single memory block, which can effectively reduce the number of main decoding signal lines corresponding to the memory block, reduce the width and spacing restrictions on the main decoding signal lines, and reduce the difficulty of wiring.

[0057] In actual applications, the number of row decoders corresponding to each storage block can be selected according to production needs. In one example, each storage block corresponds to four row decoders, and the projections of the positions corresponding to the four vertices of each storage block on the logic circuit chip are respectively located in the areas where the four row decoders corresponding to the storage block are located, and the four cross-adjacent storage blocks share the row decoders set at the positions corresponding to the central areas of the four storage blocks.

[0058] Specifically, each storage block corresponds to four row decoders, and these four row decoders are arranged around the storage block. The projections of the positions corresponding to the four vertices of each storage block on the logic circuit chip are respectively located in the areas where the four row decoders corresponding to the storage block are located. At the same time, in order to avoid repeated setting of row decoders, the row decoders can be shared by adjacent storage blocks. Every four cross-adjacent storage blocks share one row decoder. The row decoder is located in the center area of ​​the four cross-adjacent storage blocks within the projection area of ​​the logic circuit chip; wherein the four cross-adjacent storage blocks are arranged in a 2*2 array, and any two of the storage blocks are adjacent. In actual applications, the number of row decoders corresponding to each storage block can be selected according to production needs. Figure 3 is a structural schematic diagram of another memory provided by an embodiment of the present application, wherein Figure 3 is a top view of the memory. In actual applications, the storage block 100 is located at the storage array chip below, and the row decoder 200 is located at the logic circuit chip above. As shown in Figure 3, in one example, each storage block 100 corresponds to four row decoders 200. For example, the storage block MAT a1 corresponds to four row decoders X-DEC A1, X-DEC A2, X-DEC A4, and X-DEC A5. The projection areas of the four vertices of the storage block MAT a1 on the logic circuit chip are respectively located in the areas where the four row decoders X-DEC A1, X-DEC A2, X-DEC A4, and X-DEC A5 are located; and the four cross-adjacent storage blocks MAT a1, MAT a2, MAT a3, and MAT a4 share the row decoder X-DEC A5, and the row decoder X-DEC A5 is located at a position corresponding to the central area of ​​the four cross-adjacent storage blocks MAT a1, MAT a2, MAT a3, and MAT a4 as a whole.

[0059] Based on the above example, in order to enable the row decoders corresponding to each storage block to jointly generate the main decoding signal required to control the word line of the storage block, in one example, the row decoders set at the positions corresponding to different vertices of the storage block correspond to different word line ranges; the row decoders set at the positions corresponding to the same vertices of two storage blocks separated by one storage block correspond to the same word line range.

[0060] Specifically, the four row decoders corresponding to each memory block correspond to four word line ranges. Based on the word line ranges to which the row decoders correspond, the row decoders can be divided into four types: first row decoder, second row decoder, third row decoder, and fourth row decoder. Row decoders of the same type operate simultaneously, generating the same main decoding signal. To ensure that each memory block can correspond to four different row decoders, the different types of row decoders are arranged in an alternating arrangement. The row decoders corresponding to the same vertex of two memory blocks separated by one memory block correspond to the same word line range. The area where the row decoders corresponding to the vertex of a memory block are located includes the projection of the vertex's location on the logic circuit chip.

[0061] Figure 4 is a structural diagram of another memory provided in an embodiment of the present application. As shown in Figure 4, each storage block 100 is provided with four corresponding row decoders 200, specifically including a first row decoder X-DEC-1, a second row decoder X-DEC-2, a third row decoder X-DEC-3 and a fourth row decoder X-DEC-4. For the memory blocks MAT A and MAT C separated by one memory block MAT B, the projection of the upper left vertex of memory MAT A on the logic circuit chip is located in the area where the first row of decoders X-DEC-1 corresponding to memory MAT A is located, and correspondingly, the projection of the upper left vertex of memory MAT C on the logic circuit chip is located in the area where the first row of decoders X-DEC-1 corresponding to memory MAT C is located; similarly, the projection of the upper right vertex of memory MAT A on the logic circuit chip is located in the area where the second row of decoders X-DEC-2 corresponding to memory MAT A is located, and correspondingly, the projection of the upper right vertex of memory MAT C on the logic circuit chip is located in the area where the first row of decoders X-DEC-2 corresponding to memory MAT C is located; the projection of the lower left vertex of memory MAT A on the logic circuit chip is located in the area where the third row of decoders X-DEC-3 corresponding to memory MAT A is located, and correspondingly, the projection of the lower left vertex of memory MAT C on the logic circuit chip is located in the area where the third row of decoders X-DEC-3 corresponding to memory MAT C is located; memory MAT The projection of the lower right vertex of A on the logic circuit chip is located within the area where the fourth row of decoders X-DEC-4 corresponding to memory MAT A is located. Correspondingly, the projection of the lower right vertex of memory MAT C on the logic circuit chip is located within the area where the fourth row of decoders X-DEC-4 corresponding to memory MAT C is located. The same applies to memory blocks B and D and will not be further described here.

[0062] In this example, by setting the row decoders corresponding to each storage block to correspond to different word line ranges, and setting the row decoders set at the positions corresponding to the same corners of two storage blocks separated by one storage block to correspond to the same word line range, all the row decoders corresponding to each storage block can cooperate to generate the main decoding signal required to control all the word lines of the storage block, thereby allowing each row decoder to generate only part of the main decoding signal, which is beneficial to reducing the size of the row decoder and the memory.

[0063] In order to reduce the word line range corresponding to each word line driver, thereby improving the flexibility of word line driver layout, in one example, each memory block corresponds to four word line drivers;

[0064] For the memory blocks that are not at the edge of each memory segment, each memory block is provided with two word line drivers within the projection area of ​​the logic circuit chip;

[0065] For the memory blocks at the edge of each memory segment, each memory block is provided with three word line drivers within the projection area of ​​the logic circuit chip.

[0066] The storage segment may have various structures. In one example, each storage segment includes a plurality of storage blocks sequentially arranged along a first direction.

[0067] In practical applications, each memory includes multiple memory banks, and each memory bank includes multiple memory segments. FIG5 is a schematic diagram of the structure of a memory segment provided in an embodiment of the present application. As shown in FIG5 , each memory segment includes multiple memory blocks 100 arranged sequentially along a first direction shown in the figure.

[0068] Specifically, each storage block corresponds to four word line drivers, and each word line driver controls one quarter of the word lines of the storage block; wherein, for the storage blocks at the edge of each storage segment, the storage block is provided with two word line drivers within the projection area of ​​the logic circuit chip; for the storage blocks at the edge of each storage segment, each storage block is provided with three word line drivers within the projection area of ​​the logic circuit chip.

[0069] Figure 6 is a structural schematic diagram of another memory provided by an embodiment of the present application. As shown in Figure 6, the memory block MAT b2 and the memory block MAT b3 are two adjacent memory blocks 100 that are not at the edge of the memory segment. The memory block MAT b2 is provided with two word line drivers SWD b21 and SWD b22 within the projection area of ​​the logic circuit chip, and the memory block MAT b3 is provided with two word line drivers SWD b31 and SWD b32 within the projection area of ​​the logic circuit chip.

[0070] Figure 7 is a structural schematic diagram of another memory provided by an embodiment of the present application. As shown in Figure 7, the memory block MAT c1 and the memory block MAT c4 are two memory blocks at the edges of the memory segment. The memory block MAT c1 is provided with three word line drivers SWD c11, SWD c12 and SWD c13 within the projection area of ​​the logic circuit chip. The memory block MAT c4 is provided with three word line drivers SWD c41, SWD c42 and SWD c43 within the projection area of ​​the logic circuit chip.

[0071] In this example, by setting each memory block to correspond to four word line drivers, the four word line drivers can jointly drive the word lines of each memory block, thereby increasing the flexibility of word line driver layout.

[0072] Based on the memory structure described above, wordline drivers can be shared by multiple memory blocks, optimizing the memory layout and further reducing the size of the memory. In one example, for each memory block not at the edge of a memory segment, each wordline driver within the projection area of ​​the memory block on the logic circuit chip is shared by the memory block and an adjacent memory block, with different wordline drivers being shared by different adjacent memory blocks.

[0073] For the memory block at the edge of each memory segment, three word line drivers are set within the projection area of ​​the memory block on the logic circuit chip, one of which is shared by the memory block and the adjacent memory blocks of the memory block, and the remaining two word line drivers are only used to drive the word lines of the memory block.

[0074] Specifically, since the word line driver can only be shared by memory blocks belonging to the same memory segment but cannot be shared by memory blocks belonging to different memory segments, the memory blocks in the memory segment can be divided into two cases for discussion based on the structure of the memory segment.

[0075] In the first case, for a storage block that is not at the edge in each storage segment, two word line drivers arranged in the projection area of ​​the storage block in the logic circuit chip are shared by the storage block and an adjacent storage block of the storage block, and the two word line drivers are shared by two different adjacent storage blocks.

[0076] Still as shown in Figure 6, the word line driver SWD b21 is shared by the memory block MAT b2 and the memory block MAT b1 adjacent to the memory block MAT b2, the word line driver SWD b22 is shared by the memory block MAT b2 and the memory block MAT b3 adjacent to the memory block MAT b2, the word line driver SWD b31 is shared by the memory block MAT b3 and the memory block MAT b2 adjacent to the memory block MAT b3, and the word line driver SWD b32 is shared by the memory block MAT b3 and the memory block MAT b4 adjacent to the memory block MAT b3.

[0077] For the memory block at the edge of each memory segment, three word line drivers are set within the projection area of ​​the memory block on the logic circuit chip, one of which is shared by the memory block and the adjacent memory blocks of the memory block, and the remaining two word line drivers are only used to drive the word lines of the memory block.

[0078] Still as shown in Figure 7, word line drivers SWD c11 and SWD c12 are not shared by multiple memory blocks 100, and only drive the word lines of memory block MAT c1; word line driver SWD c13 is shared by memory block MAT c1 and memory block MAT c2 adjacent to memory block MAT c1; word line driver SWD c41 is shared by memory block MAT c4 and memory block MAT c3 adjacent to memory block MAT c4; word line drivers SWD c42 and SWD c43 are not shared by multiple memory blocks 100, and only drive the word lines of memory block MAT c4.

[0079] In this example, different memory blocks are set to share word line drivers, wherein each word line driver of a memory block set at the edge of the memory segment within the projection area of ​​the logic circuit chip is shared by the memory block and an adjacent memory block of the memory block, and among the three word line drivers of a memory block set at the edge of the memory segment within the projection area of ​​the logic circuit chip, one word line driver is shared by the memory block and the adjacent memory block of the memory block, and the remaining two word line drivers are only used to drive the word line of the memory block, effectively reducing the word line range driven by each word line driver, thereby reducing the volume of the word line driver, which is beneficial to optimizing the internal layout of the memory and reducing the volume of the memory.

[0080] Based on the above example, when setting the word line driver to be shared by multiple memory blocks, in order to shorten the signal transmission path from the word line driver to the word line of the memory block, the word line driver can be set to be shared by adjacent memory blocks. In one example, for the memory blocks that are not at the edge in each memory segment, each word line driver set within the projection area of ​​the memory block in the logic circuit chip is located within the projection area, on one side of the projection area corresponding to the memory block that is adjacent to the memory block that shares the word line driver.

[0081] Specifically, for a storage block that is not at the edge in each storage segment, two word line drivers are sequentially arranged in the first direction within the projection area of ​​the logic circuit chip, and each word line driver is adjacent to the storage block that shares the word line driver on one side of the projection area corresponding to the logic circuit chip.

[0082] Still as shown in Figure 6, for the memory block MAT b2 that is not at the edge of the storage segment, the memory block MAT b2 is provided with two word line drivers SWD b21 and SWD b22 in sequence along the first direction within the projection area of ​​the logic circuit chip, wherein the word line driver SWD b21 is shared by the memory block MAT b2 and the memory block MAT b1 adjacent to the memory block MAT b2, and the word line driver SWD b22 is shared by the memory block MAT b2 and the memory block MAT b3 adjacent to the memory block MAT b2. Correspondingly, the word line driver SWD b21 is located on the side of the projection area corresponding to the memory block MAT b1 on the logic circuit chip, and the word line driver SWD b22 is located on the side of the projection area corresponding to the memory block MAT b3 on the logic circuit chip.

[0083] In this example, for the memory blocks that are not at the edge of the memory segment, the word line memory of each memory block in the projection area of ​​the logic circuit chip is shared by the memory block adjacent to the word line memory in the projection area on the logic circuit chip, thereby effectively shortening the distance between the word line driver and the corresponding driven word line, reducing the word line drive delay, and optimizing the performance of the memory.

[0084] In addition to shortening the signal transmission path from the wordline driver to the memory block's wordline, the signal transmission path from the row decoder to the wordline driver can also be shortened, further improving memory performance. In one example, for each non-edge memory block in each memory segment, each wordline driver is connected to the main decoding signal lines of two adjacent row decoders. The adjacent row decoders are the row decoders shared by the memory block and the memory block that shares the wordline driver.

[0085] Specifically, for the memory blocks that are not at the edge of each memory segment, each word line driver is connected to the main decoding signal lines of two adjacent row decoders, which are row decoders shared by the memory block and the memory block that shares the word line driver.

[0086] FIG8 is a schematic structural diagram of another memory provided by an embodiment of the present application. As shown in FIG8 , for a memory block MAT b2 that is not at the edge of a memory segment, the memory block MAT b2 is provided with two word line drivers SWD b21 and SWD b22 in sequence along a first direction within the projection area of ​​the logic circuit chip, wherein the word line driver SWD b21 is shared by the memory block MAT b2 and the memory block MAT b1 adjacent to the memory block MAT b2, and the word line driver SWD b22 is shared by the memory block MAT b2 and the memory block MAT b3 adjacent to the memory block MAT b2. The memory block MAT b2 corresponds to four row decoders XDEC d1, XDEC d2, XDEC d4, and XDEC d5, wherein the memory block MAT b2 shares row decoders XDEC d1 and XDEC d4 with the adjacent memory block MAT b1, and the memory block MAT b2 shares row decoders XDEC d2 and XDEC d5 with the adjacent memory block MAT b3. d5, the word line driver SWD b21 is connected to the main decoding signal lines of the two adjacent row decoders XDEC d1 and XDEC d4, and the word line driver SWD b22 is connected to the main decoding signal lines of the two adjacent row decoders XDEC d2 and XDEC d5.

[0087] In this example, for the memory blocks that are not at the edge in each memory segment, each word line driver is connected to the main decoding signal line of the two row decoders shared by the memory block and the memory blocks that share the word line driver, so that each word line driver can be connected to the row decoder adjacent to the word line driver, shortening the transmission path from the row decoder to the word line driver, which is beneficial to improving the driving speed of the word line in the memory and effectively improving the processor performance.

[0088] Correspondingly, for edge memory blocks in a memory segment, word line drivers within the projection area of ​​the memory block on the logic circuit chip can be shared by multiple memory blocks, optimizing the memory layout. In one example, for edge memory blocks in each memory segment, of the three word line drivers within the projection area of ​​the memory block on the logic circuit chip, the word line driver shared by adjacent memory blocks is located within the projection area, adjacent to one side of the projection area corresponding to the adjacent memory block, and the remaining two word line drivers are located on the other side of the projection area.

[0089] Specifically, for the memory block at the edge of each memory segment, among the three word line drivers arranged in the projection area of ​​the memory block on the logic circuit chip, the word line driver shared by adjacent memory blocks is located within the projection area, adjacent to one side of the projection area corresponding to the adjacent memory block, and the remaining two word line drivers are located on the other side of the projection area.

[0090] Still as shown in FIG7 , for the memory block MAT c1 at the edge of the memory segment, the memory block MAT c1 is provided with three word line drivers SWD c11, SWD c12, and SWD c13 within the projection area of ​​the logic circuit chip. The word line drivers SWD c11 and SWD c12 are not shared and only drive the word lines of the memory block MAT c1; the word line driver SWD c13 is shared by the memory block MAT c1 and the memory block MAT c2 adjacent to the memory block MAT c1. Correspondingly, the word line driver SWD c13 is located on one side of the projection area corresponding to the adjacent memory block MAT c2, and the word line drivers SWD c11 and SWD c12 are located on the other side of the projection area.

[0091] In this example, for a memory block at the edge of a memory segment, the three wordline drivers arranged within the projection area of ​​the logic circuit chip are positioned so that the wordline driver shared by adjacent memory blocks is located within the projection area, adjacent to one side of the projection area corresponding to the adjacent memory block, while the remaining two wordline drivers are located on the other side of the projection area. This effectively shortens the distance between the wordline drivers and the wordlines they drive, reduces wordline drive latency, and helps optimize memory performance.

[0092] Based on the above example, the signal transmission path from the row decoder to the word line driver can be shortened, which helps further improve memory performance. In one example, for each edge memory block in a memory segment, the word line driver shared by adjacent memory blocks is connected to the main decoding signal lines of the two row decoders shared by that memory block and the adjacent memory block; the remaining two word line drivers are connected to the main decoding signal lines of the remaining two row decoders corresponding to that memory block.

[0093] Specifically, for the memory blocks at the edge of each memory segment, the word line driver shared by adjacent memory blocks is connected to the main decoding signal lines of the two row decoders shared by the memory block and the adjacent memory blocks; the remaining two word line drivers are connected to the main decoding signal lines of the remaining two row decoders corresponding to the memory block.

[0094] FIG9 is a schematic structural diagram of another memory provided by an embodiment of the present application. As shown in FIG9 , for a memory block MAT c1 located at the edge of a memory segment, the memory block MAT c1 is provided with three word line drivers SWD c11, SWD c12, and SWD c13 within the projection area of ​​the logic circuit chip. The word line drivers SWD c11 and SWD c12 only drive the word lines of the memory block MAT c1; the word line driver SWD c13 is shared by the memory block MAT c1 and the memory block MAT c2 adjacent to the memory block MAT c1. Memory block MAT c1 corresponds to four row decoders XDEC e1, XDEC e2, XDEC e5, and XDEC e6, where row decoders XDEC e2 and XDEC e6 are shared by memory block MAT c1 and memory block MAT c2 adjacent to memory block MAT c1. Correspondingly, word line driver SWD c13 is connected to the main decoding signal lines of row decoders XDEC e2 and XDEC e6, and word line drivers SWD c11 and SWD c12 are connected to the main decoding signal lines of row decoders XDEC e1 and XDEC e5.

[0095] In this example, for the memory blocks at the edge of each memory segment, a word line driver shared by adjacent memory blocks is connected to the main decoding signal lines of the two row decoders shared by the memory block and the adjacent memory blocks; the remaining two word line drivers are connected to the main decoding signal lines of the remaining two row decoders corresponding to the memory block, so that each word line driver can be connected to the row decoder adjacent to the word line driver, shortening the transmission path from the row decoder to the word line driver, which is beneficial to improving the driving speed of the word lines in the memory and effectively improving the processor performance.

[0096] Based on the above example, each word line driver receives main decoding signals from two row decoders. Therefore, each word line driver can be divided into two sub-word line drivers, each of which is connected to the main decoding signal line of a corresponding row decoder. In one example, each word line driver includes two sub-word line drivers, and the two sub-word line drivers have the same number of driving ports.

[0097] Specifically, each word line driver includes two sub-word line drivers, and the two sub-word line drivers have the same number of drive ports. For example, each word line driver includes 256 drive ports, which respectively control the 256 word lines of each storage block corresponding to the word line driver; each word line driver includes two sub-word line drivers, each sub-word line driver includes 128 drive ports, which respectively control the 128 word lines of each storage block corresponding to the sub-word line driver, and the word line ranges corresponding to the two sub-word line drivers are different.

[0098] FIG10 is a schematic diagram of another memory structure provided by an embodiment of the present application. As shown in FIG10 , excluding memory blocks 100 that are not located at the edge of a memory segment, each memory block 100 includes two word line drivers 300. Each word line driver 300 includes two sub-word line drivers 310 arranged perpendicular to a first direction, and each sub-word line driver 310 has the same number of ports. The sub-word line driver 310, located within the projection area of ​​the logic circuit chip of each memory block 100, receives a main decoding signal from the row decoder 200 corresponding to the memory block 100. Each sub-word line driver 310 receives a main decoding signal from an adjacent row decoder 200. Assuming that each row decoder 200 generates 32 main decoding signals, when sending the main decoding signals to the corresponding sub-word line drivers 310, 16 of the main decoding signals are sent via 16 main decoding signal lines to each corresponding sub-word line driver 310 located on one side of the row decoder 200 in a first direction, and the remaining 16 main decoding signals are sent to the corresponding sub-word line drivers 310 located on the other side of the row decoder 200 in the first direction. Each sub-word line driver 310 receives the 16 main decoding signals generated by a decoder 200. Combined with the 8 sub-decoding signals sent by the sub-decoder 400 to the sub-word line driver 310, each sub-word line driver 310 can control 16*8=128 word lines of each corresponding memory block 100. Each memory block 100 corresponds to four word line drivers 300 , that is, eight sub-word line drivers 310 . The eight sub-word line drivers 310 correspond to different word line ranges. Therefore, the eight sub-word line drivers 310 can jointly control 16*8*8=1024 word lines of the memory block 100 .

[0099] One sub-word line driver 310 sends 16 main decoding signals, and two sub-word line drivers corresponding to each word line driver receive main decoding signals generated by different row decoders.

[0100] The sub-word line drivers corresponding to each word line driver may be arranged perpendicular to the first direction, and each sub-word line driver receives a main decoding signal sent by an adjacent row decoder.

[0101] As shown in FIG. 2 , based on the main decoding signal lines arranged perpendicular to the first direction, the transmission path from the row decoder to the word line driver is short, and the delays of the transmission paths from each row decoder to the word line driver are substantially the same, which is beneficial for improving the word line driving speed while optimizing the timing and sensing margin of the memory.

[0102] The primary decoding signal lines connect the row decoder and the wordline driver, while the secondary decoding signal lines connect the secondary decoder and the wordline driver. In practical applications, the primary and secondary decoding signal lines can be routed in a variety of ways. To shorten the signal transmission path between the row decoder and the wordline driver, in one example, the secondary decoding signal lines are parallel to a first direction, while the primary decoding signal lines are perpendicular to the first direction.

[0103] Specifically, the memory's logic circuit chip is located above the memory array chip. The logic circuit chip is provided with a wiring layer and a device layer. The wiring layer is arranged with primary and secondary decoding signal lines, and the device layer is arranged with word line drivers, row decoders, and secondary decoders. The secondary decoding signal lines are arranged parallel to a first direction in the wiring layer and pass down to the device layer, connecting the output of the secondary decoder with the input of the word line driver. The primary decoding signal lines are arranged perpendicular to the first direction in the wiring layer and pass down to the device layer, connecting the output of the row decoder with the input of the word line driver. As shown in Figures 8 and 9, the primary decoding signal lines are perpendicular to the first direction and connect the row decoder 200 and the word line driver 300, effectively shortening the signal transmission path between the row decoder 200 and the word line driver 300.

[0104] Based on this wiring scheme, as shown in FIG10 , excluding memory blocks 100 not located at the edge of a memory segment, each memory block 100 includes two word line drivers 300. The word line driver 300, located within the projection area of ​​the logic circuit chip, receives the main decoding signals sent by the row decoder 200 corresponding to the memory block 100. Assuming that each row decoder 200 generates 32 main decoding signals, when sending the main decoding signals to the corresponding word line drivers 300, 16 of these main decoding signals are sent via 16 main decoding signal lines to each corresponding word line driver 300 located on one side of the row decoder 200 in a first direction, and the remaining 16 main decoding signals are sent to the corresponding word line drivers 300 located on the other side of the row decoder 200 in the first direction. Each wordline driver 300 receives 16 primary decoding signals generated by the two row decoders 200. Combined with the 8 secondary decoding signals received from the secondary decoder 400, each wordline driver 300 can control 16*2*8=128 wordlines for each corresponding memory block 100. Each memory block 100 corresponds to four wordline drivers 300, and the four sub-wordline drivers 310 correspond to different wordline ranges. Therefore, the four wordline drivers 300 can collectively control 16*2*8*4=1024 wordlines for that memory block 100. The projection area of ​​the logic circuit chip above each memory block 100 is divided into two sub-areas arranged perpendicular to the first direction. Each sub-area only requires 32 primary decoding signal lines arranged parallel to and perpendicular to the first direction. Compared to traditional methods that require 128 primary decoding signal lines per memory block 100, this effectively reduces the restrictions on the width and spacing of the primary decoding signal lines, thereby reducing wiring difficulty.

[0105] Through the above wiring method, the wiring is orderly and the signal transmission path between the row decoder and the word line driver can be shortened, the delay difference between different transmission paths is reduced, and the memory timing is optimized.

[0106] This embodiment provides a memory, which includes a bonded memory array chip and a logic circuit chip, wherein the logic circuit chip is located above the memory array chip, a memory block is arranged on the memory array chip, and a row decoder, a sub-decoder, and a word line driver are arranged on the logic circuit chip. Compared with a planar memory structure, this provides more circuit layout space and eliminates the need to arrange row decoders and word line drivers around the memory block, which can effectively reduce the length of signal lines, reduce latency, and improve memory performance. By providing at least one corresponding row decoder and at least one word line driver for each memory block, control of the word line of each memory block is achieved, wherein the product of the sum of the number of main decoding signals of all row decoders corresponding to a single memory block and a second number is equal to the number of word lines of the single memory block. This can effectively reduce the number of main decoding signal lines corresponding to the memory block, reduce the width and spacing restrictions on the main decoding signal lines, and reduce wiring difficulty.

[0107] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0108] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A memory, characterized in that, The memory includes: a bonded memory array chip and a logic circuit chip, the logic circuit chip being located above the memory array chip, the memory array chip being provided with a plurality of memory segments arranged in an array, and each memory segment including a plurality of memory blocks (100); wherein, Each memory block corresponds to at least one row decoder (200), each row decoder providing a first number of main decoding signal lines for transmitting main decoding signals; each memory segment corresponds to one sub-decoder (400), the sub-decoder providing a second number of sub-decoding signal lines for transmitting sub-decoding signals; wherein, the product of the sum of the number of main decoding signals of all row decoders corresponding to a single memory block and the second number is the same as the number of word lines of the single memory block; Each memory block corresponds to at least one word line driver (300), the word line driver providing a plurality of driving ports for driving the word lines of the corresponding memory block according to the main decoding signal and the sub-decoding signal; wherein, the sum of the number of driving ports of all word line drivers corresponding to a single memory block is the same as the number of word lines of the memory block; wherein, the row decoder, the sub-decoder, and the word line driver are all arranged on the logic circuit chip.

2. The memory according to claim 1, wherein Each memory block corresponds to four row decoders, and the projections of the four vertices of each memory block on the logic circuit chip are respectively located in the regions where the four row decoders corresponding to the memory block are located, and the four row decoders are shared by four cross-adjacent memory blocks at the position corresponding to the central region of the four memory blocks.

3. The memory according to claim 2, wherein The word line ranges corresponding to the row decoders provided at the positions corresponding to different vertices of the memory block are different; the row decoders provided at the positions corresponding to the same vertices of two memory blocks separated by one memory block correspond to the same word line range.

4. The memory according to claim 3, wherein Each memory segment includes a plurality of memory blocks arranged in sequence along a first direction.

5. The memory according to claim 4, wherein Each memory block corresponds to four word line drivers; For each memory block that is not at the edge in each memory segment, two word line drivers are provided in the projection area of the memory block on the logic circuit chip; For each memory block that is at the edge in each memory segment, three word line drivers are provided in the projection area of the memory block on the logic circuit chip.

6. The memory according to claim 5, wherein For each memory block that is not at the edge in each memory segment, each word line driver provided in the projection area of the memory block on the logic circuit chip is shared by the memory block and one adjacent memory block of the memory block, and different word line drivers are shared by different adjacent memory blocks; For each memory block that is at the edge in each memory segment, among the three word line drivers provided in the projection area of the memory block on the logic circuit chip, one word line driver is shared by the memory block and the adjacent memory block of the memory block, and the remaining two word line drivers are only used to drive the word lines of the memory block.

7. The memory according to claim 6, characterized in that, For each memory block that is not at the edge in each memory segment, each word line driver provided in the projection area of the memory block on the logic circuit chip is located in the projection area, on one side adjacent to the projection area corresponding to the memory block sharing the word line driver.

8. The memory according to claim 7, wherein For each memory block that is not at the edge in each memory segment, each word line driver is connected to the main decoding signal lines of two adjacent row decoders, where the adjacent row decoders are the row decoders shared by this memory block and the memory block sharing the same word line driver.

9. The memory according to claim 6, wherein For each memory block at the edge in each memory segment, among the three word line drivers set within the projection area of this memory block on the logic circuit chip, the word line driver shared by adjacent memory blocks is located within the projection area, on the side adjacent to the projection area corresponding to the adjacent memory block, and the other two word line drivers are located on the other side of the projection area.

10. The memory according to claim 9, wherein For each memory block at the edge in each memory segment, the word line driver shared by adjacent memory blocks is connected to the main decoding signal lines of the two row decoders shared by this memory block and the adjacent memory block; the other two word line drivers are connected to the main decoding signal lines of the other two row decoders corresponding to this memory block.

11. The memory according to claim 5, wherein Each word line driver includes two sub-word line drivers, and the number of driving ports of the two sub-word line drivers is the same.

12. The memory according to claim 11, wherein The secondary decoding signal lines are parallel to the first direction, and the main decoding signal lines are perpendicular to the first direction.

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