Buffer circuit for high-speed clock and data multiplexing

Abstract

A buffer circuit for a high-speed clock and data multiplexing. The circuit comprises: a current source, a differential amplification module, a load resistor, a degeneration resistor array and a degeneration capacitor array, which are connected between the current source and the differential amplification module, a load capacitor, which is connected to the load resistor and the ground, and a logic control unit, wherein the degeneration resistor array comprises a fixed resistor unit and an adjustable resistor unit; the differential amplification module is configured to input a clock signal or a data signal, and transmit and / or amplify the clock signal or the data signal; and the logic control unit is disconnected from the degeneration capacitor array when the differential amplification module inputs the data signal, and is connected to the degeneration capacitor array and disconnected from the adjustable resistor unit in the degeneration resistor array when the differential amplification module inputs the clock signal. The buffer circuit provided in the present invention transmits a high-speed clock signal and a data signal by means of a multiplexing structure, so that the integration level of the circuit is improved, and the quality of signal transmission can be effectively ensured.

Description

High-speed clock and data multiplexing buffer circuit

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 27, 2023, with application number 202311833860.9 and invention name “Buffer Circuit for High-Speed ​​Clock and Data Multiplexing”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of circuit technology, and in particular to a buffer circuit for high-speed clock and data multiplexing. Background Art

[0003] Field Programmable Gate Arrays (FPGAs) are in high demand in applications such as aviation, industry, servers, and edge computing, and need to support diverse protocol requirements. High-speed SerDes (SERializer / Deserializer) is a critical resource within FPGAs and serves as the physical layer of the protocol. Long-distance transmission of high-speed clocks and data within SerDes can lead to signal distortion and attenuation, necessitating the insertion of one or more buffers along the path to ensure signal quality at the receiving end. CMOS (Complementary Metal Oxide Semiconductor) levels are the operating levels for very large-scale digital circuits. However, compared to CML (Current Mode Logic), CMOS logic has a larger output swing and a lower maximum operating rate. Therefore, CML circuits are typically used for the high-speed clock and data buffers within SerDes chips.

[0004] Random data signals contain a rich spectrum of components, requiring the data buffer's amplitude-frequency characteristic curve to maintain minimal fluctuations within the -3dB bandwidth. This prevents unexpected amplification or attenuation of the signal in certain frequency ranges, potentially leading to erroneous output responses in subsequent circuits. Clock signal buffers can also use a CML structure, but compared to data signals, clock signal energy primarily resides at discrete frequency points. Therefore, active or passive inductive loads can be used to amplify signals within a specific frequency range.

[0005] Traditional differential CML circuits support buffering and amplification of high-speed clock or data signals. The load resistance and parasitic capacitance of the output node form a pole in the circuit, resulting in a low-pass buffer's amplitude-frequency response. When used for clock signal buffering and amplification, low-frequency noise in the clock path is proportionally amplified, resulting in increased jitter in the output clock signal. Summary of the Invention

[0006] The embodiment of the present invention provides a buffer circuit for high-speed clock and data multiplexing, which can ensure the gain stability of the circuit in a wide frequency range when a data signal is input; and can attenuate low-frequency signals when a clock signal is input.

[0007] An embodiment of the present invention provides a high-speed clock and data multiplexing buffer circuit, the circuit comprising: a current source, a differential amplifier module, a load resistor, a degeneration resistor array and a degeneration capacitor array connected between the current source and the differential amplifier module, a load capacitor connected to the load resistor and ground, and a logic control unit; the degeneration resistor array comprises: a fixed resistor unit and an adjustable resistor unit;

[0008] The differential amplifier module is used to input a clock signal or a data signal to achieve transmission and / or amplification of the clock signal or the data signal;

[0009] The logic control unit is used to disconnect the degenerate capacitor array when the differential amplifier module inputs a data signal; and to connect the degenerate capacitor array and disconnect the adjustable resistor unit in the degenerate resistor array when the differential amplifier module inputs a clock signal.

[0010] Optionally, the differential amplification module includes: two differential amplifiers connected in parallel;

[0011] in:

[0012] a first differential amplifier, configured to input the data signal;

[0013] The second differential amplifier is configured to input the clock signal.

[0014] Optionally, the two input terminals of the first differential amplifier are respectively connected to the ground through a first switch; the two input terminals of the second differential amplifier are respectively connected to the ground through a second switch; the first switch is controlled by a clock enable signal, and the second switch is controlled by a data enable signal; the clock enable signal and the data enable signal are complementary signals.

[0015] Optionally, the differential amplifier includes two differential pairs of transistors; the degeneration resistor array is connected between the two differential pairs of transistors; and the degeneration capacitor array is connected between the two differential pairs of transistors.

[0016] Optionally, the differential pair transistors are any one of the following: MOS transistors and triodes.

[0017] Optionally, the adjustable resistance units include one or more groups, and each group of adjustable resistance units includes two resistors with the same resistance value and connected in series between the two differential pair transistors.

[0018] Optionally, the degenerate capacitor array has one or more groups of capacitor units, and each group of capacitor units includes two capacitors with the same capacitance value and connected in series between the two differential pair transistors.

[0019] Optionally, the differential amplifier module includes a first output terminal and a second output terminal, for outputting a differential clock signal or a differential data signal; the load capacitors are respectively connected between the first output terminal and the ground, and between the second output terminal and the ground.

[0020] Optionally, the load capacitor is an adjustable capacitor or an adjustable capacitor array.

[0021] Optionally, the logic control unit includes:

[0022] a first logic unit, configured to input the data enable signal or the clock enable signal and output a first control signal for the degeneration resistor array;

[0023] The second logic unit is configured to input the data enable signal or the clock enable signal and output a second control signal for the degenerate capacitor array.

[0024] Optionally, a width-to-length ratio of the two differential pairs of transistors of the first differential amplifier is smaller than a width-to-length ratio of the two differential pairs of transistors of the second differential amplifier.

[0025] Optionally, when transmitting a low-speed clock signal, the capacitance of the degenerate capacitor array and the load capacitor is greater than the capacitance when transmitting a high-speed clock signal.

[0026] The high-speed clock and data multiplexing buffer circuit provided in an embodiment of the present invention can configure the circuit's transmission characteristics based on the characteristics of the input signal. In certain application scenarios, such as when random data signals and high-speed clock signals need to be transmitted simultaneously, the multiplexing structure improves the circuit's integration while ensuring circuit performance. When the circuit operates in clock buffer mode, a low-frequency gain of less than 0dB can suppress low-frequency noise such as the common-mode offset of the input signal; when the circuit operates in data buffer mode, while ensuring the stability of the output common-mode point, multiple sets of configurable gain are provided, making it more flexible to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a schematic diagram of the structure of a conventional CML circuit;

[0028] 2 is a schematic structural diagram of a high-speed clock and data multiplexing buffer circuit provided by an embodiment of the present invention;

[0029] 3 is another schematic structural diagram of a high-speed clock and data multiplexing buffer circuit provided by an embodiment of the present invention;

[0030] FIG4 is a schematic structural diagram of a degenerate resistor array according to an embodiment of the present invention;

[0031] FIG5 is a schematic structural diagram of a first logic unit for controlling the degenerate resistor array shown in FIG4 according to an embodiment of the present invention;

[0032] FIG6 is a schematic structural diagram of a degenerate capacitor array according to an embodiment of the present invention;

[0033] 7 is a schematic structural diagram of a second logic unit for controlling the degenerate capacitor array shown in FIG. 4 according to an embodiment of the present invention;

[0034] FIG8 is a schematic diagram of a structure of a load capacitor according to an embodiment of the present invention;

[0035] 9 is a schematic diagram of an equivalent circuit of the high-speed clock and data multiplexing buffer circuit shown in FIG3 when a data signal is input;

[0036] 10 is a schematic diagram of an equivalent circuit of the high-speed clock and data multiplexing buffer circuit shown in FIG3 when a clock signal is input;

[0037] 11 is a schematic diagram of gain characteristics of a high-speed clock and data multiplexing buffer circuit in data mode according to an embodiment of the present invention;

[0038] FIG12 is a schematic diagram showing gain characteristics of a high-speed clock and data multiplexing buffer circuit in a clock mode provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The principles and spirit of the present invention will be described below with reference to the exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described only to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way.

[0040] The working principle of the CML circuit is to achieve signal transmission and amplification by controlling current. In order to more clearly understand the solution of the present invention, the traditional CML structure and its working principle are briefly described below.

[0041] The traditional CML structure, shown in Figure 1, consists of two main components: a current source Ib and a differential amplifier consisting of a differential pair of transistors M1 and M2. Resistor R is the load resistor. Source Ib generates a constant current, while the differential amplifier amplifies the signal. Its input signals, Vin and Vip, are differential signals—positive and negative phases—and it outputs differential signals, Voutp and Voutn.

[0042] The gain of the CML structure can be achieved by adjusting the operating current of the differential amplifier, thereby increasing the amplitude of the output signal and realizing signal transmission and amplification.

[0043] In circuits such as high-speed interfaces, some signal paths must transmit both clock signals and data. When data transmission is required, the circuit's gain must be stable within the -3dB bandwidth while ensuring sufficient bandwidth. However, for clock signals, clock buffers must reduce noise and jitter.

[0044] In response to the above application requirements, an embodiment of the present invention provides a high-speed clock and data multiplexing buffer circuit that can simultaneously support buffering and amplification of high-speed clock and data signals, and can adjust the device parameters of the circuit according to the characteristics of the input signal to achieve optimal circuit performance.

[0045] FIG2 is a schematic diagram showing the structure of a high-speed clock and data multiplexing buffer circuit provided by an embodiment of the present invention.

[0046] The high-speed clock and data multiplexing buffer circuit includes:

[0047] A current source Ib, a differential amplifier module 20, a load resistor R1, a degeneration resistor array Rd and a degeneration capacitor array Cd connected between the current source Ib and the differential amplifier module 20, a load capacitor Cl connected to the load resistor R1 and ground, and a logic control unit (not shown).

[0048] The differential amplifier module 20 is configured to receive differential signals Vin_p and Vin_n, transmit and / or amplify them, and generate differential output signals Voutn and Voutp. The input signal may be a clock signal or a data signal, and the module transmits and / or amplifies the clock signal or data signal.

[0049] In a non-limiting embodiment, the differential amplifier module 20 can be a differential amplifier composed of a pair of differential transistors 1 and 2. The differential transistors 1 and 2 can be MOS transistors, such as the MOS transistors M1 and M2 shown in FIG2 , or can be triodes, which is not limited in this embodiment of the present invention.

[0050] Taking the MOS transistor shown in Figure 2 as an example, each MOS transistor has a gate as the input terminal, which receives a clock signal or data signal; a drain as the output terminal; a source connected to its respective current source Ib, and a drain connected to voltage VCC via a load resistor R1. Current source Ib can be generated by a current mirror to provide a controllable current.

[0051] The degeneration resistor array Rd and the degeneration capacitor array Cd are connected between the sources of the two MOS transistors and the current source Ib, respectively. The load capacitor Cl is connected between the drain of the MOS transistor and ground.

[0052] In this embodiment, the degenerate resistor array Rd includes a fixed resistor unit and an adjustable resistor unit.

[0053] Correspondingly, the logic control unit is used to disconnect the degenerate capacitor array Cd when the differential amplifier module 20 inputs a data signal; and to connect the degenerate capacitor array Cd and disconnect the adjustable resistor unit in the degenerate resistor array Rd when the differential amplifier module 20 inputs a clock signal.

[0054] In this buffer circuit, the low-frequency gain of the circuit can be adjusted through the degeneration resistor array Rd, and the gain range of the circuit can be jointly controlled by the degeneration capacitor array Cd and the load capacitor array Cl.

[0055] Through the above circuit structure, the bias and load can be multiplexed in two working modes, thereby improving the applicability and flexibility of the buffer circuit.

[0056] Furthermore, considering that the transmission of clock signals and data signals often have different requirements for the size of transmission tubes, as shown in FIG3 , in another non-limiting embodiment, the differential amplification module may use two differential amplifiers connected in parallel, namely, a first differential amplifier composed of MOS transistors M1 and M2 in FIG3 , for inputting differential data signals Vin_data_p and Vin_data_n; and a second differential amplifier composed of MOS transistors M3 and M4, for inputting differential clock signals Vin_clk_p and Vin_clk_n.

[0057] It should be noted that during signal transmission, only one signal can be transmitted at a time, namely, the data signal or the clock signal. To facilitate the operation of the two differential amplifiers, as shown in FIG3 , the two input terminals of the first differential amplifier are connected to ground via a first switch K1; the two input terminals of the second differential amplifier are connected to ground via a second switch K2; the first switch K1 is controlled by a clock enable signal clk_en, and the second switch K2 is controlled by a data enable signal clk_enb; the clock enable signal clk_en and the data enable signal clk_enb are complementary signals, i.e., when one is high, the other is low.

[0058] When the data signal needs to be transmitted, the clock enable signal clk_en controls the first switch K1 to be opened, and correspondingly, the data enable signal clk_enb controls the second switch K2 to be closed, and the two input terminals of the second differential amplifier are grounded; conversely, when the clock signal needs to be transmitted, the clock enable signal clk_en controls the first switch K1 to be closed, and correspondingly, the data enable signal clk_enb controls the second switch K2 to be opened, and the two input terminals of the first differential amplifier are grounded.

[0059] In the embodiment of the present invention, the adjustable resistor units in the degenerate resistor array Rd may include one or more groups, and each group of adjustable resistor units includes two resistors with the same resistance value and connected in series between the two differential pair transistors.

[0060] Similarly, the degenerate capacitor array Cd may have one or more groups of capacitor units, each group of capacitor units including two capacitors with the same capacitance value connected in series between the two differential pair transistors.

[0061] In order to facilitate the control of the above-mentioned degenerate resistor array Rd and degenerate capacitor array Cd, different logic units can be set to control them.

[0062] For example, in a non-limiting embodiment, the logic control unit may include:

[0063] A first logic unit is configured to input the data enable signal or the clock enable signal and output a first control signal for the degeneration resistor array Rd.

[0064] The second logic unit is configured to input the data enable signal or the clock enable signal and output a second control signal for the degenerate capacitor array Cd.

[0065] The structures of the degenerate resistor array Rd and the degenerate capacitor array Cd in the embodiment of the present invention are described in detail below with examples.

[0066] 4 and 5 , FIG. 4 shows a schematic structural diagram of a degenerate resistor array according to an embodiment of the present invention, and FIG. 5 is a schematic structural diagram of a first logic unit for controlling the degenerate resistor array shown in FIG. 4 .

[0067] In the example shown in FIG4 , the degenerate resistor array Rd is composed of a set of fixed resistor units Rd_on and three sets of adjustable resistor units Rd0, Rd1, and Rd2. Each set of resistor units includes two resistors with the same resistance value connected in series between the two differential pair nodes A and B. A control switch is provided between the two resistors of each set of adjustable resistor units, which are respectively controlled by the control signal ctrl <0> 、ctrl <1> 、ctrl <2> control.

[0068] Control signal ctrl <0> 、ctrl <1> 、ctrl <2> Generated by the corresponding logic circuit, the first logic unit shown in FIG5 is composed of a plurality of gate circuits to realize the decoding logic control of Rd0 to Rd2.

[0069] The first logic unit shown in FIG5 includes three input signals, namely a data enable signal clk_enb and a resistance logic control signal r_ctrl <0> and r_ctrl <1> , three-way output signal ctrl <0> 、ctrl <1> 、ctrl <2> The three groups of adjustable resistor units in the degenerate resistor array Rd are controlled to connect to or disconnect the circuit. <0> and r_ctrl <1> It can be generated by an external register or an I / O pin of a control module and input to the first logic unit.

[0070] 3, 4 and 5, when clk_enb = 1, Rd_on is connected to the circuit, and Rd0 to Rd2 are controlled by the first logic unit shown in FIG5. The control logic is as follows:

[0071] ctrl <0> 、ctrl <1> 、ctrl <2> When it is 1, resistors Rd0, Rd1, and Rd2 are connected to the circuit, otherwise they are disconnected.

[0072] When clk_enb=0, ctrl<2:0>=3b000, that is, ctrl <2> 、ctrl <1> 、ctrl <0> All are 0, and the resistors Rd0, Rd1, and Rd2 are disconnected and not connected to the circuit;

[0073] When clk_enb = 1, ctrl<2:0> is the thermometer decoding of r_ctrl<1:0>, that is:

[0074] When r_ctrl<1:0>=2b00, ctrl<2:0>=3b000, that is, ctrl <2> 、ctrl <1> 、ctrl <0> All are 0, and the resistors Rd2, Rd1, and Rd0 are disconnected;

[0075] When r_ctrl<1:0>=2b01, ctrl<2:0>=3b001, that is, ctrl <2> and ctrl <1> is 0, ctrl <0> is 1, resistors Rd2 and Rd1 are disconnected, and Rd0 is connected to the circuit;

[0076] When r_ctrl<1:0>=2b10, ctrl<2:0>=3b011, that is, ctrl <2> is 0, ctrl <1> and ctrl <0> When it is 1, resistor Rd2 is disconnected and Rd1 and Rd0 are connected to the circuit;

[0077] When r_ctrl<1:0>=2b11, ctrl<2:0>=3b111, that is, ctrl <2> 、ctrl <1> 、ctrl <0> All are 1, and resistors Rd2, Rd1, and Rd0 are all connected to the circuit.

[0078] It can be seen that as r_ctrl<1:0> increases, resistors Rd0, Rd1, and Rd2 are sequentially connected to the circuit.

[0079] 6 and 7 , FIG. 6 is a schematic structural diagram of a degenerate capacitor array according to an embodiment of the present invention, and FIG. 7 is a schematic structural diagram of a second logic unit for controlling the degenerate capacitor array shown in FIG. 6 .

[0080] In the example shown in Figure 6, the degenerate capacitor array Cd is composed of four groups of capacitor units Cd_on, Cd0, Cd1, and Cd2. Each group of capacitor units includes two capacitors with the same capacitance value and connected in series between the two differential pair nodes A and B. A control switch is set between the two capacitors of each group of capacitor units, which are respectively controlled by the control signals clk_en and degc <0> 、degc <1> 、degc <2> control.

[0081] The second logic unit shown in FIG7 includes three input signals, namely a data enable signal clk_enb and a resistance logic control signal c_ctrl. <0> and c_ctrl <1> , three-way output signal degc <0> 、degc <1> 、degc <2> The three groups of adjustable resistance units Cd0, Cd1, and Cd2 in the degenerate capacitor array Cd are controlled to be connected to the circuit or disconnected. <0> and c_ctrl <1> It can be generated by an external register or an I / O pin of a control module and input to the second logic unit.

[0082] Referring to FIG3 , FIG6 and FIG7 together, the control logic of the second logic unit on the capacitor array is as follows:

[0083] When the control signal clk_en, degc <0> 、degc <1> 、degc <2> When it is 1, capacitors Cd_on, Cd0, Cd1, and Cd2 are connected to the circuit, otherwise they are disconnected.

[0084] When clk_en=0, clk_enb=1, degc<2:0>=3b000, that is, capacitors Cd_on, Cd0, Cd1, and Cd2 are not connected to the circuit;

[0085] When clk_en=1, Cd_on is connected to the circuit, degc<2:0> is the inverse thermometer decoding of c_ctrl<1:0>, that is:

[0086] When c_ctrl<1:0>=2b00, degc<2:0>=3b111, that is, degc <2> 、degc <1> 、degc <0> All are 1, and capacitors Cd2, Cd1, and Cd1 are all connected to the circuit;

[0087] When c_ctrl<1:0>=2b01, degc<2:0>=3b110, that is, degc <2> and degc <1> Both are 1, degc <0> is 0, capacitors Cd2 and Cd1 are connected to the circuit, and Cd0 is disconnected;

[0088] When c_ctrl<1:0>=2b10, degc<2:0>=3b100, that is, degc <2> is 1, degc <1> and degc <0> is 0, capacitor Cd2 is connected to the circuit, and Cd1 and Cd0 are disconnected;

[0089] When c_ctrl<1:0>=2b11, degc<2:0>=3b000, that is, degc <2> 、degc <1> and degc <0> All are 0, and capacitors Cd2, Cd1, and Cd0 are disconnected.

[0090] It can be seen that as c_ctrl<1:0> increases, capacitors Cd0, Cd1, and Cd2 are disconnected from the circuit in sequence.

[0091] 3 , in an embodiment of the present invention, two load capacitors C1 are connected between the first output terminal and ground, and between the second output terminal and ground, respectively. In a specific application, the load capacitors C1 may be adjustable capacitors or adjustable capacitor arrays.

[0092] FIG8 is a schematic diagram of a structure of a load capacitor according to an embodiment of the present invention.

[0093] In this example, the load capacitor Cl is an adjustable capacitor array consisting of three capacitors Cl0, Cl1, and Cl2. Capacitors Cl0, Cl1, and Cl2 are adjustable capacitors, each controlled by a corresponding switch. These switches can also be controlled by the control signal degc generated by the second logic unit shown in FIG7. <0> 、degc <1> 、degc <2> control.

[0094] 3 , the process and performance of transmitting data signals and clock signals by the high-speed clock and data multiplexing buffer circuit provided by the present invention will be described in detail.

[0095] When the buffer circuit shown in FIG3 operates in data buffer mode, clk_en=0, clk_enb=1, that is, the input differential pair transistors M1 and M2 operate normally, the gates of M3 and M4 are pulled down to ground, and the degeneration capacitor Cd is not connected to the circuit. At this time, the buffer circuit shown in FIG3 can be simplified as shown in FIG9.

[0096] Referring to Figure 9, the resistance of the adjustable resistor array Rd is much smaller than the output impedance ro of the tail current source Ib. The resistance of the resistor array Rd shown in Figure 9 decreases as r_ctrl<1:0> increases. The circuit's low-frequency gain can be expressed as gm1×Rl / (1+gm1×Rd), where gm1 represents the transconductance of the input differential pair transistors in data mode. Because the data buffer has multiple adjustable gain levels, by properly configuring the resistances of Rd_on and Rd0-Rd3, multi-level gain adjustment can be achieved for the input data signal, ranging from attenuation to amplification. Its amplitude-frequency characteristics are shown in Figure 11.

[0097] When the circuit shown in Figure 3 operates in clock buffer mode, clk_en = 1, clk_enb = 0, Rd0 to Rd2 of the adjustable resistor array Rd are not connected to the circuit, and the capacitor array Cd is connected to the sources of the input differential pair transistors M3 and M4. At this time, the buffer circuit shown in Figure 3 can be simplified as shown in Figure 10.

[0098] Referring to Figure 10, the low-frequency gain of the circuit is less than 0dB. The zero point formed by the degeneration capacitor Cd and the fixed resistance unit Rd_on in the resistor array Rd is 1 / (Rd_on×Cd). The main pole of the circuit is (1+gm3×Rd) / (Rd_on×Cd), where gm3 represents the transconductance of the input differential pair in clock mode. The output pole is 1 / (Rl×Cl). The gain of the buffer for signals with frequencies in the range of (1+gm3×Rd) / (Rd_on×Cd) to 1 / (Rl×Cl) is approximately gm3×Rl.

[0099] By properly configuring the values ​​of the degeneration capacitor Cd and the load capacitor Cl, the fundamental wave of the clock signal can be amplified while the higher harmonics and low-frequency components can be attenuated. The buffer's amplitude-frequency characteristic curve is shown in Figure 12.

[0100] Adjusting the circuit's passband according to the input clock signal frequency minimizes circuit output noise and further reduces clock jitter. Specifically, c_ctrl<1:0> increases as the input clock frequency increases, while the degeneration capacitor Cd and load capacitor Cl adjust in the same direction, as shown in Figure 8.

[0101] When the buffer input signal is a low-speed clock, the capacitance values ​​of Cd and Cl are large, and the frequencies of the main and output poles are low. When the input signal is a high-speed clock, the capacitance values ​​of Cd and Cl are small, and the frequencies of the main and output poles are high. This ensures better transmission quality for clock signals of different frequencies.

[0102] It should be noted that, in specific applications, the width-to-length ratios of the two differential pair transistors can be the same or different, and this is not limited in this embodiment of the present invention. Preferably, when the buffer input signal is random data, circuit linearity must be ensured, and the overdrive voltage of transistor M1 is relatively high, resulting in a smaller width-to-length ratio. When the input signal is a high-speed clock consistent with CMOS logic and its high level is less than the buffer supply voltage, the width-to-length ratio of transistor M3 is relatively large, which can better ensure the output signal swing.

[0103] In specific implementations, the modules / units included in the various devices and products described in the above embodiments may be software modules / units or hardware modules / units, or may be partially software modules / units and partially hardware modules / units.

[0104] For example, for each device or product applied to or integrated into a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated into a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The element can be implemented in the form of a software program, which runs on the processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on the processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0105] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A buffer circuit for high-speed clock and data multiplexing, characterized in that The circuit includes: a current source, a differential amplification module, a load resistor, a degeneration resistor array and a degeneration capacitor array connected between the current source and the differential amplification module, a load capacitor connected to the load resistor and the ground, and a logic control unit; the degeneration resistor array includes: a fixed resistor unit and an adjustable resistor unit; The differential amplification module is configured to input a clock signal or a data signal, and implement the transmission and / or amplification of the clock signal or the data signal; The logic control unit is configured to disconnect the degeneration capacitor array when the differential amplification module inputs a data signal; and connect the degeneration capacitor array and disconnect the adjustable resistor unit in the degeneration resistor array when the differential amplification module inputs a clock signal.

2. The buffer circuit for high-speed clock and data multiplexing according to claim 1, wherein The differential amplification module includes: two differentially-connected differential amplifiers; wherein: The first differential amplifier is configured to input the data signal; The second differential amplifier is configured to input the clock signal.

3. The buffer circuit for high-speed clock and data multiplexing according to claim 2, wherein: Two input terminals of the first differential amplifier are respectively connected to the ground through a first switch; Two input terminals of the second differential amplifier are respectively connected to the ground through a second switch; The first switch is controlled by a clock enable signal, and the second switch is controlled by a data enable signal; the clock enable signal and the data enable signal are complementary signals.

4. The buffer circuit for high-speed clock and data multiplexing according to claim 3, wherein The differential amplifier includes two differential pair transistors; The degeneration resistor array is connected between the two differential pair transistors; The degeneration capacitor array is connected between the two differential pair transistors.

5. The buffer circuit for high-speed clock and data multiplexing according to claim 4, characterized in that The differential pair transistor is any one of the following: a MOS transistor, a bipolar transistor.

6. The buffer circuit for high-speed clock and data multiplexing according to claim 4, wherein There is one group or multiple groups of adjustable resistor units, and each group of adjustable resistor units includes two resistors with the same resistance value and connected in series between the two differential pair transistors.

7. The buffer circuit for high-speed clock and data multiplexing according to claim 4, wherein The degeneration capacitor array has one group or multiple groups of capacitor units, and each group of capacitor units includes two capacitors with the same capacitance value and connected in series between the two differential pair transistors.

8. The buffer circuit for high-speed clock and data multiplexing according to claim 1, wherein The differential amplification module includes a first output terminal and a second output terminal, and is configured to output a differential clock signal or a differential data signal; The load capacitors are respectively connected between the first output terminal and the ground, and between the second output terminal and the ground.

9. The buffer circuit for high-speed clock and data multiplexing according to claim 8, wherein The load capacitor is an adjustable capacitor or an adjustable capacitor array.

10. The buffer circuit for high-speed clock and data multiplexing according to claim 3, characterized in that, The logic control unit includes: A first logic unit, configured to input the data enable signal or the clock enable signal, and output a first control signal for the degeneration resistor array A second logic unit, configured to input the data enable signal or the clock enable signal, and output a second control signal for the degeneration capacitor array.

11. The buffer circuit for high-speed clock and data multiplexing according to claim 4, wherein The aspect ratio of the two differential pair transistors of the first differential amplifier is smaller than the aspect ratio of the two differential pair transistors of the second differential amplifier.

12. The buffer circuit for high-speed clock and data multiplexing according to claim 1, wherein The capacitance values of the degeneration capacitor array and the load capacitor when transmitting a low-speed clock signal are greater than the capacitance values when transmitting a high-speed clock signal.

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