Data reading method for chip, and chip, computer device, storage medium and computer program product

Abstract

Disclosed in the embodiments of the present disclosure are a data reading method for a chip, and a chip, a computer device, a storage medium and a computer program product. The method comprises: acquiring a data reading instruction, wherein the data reading instruction is used for instructing data reading to be performed according to reading information and data prefetching to be performed according to prefetching information; on the basis of the data reading instruction, acquiring a first data reading request, wherein the first data reading request includes the reading information and the prefetching information; sending the first data reading request to a cache module, so that in response to the first data reading request, the cache module reads and returns first target data according to the reading information, and pre-fetches and caches second target data according to the prefetching information; and receiving the first target data returned by the cache module. The embodiments of the present disclosure can reduce data request pressure between a request source and a cache module, compress a request bandwidth, improve the performance of a processor, and facilitate flexible control over a prefetching mode on a per-task basis, thereby better satisfying data reading requirements of tasks.

Description

Data reading method for chip, chip, computer device, storage medium and computer program product

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on the Chinese patent application with application number 202311809260.9, application date December 26, 2023, and invention name “Data reading method, chip, computer device and storage medium for chip”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this disclosure as a reference. Technical Field

[0003] The present disclosure relates to, but is not limited to, the field of computer technology, and in particular to a data reading method for a chip, a chip, a computer device, a storage medium, and a computer program product. Background Art

[0004] A cache module (Cache) is usually designed in the processor to make the speed of data reading and writing adapt to the computing speed of the computing module in the processor, thereby improving system performance. In the related art, most processors use data prefetching technology to predict future memory accesses and issue access requests for corresponding memory blocks before explicit access, so as to fetch the data in the memory blocks into the cache module in advance, thereby improving the cache hit rate. However, the data prefetching scheme adopted in the related art will increase the data request pressure between the request source and the cache module, affecting other normal memory access requests, and it is also difficult to flexibly control prefetching in some data prefetching schemes in the related art. Summary of the Invention

[0005] In view of this, the embodiments of the present disclosure at least provide a data reading method for a chip, a chip, a computer device, a storage medium, and a computer program product.

[0006] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0007] An embodiment of the present disclosure provides a data reading method for a chip, the method comprising:

[0008] Obtaining a read data instruction; the read data instruction is used to instruct data reading according to the read information and data prefetching according to the prefetch information;

[0009] Acquire a first read data request according to the read data instruction; the first read data request includes the read information and the pre-fetch information;

[0010] Sending the first read data request to a cache module, so that the cache module responds to the first read data request, reads and returns the first target data according to the read information, and pre-fetches and caches the second target data according to the pre-fetch information;

[0011] Receive the first target data returned by the cache module.

[0012] An embodiment of the present disclosure provides a data reading method for a chip, the method comprising:

[0013] receiving a first data read request sent by a request source, wherein the first data read request is used to request data reading according to read information and data prefetching according to prefetch information;

[0014] acquiring the read information and the prefetch information according to the first read data request;

[0015] Based on the read information, read the first target data from the storage space and / or memory of the cache module, and return the first target data to the request source;

[0016] Based on the prefetch information, second target data is prefetched from the memory, and the second target data is cached in at least one cache unit of the cache module.

[0017] An embodiment of the present disclosure provides a chip, comprising:

[0018] The computing module is configured to: obtain a read data instruction, wherein the read data instruction is used to instruct data reading according to the read information and data prefetching according to the prefetch information; obtain a first read data request according to the read data instruction, wherein the first read data request includes the read information and the prefetch information; send the first read data request to a cache module, so that the cache module responds to the first read data request by reading and returning first target data according to the read information and prefetching and caching second target data according to the prefetch information; and receive the first target data returned by the cache module;

[0019] The cache module is configured to: receive a first read data request sent by the computing module, the first read data request being used to request data reading according to read information and data prefetching according to prefetch information; obtain the read information and the prefetch information according to the first read data request; read first target data from the storage space and / or memory of the cache module based on the read information, and return the first target data to the computing module; prefetch second target data from the memory based on the prefetch information, and cache the second target data in at least one cache unit of the cache module.

[0020] An embodiment of the present disclosure provides a computer device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, some or all of the steps in the above method are implemented, or the processor includes the above chip.

[0021] An embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, some or all of the steps in the above method are implemented.

[0022] An embodiment of the present disclosure provides a computer program product, including a computer program or instructions. When the computer program or instructions are executed by a processor, some or all of the steps in the above method are implemented.

[0023] In the embodiment of the present disclosure, a read data instruction is obtained, the read data instruction is used to instruct data reading according to read information and data prefetching according to prefetch information; a first read data request is obtained according to the read data instruction, the first read data request containing the read information and the prefetch information; the first read data request is sent to the cache module, so that the cache module responds to the first read data request, reads and returns the first target data according to the read information, and prefetches and caches the second target data according to the prefetch information; and the first target data returned by the cache module is received. In this way, the request source of the read data request can send the prefetch information along with the read data request to the cache module, so that data reading and prefetching can be achieved through a single read data request. Therefore, on the one hand, the data request pressure between the request source and the cache module can be reduced, the request bandwidth can be compressed, and the processor performance can be improved. On the other hand, the prefetch information contained in the read data request can be used to control data prefetching, which can facilitate flexible control of the prefetching method task by task to better meet the data reading requirements of each task.

[0024] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0026] FIG1 is a schematic diagram of an implementation flow of a data reading method provided by an embodiment of the present disclosure;

[0027] FIG2 is a schematic diagram of an implementation flow of a data reading method provided by an embodiment of the present disclosure;

[0028] FIG3 is a schematic diagram of an implementation flow of a data reading method provided by an embodiment of the present disclosure;

[0029] FIG4 is a schematic diagram of an implementation flow of a data reading method provided by an embodiment of the present disclosure;

[0030] FIG5A is a schematic diagram of an implementation architecture of a data cache provided by an embodiment of the present disclosure;

[0031] FIG5B is a schematic diagram of the interaction between modules in a data reading method provided by an embodiment of the present disclosure;

[0032] FIG5C is a schematic diagram illustrating an implementation of a read data request carrying a pre-fetched data length provided by an embodiment of the present disclosure;

[0033] FIG6 is a schematic diagram of the composition structure of a chip provided in an embodiment of the present disclosure;

[0034] FIG7 is a schematic diagram of a hardware entity of a computer device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0036] In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. The terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understood that the specific order or sequence of "first / second / third" may be interchanged where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure pertains. The terms used herein are for the purpose of describing the present disclosure only and are not intended to limit the present disclosure.

[0038] The present disclosure provides a data reading method, which can be applied to a chip, for example, it can be executed by a cache module in the chip. The chip can be, for example, at least one of a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a data processing unit (DPU) chip, etc. The chip can be used in any suitable computer device, and the computer device can refer to a server, a laptop computer, a tablet computer, a desktop computer, a smart TV, a set-top box, a mobile device (such as a mobile phone, a portable video player, a personal digital assistant, a dedicated messaging device, a portable gaming device), and other devices with data processing capabilities.

[0039] FIG1 is a schematic diagram of an implementation flow of a data reading method provided by an embodiment of the present disclosure. As shown in FIG1 , the method includes the following steps S101 to S104:

[0040] Step S101 : receiving a first data read request sent by a request source, wherein the first data read request is used to request data reading according to read information and data prefetching according to prefetch information.

[0041] Step S102: Acquire the read information and the pre-fetch information according to the first data read request.

[0042] Here, the request source may include but is not limited to at least one of a computing module in a chip, an upstream cache module of a cache module currently to read data, and the like.

[0043] In some embodiments, a cache module in the chip (referred to as the current cache module) may receive the first read data request, and the request source may send at least one first read data request to the current cache module as needed. For example, when the request source is a computing module, the computing module may generate a first read data request after parsing the read data instruction in the task, and send the first read data request to the cache module. For another example, when the request source is an upstream cache module of the current cache module, the upstream cache module may send at least one first read data request to the current cache module according to the upstream read data request when the cache unit corresponding to the received upstream read data request is missing.

[0044] In some embodiments, the first read data request may include read information and prefetch information. After receiving the first read data request sent by the request source, the first read data request may be parsed to obtain the read information and prefetch information corresponding to the first read data request. The read information may include any suitable information indicating data reading, for example, the read information may include but is not limited to at least one of the first read request address, the first read data length, etc. The first read request address is the starting address of the data to be requested to be read corresponding to the first read data request. The first read data length refers to the length of the data to be requested to be read. The prefetch information may include any suitable information indicating data prefetching, for example, the prefetch information may include but is not limited to at least one of whether to prefetch data, the length of prefetched data, etc.

[0045] During implementation, the first data read request may be parsed in any appropriate parsing manner according to actual circumstances, and the embodiments of the present disclosure are not limited thereto.

[0046] In some embodiments, the first read data request may include a read request address signal, a read data length signal, and a prefetch control signal. Parsing the read request address signal can obtain the first read request address, parsing the read data length signal can obtain the first read data length, and parsing the prefetch control signal can obtain prefetch information. During implementation, a correspondence between multiple prefetch control signals and prefetch information can be pre-set, and the prefetch information corresponding to the prefetch control signal in the first read data request can be determined based on the correspondence. Those skilled in the art can set a suitable correspondence between the prefetch control signal and the prefetch information according to actual conditions, and the embodiments of the present disclosure are not limited to this.

[0047] In some embodiments, the prefetch information includes a prefetch switch state indicating whether data prefetching is to be performed, and the prefetch switch state can be indicated by the value of a prefetch control signal. For example, when the prefetch control signal is 0'b0, the prefetch switch state can be determined to be an off state indicating that data prefetching is not to be performed, and when the prefetch control signal is 0'b1, the prefetch switch state can be determined to be an on state indicating that data prefetching is to be performed. When the prefetch switch state is an on state indicating that data prefetching is to be performed, the prefetched data length can be a default value or can be controlled by other signals, which is not limited here.

[0048] In some embodiments, the prefetch information includes the prefetch data length, and the prefetch data length can be indicated by the value of the prefetch control signal. For example, when the prefetch control signal is 0'b0, the prefetch data length can be determined to be 0, and when the prefetch control signal is 0'b1, the prefetch data length can be determined to be 1 cache unit. For another example, when the prefetch control signal is 0'b00, the prefetch data length can be determined to be 0, when the prefetch control signal is 0'b01, the prefetch data length can be determined to be 1 cache unit, when the prefetch control signal is 0'b10, the prefetch data length can be determined to be 2 cache units, and when the prefetch control signal is 0'b11, the prefetch data length can be determined to be 3 cache units.

[0049] In some embodiments, the first read data request may include a request type signal, a read request address signal, and a read data length signal. Parsing the read request address signal may obtain the first read request address, parsing the read data length signal may obtain the first read data length, and parsing the request type signal may obtain pre-fetch information. During implementation, a plurality of request type signals may be pre-defined, and the request types indicated by different request type signals may correspond to different pre-fetch information, so that the corresponding pre-fetch information may be determined based on the request type signal in the first read data request. Those skilled in the art may define appropriate request type signals, and the correspondence between the request types indicated by each request type signal and the pre-fetch information according to actual conditions, and the embodiments of the present disclosure do not limit this.

[0050] In some embodiments, the prefetch information includes a prefetch switch state indicating whether data prefetching is to be performed. The request type may be indicated by the value of a request type signal, and the prefetch switch state may be determined based on the request type. For example, when the request type signal is 0'b101, the request type may be determined to be a read-only type, i.e., only data reading is performed without data prefetching, and the prefetch switch state is thus in the off state, indicating that data prefetching is not performed. When the request type signal is 0'b110, the request type may be determined to be a read-with-prefetch type, i.e., both data reading and data prefetching are performed, and the prefetch switch state is thus in the on state, indicating that data prefetching is performed.

[0051] In some embodiments, the prefetch information includes the prefetch data length. The request type can be indicated by the value of the request type signal, and the prefetch data length can be determined based on the request type. For example, when the request type signal is 0'b101, the request type can be determined to be a read-only type, thereby determining the prefetch data length to be 0. When the request type signal is 0'b110, the request type can be determined to be a read type with a prefetch of 1 cache unit, thereby determining the prefetch data length to be 1 cache unit. When the request type signal is 0'b111, the request type can be determined to be a read type with a prefetch of 4 cache units, thereby determining the prefetch data length to be 4 cache units.

[0052] Step S103: Based on the read information, read the first target data from the storage space and / or memory of the cache module, and return the first target data to the request source.

[0053] Here, based on the read information, a cache unit hit detection can be performed in the storage space of the cache module. If the cache unit corresponding to the read information hits, the first target data is obtained from the cache unit; if the cache unit corresponding to the read information is missing, the first target data is obtained from the memory based on the read information.

[0054] In some embodiments, when the read information includes a first read request address and a first read data length, a cache unit hit detection can be performed in the storage space of the cache module based on the first read request address and the first read data length. If the cache unit corresponding to the first read request address and the first read data length hits, the first target data is obtained from the cache unit; if the cache unit corresponding to the first read request address and the first read data length is missing, the first target data is obtained from the memory based on the first read request address and the first read data length.

[0055] Step S104 : pre-fetching second target data from the memory based on the pre-fetch information, and caching the second target data into at least one cache unit of the cache module.

[0056] Here, a prefetch start address and a prefetch data length can be determined based on the prefetch information, so that the second target data can be prefetched from the memory based on the prefetch start address and the prefetch data length, and the second target data can be cached in at least one cache unit of the cache module. The cache unit can include but is not limited to a cache block, a cache sector, etc.

[0057] In some embodiments, the prefetch start address and the prefetch data length can be determined based on the prefetch information, so that a cache unit hit detection can be performed in the storage space of the cache module based on the prefetch start address and the prefetch data length. If the cache unit corresponding to the prefetch start address and the prefetch data length is missing, the second target data is prefetched from the memory and cached in at least one cache unit of the cache module; if the cache unit corresponding to the prefetch start address and the prefetch data length hits, the second target data does not need to be prefetched from the memory.

[0058] It can be understood that the first target data is the data requested to be read by the first read data request, and the second target data is the data requested to be pre-fetched by the first read data request. During the current request process, the first target data will be returned to the request source, and the second target data will be cached in at least one cache unit of the cache module. In subsequent read data requests, if the second target data is requested to be read, the cached second target data can be read directly from the cache module. In this way, the cache hit rate can be improved, thereby improving the efficiency of data reading.

[0059] In an embodiment of the present disclosure, a first read data request sent by a request source is received, and the first read data request is used to request data reading according to read information and data prefetching according to prefetch information; according to the first read data request, read information and prefetch information are obtained; based on the read information, first target data is read from the storage space and / or memory of the cache module, and the first target data is returned to the request source; based on the prefetch information, second target data is prefetched from the memory, and the second target data is cached in at least one cache unit of the cache module. In this way, the request source can send the prefetch information along with the read data request to the cache module, so that data reading and prefetching can be achieved through a single read data request. Therefore, on the one hand, the data request pressure between the request source and the cache module can be reduced, the request bandwidth can be compressed, and the processor performance can be improved. On the other hand, the prefetch information obtained from the read data request can be used to control data prefetching, and then it can be convenient to flexibly control the prefetching method task by task to better meet the data reading requirements of each task.

[0060] In some embodiments, the above steps S101 to S104 can be executed by a cache module in the chip; the first target data includes at least one first sub-target data, and the cache module includes a first cache sub-module and a second cache sub-module.

[0061] The above step S101 may include the following step S111:

[0062] Step S111: the first cache submodule receives a first data read request sent by a request source.

[0063] The above step S102 may include the following step S112:

[0064] Step S112: the first cache submodule obtains the read information and the prefetch information according to the first read data request; the read information includes a first read request address and a first read data length.

[0065] The above step S103 may include the following steps S113 to S114:

[0066] Step S113: The first cache submodule determines at least one read data subrequest based on the first read request address and the first read data length, and the data request length corresponding to each read data subrequest is equal to the cache unit length of the first cache submodule.

[0067] Here, the first read request address and the first read data length may correspond to one read data sub-request or to multiple read data sub-requests. The data request length corresponding to each read data sub-request is equal to the cache unit length of the first cache sub-module. That is, the requested data volume corresponding to each read data sub-request is aligned according to the cache unit length of the first cache sub-module.

[0068] In some embodiments, the first read data length is smaller than the cache unit length of the first cache submodule, indicating that the amount of data in the first read data request is less than one cache unit. The first read request address and the first read data length can be aligned according to the cache unit length to obtain a read data subrequest having a data request length equal to the cache unit length of the first cache submodule.

[0069] In some embodiments, the first read data length is equal to the cache unit length of the first cache submodule, indicating that the data amount of the first read data request corresponds to a cache unit, and a read data sub-request can be obtained directly based on the first read request address and the first read data length.

[0070] In some embodiments, the first read data length is greater than the cache unit length of the first cache sub-module, indicating that the data amount of the first read data request exceeds one cache unit. The first read request address and the first read data length can be split and aligned according to the cache unit length to obtain multiple read data sub-requests, and the data request length corresponding to each read data sub-request is equal to the cache unit length of the first cache sub-module.

[0071] Step S114, the first cache sub-module obtains the first sub-target data corresponding to each of the read data sub-requests from the storage space of the first cache sub-module, the storage space of the second cache sub-module, and / or the memory, and returns each of the first sub-target data to the request source.

[0072] The above step S104 may include the following step S115:

[0073] Step S115 : The second cache submodule pre-fetches second target data from the memory based on the pre-fetch information, and caches the second target data in at least one cache unit of the second cache submodule.

[0074] In the above embodiment, the cache module includes a first cache submodule and a second cache submodule. The first cache submodule, in response to receiving a first read data request sent by a request source, parses the first read data request to obtain a first read request address, a first read data length, and prefetch information. The first cache submodule determines at least one read data subrequest based on the first read request address and the first read data length, where the data request length corresponding to each read data subrequest is equal to the length of a cache unit of the first cache submodule. The first cache submodule retrieves the first subtarget data corresponding to each read data subrequest from the storage space of the first cache submodule, the storage space of the second cache submodule, and / or the memory, and returns each first subtarget data to the request source. The second cache submodule prefetches the second target data from the memory based on the prefetch information and caches the second target data into at least one cache unit of the second cache submodule. In this way, in a cache module including multi-level caches, data reading and prefetching can be simply and quickly achieved through a single read data request from the request source.

[0075] In some embodiments, the first cache submodule in step S114 obtains the first sub-target data corresponding to each of the read data sub-requests from the storage space of the first cache submodule, the storage space of the second cache submodule, and / or the memory, which may include the following steps S121 to S122:

[0076] In step S121 , the first cache submodule performs cache unit hit detection in the storage space of the first cache submodule based on each of the read data subrequests, and obtains a second detection result corresponding to each of the read data subrequests.

[0077] Step S122, for each of the read data sub-requests, when the second detection result corresponding to the read data sub-request indicates that the cache unit corresponding to the read data sub-request is hit, the first cache sub-module reads the first sub-target data corresponding to the read data sub-request from the hit cache unit, and when the second detection result corresponding to the read data sub-request indicates that the cache unit corresponding to the read data sub-request is missing, the first cache sub-module sends a second read data request to the second cache sub-module based on the second read request address and second read data length corresponding to the read data sub-request, and the prefetch information, and receives the first sub-target data corresponding to the read data sub-request returned by the second cache sub-module.

[0078] Here, the second read request address corresponding to the read data sub-request refers to the starting address of the data requested by the read data sub-request, and the second read data length corresponding to the read data sub-request refers to the length of the data requested by the read data sub-request.

[0079] If the second detection result corresponding to the read data sub-request indicates that the cache unit corresponding to the read data sub-request is missing, a second read data request can be generated based on the second read request address and second read data length corresponding to the read data sub-request, as well as the prefetch information, and sent to the second cache sub-module. During implementation, those skilled in the art can use any appropriate method to generate the second read data request based on the second read request address and second read data length corresponding to the read data sub-request, as well as the prefetch information, according to actual circumstances. The presently disclosed embodiments are not limited to this.

[0080] In some embodiments, a read request address signal, a read data length signal, and a request type signal may be determined based on the second read request address, the second read data length, and the prefetch information, respectively. A second read data request may be generated based on the read request address signal, the read data length signal, and the request type signal. For example, the second read request address may be encoded as a read request address signal in the second read data request, the second read data length may be encoded as a read data length signal in the second read data request, and based on a correspondence between a request type indicated by a preset request type signal and the prefetch information, a request type signal corresponding to the prefetch information may be determined, and the request type signal may be used as the request type signal for the second read data request.

[0081] In some embodiments, a read request address signal, a read data length signal, and a prefetch control signal may be determined based on the second read request address, the second read data length, and the prefetch information, and a second read data request may be generated based on the read request address signal, the read data length signal, and the prefetch control signal. For example, a prefetch control signal corresponding to the prefetch information may be determined based on a predetermined correspondence between the prefetch control signal and the prefetch information.

[0082] The second cache submodule in the above step S115 pre-fetches the second target data from the memory based on the pre-fetch information, which may include the following steps S123 to S125:

[0083] Step S123 : In response to receiving the second read data request sent by the first cache submodule, the second cache submodule parses the second read data request to obtain a second read request address, a second read data length, and the prefetch information.

[0084] Step S124, the second cache submodule obtains the first sub-target data from the storage space and / or memory of the second cache submodule based on the second read request address and the second read data length, and returns the first sub-target data to the first cache submodule.

[0085] In step S125 , the second cache submodule pre-fetches second target data from the memory based on the pre-fetch information, and caches the second target data in at least one cache unit of the second cache submodule.

[0086] Here, steps S123 to S125 correspond to steps S101 to S104 in the aforementioned embodiment, respectively. When implementing, reference may be made to the implementation of the aforementioned steps S101 to S104.

[0087] In the above embodiment, for each read data subrequest, if the second detection result corresponding to the read data subrequest indicates a hit in the cache unit corresponding to the read data subrequest, the first cache submodule reads the first subtarget data corresponding to the read data subrequest from the hit cache unit. If the second detection result corresponding to the read data subrequest indicates a miss in the cache unit corresponding to the read data subrequest, the first cache submodule sends a second read data request to the second cache submodule based on the second read request address and second read data length corresponding to the read data subrequest, as well as the prefetch information. In response to receiving the second read data request sent by the first cache submodule, the second cache submodule parses the second read data request to obtain the second read request address, second read data length, and the prefetch information. In this way, if a portion of the read data subrequest corresponding to the first read data request does not hit a cache unit in the first cache submodule, the prefetch information can be carried to the second cache submodule via the second read data request corresponding to the portion of the read data subrequest. This can reduce the data request pressure between the request source and the first cache submodule in a cache module including a multi-level cache, reduce request bandwidth usage, and improve processor performance.

[0088] In some embodiments, when all cache units corresponding to read data sub-requests are hit, the pre-fetch information can be discarded, that is, the pre-fetch information is not sent to the second cache sub-module. In this way, since all cache units corresponding to read data sub-requests are hit, the data request pressure between the first cache sub-module and the second cache sub-module can be reduced, thereby reducing the situation where the request bandwidth between the first cache sub-module and the second cache sub-module becomes a memory access bottleneck. Usually, the request bandwidth between the request source and the first cache sub-module is not less than the request bandwidth between the first cache sub-module and the second cache sub-module, thereby also reducing the situation where the request bandwidth between the first cache sub-module and the second cache sub-module becomes a memory access bottleneck. In this way, the request source can pre-fetch the data corresponding to the discarded pre-fetch information by sending a separate pre-fetch request to the first cache sub-module, so as to reduce the processing resources occupied by the second cache sub-module for processing the pre-fetch information carried by the read request. In addition, when the scenario where prefetching is used is a cyclic calculation scenario, there is usually no overlap in the data requested during each cyclic calculation process, and the data corresponding to the prefetch information is usually missing in the case of the first request. Therefore, the prefetch information carried in the first read data request for the data, which is used to prefetch the next data to be prefetched, will usually be carried to the second cache sub-module.

[0089] The present disclosure provides a data reading method that can be applied to a chip, for example, it can be executed by a cache module in the chip. FIG2 is a schematic diagram of an implementation flow of a data reading method provided by the present disclosure. As shown in FIG2 , the method includes the following steps S201 to S205:

[0090] Step S201 : receiving a first data read request sent by a request source, wherein the first data read request is used to request data reading according to read information and data prefetching according to prefetch information.

[0091] Step S202: Acquire the read information and the pre-fetch information according to the first read data request; wherein the pre-fetch information includes the pre-fetch data length.

[0092] Step S203: Based on the read information, read the first target data from the storage space and / or memory of the cache module, and return the first target data to the request source.

[0093] Here, steps S201 to S203 may respectively correspond to steps S101 to S103 in the aforementioned embodiment, and reference may be made to the implementation of the aforementioned steps S101 to S103 during implementation.

[0094] Step S204 : When the pre-fetched data length is greater than 0, determine a pre-fetch start address based on the first read request address and the first read data length.

[0095] Here, the prefetch start address is a start address for data prefetching.

[0096] In some implementations, the first read request address may be added to the first read data length to obtain a prefetch start address.

[0097] In some embodiments, the first read request address and the first read data length can be aligned according to the cache unit length in the cache module to obtain the aligned first read request address and the first read data length, and the aligned first read request address is added to the aligned first read data length to obtain the prefetch start address.

[0098] Step S205 : prefetching second target data from the memory based on the prefetch start address and the prefetch data length, and caching the second target data into at least one cache unit of the cache module.

[0099] In the disclosed embodiment, when the prefetched data length is greater than 0, a prefetch start address is determined based on the first read request address and the first read data length. Second target data is then prefetched from the memory based on the prefetch start address and the prefetched data length, and the second target data is cached in at least one cache unit of the cache module. In this way, whether data prefetching is performed can be simply and conveniently controlled based on whether the prefetched data length is greater than 0. Furthermore, when the prefetched data length is greater than 0, the prefetched second target data can be controlled based on the prefetched data length, thereby flexibly meeting the data reading requirements of various tasks.

[0100] In some embodiments, the read information includes a first read request address and a first read data length. The above step S202 may include the following steps S211 to S212:

[0101] Step S211 , respectively analyzing the request type signal, the read request address signal, and the read data length signal in the first read data request to obtain the first request type, the first read request address, and the first read data length.

[0102] Here, the first read data request sent by the request source to the cache module may include a request type signal, a read request address signal, and a read data length signal, wherein the request type signal is used to indicate the request type of the first read data request, the read request address signal is used to indicate the starting address of the data to be requested to be read corresponding to the first read data request, and the read data length signal is used to indicate the length of the data to be requested to be read. Therefore, by respectively parsing the request type signal, the read request address signal, and the read data length signal in the first read data request, the first request type, the first read request address, and the first read data length of the first read data request can be obtained.

[0103] Step S212: Determine the pre-fetched data length based on the first request type.

[0104] Here, multiple request types can be predefined, and different request types can correspond to different pre-fetched data lengths, so that the corresponding pre-fetched data length can be determined based on the first request type. During implementation, those skilled in the art can define the corresponding relationship between each request type and the pre-fetched data length based on actual circumstances, and the embodiments of the present disclosure are not limited to this.

[0105] For example, when the request type signal is 0'b101, the first request type is determined to be a read-only type, thereby determining the pre-fetched data length to be 0; when the request type signal is 0'b110, the first request type is determined to be a read and pre-fetch type of 1 cache unit, thereby determining the pre-fetched data length to be 1 cache unit; when the request type signal is 0'b111, the first request type is determined to be a read and pre-fetch type of 4 cache units, thereby determining the pre-fetched data length to be 4 cache units.

[0106] In the above embodiment, the request type signal, the read request address signal, and the read data length signal in the first read data request are parsed separately to obtain the first request type, the first read request address, and the first read data length of the first read data request, and the pre-fetched data length is determined based on the first request type. In this way, the pre-fetched data length can be determined simply and quickly based on the request type.

[0107] In some embodiments, the read information includes a first read request address and a first read data length. The above step S202 may include the following step S221:

[0108] Step S221 , respectively analyzing the read request address signal, the read data length signal, and the prefetch control signal in the first read data request to obtain the first read request address, the first read data length, and the prefetch data length.

[0109] Here, the first read data request may include a read request address signal, a read data length signal and a prefetch control signal. The first read request address can be obtained by parsing the read request address signal, the first read data length can be obtained by parsing the read data length signal, and the prefetch control signal can be parsed to obtain the prefetch data length. During implementation, a correspondence between multiple prefetch control signals and prefetch data lengths can be pre-set, and the prefetch data length corresponding to the prefetch control signal in the first read data request can be determined based on the correspondence. Those skilled in the art can set a suitable correspondence between the prefetch control signal and the prefetch data length according to actual conditions, and the embodiments of the present disclosure are not limited to this. For example, when the prefetch control signal is 0'b0, the prefetch data length can be determined to be 0, and when the prefetch control signal is 0'b1, the prefetch data length can be determined to be 1 cache unit.

[0110] In the above embodiment, the read request address signal, the read data length signal, and the prefetch control signal in the first read data request are parsed separately to obtain the first read request address, the first read data length, and the prefetch data length of the first read data request. In this way, the prefetch data length can be determined simply and quickly using the prefetch control signal.

[0111] In some embodiments, the above step S205 may include the following steps S231 to S232:

[0112] Step S231 : determining at least one prefetch sub-request based on the prefetch start address and the prefetch data length, wherein the data request length corresponding to each prefetch sub-request is equal to the cache unit length of the cache module.

[0113] Here, the prefetch start address and the prefetch data length may correspond to one prefetch sub-request or multiple prefetch sub-requests. The data request length corresponding to each prefetch sub-request is equal to the cache unit length of the first cache sub-module. That is, the requested data volume corresponding to each prefetch sub-request is aligned according to the cache unit length of the first cache sub-module.

[0114] In some embodiments, the prefetched data length is smaller than the cache unit length of the first cache submodule, indicating that the amount of data requested to be prefetched by the first read data request is less than one cache unit. The prefetch start address and the prefetched data length can be aligned according to the cache unit length to obtain a prefetch sub-request whose data request length is equal to the cache unit length of the first cache submodule.

[0115] In some embodiments, the first read data length is equal to the cache unit length of the first cache submodule, indicating that the amount of data requested to be pre-fetched by the first read data request corresponds to a cache unit, and a pre-fetch sub-request can be obtained directly based on the pre-fetch start address and the pre-fetch data length.

[0116] In some embodiments, the first read data length is greater than the cache unit length of the first cache sub-module, indicating that the amount of data requested to be pre-fetched by the first read data request exceeds one cache unit. The pre-fetch start address and the pre-fetch data length can be split and aligned according to the cache unit length to obtain multiple pre-fetch sub-requests, and the data request length corresponding to each pre-fetch sub-request is equal to the cache unit length of the first cache sub-module.

[0117] In step S232, for each of the prefetch sub-requests, a cache unit hit detection is performed in the storage space of the cache module based on the prefetch sub-request to obtain a first detection result. When the first detection result indicates that the cache unit corresponding to the prefetch sub-request is missing, the second target data is prefetched from the memory based on the prefetch sub-request, and the second target data is cached in at least one cache unit of the cache module.

[0118] In the above embodiment, a cache hit check can be performed for each prefetch sub-request. If the cache unit corresponding to the prefetch sub-request is missing, the second target data is prefetched from the memory based on the prefetch sub-request. In this way, data prefetching is performed at the granularity of prefetch sub-requests, which can improve the flexibility of controlling data prefetching.

[0119] In some embodiments, the pre-fetched data length is an integer multiple of the length of a cache unit, and the cache unit includes a cache block or a cache sector. In this way, a cache module with a corresponding cache unit granularity can be better adapted.

[0120] The present disclosure provides a data reading method that can be applied to a chip, for example, it can be executed by a cache module in the chip. FIG3 is a schematic diagram of an implementation flow of a data reading method provided by the present disclosure. As shown in FIG3 , the method includes the following steps S301 to S306:

[0121] Step S301 : receiving a plurality of first read data requests sent by a request source, wherein the first read data requests are used to request data reading according to read information corresponding to the first read data requests and data prefetching according to prefetch information corresponding to the first read data requests.

[0122] Step S302 : acquiring read information corresponding to each first read data request and prefetch information corresponding to the first read data request according to each first read data request; wherein the read information includes a first read request address and a first read data length.

[0123] Here, steps S301 and S302 correspond to steps S101 and S102 in the aforementioned embodiment, respectively. When implementing, reference may be made to the implementation of the aforementioned steps S101 and S102.

[0124] Step S303 : for each first read data request, determining a cache unit corresponding to the first read data request based on a first read request address and a first read data length corresponding to the first read data request.

[0125] Here, the cache unit corresponding to the first read data request may be obtained by mapping based on the first read request address and the first read data length corresponding to the first read data request.

[0126] In step S304, when the cache units corresponding to the multiple first read data requests overlap, the first read request addresses and first read data lengths corresponding to the multiple first read data requests are merged to obtain the merged first read request address and first read data length, and the prefetch information corresponding to the multiple first read data requests is merged to obtain the merged prefetch information.

[0127] Here, the first read request address and the first read data length corresponding to each first read data request may respectively determine an address interval.

[0128] In some embodiments, the union of the address intervals corresponding to the first read data requests can be determined as the target address interval, the starting address of the target address interval can be determined as the merged first read request address, and the length of the target address interval can be determined as the merged first read data length.

[0129] In some embodiments, the address intervals corresponding to each first read data request can be aligned according to the length of the cache unit in the cache module, and the union of the aligned address intervals can be determined as the target address interval. The starting address of the target address interval is then determined as the merged first read request address, and the length of the target address interval is determined as the merged first read data length.

[0130] Step S305 : Based on the combined first read request address and the first read data length, obtain first target data from the storage space and / or memory of the cache module, and return the first target data to the request source.

[0131] Step S306 : pre-fetching second target data from the memory based on the combined pre-fetch information, and caching the second target data into at least one cache unit of the cache module.

[0132] Here, steps S305 to S306 correspond to steps S103 to S104 in the aforementioned embodiment, respectively. When implementing, reference may be made to the implementation of the aforementioned steps S103 to S104.

[0133] In an embodiment of the present disclosure, for multiple received first read data requests, when the cache units corresponding to the multiple first read data requests overlap, the first read request addresses and first read data lengths corresponding to the multiple first read data requests can be merged to obtain merged first read request addresses and first read data lengths, and the prefetch information corresponding to the multiple first read data requests can be merged to obtain merged prefetch information. In this way, the second target data can be prefetched from the memory based on the merged prefetch information, thereby reducing the number of data prefetches from the memory, and further reducing the number of data requests between the cache module and the memory, further improving processor performance.

[0134] In some embodiments, the step S304 of merging the prefetch information corresponding to the plurality of first read data requests to obtain merged prefetch information includes the following step S311:

[0135] Step S311 : determining prefetch information corresponding to a first read data request with a latest first read request address among the multiple first read data requests as merged prefetch information.

[0136] Here, because the cache units corresponding to multiple first read data requests overlap, the data to be prefetched indicated by the prefetch information corresponding to a first read data request may overlap with the data requested to be read by other first read data requests whose first read request addresses are subsequent to the first read request address corresponding to the first read data request. Therefore, the prefetch information corresponding to the first read data request with the latest first read request address among the multiple first read data requests can be determined as the merged prefetch information. This can reduce unnecessary data prefetching and further improve processor performance.

[0137] The present disclosure provides a data reading method that can be applied to a chip. FIG4 is a schematic diagram of an implementation flow of a data reading method provided by the present disclosure. As shown in FIG4 , the method includes the following steps S401 to S404:

[0138] Step S401 , obtaining a read data instruction; the read data instruction is used to instruct to read data according to the read information and to prefetch data according to the prefetch information.

[0139] Here, the data read instruction may be an instruction for reading data in a task currently executed by a computing module in the chip. During implementation, those skilled in the art may set an appropriate data read instruction according to the task actually executed.

[0140] In some embodiments, a read data instruction may be generated by application software and sent to a computing module in the chip, instructing the computing module to read data according to the read data instruction and to prefetch data according to the prefetch information. The read information and prefetch information may be determined by the application software based on actual data reading requirements.

[0141] In some embodiments, a data read instruction may be generated by a computing module in the chip and then sent to another computing module to instruct the other computing module to read data according to the read instruction and to prefetch data according to the prefetch information. The read information and prefetch information may be determined by the computing module based on actual data reading requirements.

[0142] Step S402 : obtaining a first read data request according to the read data instruction; the first read data request includes the read information and the pre-fetch information.

[0143] Here, the read data instruction can be parsed to obtain read information and prefetch information corresponding to the read data instruction, and a first read data request can be generated based on the read information and prefetch information. During implementation, any appropriate parsing method can be used to parse the read data instruction according to actual circumstances, and the embodiments of the present disclosure are not limited to this.

[0144] In some implementations, the read data instruction may include a read control code and a prefetch control code. Parsing the read control code may obtain read information, and parsing the prefetch control code may obtain prefetch information.

[0145] In some embodiments, the read data instruction may include a read request address code, a read data length code, and a prefetch control code. Parsing the read request address code can obtain a first read request address, parsing the read data length code can obtain a first read data length, and parsing the prefetch control code can obtain prefetch information. During implementation, a correspondence between multiple prefetch control codes and prefetch information can be pre-set, and the prefetch information corresponding to the prefetch control code in the read data instruction can be determined based on the correspondence. Those skilled in the art can set a suitable correspondence between the prefetch control code and the prefetch information according to actual conditions, and the embodiments of the present disclosure are not limited to this.

[0146] In some embodiments, the prefetch information includes a prefetch switch state indicating whether data prefetching is to be performed, and the prefetch switch state can be indicated by a prefetch control code. For example, when the prefetch control code is 0'b0, the prefetch switch state can be determined to be an off state indicating that data prefetching is not to be performed, and when the prefetch control code is 0'b1, the prefetch switch state can be determined to be an on state indicating that data prefetching is to be performed. When the prefetch switch state is an on state indicating that data prefetching is to be performed, the prefetched data length can be a default value or can be controlled by other bit fields in the read data instruction, which is not limited here.

[0147] In some embodiments, the prefetch information includes the prefetch data length, and the prefetch data length can be indicated by a prefetch control code. For example, when the prefetch control code is 0'b0, the prefetch data length can be determined to be 0, and when the prefetch control code is 0'b1, the prefetch data length can be determined to be 1 cache unit. For another example, when the prefetch control code is 0'b00, the prefetch data length can be determined to be 0, when the prefetch control code is 0'b01, the prefetch data length can be determined to be 1 cache unit, when the prefetch control code is 0'b10, the prefetch data length can be determined to be 2 cache units, and when the prefetch control code is 0'b11, the prefetch data length can be determined to be 3 cache units.

[0148] In some embodiments, the read data instruction may include an instruction type code, a read request address code, and a read data length code. Parsing the read request address code may obtain a first read request address, parsing the read data length code may obtain a first read data length, and parsing the instruction type code may obtain prefetch information. During implementation, a plurality of instruction type codes may be predefined, the request type may be indicated by the instruction type code, and the request types indicated by different instruction type codes may correspond to different prefetch information, so that the corresponding prefetch information may be determined based on the instruction type code in the read data instruction. Those skilled in the art may define appropriate instruction type codes, and the correspondence between the request types indicated by each instruction type code and the prefetch information according to actual conditions, and the embodiments of the present disclosure do not limit this.

[0149] In some embodiments, the prefetch information includes a prefetch switch state indicating whether data prefetching is to be performed. The request type may be indicated by an instruction type code, and the prefetch switch state may be determined based on the request type. For example, when the instruction type code is 0'b101, the request type may be determined to be a read-only type, i.e., only data reading is performed without data prefetching, and the prefetch switch state is thus in the off state, indicating that data prefetching is not performed. When the instruction type code is 0'b110, the request type may be determined to be a read-with-prefetch type, i.e., both data reading and data prefetching are performed, and the prefetch switch state is thus in the on state, indicating that data prefetching is performed.

[0150] In some embodiments, the prefetch information includes the prefetch data length, and the request type can be indicated by the instruction type encoding, and the prefetch data length can be determined based on the request type. For example, when the instruction type encoding is 0'b101, the request type can be determined to be a read-only type, and the prefetch data length can be determined to be 0. When the instruction type encoding is 0'b110, the request type can be determined to be a read type with a prefetch of 1 cache unit, and the prefetch data length can be determined to be 1 cache unit. When the instruction type encoding is 0'b111, the request type can be determined to be a read type with a prefetch of 4 cache units, and the prefetch data length can be determined to be 4 cache units.

[0151] In some embodiments, the read information may be included in a read control signal in the first read data request, and the prefetch information may be included in a request type signal in the first read data request. The read control signal and the request type signal may be determined based on the read information and the prefetch information, respectively, and the first read data request may be generated based on the read control signal and the request type signal.

[0152] In some embodiments, the read information may be included in a read control signal in the first read data request, and the prefetch information may be included in a prefetch control signal in the first read data request. The read control signal and the prefetch control signal may be determined based on the read information and the prefetch information, respectively, and the first read data request may be generated based on the read control signal and the prefetch control signal.

[0153] Step S403 : sending the first read data request to the cache module, so that the cache module responds to the first read data request, reads and returns the first target data according to the read information, and prefetches and caches the second target data according to the prefetch information.

[0154] Step S404: receiving the first target data returned by the cache module.

[0155] In the embodiment of the present disclosure, a read data instruction is obtained, the read data instruction is used to instruct data reading according to the read information and data prefetching according to the prefetch information; a first read data request is obtained according to the read data instruction, the first read data request includes the read information and the prefetch information; the first read data request is sent to the cache module, so that the cache module responds to the first read data request, reads and returns the first target data according to the read information, and prefetches and caches the second target data according to the prefetch information; and the first target data returned by the cache module is received. In this way, the request source of the read data request can send the prefetch information along with the read data request to the cache module, so that data reading and prefetching can be achieved through a single read data request. Therefore, on the one hand, the data request pressure between the computing module and the cache module can be reduced, the request bandwidth can be compressed, and the processor performance can be improved. On the other hand, data prefetching can be controlled by parsing the prefetch information obtained from the read data instruction, realizing instruction-level prefetching control, thereby better meeting the data reading requirements of each task.

[0156] In some embodiments, the read information includes a first read request address and a first read data length. The above step S401 may include the following step S411:

[0157] Step S411 , performing instruction encoding according to the first read request address, the first read data length, and the prefetch information to obtain the read data instruction.

[0158] Here, the first read request address, the first read data length and the prefetch information may be encoded into a read data instruction by performing instruction encoding on the first read request address, the first read data length and the prefetch information, thereby obtaining the read data instruction simply and quickly.

[0159] In some embodiments, the read data instruction includes an instruction type code, a read request address code, and a read data length code. The above step S411 may include the following steps S421 to S423:

[0160] Step S421 : Determine the instruction type code corresponding to the prefetch information from a preset instruction type code set.

[0161] Step S422: Encode the first read request address to obtain the read request address code.

[0162] Step S423: Encode the first read data length to obtain the read data length code.

[0163] Here, the instruction type code set may include at least one pre-set instruction type code, and different instruction type codes may represent different request types. During implementation, those skilled in the art may pre-set an appropriate instruction type code set based on actual application scenarios, and the embodiments of the present disclosure are not limited thereto.

[0164] In the above embodiment, by encoding the prefetch information into the instruction type code, the occupation of the bit field in the read data instruction can be reduced, thereby simplifying the design of the instruction set.

[0165] In some embodiments, the above step S402 may include the following steps S431 to S432:

[0166] Step S431, respectively parsing the instruction type code, the read request address code, and the read data length code to obtain the prefetch information, the first read request address, and the first read data length;

[0167] Step S432 : Generate the first read data request according to the prefetch information, the first read request address, and the first read data length.

[0168] Here, the read data instruction may include an instruction type code, a read request address code, and a read data length code. Parsing the read request address code can obtain a first read request address, parsing the read data length code can obtain a first read data length, and parsing the instruction type code can obtain prefetch information. In some embodiments, the prefetch information includes the prefetch data length. During implementation, multiple instruction type codes can be predefined, and the request types indicated by different instruction type codes can correspond to different prefetch data lengths, so that the corresponding prefetch data length can be determined based on the instruction type code in the read data instruction.

[0169] In the above embodiment, the instruction type code, read request address code, and read data length code in the read data instruction are parsed separately to obtain prefetch information, a first read request address, and a first read data length. In this way, the prefetch information can be simply and quickly determined based on the request type, and the first read data request can be quickly generated based on the prefetch information, the first read request address, and the first read data length.

[0170] In some embodiments, the read data instruction includes a read request address code, a read data length code, and a pre-fetch control code. The above step S411 may include the following steps S441 to S443:

[0171] Step S441, encoding the first read request address to obtain the read request address code;

[0172] Step S442, encoding the first read data length to obtain the read data length code;

[0173] Step S443: Encode the prefetch information to obtain the prefetch control code.

[0174] It is understandable that the encoding method for the first read request address, the first read data length and the pre-fetch information may be any appropriate encoding method determined according to actual conditions, and the embodiments of the present disclosure are not limited thereto.

[0175] In this way, by encoding the prefetch information separately into the prefetch control code, there is no need to expand the existing instruction type code, thereby simplifying the encoding and decoding complexity of the instruction type code.

[0176] In some implementations, the prefetch information may include the prefetch data length, and the prefetch control code may be obtained by encoding the prefetch data length.

[0177] In some embodiments, the above step S402 may include the following steps S451 to S452:

[0178] Step S451 , respectively parsing the read request address code, the read data length code, and the prefetch control code to obtain the first read request address, the first read data length, and the prefetch information.

[0179] Step S452 : Generate the first read data request according to the prefetch information, the first read request address, and the first read data length.

[0180] Here, the read data instruction may include a read request address code, a read data length code, and a prefetch control code. Parsing the read request address code can obtain a first read request address, parsing the read data length code can obtain a first read data length, and parsing the prefetch control code can obtain prefetch information. In some embodiments, the prefetch information includes the prefetch data length. During implementation, a correspondence between multiple prefetch control codes and prefetch data lengths can be pre-set, and based on the correspondence, the prefetch data length corresponding to the prefetch control code in the read data instruction can be determined. For example, when the prefetch control code is 0'b0, the prefetch data length can be determined to be 0, and when the prefetch control code is 0'b1, the prefetch data length can be determined to be 1 cache unit.

[0181] In the above embodiment, the read request address code, read data length code, and prefetch control code in the read data instruction are parsed separately to obtain the first read request address, first read data length, and prefetch data length. In this way, the prefetch control code can be used to simply and quickly indicate prefetch information, thereby quickly generating a first read data request based on the prefetch information, the first read request address, and the first read data length.

[0182] In some embodiments, the above step S432 and / or step S452 may include the following step S461 or step S462:

[0183] Step S461, determine the read request address signal, the read data length signal and the request type signal respectively according to the first read request address, the first read data length and the pre-fetch information, and generate the first read data request according to the read request address signal, the read data length signal and the request type signal.

[0184] In some embodiments, the first read request address can be encoded as a read request address signal in the first read data request; the first read data length can be encoded as a read data length signal in the first read data request; and based on the correspondence between the request type indicated by a preset request type signal and the prefetch information, the request type signal corresponding to the prefetch information is determined, and the request type signal is used as the request type signal of the first read data request.

[0185] In some embodiments, the pre-fetch information includes the pre-fetch data length. Based on the correspondence between the request type indicated by a preset request type signal and the pre-fetch data length, a request type signal corresponding to the pre-fetch data length can be determined, and the request type signal can be used as the request type signal for the first read data request.

[0186] Step S462, determine the read request address signal, the read data length signal and the prefetch control signal respectively according to the first read request address, the first read data length and the prefetch information, and generate the first read data request according to the read request address signal, the read data length signal and the prefetch control signal.

[0187] In some implementations, the prefetch control signal corresponding to the prefetch information may be determined based on a preset correspondence between the prefetch control signal and the prefetch information.

[0188] In some embodiments, the prefetch information includes the prefetch data length, and the prefetch control signal corresponding to the prefetch data length may be determined based on a preset correspondence between the prefetch control signal and the prefetch data length.

[0189] In some embodiments, the above step S401 may include the following steps S471 to S473:

[0190] Step S471: Obtain the read data volume and estimated calculation duration of the current task.

[0191] Here, the calculation duration of the current task can be estimated to obtain the estimated calculation duration. During implementation, any suitable estimation method can be used to estimate the calculation duration of the current task, and the embodiments of the present disclosure are not limited to this.

[0192] In some implementations, the computational complexity of the current task may be determined, and the computational duration of the current task may be estimated based on the computational complexity to obtain an estimated computational duration.

[0193] The amount of data read for the current task refers to the amount of data required to read to execute the current task. In some embodiments, the amount of data read may be carried in the task information of the current task. In other embodiments, the amount of data read may be obtained by analyzing the data read requirements of the current task.

[0194] Step S472: determining the pre-fetch information according to the read data amount and the estimated calculation time.

[0195] In some embodiments, the time required to read data equal to the read data amount from the cache module is estimated to obtain an estimated reading time; and prefetch information is determined based on the relationship between the estimated reading time and the estimated calculation time.

[0196] Step S473: Determine the data read instruction according to the prefetch information.

[0197] It is understandable that since the amount of data read and the estimated calculation time of the current task can respectively reflect the data access time and data calculation time during the execution of the current task, data prefetching can improve the efficiency of the data reading process to a certain extent and reduce the time consumed in the data reading process. Therefore, based on the amount of data read and the estimated calculation time, it can be judged whether the execution scenario of the current task requires data reading accompanied by data prefetching operations. Thus, based on the amount of data read and the estimated calculation time, appropriate prefetching information can be determined for the execution scenario of the current task, and then appropriate data read instructions can be determined to better balance the calculation time and data access time consumed during the task execution process.

[0198] In some embodiments, the above step S472 may include the following steps S481 to S482:

[0199] Step S481, determining a first estimated reading duration corresponding to the read data amount when a data prefetching function is enabled, and a second estimated reading duration corresponding to the read data amount when the data prefetching function is disabled;

[0200] Step S482: determining the pre-fetch information according to the size relationship between the estimated calculation duration and the first estimated reading duration, and / or the size relationship between the estimated calculation duration and the second estimated reading duration.

[0201] Here, the case where the data prefetch function is enabled refers to the case where data is read while prefetching data, that is, the case where the prefetch information carried in the read data instruction indicates that data prefetching is to be performed. The case where the data prefetch function is disabled refers to the case where data is read without prefetching data, that is, the case where the prefetch information carried in the read data instruction indicates that data prefetching is not to be performed.

[0202] It is understandable that the first estimated reading time can reflect the data access time required to execute the current task when the data prefetch function is turned on, and the second estimated reading time can reflect the data access time required to execute the current task when the data prefetch function is turned off. Therefore, based on the relationship between the estimated calculation time and the first estimated reading time and / or the second estimated reading time, it can be determined whether the execution scenario of the current task is more suitable for turning on the data prefetch function or turning off the data prefetch function, so that appropriate prefetch information can be determined to balance the calculation time and data access time during task execution.

[0203] In some embodiments, the above step S482 may include: when the estimated calculation time is greater than the first estimated reading time and less than the second estimated reading time, determining that the prefetch information is the first prefetch information representing the activation of the data prefetch function.

[0204] In this way, since the estimated calculation time is greater than the first estimated reading time and less than the second estimated reading time, it indicates that the data access time required to execute the current task when the data prefetch function is turned on is less than the estimated calculation time of the current task, and the data access time required to execute the current task when the data prefetch function is turned off is greater than the estimated calculation time of the current task, so that in this scenario, turning on the data prefetch function can reduce the impact of data reading time on computing efficiency. Therefore, in this scenario, the prefetch information can be determined to be the first prefetch information that characterizes turning on the data prefetch function, so as to reduce the impact of data reading time on computing efficiency, thereby better balancing the computing time and data access time during task execution.

[0205] In some embodiments, the above-mentioned step S482 may include: when the estimated calculation duration is less than or equal to the first estimated reading duration, determining that the prefetch information is the first prefetch information representing the activation of the data prefetch function, or determining that the prefetch information is the second prefetch information representing the deactivation of the data prefetch function.

[0206] In this way, since the estimated calculation time is less than or equal to the first estimated reading time, it indicates that the data access time required to execute the current task when the data prefetch function is turned on is not less than the estimated calculation time of the current task. Therefore, in this scenario, turning on the data prefetch function can reduce the impact of data reading time on computing efficiency to a certain extent, but there will still be an impact on the overall task execution time due to the long data reading time. Therefore, in this scenario, the prefetch information can be determined to be the first prefetch information that represents the data prefetch function being turned on, so as to reduce the impact of data reading time on computing efficiency, thereby better balancing the computing time and data access time during task execution. The prefetch information can also be determined to be the second prefetch information that represents the data prefetch function being turned off, so as to simplify the data reading process.

[0207] In some embodiments, the above step S482 may include: when the estimated calculation duration is greater than or equal to the second estimated reading duration, determining that the prefetch information is second prefetch information indicating that the data prefetch function is disabled.

[0208] In this way, since the estimated calculation duration is greater than or equal to the second estimated read duration, it indicates that the data access time required to execute the current task when the data prefetch function is disabled does not exceed the estimated calculation duration of the current task. Therefore, in this scenario, disabling the data prefetch function will not affect the computing efficiency due to the data read time. Therefore, in this scenario, the prefetch information can be determined to be the second prefetch information indicating that the data prefetch function is disabled, so as to simplify the data reading process.

[0209] In some embodiments, the prefetch information includes a prefetch switch state. The first prefetch information may be an on state indicating that data prefetching is performed, and the second prefetch information may be an off state indicating that data prefetching is not performed.

[0210] In some implementations, the pre-fetch information includes the pre-fetch data length, the first pre-fetch information may be an integer greater than 0, and the first pre-fetch information may be 0.

[0211] It can be understood that when the prefetch information is the first prefetch information, the instruction type code or prefetch control code in the read data instruction indicates to turn on data prefetch; when the prefetch information is the second prefetch information, the instruction type code or prefetch control code in the read data instruction indicates to turn off data prefetch.

[0212] In some embodiments, the above step S481 may include the following steps S491 to S493:

[0213] In step S491, the delay of sending a single request to the cache module, the delay of the cache module returning a single data, the delay of the cache module sending a single request to the memory, and the delay of the memory returning a single data to the cache module are estimated to obtain a first estimated delay, a second estimated delay, a third estimated delay, and a fourth estimated delay, respectively.

[0214] Here, any appropriate method may be used to estimate the delay of sending a request to the cache module and the delay of the cache module returning data, and the embodiments of the present disclosure are not limited to this.

[0215] In some embodiments, the request source of the first read data request may be a computing module in the chip, and the first estimated delay, the second estimated delay, the third estimated delay, and the fourth estimated delay may be obtained by respectively performing statistics on the historical delay of the computing module sending a single request to the cache module, the historical delay of the cache module returning a single data to the computing module, the historical delay of the cache module sending a single request to the memory, and the historical delay of the memory returning a single data to the cache module.

[0216] In some embodiments, the delay for the computing module to send a single request to the cache module can be estimated based on the amount of data sent by the computing module to the cache module and the data bandwidth between the computing module and the cache module, thereby obtaining a first estimated delay; the delay for the cache module to return a single data to the computing module can be estimated based on the amount of data returned by the cache module to the computing module and the data bandwidth between the computing module and the cache module, thereby obtaining a second estimated delay; the delay for the cache module to send a single request to the memory can be estimated based on the amount of data sent by the cache module to the memory and the data bandwidth between the cache module and the memory, thereby obtaining a third estimated delay; the delay for the memory to return a single data to the cache module can be estimated based on the amount of data returned by the memory to the cache module and the data bandwidth between the cache module and the memory, thereby obtaining a fourth estimated delay.

[0217] Step S492: Determine the first estimated read duration as the sum of the first ratio between the read data volume of the current task and the target bandwidth, the first estimated delay, and the second estimated delay; the target bandwidth is the data bandwidth between the request source of the first read data request and the cache module.

[0218] Step S493: Determine the sum of the first ratio, the first estimated delay, the second estimated delay, the third estimated delay, and the fourth estimated delay as a second estimated reading duration.

[0219] In the above embodiment, the first estimated reading duration is obtained based on the first ratio between the read data volume of the current task and the target bandwidth, the first estimated delay, and the sum of the second estimated delay; the second estimated reading duration is obtained based on the sum of the first ratio, the first estimated delay, the second estimated delay, the third estimated delay, and the fourth estimated delay; when the estimated calculation duration is greater than the first estimated reading duration and less than the second estimated reading duration, the prefetch information is determined to be the first prefetch information indicating that the data prefetch function is enabled. In this way, on the one hand, the first estimated reading time is the sum of the first ratio of the read data volume of the current task to the target bandwidth, the first estimated delay for the computing module to send a single request to the cache module, and the second estimated delay for the cache module to return a single data to the computing module. Therefore, the first estimated reading time can represent the estimated lower limit of the time consumption for reading data in the current task; on the other hand, the second estimated reading time is the sum of the first ratio of the read data volume of the current task to the target bandwidth, the first estimated delay for the computing module to send a single request to the cache module, the second estimated delay for the cache module to return a single data to the computing module, the third estimated delay for the cache module to send a single request to the memory, and the fourth estimated delay for the memory to return a single data to the cache module. Therefore, the first estimated reading time can represent the estimated upper limit of the time consumption for reading data in the current task. In this way, when the estimated calculation time of the current task is greater than the first estimated reading time and less than the second estimated reading time, the prefetch information can be determined as the first prefetch information representing the activation of the data prefetch function, so that data reading and prefetching can be achieved through a single data request, thereby reducing the data request pressure between the request source and the cache module, improving system performance, and improving the cache hit rate, thereby reducing the time consumption of data reading in the current task, so that the time consumption of data reading is more covered by the calculation time, that is, reducing the impact of data reading time on computing efficiency, thereby better balancing the computing time and data access time during task execution.

[0220] The following describes the application of the data reading method provided by the embodiment of the present disclosure in a practical scenario, taking the process of using instruction-controlled read requests accompanied by data prefetching as an example based on the combination of software and hardware.

[0221] Processor memory access performance optimization is a hot topic in computer architecture. In order to solve the delay problem caused by the mismatch between the access rate of the memory (such as memory, etc.) and the calculation rate of the operation module in the processor, a cache module can be designed in the processor so that the data reading and writing rate can adapt to the calculation rate of the calculation module, thereby improving system performance. Figure 5A is a schematic diagram of an implementation architecture of a data cache provided by an embodiment of the present disclosure. As shown in Figure 5A, the architecture includes: a calculation module 511, a register 512, a cache module 513 and a memory 514. Data can be input and / or output between the calculation module 511, the cache module 513 and the memory 514. The calculation module 511 can read data from the cache module 513, the register 512 and / or the memory 514 to perform calculations, and store the calculation results in the cache module 513, the register 512 and / or the memory 514.

[0222] In related technologies, most processors use data prefetching technology to predict future memory accesses and issue access requests to corresponding memory blocks before explicit access, so as to fetch data in the memory blocks into the cache module in advance, thereby improving the cache hit rate.

[0223] In some related technologies, data prefetching can be implemented using software prefetching. In this software prefetching approach, the processor supports prefetch instructions. Application software running in the processor can send the address of the data to be prefetched to the processor hardware in the form of prefetch instructions, instructing the cache module to prefetch data based on the address. For example, in a scenario with loop calculations, the application software can allocate 1, 2, or even 4 times more register space for a single loop based on the hardware resources in the processor to store the prefetched data. Before starting the loop calculation, multiple read data requests after the current loop can be issued in advance to implement data prefetching and store the prefetched data in the additional allocated register space. Thus, in this software prefetching approach, although only ordinary read data requests are required and no additional hardware architecture support is required, the on-chip register space required is 1 to 4 times the original amount. In addition, on parallel processors, the increased number of registers consumed by a single task will lead to a decrease in task parallelism. This problem is particularly prominent in graphics memory architectures with limited on-chip register resources. In addition, the downstream request path and data return path cannot accurately distinguish between prefetch requests and current loop requests. In a multi-processor parallel architecture, it is possible that the prefetch requests of some processors will block the normal memory access requests of other processors, resulting in a decrease in the number of parallel tasks.

[0224] In some related technologies, hardware prefetching can be used to achieve automatic prefetching of data. In this hardware prefetching method, the hardware function of the cache module can be expanded. When a data request is sent to the cache module for a cache block address hit query, the cache module can automatically determine the address of the data to be prefetched according to the preset prefetching strategy, and prefetch the data according to the address. For example, the cache module can automatically perform a hit query on the next one or several cache units (recorded as prefetch blocks) of the cache unit corresponding to the read request address. If the prefetch block is missing, the request is sent to the lower-level cache or memory. In this way, although there is no need for the request source to send read requests and prefetch requests separately in this method, and the user programming complexity is simplified; however, prefetching cannot be controlled task by task. In some scenarios, there is a problem that the prefetched data will replace the data being used out of the cache, resulting in performance worse than if this solution is not applied.

[0225] Based on this, the embodiment of the present disclosure provides a data reading method, which adopts a combination of hardware and software. The data used in the subsequent loop is pre-fetched and cached in the storage space of the cache module. In this way, there is no additional register usage overhead, which does not affect the number of parallel tasks allocated. Moreover, by carrying the pre-fetched data length to the cache module through the read data request and parsing and disassembling it, no additional request path pressure will be brought, thereby compressing the request bandwidth, and the pre-fetched data length can be configured by instruction for each task, so as to flexibly and conveniently perform instruction-granular pre-fetch control to better meet the pre-fetch requirements of the task. In addition, the data reading method can also be compatible with multiple cache modes, such as multi-level cache mode, sector mode, etc.

[0226] In some embodiments, the data reading method provided by the embodiments of the present disclosure may consider the following six parts when implementing:

[0227] First, design the instruction set.

[0228] Here, the read data instruction that supports prefetch control can be extended in the instruction set. In the embodiment of the present disclosure, the extended read data instruction reuses the read request address and read data length of the ordinary read instruction in the related art, and extends the modification of the prefetch data length. In this way, the prefetch data length can be used to describe the data length of the data to be prefetched with the read request address plus the read data length as the prefetch start address, without the need for a separate prefetch instruction or the addition of the transmission of the prefetch start address in the instruction set. And when using the extended read data instruction, there is no need for additional prefetch start address calculation overhead and prefetch start address transmission overhead.

[0229] In some embodiments, the modification method for extending the prefetch data length in a read data instruction can be selected from the following two methods: 1) Type code expansion: If the current architecture instruction type has sufficient reserved codes, the instruction type can be distinguished as a read instruction (i.e., read-only type) or a read-with-prefetch instruction; 2) Adding a bit field: Adding an additional bit field (corresponding to the prefetch control code) to indicate the prefetch data length, and a code of 0 can be reserved to indicate that prefetching is disabled (i.e., no data prefetching is performed). For example, these two methods for extending the prefetch data length can be shown in Table 1 below.

[0230] Table 1 Schematic diagram of two ways to extend the prefetch data length

[0231] In some implementations, to ensure forward compatibility with instruction sets, the default value of the prefetch control encoding bit field is configured to indicate that prefetching is disabled.

[0232] Second, design the interface signals of the cache module.

[0233] The cache module's interface signal design is similar to the instruction set design. In implementation, the cache module's interface signal can retain the original read request address and read data length, while extending the prefetch data length modifier. The request source simply sends the prefetch data length along with the read data request to the downstream cache module, which then passes the prefetch data length to the cache module for parsing and splitting.

[0234] The modification of the extended prefetch data length in the interface signal of the cache module is similar to the instruction set design, and supports two categories: 1) Type signal encoding expansion: If the current architecture request type has sufficient reserved encoding, the request type signal can be used to directly distinguish between read-only requests and read requests with prefetch; 2) New prefetch control signal: The prefetch data length can be indicated by adding an additional prefetch control signal, and the prefetch control signal can retain the 0 encoding to indicate that prefetch is turned off (i.e., no data prefetching is performed).

[0235] In some implementations, the design of the interface signal may also consider compression of control information to increase information entropy.

[0236] Third, the data size of a single read request affects the data.

[0237] In some embodiments, the read data request sent to the cache module will be processed in the order of request splitting, cache block alignment, and hit detection, and finally request data from the memory, return the read data to the upstream request source, and / or cache the pre-fetched data into the cache block of the cache module.

[0238] Request splitting: At the entry of the cache module, read data requests whose read data length exceeds the length of one cache block will be split and aligned according to the cache block length. For the address range corresponding to the read request address and the read data length, after the splitting and alignment operations, multiple split read sub-requests can be obtained. For the address range corresponding to the prefetch start address (obtained by adding the read data length to the read request address) and the prefetch data length, after the splitting and alignment operations, multiple split prefetch sub-requests can be obtained. For each read sub-request and each prefetch sub-request, a cache block hit check can be performed independently.

[0239] Cache block alignment: A cache block is the basic unit of data allocation and management within the cache module. If the amount of data to be read from a single read request sent by the request source does not fit within a cache block, the cache module will align the address range corresponding to the read request address and the read data length according to the cache block length. If the amount of data to be prefetched from a single read request sent by the request source does not fit within a cache block, the cache module will align the address range corresponding to the prefetch start address and the prefetch data length according to the cache block length.

[0240] Cache block hit detection: The split read sub-request and pre-fetch sub-request will be sent to the cache block hit check unit for cache block hit detection. If a cache block is missing for a read sub-request or pre-fetch sub-request, the cache module will allocate cache space for the missing read sub-request or pre-fetch sub-request, record and update the read sub-request or pre-fetch sub-request, and transmit the missing read sub-request or pre-fetch sub-request to the downstream cache module or memory, and obtain the read data (corresponding to the first target data) or pre-fetched data (corresponding to the second target data) from the downstream cache module or memory. The read data will be returned to the request source, and the pre-fetched data will be cached in at least one cache block of the cache module.

[0241] Fourth, it is compatible with the mode in which the cache module supports sectors.

[0242] In some implementations, where the current architecture supports finer-grained control over cache, a single request is allowed to be a subset of a cache block. For example, a cache block is 128 bytes and has four cache sectors. A request source is allowed to issue read data requests to the cache module in multiples of 32 bytes (i.e., the length of a cache sector). Cache blocks are still allocated based on the cache block length (e.g., 128 bytes). In this case, the corresponding prefetched data length in the read data request can be a multiple of the cache sector length.

[0243] Fifth, it is compatible with multi-level cache mode.

[0244] For multi-level cache mode scenarios, you can consider request merging and full or partial hits of upstream cache modules.

[0245] Request merging situation: The data reading method provided by the embodiment of the present disclosure can support request merging. For example, each read data request sent by the request source or upstream cache module in the multi-level cache carries the pre-fetched data length, and the downstream cache module can merge multiple read data requests that overlap with the corresponding cache blocks / sectors, and the merged request only carries one pre-fetched data length. Since the read request address plus the read data length is used as the pre-fetch starting address, the pre-fetched data corresponding to the merged read data request will fall within the address range between the read request address of the first read data request, the read request address of the last read data request plus the read data length, and the address after the pre-fetched data length.

[0246] Case where the upstream cache module is fully hit or partially hit: In the data reading method provided by the embodiment of the present disclosure, if multiple read sub-requests corresponding to the read data request sent by the request source are partially hit in the upstream cache module, the partial read sub-requests that did not hit can carry the pre-fetched data length to the downstream cache module; if multiple read sub-requests corresponding to the read data request sent by the request source are all hit in the upstream cache module, the first sub-target data cached respectively by the multiple read sub-requests in the upstream cache module are merged to obtain the first target data corresponding to the read data request, the first target data is returned to the request source, and the pre-fetched data length is discarded.

[0247] Sixth, scene selection.

[0248] Based on their computational and memory access characteristics, tasks are typically categorized as either compute-intensive or memory-intensive. The quotient of computational scale and computational parallelism (i.e., throughput) is considered the computation time, while the quotient of the amount of data required and the memory access bandwidth is defined as the memory access time. For example, if a task's computation time is greater than its memory access time, it can be classified as compute-intensive; if its computation time is less than its memory access time, it can be classified as memory-intensive.

[0249] Figure 5B is a schematic diagram of the interaction between various modules in a data reading method provided by an embodiment of the present disclosure. As shown in Figure 5B, a request source 521 sends a read data request, representing a read request with prefetching, to a cache module 522. In response to receiving the read data request, the cache module 522 can send a read request and a prefetching request to the memory 523, and receive the read data and prefetching data returned by the memory 523. The cache module 522 returns the received read data to the request source 521 and caches the prefetching data in the storage space of the cache module 522. The time from request source 521 requesting data to the return of read data can be divided into four stages: delays 0 to 3. Delay 0 represents the estimated delay for the request source 521 to send a single request to the cache module 522, delay 1 represents the estimated delay for the cache module 522 to send a single request to the memory 523, delay 2 represents the estimated delay for the memory 523 to return a single data entry to the cache module 522, and delay 3 represents the estimated delay for the cache module 522 to return a single data entry to the request source 521.

[0250] Without prefetching, the data reading time = the requested data volume of the current task / target bandwidth + delay 0 + delay 1 + delay 2 + delay 3; where the target bandwidth is the data bandwidth between the request source 521 and the cache module 522.

[0251] In the case of prefetching, the required data is pre-fetched back into the cache in advance. When the data is requested again, it will be found in the cache module and returned directly. Therefore, there is no delay in the request to the memory due to cache misses, and there is no need to consider Delay 1 and Delay 2. Therefore, in the case of prefetching, the time to read data = the amount of data requested by the current task / target bandwidth + Delay 0 + Delay 3.

[0252] In some embodiments, when the estimated computation time of the current task satisfies the following conditions, an instruction type code or a prefetch control code may be used to indicate a read data instruction that enables data prefetching (i.e., the prefetched data length is greater than 0), thereby reducing the impact of data reading time on computation efficiency, thereby better balancing computation time and data access time during task execution:

[0253] Requested data volume of the current task / target bandwidth + delay 0 + delay 3 < estimated calculation duration of the current task < requested data volume of the current task / target bandwidth + delay 0 + delay 1 + delay 2 + delay 3.

[0254] If the estimated calculation duration of the current task is greater than the requested data volume of the current task / target bandwidth + delay 0 + delay 1 + delay 2 + delay 3, the instruction type code or prefetch control code can be used to indicate a read data instruction that turns off data prefetching (i.e., the prefetched data length is equal to 0).

[0255] The following uses a scenario where 128 bytes are requested in each loop and data in the memory is continuously retrieved in a loop as an example to introduce the application of the data reading method provided by the embodiment of the present disclosure.

[0256] Define the requested data address as 128-byte aligned. Each read request can request 128 bytes of data (i.e., the read data length is 128 bytes), and the prefetched data length is 128 bytes. Figure 5C is a schematic diagram of an implementation of a read data request with a prefetched data length provided by an embodiment of the present disclosure. As shown in Figure 5C, assuming that the prefetched data has been returned to the cache before the next loop, the processing process in different loops is as follows:

[0257] The first loop is loop 0, in which the request source requests 128 bytes of the starting address (cache block 0) and the prefetched 128 bytes (cache block 1);

[0258] In loop 1, the request source requests cache block 1. Cache block 1 can be hit in the cache module and returned to the request source with a shorter delay. A request to prefetch cache block 2 is sent to the downstream cache module or memory.

[0259] In loop 2, the request source requests cache block 2, which can be hit in the cache module and returned to the request source with a shorter delay, and a request to prefetch cache block 3 is sent to the downstream cache module or memory.

[0260] In loop 3, the request source requests cache block 3, cache block 3 can be hit in the cache module and returned to the request source with a shorter delay, and the loop ends.

[0261] It can be seen that in the scenario of continuously fetching data from the memory in a loop, when the pipeline is fully loaded, after adding support for the prefetch function, the data requested for each read data request will be hit in the cache and returned to the request source with a shorter delay.

[0262] The present disclosure provides a chip. FIG6 is a schematic diagram of the structure of a chip provided by the present disclosure. As shown in FIG6, the chip 600 includes a computing module 610 and a cache module 620, wherein:

[0263] The computing module 610 is configured to: obtain a read data instruction; the read data instruction is used to instruct data reading according to the read information and data prefetching according to the prefetch information; obtain a first read data request according to the read data instruction; the first read data request includes the read information and the prefetch information; send the first read data request to the cache module, so that the cache module responds to the first read data request by reading and returning the first target data according to the read information and prefetching and caching the second target data according to the prefetch information; and receive the first target data returned by the cache module;

[0264] The cache module 620 is configured to: receive a first read data request sent by the computing module, the first read data request being used to request data reading according to read information and data prefetching according to prefetch information; obtain the read information and the prefetch information according to the first read data request; read first target data from the storage space and / or memory of the cache module based on the read information, and return the first target data to the computing module; prefetch second target data from the memory based on the prefetch information, and cache the second target data in at least one cache unit of the cache module.

[0265] The description of the processor embodiment above is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment. In some embodiments, the functions or modules included in the processor provided by the embodiments of the present disclosure can be configured to execute the methods described in the method embodiments above. For technical details not disclosed in the processor embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0266] An embodiment of the present disclosure provides a computer device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, some or all of the steps in the above method are implemented, or the processor includes the chip described in the above embodiment.

[0267] The present disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above method. The computer-readable storage medium may be transient or non-transient.

[0268] An embodiment of the present disclosure provides a computer program, including computer-readable codes. When the computer-readable codes are executed in a computer device, a processor in the computer device executes some or all of the steps for implementing the above method.

[0269] The present disclosure provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, implements some or all of the steps in the above method. The computer program product can be implemented specifically by hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium. In other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0270] An embodiment of the present disclosure provides a computer program product, including a computer program or instructions. When the computer program or instructions are executed by a processor, some or all of the steps in the above method are implemented.

[0271] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between the embodiments, and reference can be made to the similarities or similarities between them. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above-mentioned method embodiments and have similar beneficial effects as the method embodiments. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product disclosed herein, please refer to the description of the method embodiments disclosed herein for understanding.

[0272] Figure 7 is a schematic diagram of the hardware entity of a computer device provided in an embodiment of the present disclosure. As shown in Figure 7, the hardware entity of the computer device 700 includes: a processor 701 and a memory 702, wherein the memory 702 stores a computer program that can be run on the processor 701, and when the processor 701 executes the program, the steps in the method of any of the above embodiments are implemented.

[0273] The memory 702 stores computer programs that can be run on the processor. The memory 702 is configured to store instructions and applications executable by the processor 701. It can also cache data to be processed or processed by the processor 701 and various modules in the computer device 700 (for example, image data, audio data, voice communication data, and video communication data). This can be implemented through flash memory (FLASH) or random access memory (RAM).

[0274] When the processor 701 executes the program, the steps of any of the above data reading methods are implemented. The processor 701 generally controls the overall operation of the computer device 700.

[0275] An embodiment of the present disclosure provides a computer storage medium storing one or more programs. The one or more programs can be executed by one or more processors to implement the steps of the data reading method of any of the above embodiments.

[0276] It should be noted that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0277] The processor may be at least one of an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a central processing unit (CPU), a controller, a microcontroller, and a microprocessor. It is understood that the electronic device that implements the functions of the processor may also be other electronic devices, which are not specifically limited in the embodiments of the present disclosure.

[0278] The above-mentioned computer storage medium / memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory (Flash Memory), a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); it can also be various terminals including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0279] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned steps / processes does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0280] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0281] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0282] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0283] In addition, the functional units in the embodiments of the present disclosure may all be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units. A person skilled in the art will understand that: all or part of the steps of the above-mentioned method embodiments may be completed by hardware related to program instructions, and the aforementioned program may be stored in a computer-readable storage medium, and when the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, read-only memories (ROMs), magnetic disks or optical disks.

[0284] Alternatively, if the above-mentioned integrated unit of the present disclosure is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the relevant technology, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0285] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or replacements that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed in this disclosure should be covered by the protection scope of the present disclosure. Industrial Applicability

[0286] The disclosed embodiments disclose a data reading method for a chip, a chip, a computer device, a storage medium, and a computer program product, wherein the method comprises: obtaining a read data instruction; the read data instruction is used to instruct data reading according to read information and data prefetching according to prefetch information; obtaining a first read data request according to the read data instruction; the first read data request includes read information and prefetch information; sending the first read data request to a cache module, so that the cache module responds to the first read data request, reads and returns the first target data according to the read information, and prefetches and caches the second target data according to the prefetch information; and receiving the first target data returned by the cache module. According to the disclosed embodiments, the data request pressure between the request source and the cache module can be reduced, the request bandwidth can be compressed, the processor performance can be improved, and the prefetching method can be flexibly controlled task by task to better meet the data reading requirements of each task.

Claims

1. A method for reading data of a chip, the method comprising: Obtaining a read data instruction; The read data instruction is used to indicate data reading according to the read information and data prefetching according to the prefetch information; Obtaining a first read data request according to the read data instruction; The first read data request includes the read information and the prefetch information; Sending the first read data request to a cache module, so that in response to the first read data request, the cache module reads and returns first target data according to the read information, and prefetches and caches second target data according to the prefetch information; Receiving the first target data returned by the cache module.

2. The data reading method according to claim 1, wherein, The read information includes a first read request address and a first read data length; obtaining the read data instruction includes: Performing instruction encoding according to the first read request address, the first read data length, and the prefetch information to obtain the read data instruction.

3. The data reading method according to claim 2, wherein, The read data instruction includes an instruction type encoding, a read request address encoding, and a read data length encoding; The performing instruction encoding according to the first read request address, the first read data length, and the prefetch information to obtain the read data instruction includes: Determining the instruction type encoding corresponding to the prefetch information from a preset instruction type encoding set; Encoding the first read request address to obtain the read request address encoding; Encoding the first read data length to obtain the read data length encoding.

4. The data reading method according to claim 3, wherein, The obtaining a first read data request according to the read data instruction includes: Respectively parsing the instruction type encoding, the read request address encoding, and the read data length encoding to obtain the prefetch information, the first read request address, and the first read data length; Generating the first read data request according to the prefetch information, the first read request address, and the first read data length.

5. The data reading method according to claim 2, wherein, The read data instruction includes a read request address encoding, a read data length encoding, and a prefetch control encoding; The performing instruction encoding according to the first read request address, the first read data length, and the prefetch information to obtain the read data instruction includes: Encoding the first read request address to obtain the read request address encoding; Encoding the first read data length to obtain the read data length encoding; Encoding the prefetch information to obtain the prefetch control encoding.

6. The data reading method according to claim 5, wherein, The obtaining a first read data request according to the read data instruction includes: Respectively parsing the read request address encoding, the read data length encoding, and the prefetch control encoding to obtain the first read request address, the first read data length, and the prefetch information; Generating the first read data request according to the prefetch information, the first read request address, and the first read data length.

7. The data reading method according to claim 4 or 6, wherein, The generating the first read data request according to the prefetch information, the first read request address, and the first read data length includes one of the following: According to the first read request address, the first read data length, and the prefetch information, determine a read request address signal, a read data length signal, and a request type signal respectively, and generate the first read data request according to the read request address signal, the read data length signal, and the request type signal; According to the first read request address, the first read data length, and the prefetch information, determine a read request address signal, a read data length signal, and a prefetch control signal respectively, and generate the first read data request according to the read request address signal, the read data length signal, and the prefetch control signal.

8. The data reading method according to any one of claims 1 to 6, wherein, The obtaining a read data instruction includes: Obtain the amount of data to be read and the estimated calculation duration of the current task; Determine the prefetch information according to the amount of data to be read and the estimated calculation duration; Determine the read data instruction according to the prefetch information.

9. The data reading method according to claim 8, wherein, The determining the prefetch information according to the amount of data to be read and the estimated calculation duration includes: Determine a first estimated read duration corresponding to the amount of data to be read when the data prefetch function is enabled, and a second estimated read duration corresponding to the amount of data to be read when the data prefetch function is disabled; Determine the prefetch information according to the magnitude relationship between the estimated calculation duration and the first estimated read duration, and / or the magnitude relationship between the estimated calculation duration and the second estimated read duration.

10. The data reading method according to claim 9, wherein, The determining the prefetch information according to the magnitude relationship between the estimated calculation duration and the first estimated read duration, and / or the magnitude relationship between the estimated calculation duration and the second estimated read duration includes: When the estimated calculation duration is greater than the first estimated read duration and less than the second estimated read duration, determine the prefetch information as a first prefetch information indicating that the data prefetch function is enabled.

11. The data reading method according to claim 9 or 10, wherein, The determining a first estimated read duration corresponding to the amount of data to be read when the data prefetch function is enabled, and a second estimated read duration corresponding to the amount of data to be read when the data prefetch function is disabled includes: Estimate the latency of sending a single request to the cache module, the latency of the cache module returning a single piece of data, the latency of the cache module sending a single request to the memory, and the latency of the memory returning a single piece of data to the cache module, and obtain a first estimated latency, a second estimated latency, a third estimated latency, and a fourth estimated latency respectively; Determine the sum of the first ratio between the amount of data to be read of the current task and the target bandwidth, the first estimated latency, and the second estimated latency as the first estimated read duration; the target bandwidth is the data bandwidth between the request source of the first read data request and the cache module; Determine the sum of the first ratio, the first estimated latency, the second estimated latency, the third estimated latency, and the fourth estimated latency as the second estimated read duration.

12. A method for data reading for a chip, the method includes: Receive a first read data request sent by a request source, where the first read data request is used to request data reading according to read information and data prefetching according to prefetch information; Obtain the read information and the prefetch information according to the first read data request; Based on the read information, read first target data from the storage space of the cache module and / or the memory, and return the first target data to the request source; Based on the prefetch information, prefetch second target data from the memory, and cache the second target data into at least one cache unit of the cache module.

13. The data reading method according to claim 12, wherein, The prefetch information includes a prefetch data length; The step of prefetching second target data from the memory based on the prefetch information and caching the second target data into at least one cache unit of the cache module includes: When the prefetch data length is greater than 0, determine a prefetch start address based on the first read request address and the first read data length; Based on the prefetch start address and the prefetch data length, prefetch second target data from the memory, and cache the second target data into at least one cache unit of the cache module.

14. The data reading method according to claim 13, wherein, The read information includes a first read request address and a first read data length; the step of obtaining the read information and the prefetch information according to the first read data request includes one of the following: Analyze the request type signal, read request address signal, and read data length signal in the first read data request respectively to obtain a first request type, the first read request address, and the first read data length, and determine the prefetch data length based on the first request type; Analyze the read request address signal, read data length signal, and prefetch control signal in the first read data request respectively to obtain the first read request address, the first read data length, and the prefetch data length.

15. The data reading method according to claim 13 or 14, wherein, The step of prefetching second target data from the memory based on the prefetch start address and the prefetch data length and caching the second target data into at least one cache unit of the cache module includes: Determine at least one prefetch sub-request based on the prefetch start address and the prefetch data length, where the data request length corresponding to each prefetch sub-request is equal to the length of the cache unit of the cache module; For each prefetch sub-request, perform cache unit hit detection in the storage space of the cache module based on the prefetch sub-request to obtain a first detection result, and when the first detection result indicates that the cache unit corresponding to the prefetch sub-request is missing, prefetch second target data from the memory based on the prefetch sub-request, and cache the second target data into at least one cache unit of the cache module.

16. The data reading method according to any one of claims 13 to 15, wherein, The prefetch data length is an integer multiple of the cache unit length, and the cache unit includes a cache block or a cache sector.

17. The data reading method according to any one of claims 12 to 16, wherein, The number of the first read data requests is multiple; the read information includes a first read request address and a first read data length; The step of reading first target data from the storage space of the cache module and / or the memory based on the read information includes: For each of the first read data requests, based on the first read request address and the first read data length corresponding to the first read data request, determine the cache unit corresponding to the first read data request; In the case where the cache units corresponding to the multiple first read data requests overlap, merge the first read request addresses and the first read data lengths corresponding to the multiple first read data requests respectively to obtain the merged first read request address and the first read data length, and merge the prefetch information corresponding to the multiple first read data requests to obtain the merged prefetch information; Based on the merged first read request address and the first read data length, obtain first target data from the storage space of the cache module and / or the memory; The prefetching second target data from the memory based on the prefetch information and caching the second target data into at least one cache unit of the cache module includes: Based on the merged prefetch information, prefetch second target data from the memory and cache the second target data into at least one cache unit of the cache module.

18. The data reading method according to claim 17, wherein, The merging the prefetch information corresponding to the multiple first read data requests to obtain the merged prefetch information includes: Determine the prefetch information corresponding to the first read data request with the last first read request address among the multiple first read data requests as the merged prefetch information.

19. The data reading method according to any one of claims 12 to 18, wherein, The first target data includes at least one first sub-target data, and the cache module includes a first cache sub-module and a second cache sub-module; The receiving the first read data request sent by the request source includes: the first cache sub-module receives the first read data request sent by the request source; The obtaining the read information and the prefetch information according to the first read data request includes: the first cache sub-module obtains the read information and the prefetch information according to the first read data request; the read information includes a first read request address and a first read data length; The reading the first target data from the storage space of the cache module and / or the memory based on the read information and returning the first target data to the request source includes: the first cache sub-module determines at least one read data sub-request based on the first read request address and the first read data length, and the data request length corresponding to each read data sub-request is equal to the cache unit length of the first cache sub-module; the first cache sub-module obtains the first sub-target data corresponding to each read data sub-request from the storage space of the first cache sub-module, the storage space of the second cache sub-module, and / or the memory, and returns each first sub-target data to the request source; The prefetching second target data from the memory based on the prefetch information and caching the second target data into at least one cache unit of the cache module includes: the second cache sub-module prefetchs the second target data from the memory based on the prefetch information and caches the second target data into at least one cache unit of the second cache sub-module.

20. The data reading method according to claim 19, wherein, The first cache sub-module obtains first sub-target data corresponding to each of the read data sub-requests from the storage space of the first cache sub-module, the storage space of the second cache sub-module, and / or the memory, including: The first cache sub-module respectively performs cache unit hit detection in the storage space of the first cache sub-module based on each of the read data sub-requests to obtain a second detection result corresponding to each of the read data sub-requests; For each of the read data sub-requests, when the second detection result corresponding to the read data sub-request indicates that the cache unit corresponding to the read data sub-request is hit, the first cache sub-module reads the first sub-target data corresponding to the read data sub-request from the hit cache unit, and when the second detection result corresponding to the read data sub-request indicates that the cache unit corresponding to the read data sub-request is missing, based on the second read request address and the second read data length corresponding to the read data sub-request, and the prefetch information, the first cache sub-module sends a second read data request to the second cache sub-module and receives the first sub-target data corresponding to the read data sub-request returned by the second cache sub-module; The second cache sub-module prefetches second target data from the memory based on the prefetch information, including: The second cache sub-module, in response to receiving the second read data request sent by the first cache sub-module, parses the second read data request to obtain a second read request address, a second read data length, and the prefetch information; The second cache sub-module obtains first sub-target data from the storage space of the second cache sub-module and / or the memory based on the second read request address and the second read data length, and returns the first sub-target data to the first cache sub-module; The second cache sub-module prefetches second target data from the memory based on the prefetch information, and caches the second target data into at least one cache unit of the second cache sub-module.

21. A chip, the chip includes: A computing module, configured to: obtain a read data instruction; The read data instruction is used to indicate data reading according to the reading information and data prefetching according to the prefetch information; Obtain a first read data request according to the read data instruction; The first read data request includes the reading information and the prefetch information; Send the first read data request to a cache module, so that the cache module, in response to the first read data request, reads and returns first target data according to the reading information, and prefetches and caches second target data according to the prefetch information; receive the first target data returned by the cache module; A cache module, configured to: receive the first read data request sent by the computing module, the first read data request being used to request data reading according to the reading information and data prefetching according to the prefetch information; Obtain the reading information and the prefetch information according to the first read data request; Read first target data from the storage space of the cache module and / or the memory based on the read information, and return the first target data to the computing module; Prefetch second target data from the memory based on the prefetch information, and cache the second target data in at least one cache unit of the cache module.

22. A computer device, comprising a memory and a processor, where the memory stores a computer program that can run on the processor, and when the processor executes the program, it implements the steps in the method according to any one of claims 1 to 20, or the processor includes the chip according to claim 21.

23. A computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps in the method according to any one of claims 1 to 20.

24. A computer program product, comprising a computer program or instruction, and when the computer program or instruction is executed by a processor, it implements the steps in the method according to any one of claims 1 to 20.

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