Circuit simulation verification method and apparatus, and electronic device and storage medium

Abstract

Disclosed in the present application are a circuit simulation verification method and apparatus, and an electronic device and a storage medium. The method comprises: using a hardware description language such as a Verilog-AMS modeling language to create a simulation model for a circuit device, wherein the simulation model is provided with a timer and several first simulation points, and the timer is used for generating second simulation points; acquiring an input signal of the current first simulation point and an input signal of the previous first simulation point during a simulation verification process; determining whether the input signal of the current first simulation point is the same as the input signal of the previous first simulation point; if not, controlling the timer to periodically generate second simulation points; and if so, controlling the simulation model to enter a sleep mode, wherein in the sleep mode, the timer stops generating second simulation points. The present application can reduce the number of simulation points while ensuring the simulation precision, and has a relatively high simulation speed.

Description

Circuit simulation verification method and device, electronic device, and storage medium Technical Field

[0001] The present application relates to the field of circuit simulation verification technology, and specifically to a circuit simulation verification method and device, electronic equipment, and storage medium. Background Art

[0002] In recent years, with the rapid development of wireless communication technology, higher requirements have been placed on the integrated circuits involved, requiring better signal processing capabilities and shorter product development cycles. Taking radio frequency integrated circuits as an example, the circuit is mainly composed of active devices such as transistors and passive devices such as inductors and capacitors. According to traditional design methods, designers first formulate the performance parameters of the integrated circuit according to system requirements, determine the circuit structure and draw a schematic diagram, use circuit simulation to confirm the correctness of the schematic parameter design, and then draw a layout based on the circuit schematic. After the layout is completed, it is necessary to compare and verify the layout and the schematic diagram to confirm the correctness of the layout. Then, the parasitic parameters of the layout are extracted and post-simulated. If the post-simulation results are not ideal, the schematic diagram is returned to optimize the design parameters, and the corresponding layout is modified. The parasitic parameters of the layout are then extracted and post-simulated. If the post-simulation results meet the expected design effect, the chip is sent to the foundry for production.

[0003] During the simulation verification process, a timer periodically generates simulation points. At the moment of each simulation point, the simulation tool inserts a trigger event to execute the corresponding simulation event. In other words, at each simulation point, the simulation tool needs to perform a detailed solution, such as solving the node voltages and branch currents of each part of the circuit by establishing circuit equations and performing Newton iterations. Because each simulation point requires a large number of mathematical calculations, the more simulation points there are, the more time the simulation tool spends calculating. When the timer frequency is high or high simulation accuracy is required, the simulation model will generate a large number of simulation points, which will seriously affect the simulation speed. Summary of the Invention

[0004] In view of this, the present application provides a circuit simulation verification method and device, an electronic device, and a storage medium, which can improve the problem of an increasing number of simulation points and the resulting impact on simulation speed.

[0005] This application provides a circuit simulation verification method, including:

[0006] Creating a simulation model for a circuit device using a hardware description language, wherein the simulation model includes a timer and a plurality of first simulation points, wherein the timer is used to generate second simulation points;

[0007] Obtaining input signals of the current first simulation point and the previous first simulation point during the simulation verification process;

[0008] Determine whether the input signal of the current first simulation point is the same as the input signal of the previous first simulation point;

[0009] If not, controlling the timer to periodically generate the second simulation point;

[0010] If so, the simulation model is controlled to enter a sleep mode, and in the sleep mode, the timer stops generating the second simulation point.

[0011] Optionally, the input signal includes at least one of voltage, current, frequency and power.

[0012] Optionally, the circuit device is not provided with an excitation source, and during the simulation verification process, the output signal remains unchanged when the input signal of the simulation model remains unchanged.

[0013] Optionally, a method for determining whether the circuit device is provided with an excitation source includes:

[0014] Obtain all assignment statements in the simulation model;

[0015] When the input signal of the simulation model remains unchanged, determining whether corresponding variable values ​​of two adjacent first simulation points have an associated relationship according to the assignment statement;

[0016] If so, determining that the circuit device is provided with an excitation source;

[0017] If not, it is determined that the circuit device is not provided with an excitation source.

[0018] Optionally, after the sleep mode, if it is determined that the input signal of the current first simulation point is different from the input signal of the previous first simulation point, controlling the timer to periodically generate the second simulation point includes:

[0019] Control the timer to obtain the time point of generating the second simulation point according to the relationship t2=n*T+t1; wherein t2 is the time point of generating the second simulation point, n≥1 and is a positive integer, T is the period of generating the second simulation point set by the timer itself, and t1 is the time point of the last second simulation point generated by the timer before the sleep mode.

[0020] Optionally, the hardware description language includes Verilog-AMS modeling language.

[0021] Optionally, the types of trigger events inserted at each of the first simulation points are different or partially the same, and the types of trigger events inserted at each of the second simulation points are the same.

[0022] The present application provides a circuit simulation verification device, comprising:

[0023] A creation module, configured to create a simulation model for a circuit device using a hardware description language, wherein the simulation model is provided with a timer and a plurality of first simulation points, wherein the timer is configured to generate second simulation points;

[0024] An acquisition module, used to acquire input signals of the current first simulation point and the previous first simulation point during the simulation verification process;

[0025] A judging module, configured to judge whether the input signal of the current first simulation point is the same as the input signal of the previous first simulation point;

[0026] a control module, configured to control the timer to periodically generate the second simulation point when the input signal of the current first simulation point is different from the input signal of the previous first simulation point; and control the simulation model to enter a sleep mode when the input signal of the current first simulation point is the same as the input signal of the previous first simulation point, and control the timer to stop generating the second simulation point in the sleep mode;

[0027] An inserting module is used to insert a trigger event at the second simulation point.

[0028] The present application provides an electronic device, comprising:

[0029] processor;

[0030] a memory for storing instructions executable by the processor;

[0031] The processor is configured to execute the instructions to implement the steps corresponding to any one of the above circuit simulation verification methods.

[0032] The present application provides a storage medium storing a computer program, which, when executed by a processor, implements the steps corresponding to any of the above circuit simulation verification methods.

[0033] As described above, in the present application, when the simulation model enters the sleep mode, the timer stops generating the second simulation point, thereby reducing the number of simulation points, which is conducive to maintaining and improving the simulation speed, shortening the simulation verification cycle of integrated circuits including those containing high-frequency triggered clock events (i.e., Timer events), and thereby accelerating the design iteration of the entire integrated circuit, which helps the integrated circuit to start tape-out production as soon as possible.

[0034] In addition, the circuit device is not provided with an excitation source. During the simulation verification process, the input signal of the simulation model remains unchanged, so the output signal remains unchanged, and thus the simulation accuracy can also be guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic flow chart of a circuit simulation verification method provided in an embodiment of the present application;

[0036] FIG2 is a timing diagram of a circuit simulation verification provided based on the method shown in FIG1 ;

[0037] FIG3 is a schematic structural diagram of a circuit simulation verification device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] To address the aforementioned issues in the prior art, this application provides a circuit simulation verification method and apparatus, an electronic device, and a storage medium. These various protected themes are based on the same concept and address similar or substantially identical principles. The implementations of the various protected themes can be referenced in conjunction with each other, and any repetitions will not be elaborated upon.

[0039] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only some of the embodiments of this application, not all of them. Unless there is a conflict, the following embodiments and their technical features can be combined with each other and also belong to the technical solutions of this application.

[0040] Figure 1 is a flow chart of a circuit simulation verification method provided by an embodiment of the present application. The circuit to which the method is applicable may also be referred to as an integrated circuit, including but not limited to a radio frequency integrated circuit, which may be manufactured using semiconductor integrated circuit process technology and has the characteristics of small size, low power consumption, and high reliability. The integrated circuit may be provided with at least one circuit device such as a low-noise amplifier, a power amplifier, an oscillator, and a mixer, and the operating frequency may vary from several hundred MHz to several GHz or tens of GHz. The executor of the method may be a simulation tool, which is used to simulate the circuit (of course, including all or part of the circuit devices provided in the circuit).

[0041] As shown in FIG1 , the circuit simulation verification method includes the following steps:

[0042] S1: A simulation model is created for a circuit device using a hardware description language. The simulation model is provided with a timer and a plurality of first simulation points. The timer is used to generate second simulation points.

[0043] In one example, the netlist file of the circuit can be obtained first, and the netlist file is used to at least describe the topology, excitation signal and simulation parameters of the circuit and circuit devices to be simulated; then the present application can use the Verilog-AMS modeling language to create a simulation model for the circuit device, so as to simulate and verify the analog signal circuit or the digital and analog mixed signal circuit.

[0044] As shown in Figure 2, during the entire simulation verification process, as the simulation progresses as shown on the timeline, the simulation tool will generate multiple first simulation points in chronological order. At the moment of each first simulation point, the simulation tool can trigger any event other than the event triggered by the timer, including but not limited to: changes in electrical parameters from the voltage source, Piece Wise Linear (PWL) jumps in the voltage source, and the simulation tool's own settings requiring the use of Newton iteration to calculate a certain parameter. The generation of each first simulation point is pre-set by the simulation tool according to the simulation process. The types of trigger events inserted at each first simulation point are different or only partially the same, and cannot be completely the same; the duration between two adjacent first simulation points does not follow a periodic pattern.

[0045] The second simulation points generated by the timer follow a certain periodic pattern. Specifically, the duration t between any two adjacent first simulation points must satisfy t = m * T, where m is a positive integer and T is the period set by the timer itself for generating these second simulation points, also known as the minimum duration between adjacent first simulation points. Furthermore, at each second simulation point, the trigger event inserted by the simulation tool can be the same type, a key difference from the first simulation point.

[0046] S2: Obtain input signals of the current first simulation point and the previous first simulation point during the simulation verification process.

[0047] When an input signal is received at each first simulation point, S2 may be executed.

[0048] The input signal is the electrical signal received by the circuit device. To facilitate the comparison in S3 below, electrical parameters corresponding to the electrical signal may be obtained. The electrical parameters include but are not limited to at least one of voltage, current, frequency, and power.

[0049] S3: Determine whether the input signal of the current first simulation point is the same as the input signal of the previous first simulation point.

[0050] That is, electrical parameters of the same type are compared. If the values ​​of the electrical parameters of the same type are equal, it indicates whether the input signals are the same; otherwise, it indicates that the input signals are different.

[0051] If not, execute S41: control the timer to periodically generate a second simulation point.

[0052] If yes, then execute S42: control the simulation model to enter a sleep mode, and in the sleep mode, the timer stops generating the second simulation point.

[0053] Continuing with the scenario shown in Figure 2, when an input signal is received at the second first simulation point (i.e., the corresponding trigger event is received at the moment of the second first simulation point), the input signal received at the second first simulation point is compared with the input signal received at the first first simulation point. If they are the same, the simulation model enters the sleep mode, and at this time, the timer stops generating the second simulation points. As the simulation verification process progresses, once it is detected that the input signal at the first simulation point changes, for example, if the input signal received at the x-th first simulation point is different from the input signal received at the (x - 1)-th first simulation point, then the simulation model is controlled to enter the wake-up mode. After the moment of the x-th first simulation point, the S41 is executed, that is, the timer periodically generates the second simulation points according to its own settings.

[0054] As described above, after the circuit device enters the sleep mode, the timer no longer triggers and does not insert new simulation points (i.e., the second simulation points) additionally. When the next first simulation point arrives, the simulation tool will check the input signal again. If the input signal of this circuit device still does not change, the sleep mode will continue to be maintained until it is detected that the input signal changes after the trigger event corresponding to a certain first simulation point ends (it can also be when an input signal is received at a certain first simulation point), then this circuit device will wake up from the sleep state.

[0055] In this application, when the simulation model enters the sleep mode, the timer stops generating the second simulation points, thereby reducing the number of simulation points, which is beneficial to maintaining and improving the simulation speed, shortening the simulation verification cycle of an integrated circuit including high-frequency trigger clock events (i.e., Timer events), and then accelerating the design iteration of the entire integrated circuit, helping the integrated circuit to start the tape-out production as early as possible.

[0056] After the sleep mode, if it is determined that the input signals of the current first simulation point and the previous first simulation point are different, then in the S41, it is necessary to determine the time point (i.e., the moment) when the second simulation point is generated. Optionally, the method for determining the time point when the second simulation point is generated includes: controlling the timer to obtain the time point when the second simulation point is generated according to the relational expression t2 = n*T + t1; where t2 is the time point when the second simulation point is generated, n≥1 and is a positive integer, T is the period set by the timer itself for generating the second simulation points, and t1 is the time point of the last second simulation point generated by the timer before the sleep mode.

[0057] Optionally, the time point t of the first second simulation point after entering the wake-up mode 21 also satisfies the relational expression (t 21 - t3) < T, that is, the duration between t2 and the moment t3 of the nearest first simulation point before the first second simulation point of this wake-up mode is less than the period T of the timer.

[0058] The circuit device to which this application applies may not be provided with an excitation source, i.e., a power source that provides the input signal to the circuit device. In this case, the output of the circuit device (i.e., the aforementioned output signal) is determined by an external input. During the simulation verification process, when the input signal of the simulation model remains unchanged, the output signal of the simulation model also remains unchanged, thereby ensuring simulation accuracy.

[0059] In one example, the method may further include: determining whether the circuit device is provided with an excitation source; if so, ending; if not, executing S2 to S3.

[0060] Methods for determining whether a circuit device is provided with an excitation source include:

[0061] S21: Obtain all assignment statements in the simulation model;

[0062] S22: when the input signal of the simulation model remains unchanged, determining whether corresponding variable values ​​of two adjacent first simulation points have an associated relationship according to the assignment statement; and

[0063] If yes, execute S231: determine whether the circuit device is provided with an excitation source.

[0064] If not, execute S232: determine whether the circuit device is provided with an excitation source.

[0065] The simulation tool takes the output signal of each first simulation point as the starting point and checks all assignment statements in the simulation model. If it is found that the output signal of the current first simulation point is affected by the relevant variable value of the previous first simulation point when the input signal of each first simulation point remains unchanged, it means that the circuit device is a device with its own excitation source; otherwise, it means that the circuit device does not have its own excitation source.

[0066] The variable value for executing S22 can be determined according to actual needs, such as at least one of voltage, current, resistance, frequency and power.

[0067] As shown in FIG3 , the embodiment of the present application further provides a circuit simulation verification device 30, comprising:

[0068] A creation module 31 is used to create a simulation model for the circuit device using a hardware description language, wherein the simulation model includes a timer and a plurality of first simulation points, and the timer is used to generate second simulation points;

[0069] An acquisition module 32 is configured to acquire input signals of a current first simulation point and a previous first simulation point during a simulation verification process;

[0070] A judging module 33, configured to judge whether the input signal of the current first simulation point is the same as the input signal of the previous first simulation point;

[0071] a control module 34 configured to control the timer to periodically generate a second simulation point when the input signal of the current first simulation point is different from the input signal of the previous first simulation point; and to control the simulation model to enter a sleep mode when the input signal of the current first simulation point is the same as the input signal of the previous first simulation point, and to control the timer to stop generating the second simulation point in the sleep mode;

[0072] The inserting module 35 is used to insert a trigger event at the second simulation point.

[0073] An embodiment of the present application also provides an electronic device, including a memory and a processor, wherein the memory stores instructions, such as circuit simulation verification instructions, which, when executed by the processor, implement the steps corresponding to the circuit simulation verification method of any of the above examples.

[0074] This application does not limit the specific form of the electronic device.

[0075] An embodiment of the present application further provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps corresponding to the circuit simulation verification method described in any example are implemented.

[0076] The storage medium may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0077] Since the instructions stored in the storage medium can execute the steps in any circuit simulation verification method provided in the embodiments of the present application, the beneficial effects that can be achieved by any circuit simulation verification method provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0078] In addition, the circuit simulation verification device 30, electronic device and storage medium provided in the embodiment of the present application are complete devices respectively, and also have the corresponding structures of known devices. This application only provides an illustrative description of some structural elements involved in circuit simulation verification, and does not list other structural elements one by one.

[0079] The above descriptions are only some embodiments of the present application and do not limit the patent scope of the present application. For ordinary technicians in this field, any equivalent structural changes made using the contents of this specification and drawings are also included in the patent protection scope of the present application.

[0080] Although the terms "first," "second," and the like are used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. In addition, the singular forms "a," "an," and "the" are intended to include the plural forms as well. The terms "or" and "and / or" are to be interpreted as inclusive, meaning any one or any combination. Exceptions to this definition occur only when a combination of elements, functions, steps, or operations is inherently mutually exclusive in some manner.

Claims

1. A circuit simulation and verification method, characterized in that, The method includes: Creating a simulation model for a circuit device using a hardware description language, where the simulation model is provided with a timer and a number of first simulation points, and the timer is used to generate second simulation points; Obtaining the input signals of the current first simulation point and the previous first simulation point during the simulation verification process; Determining whether the input signals of the current first simulation point and the previous first simulation point are the same; If not, controlling the timer to periodically generate the second simulation points; If so, controlling the simulation model to enter a sleep mode, in which the timer stops generating the second simulation points.

2. The method according to claim 1, wherein The input signal includes at least one of voltage, current, frequency, and power.

3. The method according to claim 1, wherein The circuit device is not provided with an excitation source. During the simulation verification process, when the input signal of the simulation model remains unchanged, the output signal remains unchanged.

4. The method according to claim 3, wherein The method for determining whether the circuit device is provided with an excitation source includes: Obtaining all assignment statements in the simulation model; When the input signal of the simulation model remains unchanged, determining whether there is an associated relationship between the corresponding variable values of two adjacent first simulation points according to the assignment statements; If so, determining that the circuit device is provided with an excitation source; If not, determining that the circuit device is not provided with an excitation source.

5. The method according to claim 1, wherein After the sleep mode, if it is determined that the input signals of the current first simulation point and the previous first simulation point are different, Then the controlling the timer to periodically generate the second simulation points includes: Controlling the timer to obtain the time point for generating the second simulation point according to the relationship t2 = n*T + t1; where t2 is the time point for generating the second simulation point, n≥1 and is a positive integer, T is the period for the timer to generate the second simulation point set by itself, and t1 is the time point of the last second simulation point generated by the timer before the sleep mode.

6. The method according to any one of claims 1 to 5, characterized in that The hardware description language includes Verilog-AMS modeling language.

7. The method according to claim 1, wherein The types of trigger events inserted at each of the first simulation points are different or partially the same, and the types of trigger events inserted at each of the second simulation points are the same.

8. A circuit simulation verification device, characterized in that, The device includes: A creation module for creating a simulation model for a circuit device using a hardware description language, where the simulation model is provided with a timer and a number of first simulation points, and the timer is used to generate second simulation points; An acquisition module for acquiring the input signals of the current first simulation point and the previous first simulation point during the simulation verification process; A judgment module for judging whether the input signals of the current first simulation point and the previous first simulation point are the same; A control module for controlling the timer to periodically generate the second simulation points when the input signals of the current first simulation point and the previous first simulation point are different; and controlling the simulation model to enter a sleep mode when the input signals of the current first simulation point and the previous first simulation point are the same, and controlling the timer to stop generating the second simulation points in the sleep mode; An insertion module for inserting trigger events at the second simulation points.

9. An electronic device, characterized in that, The electronic device includes: A processor; A memory for storing executable instructions of the processor; Wherein, the processor is configured to execute the instructions to implement the circuit simulation verification method according to any one of claims 1 to 7.

10. A storage medium, characterized in that, A computer program is stored, and when the computer program is executed by a processor, the circuit simulation verification method according to any one of claims 1 to 7 is implemented.

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