Semiconductor device

Abstract

Disclosed in the present invention is a semiconductor device. The semiconductor device comprises an epitaxial structure, a first dielectric layer, a gate, an air-gate field plate, and a second dielectric layer, wherein the first dielectric layer covers the epitaxial structure; the gate is arranged on the side of the epitaxial structure where the first dielectric layer is provided; the air-gate field plate is arranged on the side of the gate away from the epitaxial structure, and makes contact with the gate; the second dielectric layer covers all the surfaces of the first dielectric layer, the gate and the air-gate field plate facing away from the epitaxial structure; and the thickness of the portion of the gate exposed by the first dielectric layer is greater than twice the thickness of the portion of the second dielectric layer covering the first dielectric layer and overlapping with a gate field plate, and / or greater than twice the thickness of the portion of the second dielectric layer located on the surface of the air-gate field plate close to the epitaxial structure. The present invention can reduce the parasitic capacitance of the semiconductor device and prolong the service life of the semiconductor device.

Description

semiconductor devices Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and in particular to a semiconductor device. Background Art

[0002] Semiconductor devices have important applications in the field of semiconductor technology, and correspondingly, research on semiconductor devices is increasing.

[0003] However, as the operating frequencies of electronic products continue to increase, the impact of parasitic capacitance in semiconductor devices is also increasing. When parasitic capacitance is high, the operating frequency of semiconductor devices is limited. Furthermore, the service life of semiconductor devices is also shortened. Therefore, reducing the parasitic capacitance of semiconductor devices and increasing their service life are particularly important. Summary of the Invention

[0004] The present invention provides a semiconductor device to reduce the parasitic capacitance of the semiconductor device and to increase the service life of the semiconductor device.

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising an epitaxial structure, a first dielectric layer, a gate, an air grid field plate, and a second dielectric layer;

[0006] The first dielectric layer covers the epitaxial structure; the gate is arranged on a side of the epitaxial structure where the first dielectric layer is arranged; the air grid field plate is arranged on a side of the gate away from the epitaxial structure and in contact with the gate;

[0007] The second dielectric layer covers all surfaces of the first dielectric layer, the gate, and the air grid field plate that are away from the epitaxial structure; the thickness of the portion of the gate exposed by the first dielectric layer is greater than twice the thickness of the portion of the second dielectric layer covering the first dielectric layer and overlapping with the gate field plate, and / or greater than twice the thickness of the portion of the second dielectric layer located on a side of the air grid field plate close to the epitaxial structure.

[0008] Optionally, the thickness of the second dielectric layer located on a side of the air grid field plate away from the epitaxial structure is greater than the thickness of the second dielectric layer located on a side of the air grid field plate close to the epitaxial structure; and / or the thickness of the second dielectric layer located on a side of the air grid field plate away from the epitaxial structure is greater than the thickness of the second dielectric layer covering the first dielectric layer and overlapping with the gate field plate.

[0009] Optionally, the thickness of a portion of the gate exposed by the first dielectric layer is greater than twice the thickness of a portion of the second dielectric layer covering the first dielectric layer and not overlapping with the gate field plate.

[0010] Optionally, the semiconductor device further comprises a source and a drain; the source is located on one side of the gate and in contact with the epitaxial structure; the drain is located on the other side of the gate and in contact with the epitaxial structure;

[0011] The air grid field plate includes a support portion contacting the gate, a first extension portion extending from the support portion toward the drain, and a second extension portion extending from the support portion toward the source.

[0012] Optionally, the semiconductor device further includes a source field plate, which is located on a side of the gate close to the drain and electrically connected to the source.

[0013] Optionally, the source field plate is disposed between the second extension portion and the epitaxial structure; along the thickness direction of the semiconductor device, an orthographic projection of the second extension portion on the epitaxial structure partially overlaps with an orthographic projection of the source field plate on the epitaxial structure;

[0014] The semiconductor device includes an active area and an inactive area at least partially surrounding the active area, and the gate, the source, the source field plate and the drain are arranged in the active area; the semiconductor device also includes a connecting portion, which is in the same layer as the source field plate; the connecting portion is arranged in the inactive area and contacts the source and the source field plate.

[0015] Optionally, the source field plate, the connecting portion and the source are an integrated structure.

[0016] Optionally, the source field plate is arranged in contact with the first dielectric layer, and the second dielectric layer covers the source field plate.

[0017] Optionally, the thickness of a portion of the gate exposed by the first dielectric layer is greater than twice the sum of the thickness of a portion of the second dielectric layer covering the first dielectric layer and overlapping with the gate field plate and the thickness of the source field plate.

[0018] Optionally, an air dielectric layer is provided between the source field plate and the air grid field plate, and a thickness of the air dielectric layer is greater than twice a thickness of the source field plate.

[0019] Optionally, the first dielectric layer and the second dielectric layer are made of the same material.

[0020] The technical solution of an embodiment of the present invention employs a semiconductor device comprising an epitaxial structure, a first dielectric layer, a gate, an air grid field plate, and a second dielectric layer; the first dielectric layer covers the epitaxial structure; the gate is disposed on the side of the epitaxial structure where the first dielectric layer is disposed; the air grid field plate is disposed on the side of the gate away from the epitaxial structure and in contact with the gate; the second dielectric layer covers all surfaces of the first dielectric layer, the gate, and the air grid field plate that face away from the epitaxial structure; the thickness of the portion of the gate exposed by the first dielectric layer is greater than twice the thickness of the portion of the second dielectric layer covering the first dielectric layer and overlapping the gate grid field plate, and / or greater than twice the thickness of the portion of the second dielectric layer located on the side of the air grid field plate that is closer to the epitaxial structure. The second dielectric layer protects the air grid field plate and the gate, thereby increasing the service life of the semiconductor device. Furthermore, its thickness is configured to ensure the formation of an air grid field plate structure, thereby reducing the gate parasitic capacitance of the semiconductor device.

[0021] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] FIG1 is a top view of a semiconductor device provided by an embodiment of the present invention;

[0024] FIG2 is a cross-sectional view of FIG1 along the A1A2 direction;

[0025] FIG3 is a top view of another semiconductor device provided by an embodiment of the present invention;

[0026] FIG4 is a cross-sectional view taken along line A1A2 of FIG3 ;

[0027] FIG5 is a top view of another semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] FIG1 is a top view of a semiconductor device provided by an embodiment of the present invention, and FIG2 is a cross-sectional view of FIG1 taken along line A1A2. Referring to FIG1 and FIG2, the semiconductor device includes an epitaxial structure 1, a first dielectric layer 21, a gate 31, an air grid field plate 32, and a second dielectric layer 22. The first dielectric layer 21 covers the epitaxial structure 1. The gate 31 is disposed on a side of the epitaxial structure 1 where the first dielectric layer 21 is disposed. The air grid field plate 32 is disposed on a side of the gate 31 away from the epitaxial structure 1 and in contact with the gate 31. The second dielectric layer 22 covers all surfaces of the first dielectric layer 21, the gate 31, and the air grid field plate 32 that face away from the epitaxial structure 1. The thickness of the portion of the gate 31 exposed by the first dielectric layer 21 is greater than twice the thickness of the portion of the second dielectric layer 22 covering the first dielectric layer 21 and overlapping the gate field plate 32, and / or greater than twice the thickness of the portion of the second dielectric layer 22 located on a side 222 of the air grid field plate 32 that is adjacent to the epitaxial structure 1.

[0031] Specifically, the epitaxial structure 1 may include a substrate and an epitaxial layer. The substrate may be, for example, a single crystal substrate such as silicon or germanium, or a substrate such as silicon oxide, silicon carbide, or gallium arsenide. The epitaxial layer may have multiple layers, such as a buffer layer, a channel layer, and a barrier layer. Of course, the epitaxial structure 1 of this embodiment is not limited to the above structure.

[0032] The gate structure of the semiconductor device in this embodiment is an air field plate structure, that is, it includes a gate 31 that penetrates the first dielectric layer 21 and contacts the epitaxial structure 1, and an air field plate 32 that contacts the gate 31. Air dielectric exists between the air field plate 32 and the first dielectric layer 21. By providing the air field plate, the parasitic capacitance of the gate is reduced.

[0033] In this embodiment, a second dielectric layer 22 is also provided. The second dielectric layer 22 covers the surface of the first dielectric layer 21 away from the epitaxial structure 1, the side of the gate 31, the surface of the air field plate 32 close to the epitaxial structure 1, and the surface of the air field plate 32 away from the epitaxial structure 1. The second dielectric layer 22 protects the gate 31 and the air field plate 32 from corrosion by external factors such as water and oxygen, thereby reducing the probability of damage to the gate 31 and the air field plate 32, thereby increasing the service life of the semiconductor device. In addition, the second dielectric layer 22 can also reduce the probability of damage to the air field plate 32 and the gate 31 due to external physical impact, further increasing the service life of the semiconductor device.

[0034] In addition, in this embodiment, the gate 31 includes a portion exposed by the first dielectric layer 31. In some embodiments, the gate 31 may penetrate the first dielectric layer 21 and contact the epitaxial structure 1, or may partially penetrate the first dielectric layer 21. Of course, a gate dielectric layer may also be provided between the gate 31 and the epitaxial structure 1. The thickness D1 of the portion of the gate 31 exposed by the first dielectric layer 21 is set to be greater than twice the thickness of the portion of the second dielectric layer 22 covering the first dielectric layer 21 and overlapping with the gate field plate 32. This can ensure the distance between the air grid field plate 32 and the first dielectric layer 21, and / or be greater than twice the thickness of the portion of the second dielectric layer 22 located on the side 222 of the air grid field plate 32 near the epitaxial structure 1. It should be noted that the overlap described in this embodiment refers to the overlap of the orthographic projections on the substrate 1. Referring to FIG. 2 , the second dielectric layer 22 may include a first portion 221 covering the first dielectric layer 21 and overlapping the air field plate, a fourth portion 224 covering the first dielectric layer 21 and not overlapping the air field plate, a second portion 222 covering the surface of the air field plate 32 near the epitaxial structure 1, and a third portion 223 covering the surface of the air field plate 32 away from the epitaxial structure 1. Two second dielectric layers, namely the first portion 221 and the second portion 222, are located between the air field plate 32 and the first dielectric layer 21. Furthermore, because the distance between the air field plate 32 and the first dielectric layer 21 is greater than twice the thickness of the first portion 221, an air dielectric layer is ensured between the air field plate 32 and the first dielectric layer 21, thereby ensuring the formation of an air field plate structure. In other words, the second dielectric layer 21 of this embodiment not only improves the service life of the semiconductor device, but also ensures the formation of an air field plate structure, thereby reducing the gate parasitic capacitance of the semiconductor device.

[0035] The technical solution of this embodiment employs a semiconductor device comprising an epitaxial structure, a first dielectric layer, a gate, an air grid field plate, and a second dielectric layer; the first dielectric layer covers the epitaxial structure; the gate is disposed on the side of the epitaxial structure where the first dielectric layer is disposed; the air grid field plate is disposed on the side of the gate away from the epitaxial structure and in contact with the gate; the second dielectric layer covers all surfaces of the first dielectric layer, the gate, and the air grid field plate that face away from the epitaxial structure; the thickness of the portion of the gate exposed by the first dielectric layer is greater than twice the thickness of the portion of the second dielectric layer covering the first dielectric layer and overlapping the gate field plate, and / or greater than twice the thickness of the portion of the second dielectric layer located on the side of the air grid field plate that is closer to the epitaxial structure. The second dielectric layer protects the air grid field plate and the gate, thereby increasing the service life of the semiconductor device. Furthermore, its thickness is configured to ensure the formation of an air grid field plate structure, thereby reducing the gate parasitic capacitance of the semiconductor device.

[0036] Optionally, with continued reference to Figures 1 and 2, the thickness of a portion 223 of the second dielectric layer 22 located on a side of the air grid field plate 32 away from the epitaxial structure 1 is greater than the thickness of a portion of the second dielectric layer 22 located on a side of the air grid field plate 32 close to the epitaxial structure 1; and / or, the thickness of a portion 223 of the second dielectric layer 22 located on a side of the air grid field plate 32 away from the epitaxial structure 1 is greater than the thickness of a portion 221 of the second dielectric layer 22 covering the first dielectric layer 21 and overlapping with the gate field plate 32.

[0037] Specifically, since the fourth portion 224 and the third portion 223 of the second dielectric layer 22 are both located on the surface of the corresponding film layer away from the epitaxial structure 1, they are not obstructed during fabrication and can be fabricated to have the same thickness, that is, the fourth portion 224 and the third portion 223 can have the same thickness. The thickness of the third portion 223 is greater than that of the second portion 222, resulting in a thicker thickness of the third portion 223, thereby ensuring protection for the gate 31 and the air grid field plate 32. The thinness of at least one of the second portion 222 and the first portion 221 also results in a thicker thickness of the air dielectric layer between the air grid field plate 32 and the first dielectric layer 221. When the distance between the air grid field plate 32 and the first dielectric layer 21 is the same, at least one of the second portion 222 and the first portion 221 is thinner, which means that the thickness of the air dielectric layer is thicker. According to the capacitance formula, the magnitude of the gate parasitic capacitance is proportional to the equivalent dielectric constant of the dielectric layer between the air grid field plate 32 and the epitaxial layer. The dielectric constant of air is relatively small, while the dielectric constants of the second portion 222 and the first portion 221 are relatively large. The thicker air dielectric layer makes the magnitude of the gate parasitic capacitance smaller than the equivalent dielectric constant of the dielectric layer between the air grid field plate 32 and the epitaxial layer, thereby reducing the gate parasitic capacitance, which can effectively improve the efficiency and gain of the semiconductor device.

[0038] Optionally, the thickness of the portion of the gate 31 exposed by the first dielectric layer 21 is greater than twice the thickness of the portion of the second dielectric layer 22 covering the first dielectric layer 21 and not overlapping with the gate field plate 32 .

[0039] Specifically, when fabricating the second dielectric layer 22, the thickness of the fourth portion 224 and the third portion 223 is easier to control because they are not obstructed, and their thickness is also greater than that of the first portion 221 and the second portion 222. By setting the thickness of the portion of the gate 31 exposed by the first dielectric layer 21 to be greater than twice the thickness of the fourth portion 224, the thickness can be further ensured to be greater than twice the thickness of the first portion 221. It should be noted that after the second dielectric layer is fabricated, the thickness of the first portion 221 is greater than or equal to that of the second portion 222.

[0040] Optionally, with continued reference to Figures 1 and 2, the semiconductor device further includes a source 4 and a drain 5; the source 4 is located on one side of the gate 31 and in contact with the epitaxial structure 1; the drain 5 is located on the other side of the gate 31 and in contact with the epitaxial structure 1; the air grid field plate 32 includes a support portion 321 in contact with the gate 31, a first extension portion 322 extending from the support portion 321 toward the drain 5, and a second extension portion 323 extending from the support portion 321 toward the source 4. In this embodiment, the second dielectric layer 22 can cover either the source 4 or the drain 5, thereby providing protection for both the source 4 and the drain 5.

[0041] Alternatively, Figure 3 is a top view of another semiconductor device provided by an embodiment of the present invention, and Figure 4 is a cross-sectional view taken along line A1A2 of Figure 3 , with reference to Figures 3 and 4 . The semiconductor device further includes a source field plate 7 , which is located on a side of the gate 31 close to the drain 5 and is electrically connected to the source 4 .

[0042] Specifically, the source field plate 7 can reduce the size of the feedback capacitance formed between the gate 31 and the drain 5 , thereby improving the large signal gain characteristic and thus increasing the breakdown voltage of the semiconductor device.

[0043] In the related art, the source field plate is arranged on the side of the gate field plate away from the epitaxial structure and is electrically connected to the source. However, this method is difficult to implement in the air gate field plate structure. The reasons are: first, the air gate field plate structure has high production requirements, the process is not easy to control, and the gate field plate structure often lacks a complete climbing structure in the later production. If the source field plate is directly deposited on the top and side of the gate field plate structure, it is easy to break; second, the air gate field plate structure often has a large gate metal span, leaving no space for the source field plate. Based on this, as shown in Figures 3 and 4, optionally, the source field plate 7 is arranged between the second extension portion 322 and the epitaxial structure 1; along the thickness direction of the semiconductor device, the orthographic projection of the second extension portion 322 on the epitaxial structure 1 partially overlaps with the orthographic projection of the source field plate 7 on the epitaxial structure 1; the semiconductor device includes an active area 12 and a non-active area 11 that at least partially surrounds the active area 12, and the gate 31, the source 4, the source field plate 7 and the drain 5 are arranged in the active area 12; the semiconductor device also includes a connecting portion 8; the connecting portion 8 is arranged in the non-active area 11 and is in contact with the source 4 and the source field plate 7.

[0044] Specifically, in this embodiment, the source field plate 7 is disposed between the air grid field plate 32 and the epitaxial structure 1, and a dielectric layer is included between the source field plate 7 and the epitaxial structure 1. The dielectric layer can be the first dielectric layer 21, or of course, it can be another dielectric layer. The source field plate 7 partially overlaps with the air grid field plate 32, so that a portion of the parasitic capacitance between the gate and the drain is transferred to the space between the gate and the source, thereby achieving control of the channel and suppression of traps. In addition, in this embodiment, a connection portion 8 is provided in the non-active region 12. Because it is provided in the non-active region 12, the connection portion 8 does not generate additional parasitic effects that affect the active region 12. In addition, the source field plate 7 and the source 4 are electrically connected in the non-active region 12, and the source field plate 7 does not need to be provided on the air grid field plate 32, thereby greatly reducing the difficulty of manufacturing the source field plate 7 in the air grid field plate structure, and thus a semiconductor device having an air grid field plate and a source field plate can be manufactured at a lower cost and a higher yield. In addition, in this embodiment, the source field plate 7 penetrates the active region 12 , that is, the source field plate 4 and the gate overlap in the current flow direction (horizontally in FIG3 ).

[0045] Optionally, in some embodiments, as shown in FIG4 , the source field plate 7 and the connecting portion 8 are an integrated structure. When manufacturing a semiconductor device, an epitaxial structure can be first fabricated using an epitaxial process, and then a first dielectric layer 21 can be grown on the epitaxial structure. Subsequently, the source electrode 4 can be fabricated, and then the source field plate 7 can be fabricated. In addition, when fabricating the source field plate 7, the connecting portion 8 can be fabricated simultaneously, so that the connecting portion 8 is electrically connected to the source electrode 4. Subsequently, the gate 31 and the air grid field plate 32 can be fabricated, and finally, the entire surface is covered with a second dielectric layer 22. With this film layer fabrication sequence, when fabricating the source field plate 7, the air grid field plate 32 is not present, and thus the problem of the air grid field plate 32 affecting the fabrication of the source field plate 7 does not arise. Of course, as shown in FIG3 , a contact metal is provided on the source electrode 4 in FIG3 , and the contact metal extends from the active area to the non-active area and contacts the connecting portion 8. In other words, the connecting portion of this embodiment only includes the portion in FIG3 that realizes the electrical connection between the source field plate 7 and the source electrode 3 and is located in the non-active area.

[0046] Alternatively, in other embodiments, as shown in FIG5 , which is a top view of another semiconductor device provided by an embodiment of the present invention, the source field plate 7, the source electrode 4, and the connecting portion 8 are an integrated structure. During manufacturing, the source field plate 7, the source electrode 4, and the connecting portion 8 can be formed in the same process, thereby further simplifying the process steps and reducing the manufacturing cost of the semiconductor device.

[0047] 4 , the source field plate 7 is disposed in contact with the first dielectric layer 21, and the second dielectric layer 22 covers the source field plate 7. In this embodiment, the second dielectric layer 22 also covers the source field plate, thereby protecting the source field plate 7 from corrosion by external forces such as water and oxygen, thereby increasing the service life of the source field plate 7 and further improving the service life of the semiconductor device.

[0048] Optionally, the thickness D1 of the portion of the gate 31 exposed by the first dielectric layer 21 is greater than twice the sum of the thickness of the portion of the second dielectric layer 22 covering the first dielectric layer 21 and overlapping with the gate field plate and the thickness of the source field plate. This arrangement allows the air grid field plate 32 to be farther away from the first dielectric layer 21. Even if the source field plate 7, the second portion 222, and the first portion 221 of the second dielectric layer 22 are present between the two, there is still sufficient space to form an air dielectric layer, thereby ensuring that the air grid field plate structure can effectively form an air field plate structure.

[0049] Optionally, referring to FIG4 , an air dielectric layer 9 is provided between the source field plate 7 and the air grid field plate 32, and the thickness of the air dielectric layer 9 is greater than twice the thickness of the source field plate 7. This arrangement can prevent the source field plate 7 from affecting the gate metal process, that is, prevent the source field plate 7 from affecting the morphology of the air grid field plate 32, thereby ensuring the manufacturing yield of the gate 31 and the air grid field plate 32, and thus ensuring a high yield of the semiconductor device.

[0050] Alternatively, in the above embodiment, the source field plate 7 may be made of one or a stack of at least two metals such as titanium, aluminum, and gold. The source and drain electrodes may also be made of one or a stack of at least two metals such as titanium, aluminum, and gold. Alternatively, the gate 31 and the air grid field plate 32 may be made of one or a stack of at least two metals such as nickel, titanium, and platinum.

[0051] Optionally, in the above embodiment, the second dielectric layer 22 and the first dielectric layer 21 may be made of the same material, for example, both may be dielectric materials such as silicon nitride, silicon oxide or aluminum oxide.

[0052] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0053] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes an epitaxial structure, a first dielectric layer, a gate, an air-gate field plate, and a second dielectric layer; The first dielectric layer covers the epitaxial structure; the gate is disposed on one side of the epitaxial structure where the first dielectric layer is provided; the air-gate field plate is disposed on a side of the gate away from the epitaxial structure and in contact with the gate; The second dielectric layer covers all surfaces of the first dielectric layer, the gate, and the air-gate field plate that face away from the epitaxial structure; the thickness of the portion of the gate exposed by the first dielectric layer is greater than twice the thickness of the portion of the second dielectric layer that covers the first dielectric layer and overlaps with the gate field plate, and / or greater than twice the thickness of the portion of the second dielectric layer located on the side of the air-gate field plate close to the epitaxial structure.

2. The semiconductor device according to claim 1, wherein The thickness of the portion of the second dielectric layer located on the side of the air-gate field plate away from the epitaxial structure is greater than the thickness of the portion of the second dielectric layer located on the side of the air-gate field plate close to the epitaxial structure; and / or, the thickness of the portion of the second dielectric layer located on the side of the air-gate field plate away from the epitaxial structure is greater than the thickness of the portion of the second dielectric layer that covers the first dielectric layer and overlaps with the gate field plate.

3. The semiconductor device according to claim 1, wherein, The thickness of the portion of the gate exposed by the first dielectric layer is greater than twice the thickness of the portion of the second dielectric layer that covers the first dielectric layer and does not overlap with the gate field plate.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a source electrode and a drain electrode; the source electrode is located on one side of the gate and in contact with the epitaxial structure; the drain electrode is located on the other side of the gate and in contact with the epitaxial structure; The air-gate field plate includes a support portion in contact with the gate, a first extension portion extending from the support portion toward the drain electrode, and a second extension portion extending from the support portion toward the source electrode.

5. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes a source field plate, the source field plate is located on a side of the gate close to the drain electrode, and is electrically connected to the source electrode; The source field plate is disposed between the second extension portion and the epitaxial structure; In the thickness direction of the semiconductor device, the orthographic projection of the second extension portion on the epitaxial structure partially overlaps with the orthographic projection of the source field plate on the epitaxial structure; The semiconductor device includes an active region and a non-active region at least partially surrounding the active region, the gate, the source electrode, the source field plate, and the drain electrode are disposed in the active region; the semiconductor device further includes a connection portion, the connection portion is on the same layer as the source field plate; the connection portion is disposed in the non-active region and is in contact with the source electrode and the source field plate.

6. The semiconductor device according to claim 5, wherein The source field plate, the connection portion, and the source electrode are an integral structure.

7. The semiconductor device according to claim 5, wherein The source field plate is in contact with the first dielectric layer, and the second dielectric layer covers the source field plate.

8. The semiconductor device according to claim 7, wherein, The thickness of the portion of the gate exposed by the first dielectric layer is greater than twice the sum of the thickness of the portion of the second dielectric layer that covers the first dielectric layer and overlaps with the gate field plate and the thickness of the source field plate.

9. The semiconductor device according to claim 5, wherein An air dielectric layer is provided between the source field plate and the air gate field plate, and the thickness of the air dielectric layer is greater than twice the thickness of the source field plate.

10. The semiconductor device according to claim 1, characterized in that, The first dielectric layer and the second dielectric layer are made of the same material.

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