Semiconductor device

Abstract

A semiconductor device, comprising: a substrate; an epitaxial structure, located on one side of the substrate, and a two-dimensional electron gas being provided in the epitaxial structure; an electrode structure, located on the side of the epitaxial structure away from the substrate, part of the electrode structure being located in a first active area, and the other part of the electrode structure being located in a passive area; and at least one odd mode resistor, located outside the first active area and electrically connected to the electrode structure, wherein each odd mode resistor among the at least one odd mode resistor comprises a first resistor electrode and a second resistor electrode, and at least part of the first resistor electrode and at least part of the second resistor electrode are both located in a second active area; and in a same odd mode resistor, the first resistor electrode and the second resistor electrode are both in ohmic contact with the two-dimensional electron gas of the second active area, and a two-dimensional electron gas conductive channel exists between the first resistor electrode and the second resistor electrode along the arrangement direction of the first resistor electrode and the second resistor electrode. A first odd mode resistor is provided to suppress odd mode oscillation, thereby improving the stability of the semiconductor device.

Description

semiconductor devices Technical Field

[0001] The present application relates to the field of microelectronics technology, and in particular to a semiconductor device. Background Art

[0002] Gallium nitride high electron mobility transistor (HEMT) has excellent characteristics such as wide bandgap and high mobility. It is suitable for the production of high-temperature, high-frequency, high-voltage and high-power devices. It can be widely used in the fields of radio frequency microwaves and power electronics. It is one of the current research hotspots in the field of semiconductor devices.

[0003] Currently, 5G communications have increasingly higher requirements for the bandwidth and operating frequency of semiconductor chips. Gallium nitride high electron mobility transistors are high electron mobility devices formed by using the two-dimensional electron gas at the heterojunction in the epitaxial structure. They can be better applied to high frequency, high voltage and high power fields, and are naturally favored by the 5G communication field.

[0004] For GaN RF power amplifiers, increasing device power, gain, and efficiency is a constant goal for GaN chips. However, achieving higher power often leads to oscillations, which can affect device performance or stability. Therefore, improving the stability of semiconductor devices is an urgent issue. Summary of the Invention

[0005] The present application provides a semiconductor device to suppress oscillation, thereby improving the stability of the semiconductor device.

[0006] An embodiment of the present application provides a semiconductor device having a first active region and a second active region that are independent of each other, and a passive region surrounding the first active region and the second active region. The semiconductor device includes: a substrate; an epitaxial structure located on one side of the substrate, wherein a two-dimensional electron gas is provided in the epitaxial structure and exists in the first active region and the second active region; an electrode structure located on a side of the epitaxial structure away from the substrate, wherein a portion of the electrode structure is located in the first active region and another portion of the electrode structure is located in the passive region; and at least one odd-mode resistor located outside the first active region and electrically connected to the electrode structure. Each of the at least one odd-mode resistor includes a first resistor electrode and a second resistor electrode, at least a portion of the first resistor electrode and at least a portion of the second resistor electrode are located in the second active region. In the same odd-mode resistor, the first resistor electrode and the second resistor electrode both form ohmic contact with the two-dimensional electron gas in the second active region, and a two-dimensional electron gas conductive channel exists between the first resistor electrode and the second resistor electrode along an arrangement direction of the first resistor electrode and the second resistor electrode.

[0007] Optionally, the distance between the first resistor electrode and the second resistor electrode is d, and the extension lengths of the first resistor electrode and the second resistor electrode are both w; the contact resistance of the first resistor electrode is Rc1, the contact resistance of the second resistor electrode is Rc2, and the sheet resistance of the two-dimensional electron gas between the first resistor electrode and the second resistor electrode is Rsh; the resistance value of the first odd-mode resistor R=Rc1+Rc2+Rsh·d / W.

[0008] Optionally, at least one odd-mode resistor includes at least one first odd-mode resistor, the electrode structure includes a gate electrode structure, the gate electrode structure includes at least one gate electrode and a gate power supply electrode, and each gate electrode in the at least one gate electrode is independently arranged with the gate power supply electrode; the first resistor electrode in the at least one first odd-mode resistor is electrically connected to the at least one gate electrode, and the second resistor electrode in the at least one first odd-mode resistor is electrically connected to the gate power supply electrode.

[0009] Optionally, the electrode structure further includes an ohmic electrode structure, comprising an interconnected ohmic electrode and an ohmic power supply electrode; each power supply electrode in at least one of the gate power supply electrode and the ohmic power supply electrode includes at least two power supply subdivisions, with any two adjacent power supply subdivisions of the at least two power supply subdivisions being independently provided; the at least one odd-mode resistor further includes at least one second odd-mode resistor; in the same second odd-mode resistor, a first resistor electrode is electrically connected to one of the at least two power supply subdivisions, and a second resistor electrode is electrically connected to the other of the at least two power supply subdivisions.

[0010] Optionally, at least one odd-mode resistor includes at least one second odd-mode resistor, the electrode structure includes at least one electrode and at least one power supply electrode electrically connected to the at least one electrode, each of the at least one power supply electrode includes at least two power supply divisions, any adjacent two of the at least two power supply divisions are independently arranged, and in the same second odd-mode resistor, the first resistor electrode is electrically connected to one of the at least two power supply divisions, and the second resistor electrode is electrically connected to the other of the at least two power supply divisions.

[0011] The technical solution of the embodiment of the present application comprises a first resistor electrode and a second resistor electrode, each of which forms an ohmic contact with a two-dimensional electron gas. A two-dimensional electron gas conductive channel exists between the first resistor electrode and the second resistor electrode, allowing the first resistor electrode and the second resistor electrode to be conductively connected. In addition, the electrode structure is electrically connected to the odd-mode resistor, thereby achieving electrical connection of the entire electrode structure. Therefore, the odd-mode resistor can dissipate the energy of the odd-mode signal, thereby suppressing the generation of odd-mode oscillation and improving the stability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a schematic top view of a semiconductor device provided by an embodiment of the present application.

[0013] FIG. 2 is a schematic cross-sectional view of the semiconductor device provided in FIG. 1 along the section line AA′.

[0014] FIG3 is a schematic top view of another semiconductor device provided by an embodiment of the present application.

[0015] FIG4 is a schematic top view of another semiconductor device provided by an embodiment of the present application.

[0016] FIG5 is a schematic top view of another semiconductor device provided by an embodiment of the present application.

[0017] FIG6 is a schematic top view of a semiconductor device provided according to another embodiment of the present application.

[0018] FIG. 7 is a schematic cross-sectional view of the semiconductor device provided in FIG. 6 along the section line AA′.

[0019] FIG8 is a schematic cross-sectional view of a semiconductor device along section line BB′ provided in FIG6 .

[0020] FIG9 is a schematic top view of another semiconductor device provided in another embodiment of the present application.

[0021] FIG10 is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] It should be noted that the terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in sequences other than those illustrated or described herein. In addition, the terms "including," "comprising," and any variations thereof are intended to cover non-exclusive inclusions.

[0023] As described in the background, GaN RF power amplifiers (RFPAs) consistently strive to improve device power, gain, and efficiency. However, achieving higher power requires multiple gate fingers, which can easily lead to long feedback loops between the gate fingers and the drain, leading to oscillations known as odd-mode oscillations. These oscillations can affect device performance and stability. Therefore, improving the stability of semiconductor devices is an urgent issue.

[0024] To address the aforementioned issues, embodiments of the present application provide a semiconductor device. Figure 1 is a schematic top view of a semiconductor device according to one embodiment of the present application; Figure 6 is a schematic top view of a semiconductor device according to another embodiment of the present application. As shown in Figures 1 and 6 , the semiconductor device comprises a first active region aa1 and a second active region aa2, which are independent of each other, and a passive region bb surrounding the first active region aa1 and the second active region aa2. A two-dimensional electron gas (2DEG) exists in the first active region aa1 and the second active region aa2. The second active region aa2 can be understood as a region within the passive region bb that retains the 2DEG.

[0025] FIG2 is a schematic cross-sectional view of a semiconductor device along the section line AA' provided in FIG1; FIG7 is a schematic cross-sectional view of a semiconductor device along the section line AA' provided in FIG6; As shown in FIG1, 2, 6 and 7, the semiconductor device includes: a substrate 10, an epitaxial structure 20, an electrode structure 30 and at least one odd-mode resistor 40. The epitaxial structure 20 is located on one side of the substrate 10, and a two-dimensional electron gas (Two Dimensional Electron Gas) is provided in the epitaxial structure 20. The present invention relates to a first embodiment of the present invention. The present invention relates to a first embodiment of the present invention. The present invention relates to a first embodiment of the present invention. The present invention relates to a first embodiment of the present invention. The present invention relates to a first embodiment of the present invention. The present invention relates to a first embodiment of the present invention. The present invention relates to a first embodiment of the present invention. The present invention relates to a first embodiment of the present invention. The present invention relates to a second embodiment of the present invention. The present invention relates to a first embodiment of the present invention. The present invention relates to a second embodiment of the present invention.

[0026] At least a portion of the first resistor electrode 401 and at least a portion of the second resistor electrode 402 are both located in the second active area aa2. This can be understood as meaning that a portion of the first resistor electrode 401 and a portion of the second resistor electrode 402 are both located in the second active area aa2, and another portion of the first resistor electrode 401 and another portion of the second resistor electrode 402 are both located in the inactive area bb, or that the entire first resistor electrode 401 and the entire second resistor electrode 402 are both located in the second active area aa2. Figures 1 and 6 merely schematically illustrate the positional relationship between the first resistor electrode 401 and the second resistor electrode 402, respectively, and the second active area aa2.

[0027] Normally, the two-dimensional electron gas in the passive region bb will be consumed by ion implantation or other methods. In the embodiment of the present application, the odd-film resistor 40 is arranged in an area where the two-dimensional electron gas is retained in the passive region bb (i.e., the second active region aa2). That is, the two-dimensional electron gas in the area where the odd-film resistor 40 is arranged in the passive region bb is retained, so that the odd-film resistor 40 forms an ohmic contact with the two-dimensional electron gas.

[0028] For example, substrate 10 may be formed of one of silicon, sapphire, silicon carbide, or gallium arsenide. Epitaxial structure 20 located on one side of substrate 10 may be formed of one or more Group III-V nitrides, such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride.

[0029] For example, with continued reference to FIG. 2 and FIG. 7 , the epitaxial structure 20 may include a nucleation layer 202 , a buffer layer 203 , a channel layer 204 , and a barrier layer 205 ; the channel layer 204 and the barrier layer may form a heterojunction structure.

[0030] For example, with continued reference to FIG. 2 and FIG. 7 , the material of the nucleation layer 202 may be aluminum nitride, and is located between the substrate 10 and the buffer layer 203 to serve as a bonding agent for the semiconductor material layer to be grown subsequently.

[0031] For example, continuing to refer to Figures 2 and 7, the buffer layer 203 is located on one side of the substrate 10. The material of the buffer layer 203 can be gallium nitride, and the buffer layer 203 can include iron atoms, which is conducive to achieving high resistance performance of the buffer layer 203, thereby ensuring that vertical leakage can be blocked and the pinch-off performance of the semiconductor device can be improved.

[0032] Continuing with reference to Figures 2 and 7, the material of the channel layer 204 can be a Group III nitride, for example, AlxGa1-xN, where 0 ≤ x < 1. For example, x = 0 indicates that the material of the channel layer 204 is GaN. The material of the channel layer 204 can also be other Group III nitrides, for example, the material of the channel layer 204 can be InGaN or AlInGaN. The channel layer 204 can be undoped or unintentionally doped. The channel layer 204 can also be a multilayer structure, for example, the channel layer 204 can be a combination of a superlattice, GaN, or AlGaN.

[0033] For example, the barrier layer may be made of AlN, AlInN, AlGaN, or AlInGaN. The barrier layer has a sufficient thickness and a high enough Al composition so that doping forms a significant carrier concentration at the interface between the channel layer 204 and the barrier layer.

[0034] 2 and 7 , due to the band gap difference between the barrier layer and the channel layer 204 and the piezoelectric polarization effect at the interface between the barrier layer and the channel layer 204 , a two-dimensional electron gas is formed at the interface between the channel layer 204 and the barrier layer.

[0035] It is understood that the epitaxial structure 20 may further include a cap layer, which is located on the surface of the potential barrier away from the substrate 10. The cap layer can reduce surface states to reduce surface leakage of subsequent semiconductor devices and inhibit current collapse, thereby improving the stability and reliability of the epitaxial structure 20 and the semiconductor device.

[0036] In the semiconductor device provided in the embodiment of the present application, each odd-film resistor 40 includes a first resistor electrode 401 and a second resistor electrode 402. The first resistor electrode 401 and the second resistor electrode 402 both form ohmic contact with the two-dimensional electron gas. A two-dimensional electron gas conductive channel exists between the first resistor electrode 401 and the second resistor electrode 402, allowing the first resistor electrode 401 and the second resistor electrode 402 to be conductive. In addition, the electrode structure 30 is electrically connected to the odd-film resistor 40, thereby achieving electrical connection of the entire electrode structure 30. Therefore, the odd-film resistor 40 can dissipate the odd-film signal in the electrode structure 30, thereby suppressing the generation of odd-film oscillation, thereby improving the stability of the semiconductor device.

[0037] In addition, compared to preparing thin film resistors, the present application does not need to introduce additional metal layers when preparing the odd-mode resistor 40, thereby reducing the process steps in the preparation process and further reducing the complexity and manufacturing cost of the semiconductor device.

[0038] Optionally, continuing to refer to Figures 1 and 6, in the same odd-mode resistor 40, the distance between the first resistor electrode 401 and the second resistor electrode 402 is d, and the extension lengths of the first resistor electrode 401 and the second resistor electrode 402 are both w; the contact resistance of the first resistor electrode 401 is Rc1, the contact resistance of the second resistor electrode 402 is Rc2, and the square resistance of the two-dimensional electron gas between the first resistor electrode 401 and the second resistor electrode 402 is Rsh; the resistance value of the odd-mode resistor 40 is R=Rc1+Rc2+Rsh·d / W.

[0039] It should be understood that Rc refers to the ohmic contact resistance, that is, Rc1 is the ohmic contact resistance between the first resistor electrode 401 and the two-dimensional electron gas, and Rc2 is the ohmic contact resistance between the second resistor electrode 402 and the two-dimensional electron gas.

[0040] Specifically, for a certain process platform, the contact resistances Rc1 and Rc2 of the first resistor electrode 401 and the second resistor electrode 402 and the sheet resistance Rsh of the two-dimensional electron gas between the first resistor electrode 401 and the second resistor electrode 402 are fixed. Therefore, the resistance of the odd-mode resistor 40 can be changed by adjusting the distance d between the first resistor electrode 401 and the second resistor electrode 402 and / or adjusting the extension length w of the first resistor electrode 401 and the second resistor electrode 402, so that the resistance of the odd-mode resistor 40 can be diversified by adjusting the resistance of the odd-mode resistor 40, thereby achieving different suppression effects, thereby meeting the needs of various different scenarios.

[0041] It should be noted that the resistance of the odd-film resistor 40 can be designed according to the performance and stability of the semiconductor device to improve the flexibility of the configuration of the odd-film resistor 40. For example, the resistance of the odd-film resistor 40 can be several ohms to tens of ohms.

[0042] The following describes different types of semiconductor devices of the present application based on two embodiments.

[0043] A semiconductor device will be described below based on a first embodiment. The first embodiment is described from the direction of at least one odd-mode resistor 40 including at least one first odd-mode resistor 41 and at least one second odd-mode resistor 42. As shown in Figures 1 to 5, the structure of the semiconductor device is as follows.

[0044] The electrode structure 30 includes a gate electrode structure 31, which includes at least one gate electrode 301 and a gate power supply electrode 302. Each gate electrode 301 in the at least one gate electrode 301 is independently arranged from the gate power supply electrode 302. Each first odd-mode resistor 41 in the at least one first odd-mode resistor 41 includes a first resistor electrode 401 and a second resistor electrode 402. The first resistor electrode 401 and the second resistor electrode 402 both form ohmic contact with the two-dimensional electron gas, and a two-dimensional electron gas conductive channel exists between the first resistor electrode 401 and the second resistor electrode 402 along the arrangement direction of the first resistor electrode 401 and the second resistor electrode 402, that is, the first resistor electrode 401 and the second resistor electrode 402 are electrically connected via the two-dimensional electron gas. The first resistor electrode 401 in the at least one first odd-mode resistor 41 is electrically connected to the at least one gate electrode 301, and the second resistor electrode 402 in the at least one first odd-mode resistor 41 is electrically connected to the gate power supply electrode 302.

[0045] In one example, as shown in Figures 3 and 4 , when at least one gate electrode 301 includes multiple gate electrodes 301, in the same first odd-mode resistor 41, the first resistor electrode 401 is electrically connected to at least one gate electrode 301 among the multiple gate electrodes 301, and the second resistor electrode 402 is electrically connected to the gate power supply electrode 302. In other words, one gate electrode 301 corresponds to one first odd-mode resistor 41, or multiple gate electrodes 301 correspond to one first odd-mode resistor 41.

[0046] In another example, as shown in FIG1 , when the at least one gate electrode 301 includes multiple gate electrodes 301, a first odd-mode resistor 41 is provided between each gate electrode 301 of the multiple gate electrodes 301 and the gate power supply electrode 302. In other words, each gate electrode 301 corresponds to a first odd-mode resistor 41.

[0047] The gate power supply electrode 302 can be understood as a gate pad. Each gate electrode 301 is independently provided with the gate power supply electrode 302 , that is, each gate electrode 301 is not in contact with the gate power supply electrode 302 , but there is a gap between them.

[0048] The first odd-mode resistor 41 is disposed in a region within the passive region bb where the two-dimensional electron gas (2DEG) is retained. That is, the two-dimensional electron gas (2DEG) in the region within the passive region bb where the first odd-mode resistor 41 is disposed is retained, thereby establishing ohmic contact between the first odd-mode resistor 41 and the 2DEG. It should be noted that both the gate electrode 301 and the gate power supply electrode 302 have zero contact with the 2DEG in the region where the first odd-mode resistor 41 is located. That is, when the gate electrode 301 and the gate power supply electrode 302 are formed, they do not completely enclose the first resistor electrode 401 and the second resistor electrode 402 in the first odd-mode resistor 41. Instead, at least two adjacent side surfaces of the first resistor electrode 401 and the second resistor electrode 402 in the first odd-mode resistor 41 are exposed. This ensures that the first resistor electrode 401 and the second resistor electrode 402 in the first odd-mode resistor 41 are in full contact with the 2DEG while preventing contact between the gate electrode 301 and the gate power supply electrode 302 and the 2DEG. Furthermore, along the arrangement direction of the first resistor electrode 401 and the second resistor electrode 402 , a two-dimensional electron gas conductive channel exists between the first resistor electrode 401 and the second resistor electrode 402 , thereby enabling the first resistor electrode 401 and the second resistor electrode 402 to be conductively connected.

[0049] In the same first odd-mode resistor 41, the first resistor electrode 401 is electrically connected to at least one gate electrode 301, and the second resistor electrode 402 is electrically connected to the gate power supply electrode 302, so that the first odd-mode resistor 41 is set between the gate electrode 301 and the gate power supply electrode 302, thereby consuming the energy of the odd-mode signal through the first odd-mode resistor 41, that is, suppressing odd-mode oscillation, thereby improving the stability of the semiconductor device.

[0050] It should be noted that the first resistor electrode 401 can be located at the end of the gate electrode 301 close to the gate power supply electrode 302, and the second resistor electrode 402 can be located at the end of the gate power supply electrode 302 close to the gate electrode 301, so as to improve the freedom of setting the first strange membrane resistor 40.

[0051] It is understood that the electrode structure 30 may further include a source electrode 305 and a source power supply electrode electrically connected to the source electrode 305. The electrode structure 30 may further include a drain electrode structure 32, wherein the drain electrode structure 32 includes a drain electrode 303 and a drain power supply electrode 304 electrically connected to the drain electrode 303. The source electrode 305 may serve as the input terminal of the semiconductor device, and the drain electrode 303 may serve as the output terminal of the semiconductor device. The drain power supply electrode 304 may be understood as a drain pad. The drain electrode 303 in the first active area aa1 may be connected to the drain power supply electrode 304 in the passive area bb. The drain electrode 303 may receive a voltage signal through the drain power supply electrode 304 to ensure normal operation of the semiconductor device.

[0052] In the semiconductor device provided in the embodiment of the present application, the first odd-mode resistor 41 includes a first resistor electrode 401 and a second resistor electrode 402. The first resistor electrode 401 and the second resistor electrode 402 both form ohmic contact with the two-dimensional electron gas. A two-dimensional electron gas conductive channel exists between the first resistor electrode 401 and the second resistor electrode 402, allowing the first resistor electrode 401 and the second resistor electrode 402 to be channel-connected to achieve electrical connection. Furthermore, for independently provided gate electrodes 301 and gate power supply electrodes 302, in the same first odd-mode resistor 41, the first resistor electrode 401 is electrically connected to at least one gate electrode 301, and the second resistor electrode 402 is electrically connected to the gate power supply electrode 302, so that the odd-mode signal in the gate electrode 301 can be dissipated through the first odd-mode resistor 41, thereby suppressing the generation of odd-mode oscillations and thereby improving the stability of the semiconductor device.

[0053] Optionally, referring to FIG1 , when the at least one gate electrode 301 includes multiple gate electrodes 301 , any gate electrode 301 and the gate power supply electrode 302 are independently provided, and a first odd-mode resistor 41 is provided between any gate electrode 301 and the gate power supply electrode 302 .

[0054] Specifically, a first resistance electrode 401 is provided at the end position of each gate electrode 301 near the gate power supply electrode 302, and at least two second resistance electrodes 402 are provided at the position of the gate power supply electrode 302 near the gate electrode 301, and the first resistance electrode 401 and the second resistance electrode 402 are provided correspondingly, that is, the number of first odd-mode resistors 41 is the same as the number of gate electrodes 301, so that odd-mode oscillation can be further suppressed by the first odd-mode resistors 41, thereby improving the stability of the semiconductor device.

[0055] Optionally, continuing to refer to Figure 1, when at least one gate electrode 301 includes multiple gate electrodes 301, each gate electrode 301 of the multiple gate electrodes 301 extends along a first direction (the Y direction shown in Figure 1), and the multiple gate electrodes 301 are arranged along a second direction (the X direction shown in Figure 1), and along the second direction X, any two adjacent gate electrodes 301 are symmetrically arranged about the symmetry axis (the vertical long dashed line M shown in Figure 1), and the symmetry axis M extends along the first direction Y; the first direction Y and the second direction X intersect and are both parallel to the plane where the substrate 10 is located; the first odd-mode resistor 41 electrically connected to the two symmetrically arranged gate electrodes 301 is also symmetrically arranged about the symmetry axis M.

[0056] Specifically, the first odd-mode resistors 41 electrically connected to the two symmetrically arranged gate electrodes 301 are symmetrically arranged about the symmetry axis M, so that the phase balance of each gate electrode 301 can be ensured, so that odd-mode oscillation is not likely to occur. In addition, the symmetry of the two first odd-mode resistors 41 is consistent with the symmetry of the two gate electrodes 301, which can further reduce the possibility of odd-mode signal oscillation in the semiconductor device and is also beneficial to ensuring the stability of the radio frequency signal.

[0057] Optionally, as shown in Figure 3, when at least one gate electrode 301 includes multiple gate electrodes 301, each gate electrode 301 in the multiple gate electrodes 301 extends along the first direction Y, and the multiple gate electrodes 301 are arranged along the second direction X; the first direction Y and the second direction X intersect and are both parallel to the plane where the substrate 10 is located; for the independently arranged gate electrodes 301 and gate power supply electrodes 302, in the same first odd-mode resistor 41, the first resistor electrode 401 is electrically connected to at least two gate electrodes 301 arranged in sequence along the second direction X, and the second resistor electrode 402 is electrically connected to the gate power supply electrode 302.

[0058] Specifically, within the same first odd-film resistor 41, the first resistor electrode 401 is electrically connected to at least two gate electrodes 301 arranged sequentially along the second direction X. That is, the at least two gate electrodes 301 arranged sequentially share the same first resistor electrode 401. In other words, at least two gate electrodes 301 are connected to the gate power supply electrode 302 via the same first odd-film resistor 41. This ensures that the odd-film signal in each gate electrode 301 is suppressed, thereby facilitating phase balance for each gate electrode 301. Furthermore, it increases the resistance of the first odd-film resistor 41 and reduces the area of ​​the semiconductor device, thereby achieving a miniaturized design for the semiconductor device. Preferably, the two adjacent gate electrodes 301 are located on either side of the same drain electrode 303.

[0059] It is understood that FIG3 only illustrates the technical solution of electrically connecting the first resistor electrode 401 in the same first odd-mode resistor 41 to two gate electrodes 301 arranged sequentially along the second direction. For example, three or more gate electrodes 301 may share the same first resistor electrode 401.

[0060] Furthermore, each gate electrode 301 of the multiple gate electrodes 301 extends along the first direction Y, the multiple gate electrodes 301 are arranged along the second direction X, and any two adjacent gate electrodes 301 along the second direction X are symmetrically arranged about the symmetry axis (the vertical long dashed line M shown in Figure 3), and the symmetry axis M extends along the first direction Y; the first direction Y and the second direction X intersect and are both parallel to the plane where the substrate 10 is located; the two first odd-mode resistors 41 electrically connected to the two symmetrically arranged gate electrodes 301 are also symmetrically arranged about the symmetry axis M.

[0061] Optionally, as shown in Figure 4, the electrode structure 30 further includes a source electrode 305, and along the second direction X, the source electrode 305 is located between two adjacent gate electrodes 301; in the same first odd-mode resistor 41, the first resistor electrode 401 is electrically connected to the two gate electrodes 301 adjacent to the source electrode 305, and the second resistor electrode 402 is electrically connected to the gate power supply electrode 302.

[0062] Specifically, in the same first odd-mode resistor 41, the first resistor electrode 401 is electrically connected to two gate electrodes 301 adjacent to the source electrode 305, and the second resistor electrode 402 is electrically connected to the gate power supply electrode 302. That is, along the second direction X, the gate electrodes 301 located on both sides of the source electrode 305 are electrically connected to the same first resistor electrode 401, and the second resistor electrode 402 is arranged corresponding to the first resistor electrode 401.

[0063] Continuing with reference to FIG3 , in the same first odd-mode resistor 41 , the first resistor electrode 401 is electrically connected to two gate electrodes 301 adjacent to the drain electrode 303 , and the second resistor electrode 402 is electrically connected to the gate power supply electrode 302 , that is, the two gate electrodes 301 on both sides of the drain electrode 303 are connected to the same first resistor electrode 401 , thereby enabling the diversity of semiconductor device settings to be achieved.

[0064] Optionally, continuing to refer to Figure 1, the gate electrode 301 includes a connected gate body 3011 and a gate tail 3012, the gate tail 3012 is located on a side of the gate body 3011 close to the gate power supply electrode 302, and along the second direction X, the extension width of the gate tail 3012 is greater than the extension width of the gate body 3011; the second direction X intersects with the extension direction of the gate electrode 301; the first resistor electrode 401 is electrically connected to the gate tail 3012, and at the position of the portion of the gate tail 3012 connected to the first resistor electrode 401, a portion of the two-dimensional electron gas is retained in the semiconductor structure.

[0065] Specifically, along the second direction X, the extended width of the gate tail portion 3012 is greater than the extended width of the gate main portion 3011. That is, along the second direction X, the width of the gate electrode 301 located in the passive region bb is greater than the width of the gate electrode 301 located in the first active region aa1, thereby improving reliability. Furthermore, the radius of curvature of the gate tail portion 3012 located in the passive region bb along the second direction X can be greater than the width of the gate main portion 3011 located in the first active region aa1 along the second direction X. This reduces the difficulty of developer solution penetrating from the ends of the gate electrode 301 to the center, thereby reducing display difficulty. Appropriate compensation can also be applied to the gate electrodes 301 at the corners of the source electrode 305 or the drain electrode 303 to compensate for or completely eliminate the problem of reduced gate electrode 301 width caused by light diffraction. Furthermore, the first resistor electrode 401 is electrically connected to the gate tail 3012, that is, the first resistor electrode 401 is electrically connected to the wider area of ​​the gate electrode 301, so that on the one hand, the connection stability is ensured, and on the other hand, it is beneficial for the first resistor electrode 401 to have a smaller contact resistance, thereby avoiding the problem of poor contact or large signal loss between the gate electrode 301 and the first resistor electrode 401.

[0066] Furthermore, the two-dimensional electron gas portion below the gate tail 3012 in the passive region bb is retained, and the gate tail 3012 has zero contact with the two-dimensional electron gas, thereby ensuring that the first resistor electrode 401 forms an ohmic contact with the two-dimensional electron gas while being electrically connected to the gate tail 3012 and avoiding contact between the gate tail 3012 and the two-dimensional electron gas.

[0067] Optionally, continuing to refer to Figure 1, the gate power supply electrode 302 includes a power supply body portion 3021 and at least one power supply protrusion 3022, the power supply body portion 3021 and the at least one power supply protrusion 3022 are connected to each other, and the at least one power supply protrusion 3022 is located on the side of the power supply body portion 3021 close to the gate electrode 301; the second resistor electrode 402 is electrically connected to the power supply protrusion 3022.

[0068] Specifically, the power supply protrusion 3022 is located on the side of the power supply body 3021 close to the gate electrode 301, the second resistor electrode 402 is electrically connected to the power supply protrusion 3022, and the power supply body 3021 serves as the main power supply pad, thereby not affecting the working characteristics of the gate power supply electrode 302. In addition, adjusting the shape of the power supply protrusion 3022 can ensure the contact effect between the gate power supply electrode 302 and the second resistor electrode 402, which is conducive to ensuring the stability of the contact between the gate power supply electrode 302 and the second resistor electrode 402; adjusting the length of the power supply protrusion 3022 can adjust the distance between the first resistor electrode 401 and the second resistor electrode 402, so as to adjust the resistance value of the first odd-mode resistor 41, so that the resistance value of the first odd-mode resistor 41 is adjustable and the adjustment method is simple, thereby meeting the needs of various different scenarios.

[0069] Optionally, continuing to refer to Figure 1, in the same first odd-mode resistor 41, the first resistor electrode 401 and the second resistor electrode 402 are arranged along the first direction Y and extend along the second direction X; the first direction Y and the second direction X intersect and are both parallel to the plane where the substrate 10 is located, and the first direction Y is parallel to the extension direction of the gate electrode 301.

[0070] Specifically, since the strange film signal existing in the gate electrode 301 will affect the stability of the semiconductor device, the arrangement direction of the first resistance electrode 401 and the second resistance electrode 402 is set to be the same as the extension direction of the gate electrode 301, so that the strange film signal in the gate electrode 301 can be dissipated through the first strange film resistor 41, thereby suppressing strange film oscillation and ensuring the stability of the semiconductor device.

[0071] Optionally, continuing to refer to Figure 1, in the same first odd-mode resistor 41, the distance between the first resistor electrode 401 and the second resistor electrode 402 is d, the extension lengths of the first resistor electrode 401 and the second resistor electrode 402 are both w, the contact resistance of the first resistor electrode 401 is Rc1, the contact resistance of the second resistor electrode 402 is Rc2, the square resistance of the two-dimensional electron gas between the first resistor electrode 401 and the second resistor electrode 402 is Rsh, and the resistance value of the first odd-mode resistor 41 is R=Rc1+Rc2+Rsh·d / W.

[0072] 1 and 2 , the electrode structure 30 may further include an ohmic electrode and a Schottky electrode, the ohmic electrode including a source electrode 305 and / or a drain electrode 303, and the Schottky electrode including a gate electrode 301. It is understood that the ohmic electrode forms an ohmic contact with the epitaxial structure 20, and the Schottky electrode forms a Schottky contact with the epitaxial structure 20.

[0073] The first resistor electrode 401 and the second resistor electrode 402 are both arranged in the same layer as the ohmic electrode, and the gate electrode 301 covers and contacts the first resistor electrode 401 to achieve electrical connection, and the second resistor electrode 402 contacts the gate power supply electrode 302 to achieve electrical connection, thereby ensuring that the first odd-mode resistor 41 forms an ohmic contact with the two-dimensional electron gas, and suppressing the odd-mode signal during the signal transmission process of each gate electrode 301.

[0074] Specifically, this embodiment is described by taking the ohmic electrode as the drain electrode 303 as an example. The first resistor electrode 401 and the second resistor electrode 402 are both arranged in the same layer as the drain electrode 303, that is, the first resistor electrode 401, the second resistor electrode 402 and the drain electrode 303 are prepared using the same mask process, that is, the resistor electrodes in the first odd-mode resistor 41 are all arranged in the ohmic contact metal layer, that is, the first resistor electrode 401, the second resistor electrode 402 and the drain electrode 303 are arranged in the same layer. On the one hand, while ensuring a good ohmic contact effect between the resistor electrodes and the two-dimensional electron gas, the semiconductor device can be thinned and the process flow can be simplified.

[0075] Optionally, as shown in FIG5 , the electrode structure 30 further includes an ohmic electrode structure. For example, the ohmic electrode structure may be a drain electrode structure 32, the drain electrode structure 32 including a drain electrode 303 and a drain power supply electrode 304 connected to each other; the gate power supply electrode 302 and / or the drain power supply electrode 304 including at least two independently provided power supply subsections 100; the at least one odd-mode resistor 40 further includes at least one second odd-mode resistor 42, each second odd-mode resistor 42 including a first resistor electrode 401 and a second resistor electrode 402, in the same second odd-mode resistor 40. In the second odd-mode resistor 42, the first resistor electrode 401 and the second resistor electrode 402 both form ohmic contact with the two-dimensional electron gas, and a two-dimensional electron gas conductive channel exists between the first resistor electrode 401 and the second resistor electrode 402 along the arrangement direction of the second resistor electrode 401 and the second resistor electrode 402; in the same second odd-mode resistor 42, the first resistor electrode 401 is electrically connected to one of the two adjacent power supply divisions 100, and the second resistor electrode 402 is electrically connected to the other of the two adjacent power supply divisions 100.

[0076] Specifically, the gate power supply electrode 302 and / or the drain power supply electrode 304 includes at least two independently arranged power supply sub-sections 100, and the two adjacent power supply sub-sections 100 are independently arranged. That is, the gate power supply electrode 302 and / or the drain power supply electrode 304 are not a whole, but are disconnected, so that the semiconductor device can be divided into at least two unit cells. Therefore, by increasing the disconnection distance between the two adjacent power supply sub-sections 100, the isolation between the two adjacent unit cells can be increased.

[0077] As a feasible embodiment, the gate power supply electrode 302 includes at least two independently disposed power supply subsections 100. Within the same second odd-mode resistor 42, the first resistor electrode 401 is electrically connected to one of the two adjacent power supply subsections 100, and the second resistor electrode 402 is electrically connected to the other of the two adjacent power supply subsections 100. Both the first resistor electrode 401 and the second resistor electrode 402 form ohmic contact with the two-dimensional electron gas. The second odd-mode resistor 42 is disposed within the passive region bb in a region where the two-dimensional electron gas is retained. That is, the two-dimensional electron gas in the region where the second odd-mode resistor 42 is disposed within the passive region bb is connected, thereby forming an ohmic contact between the second odd-mode resistor 42 and the two-dimensional electron gas. Furthermore, along the arrangement direction of the first and second resistor electrodes 401, 402, a two-dimensional electron gas conductive channel exists between the first and second resistor electrodes 401, 402. That is, the channel between the first and second resistor electrodes 401, 402 is conductive. Furthermore, the first resistor electrode 401 is electrically connected to one of the two adjacent power supply divisions 100, and the second resistor electrode 402 is electrically connected to the other of the two adjacent power supply divisions 100, so that the electrical connection between the two adjacent power supply divisions 100 can be achieved through the first resistor electrode 401 and the second resistor electrode 402. That is, a second odd-mode resistor 42 is provided between the two adjacent power supply divisions 100, so that the energy of the odd-mode signal is consumed by the second odd-mode resistor 42, that is, the odd-mode oscillation in the feedback loop formed by the gate electrode 301 and the drain electrode 303 can be further suppressed, thereby improving the stability of the semiconductor device.

[0078] As another feasible embodiment, the drain power supply electrode 303 includes at least two independently arranged power supply divisions 100. In the same second odd-mode resistor 42, the first resistor electrode 401 is electrically connected to one of the two adjacent power supply divisions 100, and the second resistor electrode 402 is electrically connected to the other of the two adjacent power supply divisions 100, so that the electrical connection between the two adjacent power supply divisions 100 can be achieved through the first resistor electrode 401 and the second resistor electrode 402. That is, a second odd-mode resistor 42 is provided between the two adjacent power supply divisions 100, so that the energy of the odd-mode signal is consumed by the second odd-mode resistor 42, that is, the odd-mode oscillation in the feedback loop formed by the gate electrode 301 and the drain electrode 303 can be further suppressed, thereby improving the stability of the semiconductor device.

[0079] It can be understood that the gate power supply electrode 302 shown in Figure 5 includes two independently arranged power supply divisions 100, and the power supply division 100 includes a power supply main body 101 and at least one power supply interdigital portion 102 electrically connected to the power supply main body 101. Along the second direction X, at least one power supply interdigital portion 102 is located on one side of the power supply main body 101, and each power supply interdigital portion 102 in the at least one power supply interdigital portion 102 extends along the second direction X; at least one power supply interdigital portion 102 of one of the two power supply divisions 100 adjacently arranged along the second direction X and at least one power supply interdigital portion 102 of the other of the two power supply divisions 100 adjacently arranged along the second direction X are alternately arranged along the first direction Y; the first direction Y is parallel to the plane where the substrate 10 is located and intersects with the second direction X. Exemplarily, the number of power supply fork fingers 102 can be at least two, so that at least two second odd-mode resistors 42 can be set in parallel, thereby achieving diversity in the resistance values ​​of the second odd-mode resistors 42 to achieve different suppression effects, thereby meeting the needs of various different scenarios.

[0080] As another feasible embodiment, the gate power supply electrode 302 and the drain power supply electrode 304 each include at least two independently arranged power supply divisions 100. That is, a second strange-membrane resistor 42 is provided between the power supply divisions 100 of the drain power supply electrode 304 and the power supply divisions 100 of the gate power supply electrode 302. This can, on the one hand, further suppress strange-membrane oscillations in the feedback loop formed by the gate electrode 301 and the drain electrode 303 to improve the stability of the semiconductor device, and on the other hand, is conducive to realizing diversified settings of the semiconductor device.

[0081] The above is an explanation of a semiconductor device based on the first embodiment. The following is an explanation of another semiconductor device based on the second embodiment. The second embodiment is described from the direction that at least one odd-mode resistor 40 only includes at least one second odd-mode resistor 42. As shown in Figures 6 to 9, the structure of the semiconductor device is as follows.

[0082] The electrode structure 30 includes at least one electrode 300-1 and at least one power supply electrode 300-2 electrically connected to the at least one electrode 300-1; each of the at least one power supply electrode 300-2 includes at least two power supply subsections 100, and any two adjacent power supply subsections 100 are independently arranged; each of the at least one second odd-mode resistor 42 includes a first resistor electrode 401 and a second resistor electrode 402. In the same second odd-mode resistor 42, the first resistor electrode 401 and the second resistor electrode 402 both form ohmic contact with the two-dimensional electron gas, and a two-dimensional electron gas conductive channel exists between the first resistor electrode 401 and the second resistor electrode 402 along the arrangement direction of the first resistor electrode 401 and the second resistor electrode 402; in the same second odd-mode resistor 42, the first resistor electrode 401 is electrically connected to one of the two adjacent power supply subsections 100, and the second resistor electrode 402 is electrically connected to the other of the two adjacent power supply subsections 100.

[0083] Specifically, the electrode structure 30 may include a source electrode structure 33, a gate electrode structure 31, and a drain electrode structure 32. The source electrode structure 33 may include a source electrode 305. The gate electrode structure 31 may include a gate electrode 301 and a gate power supply electrode 302 connected to the gate electrode 301. The drain electrode structure 32 may include a drain electrode 303 and a drain power supply electrode 304 electrically connected to the drain electrode 303. The source electrode 305 may serve as an input terminal of the semiconductor device, and the drain electrode 303 may serve as an output terminal of the semiconductor device. The drain power supply electrode 304 may be understood as a drain pad. The drain electrode 303 in the first active area aa1 may be connected to the drain power supply electrode 304 in the passive area bb. The gate electrode structure 31 may include a gate electrode 301 in the first active area aa1 and a gate power supply electrode 302 in the passive area bb. The gate power supply electrode 302 is a gate pad and is connected to the gate electrode 301 in the first active area aa1. It provides a gate voltage signal to the gate electrode 301 to ensure normal operation of the semiconductor device. The electrode 300 of the semiconductor device of the present application can include an ohmic electrode and a Schottky electrode. The ohmic electrode includes the source electrode 305 and / or the drain electrode 303, and the Schottky electrode includes the gate electrode 301. It will be understood that the ohmic electrode forms an ohmic contact with the epitaxial structure 20, and the Schottky electrode forms a Schottky contact with the epitaxial structure 20.

[0084] Furthermore, at least one electrode 300 - 1 may include a gate electrode 301 and / or a drain electrode 303 , and at least one power supply electrode 300 - 2 may include a gate power supply electrode 302 electrically connected to the gate electrode 301 and / or a drain power supply electrode 304 electrically connected to the drain electrode 303 .

[0085] Specifically, each of the at least one power supply electrode 300-2 includes at least two power supply subsections 100, with two adjacent power supply subsections 100 independently disposed. That is, each power supply electrode 300-2 is not integral but rather disconnected, thereby dividing the semiconductor device into at least two unit cells 800. Increasing the disconnected spacing between two adjacent power supply subsections 100 can increase the isolation between the two adjacent unit cells 800. Furthermore, the second odd-film resistor 42 is disposed in a region within the passive region bb where the two-dimensional electron gas is retained. Specifically, the two-dimensional electron gas within the region where the second odd-film resistor 42 is disposed is retained within the passive region bb, thereby forming an ohmic contact between the second odd-film resistor 42 and the two-dimensional electron gas. The power supply electrode 300-2 has zero contact with the two-dimensional electron gas in the area where the second odd-mode resistor 42 is located. That is, when preparing the power supply electrode 300-2, the power supply electrode 300-2 cannot completely cover the first resistor electrode 401 and the second resistor electrode 402 in the second odd-mode resistor 42. Instead, the power supply electrode 300-2 at least exposes two adjacent side surfaces of the first resistor electrode 401 and the second resistor electrode 402 in the second odd-mode resistor 42. This ensures that the first resistor electrode 401 and the second resistor electrode 402 in the second odd-mode resistor 42 are in full contact with the two-dimensional electron gas while preventing the power supply electrode 300-2 from contacting the two-dimensional electron gas. In addition, along the arrangement direction of the first resistor electrode 401 and the second resistor electrode 402 in the second odd mode resistor 42, a two-dimensional electron gas conductive channel exists between the first resistor electrode 401 and the second resistor electrode 402 in the second odd mode resistor 42, that is, the channel between the first resistor electrode 401 and the second resistor electrode 402 in the second odd mode resistor 42 is conductive, and the first resistor electrode 401 and the second resistor electrode 402 in the second odd mode resistor 42 are electrically connected by the two-dimensional electron gas. Furthermore, a second odd-mode resistor 42 is provided between two adjacent power supply subdivisions 100. A first resistor electrode 401 in the second odd-mode resistor 42 is electrically connected to one of the two adjacent power supply subdivisions 100, and a second resistor electrode 402 in the second odd-mode resistor 42 is electrically connected to the other of the two adjacent power supply subdivisions 100. This allows electrical connection between the two adjacent power supply subdivisions 100 via the first resistor electrode 401 and the second resistor electrode 402. That is, a second odd-mode resistor 42 is provided between the two adjacent power supply subdivisions 100, thereby consuming energy of the odd-mode signal via the second odd-mode resistor 42. This can suppress odd-mode oscillation in the feedback loop formed by the gate electrode 301 and the drain electrode 303, thereby improving the stability of the semiconductor device.

[0086] In the semiconductor device provided by the embodiments of the present application, the power supply segments 100 of the power supply electrode 300-2 are independently provided. That is, the power supply electrode 300-2 is disconnected to form different power supply segments 100. This allows the semiconductor device to be divided into at least two unit cells 800, while also increasing the spacing between the power supply segments 100, thereby increasing the isolation of each unit cell 800. Furthermore, within the same second odd-mode resistor 42, the first resistor electrode 401 is electrically connected to one of the two adjacent power supply segments 100, and the second resistor electrode 402 is electrically connected to the other of the two adjacent power supply segments 100. In other words, the second odd-mode resistor 42 is provided between the two adjacent power supply segments 100. This allows the second odd-mode resistor 42 to dissipate the energy of the odd-mode signal, thereby suppressing the generation of odd-mode oscillations. This reduces the parasitic capacitance introduced by the power supply electrode 300-2, thereby improving the stability of the semiconductor device.

[0087] Optionally, referring to FIG6 , the electrode structure 30 includes a gate electrode structure 31 and a drain electrode structure 32. The gate electrode structure 31 includes a gate electrode 301 and a gate power supply electrode 302 electrically connected to the gate electrode 301. The drain electrode structure 32 includes a drain electrode 303 and a drain power supply electrode 304 electrically connected to the drain electrode 303. The gate power supply electrode 302 includes at least two gate power supply subdivisions 100-1. Two adjacent gate power supply subdivisions 100-1 are independently provided. In the same second odd-mode resistor 42, the first resistor electrode 401 is connected to one of the gate power supply subdivisions 100-1. The drain power supply electrode 304 includes at least two drain power supply sub-sections 100-2, and the two adjacent drain power supply sub-sections 100-2 are independently arranged. In the same second odd-mode resistor 42, the first resistor electrode 401 is electrically connected to one of the two adjacent drain power supply sub-sections 100-2, and the second resistor electrode 402 is electrically connected to the other of the two adjacent drain power supply sub-sections 100-2.

[0088] Specifically, with continued reference to FIG6 , as a feasible embodiment, in the same second odd-mode resistor 42, the first resistor electrode 401 is electrically connected to one of two adjacent gate power supply segments 100-1, and the second resistor electrode 402 is electrically connected to the other of the two adjacent gate power supply segments 100-1. The second odd-mode resistor 42 forms an ohmic contact with the two-dimensional electron gas, and the first resistor electrode 401 and the second resistor electrode 402 of the second odd-mode resistor 42 are respectively electrically connected to the two adjacent gate power supply segments 100-1. That is, the first resistor electrode 401 and the second resistor electrode 402 are electrically connected via the two-dimensional electron gas. This allows the provision of the second odd-mode resistor 42 to suppress odd-mode oscillations, thereby improving the stability of the semiconductor device.

[0089] As another feasible embodiment, referring again to FIG6 , in the same second odd-mode resistor 42, the first resistor electrode 401 is electrically connected to one of two adjacent drain power supply segments 100-2, and the second resistor electrode 402 is electrically connected to the other of the two adjacent drain power supply segments 100-2. The second odd-mode resistor 42 forms an ohmic contact with the two-dimensional electron gas, and the first resistor electrode 401 and the second resistor electrode 402 in the second odd-mode resistor 42 are respectively electrically connected to the two adjacent drain power supply segments 100-2. That is, the first resistor electrode 401 and the second resistor electrode 402 are electrically connected via the two-dimensional electron gas. This allows the provision of the second odd-mode resistor 42 to suppress odd-mode oscillation, thereby improving the stability of the semiconductor device.

[0090] As another feasible implementation, referring to FIG6 , providing a second strange-film resistor 42 located between the gate power supply division 100 - 1 and a second strange-film resistor 42 located between the drain power supply division 100 - 2 can further suppress the strange-film oscillation in the feedback loop formed by the gate electrode 301 and the drain electrode 303 , thereby further improving the stability of the semiconductor device.

[0091] Optionally, continuing to refer to Figures 7 and 8, the electrode 300-1 includes an ohmic electrode, the first resistance electrode 401 and the second resistance electrode 402 of the second odd-mode resistor 42 are both arranged in the same layer as the ohmic electrode, and the ohmic electrode includes a drain electrode 303 and / or a source electrode 305. In the second strange-film resistor 42 located between the gate power supply sub-sections 100-1, the first resistor electrode 401 and the second resistor electrode 402 are both arranged in the same layer as the ohmic electrode, for example, they can be arranged in the same layer as the drain electrode 303 or the source electrode 305, thereby ensuring that the second strange-film resistor 42 located between the gate power supply sub-sections 100-1 forms an ohmic contact with the two-dimensional electron gas; in the second strange-film resistor 42 located between the drain power supply sub-sections 100-2, the first resistor electrode 401 and the second resistor electrode 402 are both arranged in the same layer as the ohmic electrode, for example, they can be arranged in the same layer as the drain electrode 303 or the source electrode 305, thereby ensuring that the second strange-film resistor 42 located between the drain power supply sub-sections 100-2 forms an ohmic contact with the two-dimensional electron gas.

[0092] Specifically, this embodiment uses the ohmic electrode as the drain electrode 303 as an example. In the second odd-film resistor 42 located between the gate power supply subsections 100-1, the first resistor electrode 401 and the second resistor electrode 402 are both arranged in the same layer as the drain electrode 303. Moreover, in the second odd-film resistor 42 located between the drain power supply subsections 100-2, the first resistor electrode 401 and the second resistor electrode 402 are both arranged in the same layer as the drain electrode 303. That is, the resistor electrodes in the second odd-film resistor 42 are all arranged in the ohmic contact metal layer. This allows the first resistor electrode 401, the second resistor electrode 402, and either the drain electrode 303 or the source electrode 305 to be simultaneously formed on the side of the epitaxial structure 20 away from the substrate 10 using the same mask process. This eliminates the need to add a new process flow to form the two resistor electrodes in the second odd-film resistor 42. That is, the manufacturing process of the second odd-film resistor 42 is compatible with the process flow of the semiconductor chip, and therefore, the process is simple. In addition, the first resistor electrode 401 and the second resistor electrode 402 are both provided in the same layer and process as the ohmic electrode of the semiconductor device. Therefore, while ensuring good ohmic contact between the resistor electrode and the two-dimensional electron gas, the semiconductor device can also be thinned.

[0093] Furthermore, the second odd-film resistor 42 forms an ohmic contact with the two-dimensional electron gas and is internally electrically connected by the two-dimensional electron gas, and the second odd-film resistor 42 contacts the drain power supply electrode 304 and the gate power supply electrode 302 to achieve electrical connection, thereby suppressing odd-film oscillation and improving the stability of the semiconductor device.

[0094] Optionally, with continued reference to FIG6 , at least two power supply divisions 100 in the same power supply electrode 300-2 are arranged along a second direction (the X direction as shown in FIG6 ); the second direction X is parallel to the plane where the substrate 10 is located; the power supply division 100 includes a power supply main body 101, and the power supply main bodies 101 of two power supply divisions 100 adjacently arranged along the second direction X are arranged along the second direction X; in the same second odd-mode resistor 42, the first resistor electrode 401 and the second resistor electrode 402 are arranged along the second direction X and extend along the first direction (the Y direction as shown in FIG6 ); in the same second odd-mode resistor 42, the first resistor electrode 401 is electrically connected to one of the two power supply main bodies 101 adjacently arranged along the second direction X, and the second resistor electrode 402 is electrically connected to the other of the two power supply main bodies 101 adjacently arranged along the second direction X; the first direction Y is parallel to the plane where the substrate 10 is located and intersects with the second direction X.

[0095] Specifically, referring to FIG. 6 , the gate power supply segments 100 - 1 and the second odd-film resistor 42 located between the gate power supply segments 100 - 1 are used as an example for explanation. At least two gate power supply segments 100 - 1 in the gate power supply electrodes 302 are arranged along the second direction X. In the same second odd-film resistor 42 , the first resistor electrode 401 and the second resistor electrode 402 are arranged along the second direction X and extend along the first direction Y. In the same second odd-film resistor 42 , the first resistor electrode 401 is electrically connected to the power supply main body 101 in the gate power supply segment 100 - 1, and the second resistor electrode 402 is electrically connected to the power supply main body 101 in another adjacent gate power supply segment 100 - 1. This allows the second odd-film resistor 42 to suppress odd-film oscillation, thereby improving the stability of the semiconductor device.

[0096] Optionally, with continued reference to FIG6 , at least two power supply subdivisions 100 in the same power supply electrode 300-2 are arranged along the second direction X; the second direction X is parallel to the plane where the substrate 10 is located; the power supply subdivision 100 includes a power supply main body 101 and at least one power supply fork portion 102, the power supply main body 101 and the at least one power supply fork portion 102 are connected to each other, along the second direction X, the power supply fork portion 102 is located on one side of the power supply main body 101, and the power supply fork portion 102 extends along the second direction X; at least one power supply fork finger 102 of one of the two power supply subdivisions 100 adjacently arranged along the second direction X is aligned with the two power supply subdivisions adjacently arranged along the second direction X. At least one power supply interdigital portion 102 of another power supply sub-portion 100 in the portion 100 is alternately arranged along the first direction Y; the first direction Y is parallel to the plane of the substrate 10 and intersects with the second direction X; in the same second odd-mode resistor 42, the first resistor electrode 401 and the second resistor electrode 402 extend along the second direction X and are arranged along the first direction Y; in the same second odd-mode resistor 42, the first resistor electrode 401 is electrically connected to one of the two power supply interdigital portions 102 adjacent to each other along the first direction Y, and the second resistor electrode 402 is electrically connected to the other of the two power supply interdigital portions 102 adjacent to each other along the first direction Y.

[0097] Specifically, referring to FIG. 6 , the drain power supply segment 100 - 2 and the second odd-mode resistor 42 located between the drain power supply segments 100 - 2 are used as an example for explanation. The drain power supply segment 100 - 2 includes a power supply main body 101 and at least one power supply interdigital portion 102. In the same second odd-mode resistor 42 , a first resistor electrode 401 and a second resistor electrode 402 extend along the second direction X and are arranged along the first direction Y. In the same second odd-mode resistor 42 , the first resistor electrode 401 is electrically connected to one of the two power supply interdigital portions 102 adjacent to each other along the first direction Y, and the second resistor electrode 402 is electrically connected to the other of the two power supply interdigital portions 102 adjacent to each other along the first direction Y. This allows for diversified configuration of semiconductor devices, and the provision of the second odd-mode resistor 42 can suppress odd-mode oscillation, thereby improving the stability of the semiconductor device.

[0098] For example, each drain power supply division 100-2 shown in Figure 6 includes only one power supply fork finger portion 102. It can be understood that each drain power supply division 100-2 can also include at least two power supply fork fingers 102, and the at least two power supply fork fingers 102 form a "comb structure". The embodiment of the present application does not specifically limit the number of power supply fork fingers 102 included in each power supply division 100.

[0099] Optionally, as shown in Figure 9, two power supply divisions 100 adjacently arranged along the second direction X each include at least two power supply fork fingers 102; one power supply fork finger 102 of any two power supply fork fingers 102 adjacently arranged along the first direction Y is electrically connected to the first resistor electrode 401, and the other power supply fork finger 102 of any two power supply fork fingers 102 adjacently arranged along the first direction Y is electrically connected to the second resistor electrode 402; at least one second odd-mode resistor 42 includes at least two second odd-mode resistors 42, and at least two second odd-mode resistors 42 are arranged in parallel.

[0100] Specifically, using drain power supply subsection 100-2 and second odd-film resistor 42 located between drain power supply subsections 100-2 in FIG9 as an example, two adjacent drain power supply subsections 100-2 arranged along second direction X include three power supply fingers 102 arranged along first direction Y, each of which is electrically connected to a resistor electrode. For example, along first direction Y, the second odd-film resistors 42 may be arranged in a "first resistor electrode 401 - second resistor electrode 402 - first resistor electrode 401" pattern. That is, three power supply fingers 102 correspond to two second odd-film resistors 42, and the two second odd-film resistors 42 are arranged in parallel via the second resistor electrode 402.

[0101] Specifically, taking the gate power supply subsection 100-1 and the second odd-film resistor 42 located between them in FIG. 9 as an example, two adjacent gate power supply subsections 100-1 arranged along the second direction X include a total of four power supply fingers 102 arranged along the first direction Y. Each power supply finger 102 is electrically connected to a resistor electrode. For example, along the first direction Y, the second odd-film resistors 42 can be arranged in a "first resistor electrode 401 - second resistor electrode 402 - first resistor electrode 401 - second resistor electrode 402" pattern. That is, four power supply fingers 102 correspond to three second odd-film resistors 42, and the three second odd-film resistors 42 are arranged in parallel.

[0102] It should be noted that Figure 9 only exemplarily shows the technical solution of two second strange-film resistors 42 or three second strange-film resistors 42 connected in parallel. It can be understood that the number of second strange-film resistors 42 can also be greater than or equal to four. The embodiment of the present application does not specifically limit the number of second strange-film resistors 42. By setting at least two second strange-film resistors 42 in parallel, the resistance value of the second strange-film resistor 42 can be further diversified to achieve different suppression effects, thereby meeting the needs of various different scenarios.

[0103] Optionally, continuing to refer to Figures 6 and 7, in the same second odd-mode resistor 42, the distance between the first resistor electrode 401 and the second resistor electrode 402 is d, the extension lengths of the first resistor electrode 401 and the second resistor electrode 402 are both w, the contact resistance of the first resistor electrode 401 is Rc1, the contact resistance of the second resistor electrode 402 is Rc2, the square resistance of the two-dimensional electron gas between the first resistor electrode 401 and the second resistor electrode 402 is Rsh, and the resistance value of the second odd-mode resistor 42 is R=Rc1+Rc2+Rsh·d / W.

[0104] It can be understood that compared with the thin film resistors in the related art, the second strange film resistor 42 provided in the embodiment of the present application is arranged in the same layer as the drain electrode 303, and the electrical connection and ohmic contact are achieved by the two-dimensional electron gas in the second strange film resistor 42. Therefore, there is no need to add a new film layer, which reduces material costs, simplifies the process flow, and is suitable for large-scale commercial applications.

[0105] The above is an explanation of another semiconductor device based on the second embodiment. The following will explain the similarities between a semiconductor device based on the first embodiment and another semiconductor device based on the second embodiment. As shown in Figures 5, 6 and 9, the semiconductor device also includes at least two unit cells 800; each unit cell 800 includes a power supply electrode portion, and a second odd-mode resistor 42 is arranged between two adjacent unit cells 800.

[0106] Specifically, the power supply electrode portion can be understood as the gate power supply electrode 302 or the drain power supply electrode 304 in the unit cell 800. That is, each unit cell 800 includes a drain power supply electrode 304 electrically connected to the drain electrode 303 and a gate power supply electrode 302 electrically connected to the gate electrode 301. Figures 5, 6, and 9 only illustrate a technical solution in which the semiconductor device includes two unit cells 800. It is understood that the semiconductor device may also include more than two unit cells 800. A second odd-mode resistor 42 is provided between two adjacent unit cells 800. This second odd-mode resistor 42 can suppress odd-mode oscillation, thereby improving the stability of the semiconductor device.

[0107] It should be noted that the number of gate electrodes 301 included in each unit cell 800 may be the same or different, and the embodiment of the present application does not specifically limit the number of gate electrodes 301 included in each unit cell 800.

[0108] It should be understood that the embodiments of the present application, from the perspective of semiconductor device design, utilize the provision of a special-film resistor 40 to suppress special-film oscillations, thereby improving the stability of the semiconductor device. Semiconductor devices include, but are not limited to, high electron mobility transistors or other field-effect transistors. The special-film resistor 40 provided in the semiconductor device provided in the embodiments of the present application can be widely used in semiconductor device manufacturing fields such as radio frequency microwaves and power electronics. In particular, gallium nitride electronic devices with large bandgap widths, high electron mobility, high breakdown field strength, and good thermal conductivity have significant advantages and can better meet the high-performance requirements of rapidly developing fields such as electronic communications.

[0109] Based on the same inventive concept, the present application also provides a method for fabricating a semiconductor device. This method has the same beneficial effects as the aforementioned semiconductor device. For any unexplained details, reference can be made to the description of the aforementioned embodiment. Figure 10 is a flow chart of a method for fabricating a semiconductor device provided in an embodiment of the present application. As shown in Figure 10 , the method for fabricating a semiconductor device includes the following steps.

[0110] S101 , providing a substrate and preparing an epitaxial structure on one side of the substrate, wherein a two-dimensional electron gas is formed in the epitaxial structure, and the two-dimensional electron gas exists in the first active region and the second active region.

[0111] Specifically, a heterojunction structure is included between the channel layer and the barrier layer of the epitaxial structure, and the heterojunction structure may be a two-dimensional electron gas.

[0112] S102. Prepare at least one odd-mode resistor and an electrode structure on a side of the epitaxial structure away from the substrate, wherein a portion of the electrode structure is located in a first active region, another portion of the electrode structure is located in a passive region, at least one odd-mode resistor is electrically connected to the electrode structure, each first odd-mode resistor in the at least one odd-mode resistor includes a first resistor electrode and a second resistor electrode, at least part of the odd-mode resistor is located in the second active region, and in the same odd-mode resistor, the first resistor electrode and the second resistor electrode both form ohmic contact with the two-dimensional electron gas, and a two-dimensional electron gas conductive channel exists between the first resistor electrode and the second resistor electrode along an arrangement direction of the first resistor electrode and the second resistor electrode.

[0113] Before preparing the electrode structure, the two-dimensional electron gas in the inactive area is eliminated, while the two-dimensional electron gas in the area where the odd-mode resistor is located (i.e., the second active area) is retained, so that the odd-mode resistor and the two-dimensional electron gas form an ohmic contact.

[0114] In the method for preparing a semiconductor device provided in an embodiment of the present application, in the same odd-mode resistor, the first resistor electrode and the second resistor electrode are electrically connected to the electrode structure respectively, so that the energy of the odd-membrane signal can be dissipated through the odd-membrane resistor, thereby suppressing the generation of odd-membrane oscillation and improving the stability of the semiconductor device.

[0115] Optionally, when at least one odd-mode resistor includes at least one first odd-mode resistor, the electrode structure includes a gate electrode structure and an ohmic electrode structure, the ohmic electrode structure includes an ohmic electrode, the gate electrode structure includes at least one gate electrode and a gate power supply electrode, and each gate electrode in the at least one gate electrode is independently arranged with the gate power supply electrode, step S102 specifically includes: using the same mask process to prepare the first resistor electrode and the second resistor electrode, as well as the ohmic electrode in each of the at least one first odd-mode resistor on the side of the epitaxial structure away from the substrate; preparing at least one gate electrode in an area outside the ohmic electrode, wherein the at least one gate electrode is in contact with the first resistor electrode to achieve electrical connection; and preparing a gate power supply electrode, wherein the gate power supply electrode is in contact with the second resistor electrode to achieve electrical connection.

[0116] Optionally, when at least one odd-mode resistor includes at least one second odd-mode resistor, the electrode structure includes at least one electrode and at least one power supply electrode electrically connected to the at least one electrode, each of the at least one power supply electrode includes at least two power supply divisions, any two adjacent power supply divisions of the at least two power supply divisions are independently arranged, and at least one electrode includes an ohmic electrode, step S102 specifically includes: using the same mask process to prepare a first resistor electrode and a second resistor electrode, as well as an ohmic electrode in each of the at least one second odd-mode resistor on a side of the epitaxial structure away from the substrate; preparing at least one power supply electrode, wherein, in the same second odd-mode resistor, the first resistor electrode contacts one of the at least two power supply divisions to achieve electrical connection, and the second resistor electrode contacts the other of the at least two power supply divisions to achieve electrical connection.

[0117] Note that the above are only preferred embodiments of the present application and the technical principles employed. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present application. The scope of the present application is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has a first active region and a second active region that are independent of each other, and a passive region surrounding the first active region and the second active region. The semiconductor device includes: a substrate; an epitaxial structure located on one side of the substrate. A two-dimensional electron gas is provided in the epitaxial structure, and the two-dimensional electron gas exists in the first active region and the second active region; an electrode structure located on the side of the epitaxial structure away from the substrate. A part of the electrode structure is located in the first active region, and another part of the electrode structure is located in the passive region; at least one odd-mode resistor located outside the first active region and electrically connected to the electrode structure. Each odd-mode resistor in the at least one odd-mode resistor includes a first resistor electrode and a second resistor electrode. At least part of the first resistor electrode and at least part of the second resistor electrode are both located in the second active region. In the same odd-mode resistor, both the first resistor electrode and the second resistor electrode form ohmic contacts with the two-dimensional electron gas in the second active region, and along the arrangement direction of the first resistor electrode and the second resistor electrode, there is a two-dimensional electron gas conduction channel between the first resistor electrode and the second resistor electrode.

2. The semiconductor device according to claim 1, wherein, In the same odd-mode resistor, the distance between the first resistor electrode and the second resistor electrode is d, and the extension lengths of both the first resistor electrode and the second resistor electrode are w; The contact resistance of the first resistor electrode is Rc1, the contact resistance of the second resistor electrode is Rc2, and the sheet resistance of the two-dimensional electron gas between the first resistor electrode and the second resistor electrode is Rsh; The resistance value R of the odd-mode resistor is R = Rc1 + Rc2 + Rsh·d / W.

3. The semiconductor device according to claim 1 or 2, characterized in that, The at least one odd-mode resistor includes at least one first odd-mode resistor. The electrode structure includes a gate electrode structure. The gate electrode structure includes at least one gate electrode and a gate power supply electrode. Each gate electrode in the at least one gate electrode is independently arranged with the gate power supply electrode; The first resistor electrode in the at least one first odd-mode resistor is electrically connected to the at least one gate electrode, and the second resistor electrode in the at least one first odd-mode resistor is electrically connected to the gate power supply electrode.

4. The semiconductor device according to claim 3, wherein When the at least one gate electrode includes multiple gate electrodes, in the same first odd-mode resistor, the first resistor electrode is electrically connected to at least one of the multiple gate electrodes, and the second resistor electrode is electrically connected to the gate power supply electrode; or When the at least one gate electrode includes multiple gate electrodes, a first odd-mode resistor is provided between each of the multiple gate electrodes and the gate power supply electrode.

5. The semiconductor device according to claim 3, wherein, The electrode structure further includes a source electrode. Along the second direction, the source electrode is located between two adjacent gate electrodes; In the same first odd-mode resistor, the first resistor electrode is electrically connected to the two gate electrodes adjacent to the source electrode, and the second resistor electrode is electrically connected to the gate power supply electrode.

6. The semiconductor device according to any one of claims 3 to 5, characterized in that, In the case where the at least one gate electrode includes a plurality of gate electrodes, each of the plurality of gate electrodes extends in a first direction, the plurality of gate electrodes are arranged in a second direction, any two adjacent gate electrodes are symmetrically arranged with respect to a symmetry axis, a first odd-mode resistor electrically connected to the two adjacent symmetrically arranged gate electrodes is symmetrically arranged with respect to the symmetry axis, the symmetry axis extends in the first direction, and the first direction and the second direction intersect and are both parallel to the plane of the substrate.

7. The semiconductor device according to any one of claims 3 to 6, characterized in that, The gate electrode includes a gate main body portion and a gate tail portion connected to each other. The gate tail portion is located on a side of the gate main body portion close to the gate power supply electrode and extends in the second direction. The extension width of the gate tail portion is greater than the extension width of the gate main body portion. The second direction intersects with the extension direction of the gate electrode. The gate tail portion is electrically connected to the first resistor electrode in the corresponding first odd-mode resistor.

8. The semiconductor device according to any one of claims 3 to 7, characterized in that, The gate power supply electrode includes a power supply main body portion and at least one power supply protrusion portion. The power supply main body portion and the at least one power supply protrusion portion are connected to each other. The at least one power supply protrusion portion is located on a side of the power supply main body portion close to the gate electrode. The second resistor electrode in each of the at least one first odd-mode resistors is electrically connected to its respective power supply protrusion portion.

9. The semiconductor device according to any one of claims 3 to 8, characterized in that, The electrode structure further includes an ohmic electrode structure. The ohmic electrode structure includes an ohmic electrode and an ohmic power supply electrode connected to each other. Each of the at least one power supply electrode in the gate power supply electrode or the ohmic power supply electrode includes at least two power supply sub-portions. Any two adjacent power supply sub-portions among the at least two power supply sub-portions are independently arranged. The at least one odd-mode resistor further includes at least one second odd-mode resistor. In the same second odd-mode resistor, the first resistor electrode is electrically connected to one of the at least two power supply sub-portions, and the second resistor electrode is electrically connected to the other of the at least two power supply sub-portions.

10. The semiconductor device according to claim 1 or 2, characterized in that, The at least one odd-mode resistor includes at least one second odd-mode resistor. The electrode structure includes at least one electrode and at least one power supply electrode electrically connected to the at least one electrode. Each of the at least one power supply electrode includes at least two power supply sub-portions. Any two adjacent power supply sub-portions among the at least two power supply sub-portions are independently arranged. In the same second odd-mode resistor, the first resistor electrode is electrically connected to one of the at least two power supply sub-portions, and the second resistor electrode is electrically connected to the other of the at least two power supply sub-portions.

11. The semiconductor device according to claim 10, wherein, In the same power supply electrode, the at least two power supply sub - parts are arranged along a second direction. Each of the at least two power supply sub - parts includes a power supply main body part and at least one power supply interdigital part. The power supply main body part is connected to the at least one power supply interdigital part. Along the second direction, the at least one power supply interdigital part is located on one side of the power supply main body part, and each power supply interdigital part in the at least one power supply interdigital part extends along the second direction. The at least one power supply interdigital part of one of the adjacent two power supply sub - parts and the at least one power supply interdigital part of the other of the adjacent two power supply sub - parts are arranged alternately along a first direction; the second direction intersects with the first direction and both are parallel to the plane where the substrate is located; in the same second odd - mode resistor, the first resistor electrode and the second resistor electrode extend along the second direction and are arranged along the first direction; in the same second odd - mode resistor and in the same power supply electrode, the first resistor electrode is electrically connected to one of the adjacent two power supply interdigital parts, and the second resistor electrode is electrically connected to the other of the adjacent two power supply interdigital parts.

12. The semiconductor device according to claim 10 or 11, characterized in that, In the same power supply electrode, the two power supply sub - parts adjacent along the second direction both include at least two power supply interdigital parts; among any two adjacent power supply interdigital parts arranged along the first direction, one power supply interdigital part is electrically connected to the first resistor electrode in the corresponding second odd - mode resistor, and the other power supply interdigital part is electrically connected to the second resistor electrode in the corresponding second odd - mode resistor; the second direction intersects with the first direction and both are parallel to the plane where the substrate is located; the at least one second odd - mode resistor includes at least two second odd - mode resistors, and the at least two second odd - mode resistors are arranged in parallel.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that, The electrode structure includes an ohmic electrode structure. The ohmic electrode structure includes an ohmic electrode. The first resistor electrode and the second resistor electrode in each odd - mode resistor of the at least one odd - mode resistor are both arranged on the same layer as the ohmic electrode.

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