Data processing method, processing system, and computer-readable storage medium

Abstract

The present application belongs to the technical field of storage. Disclosed are a data processing method, a processing system, and a computer-readable storage medium. In the processing system, a first message is sent to a controller by means of a processor, the first message is received by means of the controller, and first data in a first cache unit is copied to a first part of a second cache unit on the basis of the first message, so as to obtain second data. Then, the second data is sent to the processor by means of the controller, and the second data is received by means of the processor, so that data processing is implemented. A second part other than the first part in the second cache unit has a record, which is used for invalidating data in the second part, so that the first part, in which the second data is cached, does not need to have a record used for invalidation. Therefore, even if the first data is updated after a copying process is completed, the second data does not need to be invalidated on the basis of the record, thereby saving on overheads required for invalidation, and thus reducing the overheads of a data processing process.

Description

Data processing method, processing system and computer readable storage medium

[0001] This application claims priority to Chinese patent application No. 202311841148.3 filed on December 28, 2023, with invention name “Method, device, equipment and computer-readable storage medium for processing data”. This application claims priority to Chinese patent application No. 202410353613.7 filed on March 26, 2024, with invention name “Method, processing system and computer-readable storage medium for processing data”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a method for processing data, a processing system, and a computer-readable storage medium. Background Art

[0003] In the field of storage technology, data can be stored in media such as cache to facilitate processing of the stored data. How to reduce the overhead of the data processing process has become a problem worthy of attention. Summary of the Invention

[0004] The present application provides a method, a processing system, and a computer-readable storage medium for processing data to reduce the overhead of the data processing process. The technical solution provided by the present application includes the following aspects.

[0005] In a first aspect, a method for processing data is provided. The method is applied to a processing system comprising a controller, a first cache unit, a second cache unit, and at least one processor. In this method, a first message is sent by the processor to the controller, the first message is received by the controller, and first data in the first cache unit is copied to a first portion of the second cache unit based on the first message to obtain second data. Subsequently, the second data is sent by the controller to the processor, and the second data is received by the processor. A record exists in a second portion of the second cache unit, excluding the first portion, and the record is used to invalidate the data in the second portion.

[0006] In the present application, a record for invalid data is made to exist in the second part of the second cache unit, while there is no need for a record for invalid data in the first part. Thus, after the processor sends the first message, the controller can copy the first data in the first cache unit to the second part according to the first message, and send the second data in the second part to the processor, so that the processor can receive the second data. Moreover, since there is no need for a record for invalid data in the first part, the copying process will not generate a record for invalid data. Even if the first data in the first cache unit is subsequently updated, since there is no record for invalid data, there is no need to invalidate the second data in the first part according to the record, thereby saving the overhead required for invalidation, that is, saving the overhead of maintaining consistency between the first cache unit and the second cache unit, thereby reducing the overhead of the data processing process.

[0007] In one possible implementation, before the processor sends the first message to the controller, the method further includes: sending, by the controller, a second message to the processor, and receiving, by the processor, the second message indicating that the first data needs to be written to the first cache unit. Accordingly, sending, by the processor, the first message to the controller includes: sending, by the processor, the first message to the controller based on the second message.

[0008] When the first data needs to be written into the first cache unit, the controller sends a second message to the processor, so that the processor can determine that the first data needs to be written into the first cache unit based on the second message. The processor does not need to determine that the first data needs to be written into the first cache unit through polling, which saves the overhead required for polling and thus reduces the overhead of the data processing process.

[0009] In one possible implementation, before the controller sends the second message to the processor, the method further includes: sending a third message to the controller by the processor, and receiving the third message by the controller. Accordingly, sending the second message to the processor by the controller includes: upon detecting, based on the third message, that the first data needs to be written to the first cache unit, sending the second message to the processor by the controller.

[0010] Therefore, when the first data needs to be written to any address of the first cache unit, the controller will send the second message to the processor. This implementation method is more comprehensive.

[0011] In one possible implementation, the first cache unit includes a third portion and a fourth portion. Before the controller sends the second message to the processor, the method further includes: sending a fourth message to the controller by the processor, and receiving the fourth message by the controller. Accordingly, sending the second message to the processor by the controller includes: upon detecting, based on the fourth message, that the first data needs to be written to the third portion, sending the second message to the processor, the second message indicating that the first data needs to be written to the third portion.

[0012] This implementation divides the first cache unit into a third and fourth portion. The controller sends the second message to the processor only when the first data needs to be written to the third portion of the first cache unit. However, the controller does not send the second message to the processor when the first data needs to be written to the fourth portion of the first cache unit. This implementation is highly targeted, and the third portion can be flexibly configured based on actual needs.

[0013] In a possible implementation, the method further includes: when the controller detects that the data in the second part is updated by the processor, writing the updated data in the second part back to the first cache unit.

[0014] That is, if the data in the first part is updated by the processor, the controller will not write back the updated data in the first part to the first cache unit, which further saves the overhead required for write-back and reduces the overhead of the data processing process.

[0015] In a possible implementation, the first part is part or all of the second cache unit.

[0016] If the first portion is part of the second cache unit, then the first portion and the second portion coexist in the second cache unit. If the first portion is the entire second cache unit, then the first portion is the second cache unit, the address occupied by the second portion in the second cache unit is empty, and no record of invalid data is required in the second cache unit. This implementation method is relatively flexible and has strong applicability.

[0017] In a second aspect, a processing system is provided. The processing system includes a controller, a first cache unit, a second cache unit, and at least one processor.

[0018] The processor is configured to send a first message to the controller;

[0019] A controller, configured to receive a first message;

[0020] The controller is further configured to copy the first data in the first cache unit to the first portion of the second cache unit according to the first message to obtain second data, wherein a record exists in the second portion of the second cache unit other than the first portion, and the record is used to invalidate the data in the second portion;

[0021] The controller is further configured to send second data to the processor;

[0022] The processor is further configured to receive second data.

[0023] In one possible implementation, the controller is further configured to send a second message to the processor, the second message being configured to indicate that the first data needs to be written to the first cache unit. The processor is further configured to receive the second message. The processor is configured to send the first message to the controller based on the second message.

[0024] In one possible implementation, the processor is further configured to send a third message to the controller. The controller is further configured to receive the third message. The controller is configured to, based on the third message, send a second message to the processor when detecting that the first data needs to be written into the first cache unit.

[0025] In one possible implementation, the first cache unit includes a third portion and a fourth portion. The processor is further configured to send a fourth message to the controller. The controller is further configured to receive the fourth message. The controller is configured to, upon detecting, based on the fourth message, that the first data needs to be written to the third portion, send a second message to the processor, the second message indicating that the first data needs to be written to the third portion.

[0026] In a possible implementation, the controller is further configured to write back the updated data in the second part to the first cache unit when detecting that the data in the second part is updated by the processor.

[0027] In a possible implementation, the first part is part or all of the second cache unit.

[0028] In a third aspect, a device for processing data is provided. The device is applied to at least one processor included in a processing system, the processing system also including a controller, a first cache unit, and a second cache unit. The device includes:

[0029] a transceiver module, configured to send a first message to the controller, wherein the first message causes the controller to copy the first data in the first cache unit to the first part of the second cache unit to obtain second data, and a record exists in the second part of the second cache unit except the first part, wherein the record is used to invalidate the data in the second part;

[0030] The transceiver module is further configured to receive second data sent by the controller.

[0031] In a possible implementation, the transceiver module is further configured to receive a second message sent by the controller, the second message being used to indicate that the first data needs to be written into the first cache unit, and the transceiver module is configured to send the first message to the controller according to the second message.

[0032] In a possible implementation, the transceiver module is further configured to send a third message to the controller. The third message is used for the controller to send the second message to the processor when it detects that the first data needs to be written into the first cache unit.

[0033] In one possible implementation, the first cache unit includes a third portion and a fourth portion. The transceiver module is further configured to send a fourth message to the controller. The fourth message is configured to cause the controller to send a second message to the processor, indicating that the first data needs to be written to the third portion, when the controller detects that the first data needs to be written to the third portion.

[0034] In a possible implementation, the first part is part or all of the second cache unit.

[0035] In a fourth aspect, a device for processing data is provided. The device is applied to a controller included in a processing system, the processing system also including a first cache unit, a second cache unit, and at least one processor, the device including:

[0036] a transceiver module, configured to receive a first message sent by the processor;

[0037] a copy module, configured to copy the first data in the first cache unit to the first part of the second cache unit according to the first message to obtain second data, wherein a record exists in the second part of the second cache unit except the first part, and the record is used to invalidate the data in the second part;

[0038] The transceiver module is further configured to send second data to the processor.

[0039] In a possible implementation, the transceiver module is further configured to send a second message to the processor, where the second message is configured to indicate that the first data needs to be written into the first cache unit.

[0040] In a possible implementation, the transceiver module is further configured to receive a third message sent by the processor. The transceiver module is configured to send a second message to the processor when detecting that the first data needs to be written into the first cache unit based on the third message.

[0041] In one possible implementation, the first cache unit includes a third portion and a fourth portion. The transceiver module is further configured to receive a fourth message sent by the processor. The transceiver module is configured to, based on the fourth message, send a second message to the processor when detecting that the first data needs to be written to the third portion. The second message is configured to indicate that the first data needs to be written to the third portion.

[0042] In a possible implementation, the apparatus further includes: a write-back module configured to write back the updated data in the second part to the first cache unit when detecting that the data in the second part is updated by the processor.

[0043] In a possible implementation, the first part is part or all of the second cache unit.

[0044] In a fifth aspect, a processor is provided, which is used to implement the steps executed by the processor in the method for processing data provided in the first aspect or any possible implementation manner of the first aspect.

[0045] In a sixth aspect, a cache system is provided, which includes a controller, a first cache unit and a second cache unit, and the controller is used to implement the steps performed by the controller in the method for processing data provided in the first aspect or any possible implementation of the first aspect.

[0046] In the seventh aspect, a computer-readable storage medium is provided, in which at least one computer instruction is stored, and the at least one computer instruction is loaded and executed by a processor so that the processor implements the steps executed by the processor in the method for processing data provided in the first aspect or any possible implementation of the first aspect.

[0047] In an eighth aspect, a computer-readable storage medium is provided, in which at least one computer instruction is stored. The at least one computer instruction is loaded and executed by a controller so that the controller implements the steps executed by the controller in the method for processing data provided in the first aspect or any possible implementation of the first aspect.

[0048] In a ninth aspect, a computer program product is provided, which includes computer instructions, and the computer instructions are executed by a processor to enable the processor to implement the steps executed by the processor in the method for processing data provided in the first aspect or any possible implementation of the first aspect.

[0049] In the tenth aspect, a computer program product is provided, which includes computer instructions, and the computer instructions are executed by a controller to enable the controller to implement the steps executed by the controller in the method for processing data provided in the first aspect or any possible implementation of the first aspect.

[0050] In the eleventh aspect, a chip is provided, comprising a processor for calling and executing instructions stored in a memory, so that a computer equipped with the chip executes the method for processing data provided by the first aspect or any possible implementation of the first aspect.

[0051] In the twelfth aspect, another chip is provided, comprising: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, a computer equipped with the chip executes the method for processing data provided by the first aspect or any possible implementation of the first aspect.

[0052] It should be understood that the technical effects achieved by the technical solutions provided in the second to twelfth aspects of this application and the corresponding possible implementation methods can be referred to the above description of the technical effects achieved by the technical solutions provided in the first aspect and the corresponding possible implementation methods, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] FIG1 is a schematic diagram of the structure of a processing system provided in an embodiment of the present application;

[0054] FIG2 is a schematic diagram of the structure of another processing system provided in an embodiment of the present application;

[0055] FIG3 is a schematic diagram of the structure of another processing system provided in an embodiment of the present application;

[0056] FIG4 is a flow chart of a method for processing data provided in an embodiment of the present application;

[0057] FIG5 is a schematic diagram of a data processing process provided by an embodiment of the present application;

[0058] FIG6 is a schematic structural diagram of a data processing device provided in an embodiment of the present application;

[0059] FIG7 is a schematic structural diagram of another device for processing data provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0061] An embodiment of the present application provides a processing system, as shown in Figure 1, which includes a processor 101, a controller 102, a first cache unit 103, and a second cache unit 104. The processor 101 is connected to the controller 102, and the controller 102 is further connected to the first cache unit 103 and the second cache unit 104, respectively.

[0062] Exemplarily, the processor 101 includes one or more processing cores. In an exemplary embodiment, the processor 101 also includes at least one register. The processing cores and registers are not shown in FIG1 . Optionally, the controller 102 includes but is not limited to a control circuit, the first cache unit 103 and the second cache unit 104 include but are not limited to a cache unit array, and the controller 102 and the first cache unit 103 and the second cache unit 104 constitute a cache. Exemplarily, the first cache unit 103 and the second cache unit 104 can be different parts of the same cache unit array, or can be different cache unit arrays, which is not limited in the embodiments of the present application.

[0063] Referring to Figure 2, the first cache unit 103 is a cache unit that can be directly read and written by the bus device 105, and the controller 102 is also connected to the bus device 105 via a bus. In an exemplary embodiment, the bus device 105 includes but is not limited to a network card, a graphics card, etc., and the bus includes but is not limited to a fast peripheral component interconnect express (PCIe) bus, a compute express link (CXL) bus, etc. The embodiment of the present application does not limit the type of the bus device 105 and the bus. In the case where the bus is a PCIe bus, the controller 102 and the bus device 105 are respectively connected to the PCIe root complex (RC) via the bus, thereby realizing the connection between the controller 102 and the bus device 105, and the bus device 105 can directly read and write to the first cache unit 103 through direct memory access (DMA) technology. In some embodiments, the processor 101 does not directly read and write to the first cache unit 103. In addition, the second cache unit 104 is a cache unit that the processor 101 can directly read and write. In an exemplary embodiment, the bus device 105 does not directly read or write data from the second cache unit 104 .

[0064] Exemplarily, the second cache unit 104 includes N-level cache units, where N is a positive integer greater than or equal to 1. Correspondingly, the first cache unit 103 is called an (N+1)-level cache unit or a last level cache (LLC) unit. Optionally, the N-level cache unit and the first cache unit 103 can be different parts of the same cache unit array, or different cache unit arrays. Taking the value of N equal to 2 as an example, the second cache unit 104 includes a first-level (level 1, L1) cache unit and a second-level (level 2, L2) cache unit, and the first cache unit 103 is called an L3 cache unit or an LLC unit. The L2 cache unit and the L3 cache unit can be different parts of the same cache unit array, or different cache unit arrays.

[0065] In an exemplary embodiment, the controller 102 includes multiple sub-controllers, and the first cache unit 103 and the second cache unit 104 correspond to different sub-controllers. In the case where the second cache unit 104 includes N levels of cache units, each level of the N levels of cache units also corresponds to a different sub-controller.

[0066] For example, referring to Figure 3, controller 102 includes sub-controller 1, sub-controller 2, and sub-controller 3. Second cache unit 104 includes an L1 cache unit and an L2 cache unit. First cache unit 103 is an L3 cache unit. The L1 cache unit corresponds to sub-controller 1, and the L1 cache unit and sub-controller 1 form the L1 cache. The L2 cache unit corresponds to sub-controller 2, and the L2 cache unit and sub-controller 2 form the L2 cache. The L3 cache unit corresponds to sub-controller 3, and the L3 cache unit and sub-controller 3 form the L3 cache, which can also be called the LLC.

[0067] The embodiment of the present application does not limit the number of processors 101 in the processing system, and the number of processors 101 can be one or more. In other words, the number of processors 101 is at least one. In the case where there are multiple processors 101, the multiple processors 101 can be processors of the same or different types. In the case where the multiple processors 101 are processors of different types, the processing system is a heterogeneous system. In addition, in the case where there are multiple processors 101, the multiple processors 101 can be located in the same or different computer devices. In the case where the multiple processors 101 are located in different computer devices, the processing system is a distributed system, in which case each processor 101 corresponds to a controller 102, a first cache unit 103, and a second cache unit 104.

[0068] Exemplarily, the above-mentioned processor is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor or one or more integrated circuits or application-specific integrated circuits (ASIC) for implementing the solution of the present application, a programmable logic device (PLD), other general-purpose processors or other programmable logic devices, discrete gates, transistor logic devices, discrete hardware components or any combination thereof. PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor, etc. Exemplarily, the processor may be a processor that supports the advanced reduced instruction set machine (ARM) architecture. The processor can implement or execute various logic blocks, modules and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0069] In an exemplary embodiment, the cache memory composed of the controller, the first cache unit, and the second cache unit is a volatile memory. The volatile memory may be a random access memory (RAM). Exemplarily, the RAM includes, but is not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct RAM bus random access memory (DR RAM), etc.

[0070] The structure of the processing system has been described above. The functions of the various components included in the processing system will be introduced through the method embodiment shown in FIG4 below, and will not be described in detail here.

[0071] The present application provides a method for processing data, which can be applied to the processing system shown in Figure 1. For example, the method is implemented through interaction between a processor and a controller included in the processing system, which is not limited in the present application. As shown in Figure 4, the method includes the following steps 401 to 405.

[0072] Step 401: Send a first message to a controller via a processor.

[0073] The first message is used by the controller to copy the first data in the first cache unit to the first part of the second cache unit to obtain the second data (hereinafter referred to as the copy process). In other words, the data content of the first data and the second data are the same, and the first data and the second data are located in different cache units. When the processor needs to read data, it sends the first message to the controller so that the controller can copy the first data in the first cache unit to the first part of the second cache unit according to the first message to obtain the second data, so that the processor can receive the second data sent by the controller, thereby realizing data reading.

[0074] In some embodiments, the first part is a part in the second cache unit. That is, there is a second part in addition to the first part in the second cache unit, and the second part occupies a certain address. For example, in the case where the second cache unit includes N-level cache units, the first part can be located in at least one level of cache units in the N-level cache units. For example, the first part is located in the lowest level cache unit in the N-level cache unit, and this embodiment of the application is not limited to this. Taking the N-level cache unit including the L1 cache unit and the L2 cache unit as an example, the first part can be located in the L2 cache unit. In other embodiments, the first part is all of the second cache unit. That is, the first part is the second cache unit, and the address occupied by the aforementioned second part is empty. In the embodiment of the present application, the first part and the second part in the second cache unit can be flexibly pre-allocated according to actual needs, as long as the first part and the second part are different parts in the second cache unit.

[0075] For example, when the first cache unit and the second cache unit are controlled by the same controller, the processor sends a first message to the controller, causing the controller to implement the copy process according to the first message. Alternatively, when the controller includes multiple sub-controllers, the first cache unit and the second cache unit are controlled by different sub-controllers, and the processor sends the first message to the sub-controller corresponding to the first cache unit, causing the sub-controller corresponding to the first cache unit to cooperate with the sub-controller corresponding to the second cache unit to implement the copy process according to the first message.

[0076] Exemplarily, the first message includes a data identifier and a read identifier. The data identifier is used to uniquely identify the first data, so that the controller can locate the first data in the first cache unit. As can be seen from the above description, the data content of the first data and the second data is the same, so the data identifier can also be used to uniquely identify the second data. For example, the controller is configured with a correspondence between the data identifier and the first address, and the first address is the address of the first data in the first cache unit. The controller can query the correspondence based on the data identifier to obtain the first address corresponding to the data identifier, and thus locate the first data in the first cache unit based on the first address. The read identifier is used by the controller to complete the copy process. For example, the read identifier is a string with a certain value, and the embodiment of the present application does not limit the value of the string. For the controller, the read identifier is a special identifier, and the first message including the read identifier is a special message, so that the controller can copy the first data to the first part of the second cache unit according to the first message. Exemplarily, the embodiment of the present application can modify the cache consistency protocol so that the modified cache consistency protocol supports this read identifier and the first message, and the cache consistency protocol includes but is not limited to the modified exclusive shared or invalid (MESI) protocol. In addition, there may be other identifiers different from the read identifier. When the controller receives another message including the other identifier, the controller may copy the first data to the second portion of the second cache unit according to the other message, so as to facilitate sending the copied data in the second portion to the processor. Thus, the first message including the read identifier and the other message including the other identifier are two different messages used by the processor to read data.

[0077] In some embodiments, the processor is capable of determining the address range occupied by the first portion in the second cache unit. For example, the processor is configured with the address range occupied by the first portion in the second cache unit, and the processor can determine the address range by reading the stored address range. Exemplarily, the processor determines the second address from the address range, and the first message also includes the second address. The second address is used by the controller to determine the cache location of the second data in the first portion, or in other words, the second address is used to cache the second data.

[0078] In other embodiments, the processor does not need to determine the address range occupied by the first portion in the second cache unit. For example, the processor does not need to configure the address range, which reduces the configuration requirements of the processor and reduces overhead. Accordingly, the first message does not need to include the second address within the address range. The controller then independently determines the cache location of the second data in the first portion.

[0079] As described above, when the processor needs to read data, it sends a first message to the controller (or the sub-controller corresponding to the first cache unit). The processor can send the first message to the controller in at least one of the following two implementations.

[0080] In some embodiments, the processor performs polling. For example, the processor performs polling according to the data plane development kit (DPDK) technology. When the processor determines through polling that the first data needs to be written to the first cache unit, it determines that data reading is required, thereby sending a first message to the controller. For example, when the bus device needs to write the first data to the first cache unit, the bus device sends a write request and the first data to the controller, and the controller can determine that the first data needs to be written to the first cache unit based on the write request. Thus, when the processor polls the controller, the controller can feedback to the processor that the first data needs to be written to the first cache unit, so that the processor can determine that the first data needs to be written to the first cache unit based on the feedback from the controller and send a first message to the controller.

[0081] In other embodiments, the processor does not need to perform polling, which is also referred to as a dedicated snoop mechanism. Exemplarily, before the processor sends the first message to the controller, the method further includes: sending a second message to the processor through the controller, the second message being used to indicate that the first data needs to be written into the first cache unit, and receiving the second message through the processor. Accordingly, sending the first message to the controller through the processor includes: sending the first message to the controller through the processor according to the second message. For example, when the controller determines (for example, based on a write request sent by a bus device) that the first data needs to be written into the first cache unit, it sends the second message to the processor. Optionally, the second message is in the form of an event, and the embodiment of the present application does not limit the form of the second message. Since the second message is used to indicate that the first data needs to be written into the first cache unit, the processor can determine that the first data needs to be written into the first cache unit based on the received second message, thereby determining that data reading is required and sending the first message to the controller. Thus, the processor does not need to continuously poll to determine that the first data needs to be written into the first cache unit. The processor can wait for the second message sent by the controller, thereby reducing the overhead required for continuous polling, which is conducive to reducing the overhead of the data processing process. When the data processing latency requirement is high, or when low latency needs to be guaranteed, if the processor needs to poll, the polling may be performed at a higher frequency. However, in the embodiment of the present application, the processor does not need to poll, and the amount of overhead saved is considerable.

[0082] Exemplarily, the processor includes a register, in which a code is stored. When the code is executed by the processor, the processor is used to send a first message to the controller. Therefore, after receiving the second message, the processor activates the register according to the second message to execute the code stored in the register, thereby sending the first message to the controller. Optionally, the processor sends the first message to the controller only after receiving the second message sent by the controller for the first time. That is to say, before the processor receives the second message sent by the controller for the first time, the first message will not be sent to the controller, and the controller will not perform the copy process according to the first message, so that before the processor receives the second message sent by the controller for the first time, the first part of the second cache unit does not contain the second data obtained by the copy process, thereby ensuring the reliability of the first part of the second cache unit.

[0083] In some embodiments, the controller is configured such that, upon determining that the first data needs to be written to the first cache unit, the controller sends the second message to the processor by default. For example, upon determining that the first data needs to be written to any address in the first cache unit, the controller sends the second message to the processor by default. For another example, upon determining that the first data needs to be written to a specified address in the first cache unit, the controller sends the second message to the processor by default. The specified address can be flexibly configured based on actual needs.

[0084] In other embodiments, there is no need to configure the controller, but the controller sends a second message to the processor according to the instructions of the processor. For example, the processor first makes a query from the controller to determine whether the first data needs to be written to the first cache unit. If the feedback from the controller is that the first data does not need to be written to the first cache unit, the processor instructs the controller again so that when the controller subsequently determines that the first data needs to be written to the first cache unit, it sends the second message to the processor. For another example, the processor does not make any queries from the controller, but directly instructs the controller so that when the controller determines that the first data needs to be written to the first cache unit, it sends the second message to the processor. Regardless of whether the processor makes a query, the processor can instruct the controller through any of the following two implementations.

[0085] In some embodiments, before the controller sends the second message to the processor, the method further includes: sending a third message to the controller by the processor, and receiving the third message by the controller, wherein the third message is used by the controller to send the second message to the processor when the controller detects that the first data needs to be written to the first cache unit. Accordingly, sending the second message to the processor by the controller includes: sending the second message to the processor when the controller detects that the first data needs to be written to the first cache unit based on the third message.

[0086] In other words, the processor sends a third message to the controller, instructing the controller to send the second message to the processor if it subsequently detects that the first data needs to be written to the first cache unit. Accordingly, after receiving the third message, the controller parses it and, based on the instructions in the third message, sends the second message to the processor if it subsequently detects that the first data needs to be written to any address in the first cache unit. This implementation is relatively comprehensive.

[0087] In other embodiments, the first cache unit includes a third portion and a fourth portion, and before the controller sends the second message to the processor, the method further includes: sending a fourth message to the controller by the processor, and receiving the fourth message by the controller, wherein the fourth message is used by the controller to send the second message to the processor when the controller detects that the first data needs to be written to the third portion, and the second message is used to indicate that the first data needs to be written to the third portion. Accordingly, sending the second message to the processor by the controller includes: sending the second message to the processor when the controller detects that the first data needs to be written to the third portion based on the fourth message.

[0088] That is, the processor sends a fourth message to the controller, instructing the controller to send the second message to the processor if it subsequently detects that the third part needs to write the first data, and not to send the second message to the processor if it subsequently detects that the fourth part needs to write the first data. Accordingly, after receiving the fourth message, the controller parses the fourth message and, based on the instructions of the fourth message, sends the second message to the processor if it subsequently detects that the third part in the first cache unit needs to write the first data. This implementation method is highly targeted, and the third part can be flexibly set according to actual needs.

[0089] Step 402: Receive a first message through the controller.

[0090] Since the processor sends the first message to the controller, the controller can correspondingly receive the first message sent by the processor.

[0091] Step 403: The controller copies the first data in the first cache unit to the first part of the second cache unit according to the first message to obtain second data.

[0092] The controller parses the received first message. Since the first message is used by the controller to copy the first data in the first cache unit to the first part of the second cache unit to obtain the second data, the controller can copy the first data in the first cache unit to the first part of the second cache unit according to the first message to obtain the second data, so that the processor can receive the second data sent by the controller.

[0093] Exemplarily, the controller parses the first message to obtain a data identifier and a read identifier of the first data. The controller is configured with a correspondence between the data identifier and a first address, where the first address is the address of the first data in the first cache unit. The controller queries the correspondence based on the data identifier to obtain the first address corresponding to the data identifier, thereby locating the first data in the first cache unit based on the first address, and copies the first data to the first portion of the second cache unit based on the read identifier to obtain the second data.

[0094] In some embodiments, the first message also includes the second address in the first portion of the second cache unit. If the controller parses the first message and obtains the second address, the controller locates the first data according to the first address and then copies the first data to the second address in the first portion of the second cache unit based on the read identifier and the second address. Optionally, the controller may store the correspondence between the data identifier and the second address for subsequent use.

[0095] In other embodiments, the first message does not need to include the second address. After locating the first data according to the first address, the controller determines the cache position of the second data in the first part by itself, and copies the first data to the cache position in the first part of the second cache unit according to the read identifier to obtain the second data. For example, if there is an unoccupied address in the first part of the second cache unit, the controller can use the unoccupied address as the cache position of the second data in the first part. If there is no unoccupied address in the first part of the second cache unit, the controller can use the address that has been occupied for the longest time in the first part (or, the address occupied by the data cached first in the first part) as the cache position of the second data in the first part. Optionally, the controller can store the correspondence between the data identifier and the cache position of the second data for subsequent use.

[0096] For example, if the first and second cache units are controlled by the same controller, the controller can simply implement the copy process according to the first message as described above. Alternatively, if the controller includes multiple sub-controllers, the first and second cache units are controlled by different sub-controllers, and the sub-controller corresponding to the first cache unit needs to cooperate with the sub-controller corresponding to the second cache unit according to the first message to implement the copy process. If the second cache unit includes N-level cache units, the sub-controller corresponding to the second cache unit can be the sub-controller corresponding to the first-level cache unit where the first portion is located. After locating the first data according to the description above, the sub-controller corresponding to the first cache unit sends the data identifier and the first data to the sub-controller corresponding to the second cache unit based on the read identifier. The sub-controller corresponding to the second cache unit then caches the first data in the first portion of the second cache unit, obtaining the second data, thereby implementing the copy process. Optionally, if the first message includes a second address, the sub-controller corresponding to the first cache unit sends the data identifier, the first data, and the second address to the sub-controller corresponding to the second cache unit. The sub-controller corresponding to the second cache unit then caches the first data in the second address in the first portion of the second cache unit. Optionally, the sub-controller corresponding to the second cache unit stores the correspondence between the data identifier and the second address for subsequent use. Alternatively, if the first message does not need to include the second address, the sub-controller corresponding to the first cache unit sends the data identifier and the first data to the sub-controller corresponding to the second cache unit without sending the second address. The sub-controller corresponding to the second cache unit then independently determines the cache location of the second data in the first portion. The method for independently determining the cache location of the second data in the first portion is described above and is not further elaborated here. Optionally, the sub-controller corresponding to the second cache unit stores the correspondence between the data identifier and the cache location of the second data for subsequent use.

[0097] In an embodiment of the present application, a record exists in the second portion of the second cache unit, excluding the first portion, and is used to invalidate data in the second portion. Exemplarily, the record includes a correspondence between a third address and a fourth address. The third address is the address of the third data in the first cache unit. When the third data is copied to the second portion of the second cache unit to obtain the fourth data, the fourth data belongs to the data in the second portion. The fourth address is the address of the fourth data in the second portion. The third and fourth data have the same data content, but are located in different cache units. If a reference component in the processing system detects an update to the third data in the first cache unit, for example, due to a modification of a bus device, and does not invalidate the fourth data in the second portion, the data content of the third and fourth data will differ, resulting in inconsistency between the first and second cache units. Therefore, after the third data in the first cache unit is updated, the reference component needs to invalidate the fourth data in the second portion to ensure consistency between the second portions of the first and second cache units. Because this record is used to ensure consistency between different cache units, it is also called a cache consistency record. During the invalidation process, the reference component can query the record based on the third address of the third data in the first cache unit, obtain the fourth address corresponding to the third address, and invalidate the fourth data at the fourth address to avoid errors caused by the processor subsequently reading the fourth data at the fourth address.

[0098] The embodiments of the present application do not limit the reference component. In some embodiments, the reference component is a controller, which is used to control the first cache unit and the second cache unit. In other embodiments, the reference component is a sub-controller. For example, the reference component can be a sub-controller corresponding to the first cache unit or the second cache unit. In the case where the second cache unit includes N-level cache units, the reference component can be a sub-controller corresponding to at least one level of cache unit in the N-level cache unit (for example, the cache unit where the first part is located). In some other embodiments, the processing system also includes a snoop filter (SF), and the reference component is the SF. The SF is connected to the second cache unit, and the SF is also called a snoop unit. In the case where the second cache unit includes N-level cache units, the SF can be connected to the lowest level cache unit in the second cache unit. For example, in the processing system shown in Figure 3, the SF can be located in the L2 cache (SF is not shown in Figure 3) and connected to the L2 cache unit in the L2 cache.

[0099] Unlike the second part of the second cache unit, in the embodiment of the present application, there is no record of the first part of the second cache unit. This situation where the first part is different from the second part is also called a non-consistent load mechanism. For example, after the first data in the first cache unit is copied to the first part to obtain the second data, no correspondence is generated between the first address of the first data in the first cache unit and the second address of the second data in the first part. For example, the above-mentioned reference component is configured with the address range of the first part of the second cache unit. When the second data at the second address is obtained through the copy process, the reference component determines that the second address is within the address range of the first part, and then no correspondence is generated between the first address and the second address, so that there is no record in the first part. Therefore, even if the first data in the first cache unit is updated later, the reference component will not query the second address based on the first address, so there is no need to invalidate the second data at the second address, reducing the overhead required for invalidation, or in other words, reducing the overhead required to maintain the consistency of the first cache unit and the first part of the second cache unit, thereby reducing the overhead of the data processing process. In a case where the frequency of interaction between the processor and the bus device is high, for example, the bus device writes data to the first cache unit at a high frequency and the processor reads data from the first cache unit at a high frequency, the embodiment of the present application can omit multiple invalidation processes, thereby saving a considerable amount of overhead.

[0100] For example, in an embodiment of the present application, when the processor needs to read data, it may not directly read from the first portion of the second cache unit, but instead may send a first message to copy the first data in the first cache unit to the first portion, and then read the second data from the first portion. In this way, even if the first portions of the first and second cache units are inconsistent due to the lack of invalidation, the processor can avoid errors when reading data because it does not directly read from the first portion.

[0101] Step 404: Send second data to the processor via the controller.

[0102] After completing the copy process, the controller obtains the second data in the first portion of the second cache unit. Therefore, the controller can send the second data to the processor for the processor to receive. For example, the controller can also send the data identifier included in the first message to the processor so that the processor can determine that the received second data is the data uniquely identified by the data identifier, thereby facilitating the processor to distinguish different received data.

[0103] In some embodiments, the second cache unit includes a level 1 cache unit. After the controller (or the sub-controller corresponding to the level 1 cache unit) completes the copy process, it obtains the second data in the level 1 cache unit and then directly sends the second data to the processor.

[0104] In other embodiments, the second cache unit includes multiple levels of cache units, and the first portion is located in the highest level cache unit in the multi-level cache unit. After the controller (or the sub-controller corresponding to the highest level cache unit) completes the copy process, it obtains the second data in the highest level cache unit and then directly sends the second data to the processor. For example, the second cache unit includes an L1 cache unit and an L2 cache unit, the L1 cache unit is the highest level cache unit, and the first portion is located in the L1 cache unit. The controller directly sends the second data in the first portion of the L1 cache unit to the processor.

[0105] In some other embodiments, the second cache unit includes a multi-level cache unit, and the first part is located in a non-highest level cache unit in the multi-level cache unit. After the controller (or the sub-controller corresponding to the non-highest level cache unit) completes the copy process, it obtains the second data in the non-highest level cache unit. After that, the controller copies upwards step by step until the second data is copied to the highest level cache unit in the multi-level cache unit, and sends the data in the highest level cache unit (the same data content as the second data) to the processor. For example, the second cache unit includes an L1 cache unit and an L2 cache unit, the L1 cache unit is the highest level cache unit, the L2 cache unit is a non-highest level cache unit, and the first part is located in the L2 cache unit. The controller copies the second data in the first part of the L2 cache unit to the L1 cache unit, obtains the fifth data, and sends the fifth data in the L1 cache unit to the processor.

[0106] Step 405: Receive second data through the processor.

[0107] Since the controller sends the second data to the processor, the processor can receive the second data accordingly. For the processor, after sending the first message to the controller, it can receive the second data, thereby realizing data reading. Exemplarily, the processor also receives the data identifier sent by the controller to determine that the received second data is the data uniquely identified by the data identifier, thereby distinguishing the different data received. For example, the processor sends a first message 1 including data identifier 1 and a first message 2 including data identifier 2 to the controller. Then, when the processor receives data identifier 1 and the second data, the processor can determine that the second data is the data indicated by data identifier 1, rather than the data indicated by data identifier 2.

[0108] In an exemplary embodiment, the method provided in the embodiment of the present application also includes: when the controller detects that the data in the second part is updated by the processor, the updated data in the second part is written back to the first cache unit. For example, when the processor needs to update the fourth data in the second part, it sends a fifth message to the controller, the fifth message includes the updated data (i.e., the updated fourth data), the fourth address and the write identifier, the controller parses the fifth message, obtains the updated data, the fourth address and the write identifier, locates the fourth data in the second part according to the fourth address, and replaces the fourth data with the updated data according to the write identifier. In addition, since the fourth address belongs to the address range of the second part, the controller also queries the record to obtain the third address corresponding to the fourth address, and writes the updated data to the third address, thereby realizing the write back of the updated data in the second part to the first cache unit.

[0109] Still different from the second part of the second cache unit, in an embodiment of the present application, even if the data in the first part of the second cache unit is updated by the processor, the controller will not write back the updated data in the first part to the first cache unit. For example, when the processor needs to update the second data in the first part, it sends a sixth message to the controller, the sixth message including the updated second data, the data identifier and the write identifier, and the controller parses the sixth message to obtain the updated second data, the data identifier and the write identifier. Afterwards, the controller locates the second data in the first part according to the data identifier, and replaces the second data with the updated second data according to the write identifier. For example, the controller queries the correspondence between the data identifier and the second address (or the correspondence between the data identifier and the cache position of the second data) based on the data identifier, obtains the second address corresponding to the data identifier (or the cache position of the second data), and thus can locate the second data in the first part. However, since the second address belongs to the address range of the first part, the controller does not need to write back the updated second data in the first part to the first cache unit.

[0110] In an exemplary embodiment, if the second cache unit includes a level 1 cache unit, the processor can update the second data in the first portion according to the above description. Alternatively, if the first portion is located in a highest level cache unit among multiple levels of cache units included in the second cache unit, the processor can also update the second data in the first portion according to the above description. For example, if the second cache unit includes an L1 cache unit and an L2 cache unit, the L1 cache unit is the highest level cache unit, and the first portion is located in the L1 cache unit, the processor can update the second data in the first portion of the L1 cache unit.

[0111] In addition, when the first part is located in a non-highest level cache unit among the multi-level cache units included in the second cache unit, the processor can update the data in the highest level cache unit, and the updated data will not be written back to the non-highest level cache unit, nor will it be written back to the first cache unit. For example, the second cache unit includes an L1 cache unit and an L2 cache unit, the L1 cache unit is the highest level cache unit, the L2 cache unit is a non-highest level cache unit, the first part is located in the L2 cache unit, and the second data in the first part of the L2 cache unit has the same data content as the fifth data in the L1 cache unit. The processor can update the fifth data in the L1 cache unit to obtain the updated fifth data, but the updated fifth data will not be written back to the first part of the L2 cache unit, nor will it be written back to the first cache unit.

[0112] The data processing method provided in the embodiments of the present application has been generally described above. For example, the embodiments of the present application can modify the processor's driver to enable the processor to execute steps 401 and 405 above. The driver is a type of driver-layer software. Next, the method provided in the embodiments of the present application will be illustrated using a bus device such as a network card, with reference to FIG5 .

[0113] The processor sends a fourth message to sub-controller 3. The fourth message is used by the controller to send a second message to the processor when the controller detects that the first data needs to be written to the third portion of the L3 cache. The second message is used to indicate that the first data needs to be written to the third portion. Exemplarily, the third portion is the portion of the L3 cache occupied by a completion queue. The completion queue is used to store completion queue entries (CQEs). CQEs are used to indicate completed tasks.

[0114] After receiving the message, the network card generates a CQE, which is used to indicate that the task of receiving the message has been completed. The network card sends a write request, the message and the CQE to the sub-controller 3.

[0115] After receiving the write request, message, and CQE from the network card, sub-controller 3 uses the CQE as the first data to be written to the third portion. Sub-controller 3 then sends a second message to the processor, indicating that the first data needs to be written to the third portion of the L3 cache. Sub-controller 3 also writes the CQE to the third portion of the L3 cache and the message into the L3 cache. This embodiment of the present application does not limit the location in the L3 cache where the message is written.

[0116] After receiving the second message sent by the sub-controller 3 , the processor triggers the sending of the first message to the sub-controller 3 according to the code stored in the register.

[0117] After receiving the first message, sub-controller 3 copies the CQE in the third portion of the L3 cache to the first portion of the L2 cache, obtaining the CQE in the first portion of the L2 cache, i.e., the second data. For example, sub-controller 3 sends the CQE in the third portion of the L3 cache to sub-controller 2. Sub-controller 2 caches the received CQE in the first portion of the L2 cache, thereby obtaining the CQE in the first portion of the L2 cache, completing the copy process.

[0118] For this copy process, although the reference component can detect that new data (i.e., the copied CQE) is cached in the L2 cache, since the new data is copied to the first part, the reference component will not generate a record for the copy process, that is, no correspondence will be generated between the first address of the CQE in the third part and the second address of the CQE in the first part. Exemplarily, the reference component can be the sub-controller 2, sub-controller 3, or SF in the L2 cache shown in Figure 5, which is not limited here. The first message is a special message for the controller. The controller can copy the CQE to the first part of the L2 cache according to the special message, and the reference component will not generate a record. If the controller receives other messages sent by the processor, the controller can copy the data to be copied to the second part of the L2 cache according to the other messages, and the reference component will generate a record accordingly.

[0119] In addition, sub-controller 2 also copies the CQE in the first part to the L1 cache unit, so that sub-controller 1 can return the CQE in the L1 cache unit to the processor. For example, sub-controller 2 sends the CQE in the first part to sub-controller 1, sub-controller 1 caches the received CQE in the L1 cache unit, and sub-controller 1 returns the CQE in the L1 cache unit to the processor.

[0120] After the processor determines that the message reception task has been completed based on the CQE, it sends a clear instruction to sub-controller 3 via the driver. Sub-controller 3 clears the CQE in the third portion of the L3 cache according to the clear instruction, thereby updating the CQE at the first address in the third portion. Because the CQE at the first address is updated, the reference component queries the second address corresponding to the first address. Since the reference component does not generate a record during the aforementioned copy process, the second address corresponding to the first address will not be obtained through the query. Therefore, there is no need to invalidate the CQE at the second address, reducing the overhead required for invalidation, or in other words, reducing the consistency overhead of different cache units. This avoids performance bottlenecks caused by consistency overhead, ensures the message reception performance of the network card, and improves the message reception efficiency of the network card. For example, when the processor needs to read data later, even if the data to be read is cached in the L1 cache unit or the L2 cache unit, the processor can not read the data directly from the L1 cache unit or the L2 cache unit, but can still read the data from the L3 cache via the first message as described above. Thus, although the CQE at the second address is not invalidated, it can prevent the processor from directly reading the CQE at the second address, thus preventing errors in the processor's data reading process due to differences between the data at the first address and the second address. Furthermore, the CQE at the first address in the third portion may be updated for reasons other than clearing the CQE by sub-controller 3. For example, it may be updated due to subsequent writes by the network card. Regardless of the reason for the update, the reference component can query the second address corresponding to the first address as described above to trigger subsequent processes.

[0121] In the related art, when performing data processing, the processor needs to perform polling. When it is determined through polling that data needs to be written to the first cache unit, a message for reading the written data is sent to the controller. Compared with the method in the embodiment of the present application, in which the processor sends a first message to the controller after receiving a second message sent by the controller, the method adopted by the related art has a large overhead due to the need for polling, resulting in a high data processing overhead. It can be seen that the embodiment of the present application can save the overhead required for polling, thereby reducing the overhead of data processing.

[0122] In addition, after the controller in the related art receives the message sent by the processor, the controller copies the data at a certain address (referred to as address A) in the first cache unit to a certain address (referred to as address B) in the second cache unit according to the instruction, and records the corresponding relationship between address A and address B, and sends the data at address B to the processor. When the data at address A is subsequently updated, the corresponding relationship is queried to obtain address B corresponding to address A, and the data at address B is invalidated to ensure the consistency between the first cache unit and the second cache unit. Compared to the related art, in the embodiment of the present application, a first part that does not require the generation of records is provided in the second cache unit, so there is no need to query the records and invalidate them, which reduces the overhead required for invalidation, or reduces the consistency overhead between different cache units, thereby also reducing the overhead of data processing.

[0123] In summary, the embodiments of the present application enable the second part of the second cache unit to have a record for invalid data, while the first part does not need to have a record for invalid data. Thus, after the processor sends the first message, the controller can copy the first data in the first cache unit to the second part according to the first message, and send the second data in the second part to the processor, so that the processor can receive the second data. Moreover, since there is no need for a record for invalid data in the first part, the copying process will not generate a record for invalid data. Even if the first data in the first cache unit is subsequently updated, since there is no record for invalid data, there is no need to invalidate the second data in the first part according to the record, thereby saving the overhead required for invalidation, that is, saving the overhead of maintaining consistency between the first cache unit and the second cache unit, thereby reducing the overhead of the data processing process.

[0124] In addition, when the first data needs to be written in the first cache unit, the controller sends a second message to the processor, so that the processor can determine that the first data needs to be written in the first cache unit based on the second message. The processor does not need to determine that the first data needs to be written in the first cache unit through polling, which saves the overhead required for polling and thus reduces the overhead of the data processing process.

[0125] The above describes the method for processing data provided by the embodiment of the present application. Corresponding to the above method, the embodiment of the present application also provides a device for processing data. The device is applied to at least one processor included in a processing system, and the processing system also includes a controller, a first cache unit, and a second cache unit. The device is used to execute the steps performed by the processor in the method for processing data shown in Figure 4 above through the various modules shown in Figure 6. As shown in Figure 6, the device for processing data provided by the embodiment of the present application includes the following modules.

[0126] The transceiver module 601 is configured to send a first message to the controller, where the first message causes the controller to copy the first data in the first cache unit to the first portion of the second cache unit to obtain second data. The second cache unit contains a record in the second portion other than the first portion, where the record is configured to invalidate the data in the second portion.

[0127] The transceiver module 601 is further configured to receive second data sent by the controller.

[0128] In a possible implementation, the transceiver module 601 is further configured to receive a second message sent by the controller, the second message being used to indicate that the first data needs to be written into the first cache unit, and the transceiver module 601 is configured to send the first message to the controller according to the second message.

[0129] In a possible implementation, the transceiver module 601 is further configured to send a third message to the controller. The third message is configured to enable the controller to send a second message to the processor when it detects that the first data needs to be written into the first cache unit.

[0130] In one possible implementation, the first cache unit includes a third portion and a fourth portion. The transceiver module 601 is further configured to send a fourth message to the controller. The fourth message is configured to cause the controller to send a second message to the processor when detecting that the first data needs to be written to the third portion. The second message is configured to indicate that the first data needs to be written to the third portion.

[0131] In a possible implementation, the first part is part or all of the second cache unit.

[0132] The present application also provides another data processing device. The device is applied to a controller included in a processing system, which also includes a first cache unit, a second cache unit, and at least one processor. The device is configured to execute the steps performed by the controller in the data processing method shown in FIG. 4 above, using the modules shown in FIG. 7 . As shown in FIG. 7 , the data processing device provided in the present application includes the following modules.

[0133] The transceiver module 701 is configured to receive a first message sent by the processor;

[0134] a copy module 702 configured to copy the first data in the first cache unit to the first portion of the second cache unit according to the first message to obtain second data, wherein a record exists in the second portion of the second cache unit other than the first portion, and the record is used to invalidate the data in the second portion;

[0135] The transceiver module 701 is further configured to send second data to the processor.

[0136] In a possible implementation, the transceiver module 701 is further configured to send a second message to the processor, where the second message is configured to indicate that the first data needs to be written into the first cache unit.

[0137] In a possible implementation, the transceiver module 701 is further configured to receive a third message sent by the processor. The transceiver module 701 is configured to send a second message to the processor when detecting that the first data needs to be written into the first cache unit based on the third message.

[0138] In one possible implementation, the first cache unit includes a third portion and a fourth portion. The transceiver module 701 is further configured to receive a fourth message sent by the processor. Upon detecting, based on the fourth message, that the first data needs to be written to the third portion, the transceiver module 701 is configured to send a second message to the processor indicating that the first data needs to be written to the third portion.

[0139] In a possible implementation, the apparatus further includes: a write-back module configured to write back the updated data in the second part to the first cache unit when detecting that the data in the second part is updated by the processor.

[0140] In a possible implementation, the first part is part or all of the second cache unit.

[0141] It should be understood that the beneficial effects of the device shown in Figure 6 or Figure 7 when implementing its functions are the same as the beneficial effects of the method shown in Figure 4. When the device provided in Figure 6 or Figure 7 implements its functions, it only uses the division of the above-mentioned functional modules as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0142] In an exemplary embodiment, the present application provides a processing system comprising a controller, a first cache unit, a second cache unit, and at least one processor. For example, the processing system can be applied to a computer device, enabling the computer device incorporating the processing system to implement the data processing method provided in the present application.

[0143] The processor is configured to send a first message to the controller;

[0144] A controller, configured to receive a first message;

[0145] The controller is further configured to copy the first data in the first cache unit to the first portion of the second cache unit according to the first message to obtain second data, wherein a record exists in the second portion of the second cache unit other than the first portion, and the record is used to invalidate the data in the second portion;

[0146] The controller is further configured to send second data to the processor;

[0147] The processor is further configured to receive second data.

[0148] In one possible implementation, the controller is further configured to send a second message to the processor, the second message being configured to indicate that the first data needs to be written to the first cache unit. The processor is further configured to receive the second message. The processor is configured to send the first message to the controller based on the second message.

[0149] In one possible implementation, the processor is further configured to send a third message to the controller. The controller is further configured to receive the third message. The controller is configured to, based on the third message, send a second message to the processor when detecting that the first data needs to be written into the first cache unit.

[0150] In one possible implementation, the first cache unit includes a third portion and a fourth portion. The processor is further configured to send a fourth message to the controller. The controller is further configured to receive the fourth message. The controller is configured to, upon detecting, based on the fourth message, that the first data needs to be written to the third portion, send a second message to the processor, the second message indicating that the first data needs to be written to the third portion.

[0151] In a possible implementation, the controller is further configured to write back the updated data in the second part to the first cache unit when detecting that the data in the second part is updated by the processor.

[0152] In a possible implementation, the first part is part or all of the second cache unit.

[0153] Illustratively, an embodiment of the present application provides a processor, which is used to implement the steps executed by the processor in the method embodiment shown in FIG4 .

[0154] Illustratively, an embodiment of the present application provides a cache system, which includes a controller, a first cache unit, and a second cache unit. The controller is used to implement the steps performed by the controller in the method embodiment shown in FIG. 4 .

[0155] Illustratively, an embodiment of the present application provides a computer-readable storage medium, in which at least one computer instruction is stored, and the at least one computer instruction is loaded and executed by a processor to enable the processor to implement the steps executed by the processor in the method embodiment shown in Figure 4.

[0156] In an exemplary embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores at least one computer instruction, and the at least one computer instruction is loaded and executed by a controller to enable the controller to implement the steps performed by the controller in the method embodiment shown in Figure 4.

[0157] Illustratively, an embodiment of the present application provides a computer program product, which includes computer instructions. The computer instructions are executed by a processor to enable the processor to implement the steps executed by the processor in the method embodiment shown in FIG. 4 .

[0158] In an exemplary embodiment, an embodiment of the present application provides a computer program product, which includes computer instructions. The computer instructions are executed by a controller to enable the controller to implement the steps executed by the controller in the method embodiment shown in Figure 4.

[0159] In an exemplary embodiment, an embodiment of the present application provides a chip, including a processor, for calling and executing instructions stored in a memory, so that a computer equipped with the chip executes the steps executed by the processor in the method embodiment shown in FIG. 4 above.

[0160] Illustratively, an embodiment of the present application provides another chip, comprising: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected through an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the computer equipped with the chip executes the steps executed by the processor in the method embodiment shown in FIG4 above.

[0161] In this application, the terms "first," "second," and the like are used to distinguish between identical or similar items with substantially the same purpose and function. It should be understood that "first," "second," and "nth" do not have a logical or temporal dependency, nor do they limit the quantity or order of execution. It should also be understood that although the following description uses the terms "first," "second," and the like to describe various elements, these elements should not be limited by these terms. These terms are simply used to distinguish one element from another.

[0162] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0163] In this application, the term "at least one" means one or more, and the term "plurality" means two or more. For example, a plurality of processors means two or more processors. The terms "system" and "network" are often used interchangeably herein.

[0164] It should be understood that the terminology used in the description of the various examples herein is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0165] It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the listed items. The term "and / or" describes an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this application generally indicates that the associated objects are in an "or" relationship.

[0166] It should also be understood that the terms “if” and “if” may be interpreted to mean “when” or “upon” or “in response to determining” or “in response to detecting.” Similarly, the phrases “if it is determined that ” or “if [stated condition or event] is detected” may be interpreted to mean “upon determining ” or “in response to determining ” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event],” depending on the context.

[0167] The above description is merely an embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for processing data, characterized in that, The method is applied to a processing system, which includes a controller, a first cache unit, a second cache unit, and at least one processor. The method includes: Sending a first message from the processor to the controller; Receiving the first message by the controller; Copying, by the controller according to the first message, first data in the first cache unit to a first part of the second cache unit to obtain second data. There is a record in a second part of the second cache unit other than the first part, and the record is used to invalidate the data in the second part; Sending the second data from the controller to the processor; Receiving the second data by the processor.

2. The method according to claim 1, wherein Before sending the first message from the processor to the controller, the method further includes: Sending a second message from the controller to the processor, and the second message is used to indicate that the first data needs to be written into the first cache unit; Receiving the second message by the processor; Sending the first message from the processor to the controller includes: Sending the first message from the processor to the controller according to the second message.

3. The method according to claim 2, wherein Before sending the second message from the controller to the processor, the method further includes: Sending a third message from the processor to the controller; Receiving the third message by the controller; Sending the second message from the controller to the processor includes: When the controller detects that the first data needs to be written into the first cache unit according to the third message, sending the second message to the processor.

4. The method according to claim 2, wherein The first cache unit includes a third part and a fourth part; Before sending the second message from the controller to the processor, the method further includes: Sending a fourth message from the processor to the controller; Receiving the fourth message by the controller; Sending the second message from the controller to the processor includes: When the controller detects that the first data needs to be written into the third part according to the fourth message, sending the second message to the processor, and the second message is used to indicate that the first data needs to be written into the third part.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: When the controller detects that the data in the second part is updated by the processor, writing the updated data in the second part back to the first cache unit.

6. The method according to any one of claims 1-5, characterized in that, The first part is part or all of the second cache unit.

7. A processing system, characterized in that, The processing system includes a controller, a first cache unit, a second cache unit, and at least one processor; The processor is configured to send a first message to the controller; The controller is configured to receive the first message; The controller is further configured to copy first data in the first cache unit to a first part of the second cache unit according to the first message, to obtain second data, where there is a record in a second part of the second cache unit other than the first part, and the record is used to invalidate data in the second part; The controller is further configured to send the second data to the processor; The processor is further configured to receive the second data.

8. The processing system according to claim 7, wherein The controller is further configured to send a second message to the processor, where the second message is used to indicate that the first data needs to be written into the first cache unit; The processor is further configured to receive the second message; The processor is configured to send the first message to the controller according to the second message.

9. The processing system according to claim 8, wherein The processor is further configured to send a third message to the controller; The controller is further configured to receive the third message; The controller is configured to send the second message to the processor according to the third message when it is detected that the first data needs to be written into the first cache unit.

10. The processing system according to claim 8, wherein The first cache unit includes a third part and a fourth part; The processor is further configured to send a fourth message to the controller; The controller is further configured to receive the fourth message; The controller is configured to send the second message to the processor according to the fourth message when it is detected that the first data needs to be written into the third part, where the second message is used to indicate that the first data needs to be written into the third part.

11. The processing system according to any one of claims 7-10, wherein The controller is further configured to write back updated data in the second part to the first cache unit when it is detected that the data in the second part is updated by the processor.

12. The processing system according to any one of claims 7-11, characterized in that, The first part is part or all of the second cache unit.

13. A processor, characterized in that, The processor is configured to implement the steps executed by the processor in the method for processing data according to any one of claims 1-6.

14. A cache system, characterized in that, The cache system includes a controller, a first cache unit, and a second cache unit, and the controller is configured to implement the steps executed by the controller in the method for processing data according to any one of claims 1-6.

15. A computer-readable storage medium, characterized in that, At least one computer instruction is stored in the computer-readable storage medium, and the at least one computer instruction is loaded and executed by a processor, so that the processor implements the steps executed by the processor in the method for processing data according to any one of claims 1-6.

16. A computer-readable storage medium, characterized in that, At least one computer instruction is stored in the computer-readable storage medium, and the at least one computer instruction is loaded and executed by a controller, so that the controller implements the steps executed by the controller in the method for processing data according to any one of claims 1-6.

17. A computer program product, characterized in that, The computer program product includes computer instructions, and the computer instructions are executed by a processor, so that the processor implements the steps executed by the processor in the method for processing data according to any one of claims 1-6.

18. A computer program product, characterized in that, The computer program product includes computer instructions that are executed by a controller to cause the controller to implement the steps executed by the controller in the method for processing data according to any one of claims 1-6.

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