Semiconductor device

Abstract

Provided is a novel semiconductor device. The semiconductor device comprises a first transistor, a second transistor, a driving transistor, and a light-emitting element, wherein one of the source and drain of the first transistor is connected to the gate of the driving transistor, which is a holding node for a video signal, and the other of the source and drain of the first transistor is connected to one of the source and drain of the second transistor and one electrode of a capacitive element. The first transistor and the second transistor are preferably OS transistors.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving methods or manufacturing methods thereof.

[0003] In recent years, research and development of self-luminous display devices using light-emitting elements such as light-emitting diodes (LEDs) as pixels has been actively conducted. In particular, active matrix display devices using organic electroluminescence (EL) elements as light-emitting elements have attracted attention. Generally, a pixel of an active matrix display device using light-emitting elements includes a light-emitting element and a circuit (also referred to as a "pixel circuit") that controls the light emission brightness of the light-emitting element. The pixel circuit also includes a transistor (drive transistor) that controls the amount of current supplied to the light-emitting element in accordance with a video signal.

[0004] The luminance of a light-emitting element is determined by the magnitude of the drain current of the drive transistor. Therefore, if there is variation in the electrical characteristics of the drive transistors among the pixels that make up the screen of a display device, even if the same video signal is supplied to the pixels, the luminance of each pixel will differ. In particular, variation in threshold voltage (also referred to as "Vth") has a significant impact on the degradation of the display quality of the display device.

[0005] In order to reduce the variation in the threshold voltage of the drive transistor, pixel circuits with various configurations have been proposed. For example, Patent Documents 1 and 2 disclose pixel circuits capable of correcting the threshold voltage of the drive transistor.

[0006] Furthermore, Patent Document 3 discloses a display device that reduces the refresh frequency when displaying a still image of a video signal written in a pixel circuit, thereby realizing power saving.

[0007] JP 2012-14136 A JP 2020-112795 A JP 2011-141524 A

[0008] In recent years, there has been a demand for further improvements in display quality and power savings in display devices. In particular, because the off-state current of transistors constituting pixel circuits tends to increase in high-temperature environments, there is a demand for improvements in the ability to retain video signals written to pixel circuits.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device in which the influence of variation in characteristics is reduced, or to provide a semiconductor device with low power consumption, or to provide a semiconductor device with high display quality, or to provide a semiconductor device with high reliability, or to provide a novel semiconductor device.

[0010] Note that the description of the above-mentioned problems does not preclude the existence of other problems. Those skilled in the art can naturally derive other problems from the description in the specification, drawings, claims, etc., and other problems can be extracted from the description in the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problems and other problems).

[0011] (1) One embodiment of the present invention includes first to ninth transistors, first to third capacitors, and a light-emitting element, wherein each of the first to ninth transistors has a gate, a first terminal, and a second terminal; each of the first to third capacitors has a first terminal and a second terminal; the light-emitting element has a first terminal and a second terminal; the first terminal of the first transistor is electrically connected to the first terminal of the first capacitor; the second terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first terminal of the third transistor; the second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the seventh transistor; the second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor and the first terminal of the light-emitting element; the terminal is electrically connected to the second terminal of the seventh transistor and the first terminal of the second capacitance element, the second terminal of the sixth transistor is electrically connected to the gate of the third transistor, the second terminal of the first capacitance element and the first terminal of the eighth transistor, the second terminal of the eighth transistor is electrically connected to the first terminal of the ninth transistor and the first terminal of the third capacitance element, the gate of the first transistor is electrically connected to the gate of the fourth transistor, the gate of the sixth transistor is electrically connected to the gate of the seventh transistor, the gate of the eighth transistor is electrically connected to the gate of the ninth transistor, the second terminal of the second capacitance element is electrically connected to the second terminal of the third capacitance element, and the second terminal of the fifth transistor is electrically connected to the second terminal of the ninth transistor.

[0012] Also, in (1), for example, the first terminal of the first transistor and the first terminal of the first capacitance element are electrically connected to the first wiring, the gate of the first transistor and the gate of the fourth transistor are electrically connected to the second wiring, the cathode of the light-emitting element is electrically connected to the third wiring, the second terminal of the second transistor is electrically connected to the fourth wiring, the gate of the second transistor is electrically connected to the fifth wiring, the gate of the sixth transistor and the gate of the seventh transistor are electrically connected to the sixth wiring, the gate of the eighth transistor and the gate of the ninth transistor are electrically connected to the seventh wiring, the second terminal of the second capacitance element and the second terminal of the third capacitance element are electrically connected to the eighth wiring, and the gate of the fifth transistor is electrically connected to the ninth wiring.

[0013] In (1), each of the first to fifth transistors preferably contains silicon in a semiconductor layer in which a channel is formed, and each of the sixth to ninth transistors preferably contains an oxide semiconductor in a semiconductor layer in which a channel is formed.

[0014] In (1), it is preferable to use p-type transistors as the first to fifth transistors, and n-type transistors as the sixth to ninth transistors.

[0015] (2) Another embodiment of the present invention is a semiconductor device in which a first terminal of the first transistor and a first terminal of the first capacitor are electrically connected to a first wiring, a gate of the first transistor and a gate of the fourth transistor are electrically connected to a second wiring, a second terminal of the light-emitting element is electrically connected to a third wiring, a second terminal of the second transistor is electrically connected to a fourth wiring, a gate of the second transistor is electrically connected to a fifth wiring, a gate of the sixth transistor and a gate of the seventh transistor are electrically connected to a sixth wiring, a gate of the eighth transistor and a gate of the ninth transistor are electrically connected to a seventh wiring, a second terminal of the second capacitor and a second terminal of the third capacitor are electrically connected to an eighth wiring, and a gate of the fifth transistor is electrically connected to a ninth wiring.

[0016] In (2), the first transistor preferably includes silicon in a semiconductor layer in which a channel is formed, and the second and third transistors preferably include an oxide semiconductor in a semiconductor layer in which a channel is formed.

[0017] In (2), it is preferable to use a p-type transistor as the first transistor, and to use n-type transistors as the second and third transistors.

[0018] In (1) and (2), the first terminal of the light-emitting element functions as, for example, an anode, and the second terminal of the light-emitting element functions as, for example, a cathode.

[0019] According to one embodiment of the present invention, a semiconductor device in which the influence of variations in characteristics is reduced can be provided, or a semiconductor device with low power consumption can be provided, or a semiconductor device with high display quality can be provided, or a semiconductor device with high reliability can be provided, or a novel semiconductor device can be provided.

[0020] Note that the description of the above effects does not preclude the existence of other effects. Those skilled in the art can naturally derive the other effects from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of these effects (the above effects and other effects).

[0021] FIG. 1 is a diagram illustrating an example of a circuit configuration of a semiconductor device. FIG. 2 is a diagram illustrating an example of a circuit configuration of a semiconductor device. FIG. 3 is a diagram illustrating an example of a circuit configuration of a semiconductor device. FIG. 4 is a diagram illustrating an example of a circuit configuration of a semiconductor device. FIGS. 5A and 5B are diagrams illustrating circuit symbols of transistors. FIG. 6 is a diagram illustrating an example of a circuit configuration of a semiconductor device. FIG. 7 is a diagram illustrating an example of a circuit configuration of a semiconductor device. FIG. 8 is a diagram illustrating an example of a circuit configuration of a semiconductor device. FIGS. 9A and 9B are diagrams illustrating a circuit model used in a simulation. FIG. 10 is a diagram illustrating simulation results. FIG. 11 is a diagram illustrating a circuit model used in a simulation. FIGS. 12A and 12B are diagrams illustrating simulation results. FIG. 13 is a timing chart illustrating an example of an operation of the semiconductor device. FIG. 14 is a diagram illustrating an example of an operation of the semiconductor device. FIG. 15A is a timing chart illustrating an example of an operation of the semiconductor device. FIG. 15B is a diagram illustrating an example of an operation of the semiconductor device. FIG. 16 is a diagram illustrating an example of an operation of the semiconductor device. FIG. 17 is a diagram illustrating an example of an operation of the semiconductor device. FIG. 18 is a diagram illustrating an example of an operation of the semiconductor device. FIG. 19 is a diagram illustrating an example of an operation of the semiconductor device. FIG. 20 is a diagram illustrating an example of operation of a semiconductor device. FIG. 21 is a diagram illustrating an example of operation of a semiconductor device. FIG. 22 is a diagram illustrating an example of operation of a semiconductor device. FIGS. 23A1 to 23A7 and 23B1 to 23B6 are diagrams illustrating electrical connections. FIGS. 24A to 24C are diagrams illustrating the structure of a transistor. FIGS. 25A to 25C are diagrams illustrating the structure of a transistor. FIGS. 26A and 26B are diagrams illustrating the structure of a transistor. FIGS. 27A and 27B are diagrams illustrating the structure of a transistor. FIGS. 28A to 28C are diagrams illustrating the structure of a transistor. FIGS. 29A to 29C are diagrams illustrating the structure of a transistor. FIGS. 30A to 30E are diagrams illustrating an example of a structure of a transistor. FIGS. 31A and 31B are diagrams illustrating an example of a structure of a transistor. FIGS. 32A to 32E are diagrams illustrating an example of a structure of a transistor. FIG. 33 is a diagram illustrating an example of a structure of a transistor.34A to 34E are diagrams illustrating an example of the configuration of a transistor. FIGS. 35A to 35D are cross-sectional views illustrating a method for forming a metal oxide film. FIGS. 36A to 36D are cross-sectional views illustrating a method for forming a metal oxide film. FIG. 37 is a diagram illustrating an example of the planar configuration of a semiconductor device. FIG. 38 is a diagram illustrating an example of the planar configuration of a semiconductor device. FIG. 39 is a diagram illustrating an example of the planar configuration of a semiconductor device. FIG. 40 is a diagram illustrating an example of the cross-sectional configuration of a semiconductor device. FIGS. 41A and 41B are diagrams illustrating an example of the cross-sectional configuration of a semiconductor device. FIG. 42A is a perspective view showing an example of the configuration of a display device. FIGS. 42B to 42F are plan views showing an example of a pixel array. FIGS. 43A to 43D are diagrams illustrating an example of the configuration of a light-emitting element. FIGS. 44A to 44D are diagrams illustrating an example of the configuration of a light-emitting element. FIGS. 45A to 45D are diagrams illustrating an example of the configuration of a light-emitting element. FIGS. 46A to 46C are diagrams illustrating an example of the configuration of a light-emitting element. FIG. 47 is a block diagram illustrating an example of the configuration of a display device. Figs. 48A and 48B are block diagrams showing an example of the configuration of a display device. Figs. 49A and 49B are block diagrams showing an example of the configuration of a display device. Figs. 50A to 50C and 50E are circuit diagrams showing an example of the configuration of a semiconductor device. Fig. 50D is a timing chart showing an example of the operation of the semiconductor device. Fig. 51 is a cross-sectional view showing an example of the configuration of a display device. Figs. 52A to 52D are diagrams showing an example of an electronic device. Figs. 53A to 53F are diagrams showing an example of an electronic device. Figs. 54A to 54G are diagrams showing an example of an electronic device.

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0023] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0024] In the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0025] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, plan views, etc.

[0026] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components or the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0027] In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0028] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0029] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0030] In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, depending on the situation or circumstances, terms such as "film" and "layer" may be interchanged with other terms without using terms such as "film" and "layer." For example, the term "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, the term "conductor" may be interchanged with the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" may be interchanged with the term "insulator." Or, the term "insulator" may be interchanged with the term "insulating layer" or "insulating film."

[0031] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" and "conductive layer" depending on the situation.

[0032] In this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Furthermore, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true, and terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Similarly, the reverse is also true, and terms such as "signal" may be changed to the term "potential."

[0033] In this specification, the term "source" refers to a source region, a source electrode, or a source wiring. The source region refers to one of two regions in a semiconductor layer that are adjacent to a channel formation region. The source electrode refers to a conductive layer that includes a portion connected to the source region.

[0034] In this specification, the term "drain" refers to a drain region, a drain electrode, or a drain wiring. The drain region refers to the other of two regions of a semiconductor layer that are adjacent to a channel formation region. The drain electrode refers to a conductive layer that includes a portion connected to the drain region.

[0035] In this specification, the term "gate" refers to a gate electrode or a gate wiring. The gate electrode is an electrode that overlaps with a semiconductor layer of a transistor and has a function of controlling the resistance between the source and drain of the transistor depending on a supplied voltage.

[0036] In this specification, one of the source or the drain of a transistor may be referred to as a "first terminal", and the other of the source or the drain of a transistor may be referred to as a "second terminal".

[0037] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -15° or more and 15° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0038] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged. In this specification and elsewhere, unless otherwise specified, voltage and potential can be interchanged.

[0039] In this specification and the like, a high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS. A low power supply potential VSS (hereinafter also simply referred to as "VSS") refers to a power supply potential that is lower than a high power supply potential VDD. A ground potential GND (hereinafter also simply referred to as "GND") can also be used as VDD or VSS. For example, when VDD is GND, VSS is a lower potential than GND, and when VSS is GND, VDD is a higher potential than GND.

[0040] In this specification, the "on state" of a transistor means that the source and drain of the transistor are in a conductive state (a state in which electricity can pass), and the "off state" of a transistor means that the source and drain of the transistor are in a non-conductive state (a state that can be considered as cut off).

[0041] In this specification, the term "on-state current" refers to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" refers to a current that flows between a source and a drain when a transistor is off.

[0042] In this specification and the like, potential H is a potential that turns on an n-channel field effect transistor (also referred to as an "n-type transistor") and turns off a p-channel field effect transistor (also referred to as a "p-type transistor"). Potential L is a potential that turns off an n-type transistor and turns on a p-type transistor. Therefore, potential H is a potential higher than potential L. Potential H may be equal to VDD. Potential L may be equal to VSS. Unless otherwise specified, the transistors described in this specification are enhancement-type (normally-off) transistors.

[0043] In addition, in drawings and the like, to clearly show the potential of wirings, electrodes, etc., "H" indicating a potential H or "L" indicating a potential L may be added adjacent to the wirings, electrodes, etc. Furthermore, "H" or "L" may be enclosed in a box next to wirings, electrodes, etc. where a potential change has occurred. Furthermore, when a transistor is in an off state, an "x" symbol may be added over the transistor. Furthermore, an arrow may be added to indicate the direction of current flow.

[0044] In this specification, when referring to counting values ​​and measurement values, terms such as "identical," "same," "equal," or "uniform" (including synonyms thereof) are used, this includes an error of plus or minus 10%, unless otherwise specified.

[0045] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, or Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0046] Generally, a "capacitance" has a configuration in which two electrodes face each other with an insulator (dielectric) interposed therebetween. In this specification, etc., the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., the term "capacitance element" includes a configuration in which two electrodes face each other with an insulator interposed therebetween, a configuration in which two wires face each other with an insulator interposed therebetween, or a configuration in which two wires are arranged with an insulator interposed therebetween. Note that in this specification, one of the two electrodes may be referred to as a first electrode or a first terminal, and the other may be referred to as a second electrode or a second terminal.

[0047] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m, n]” may be added to the symbol.

[0048] In this specification, "connection" includes, as an example, "electrical connection." When the term "electrical connection" is used to define the connection relationship between circuit elements as a physical entity, "electrical connection" includes, as examples, "direct connection" and "indirect connection." "A and B are directly connected" refers to a case where A and B are connected without a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a case where A and B are connected via one or more circuit elements.

[0049] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0050] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 23A1 and 23A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases where multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 23A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0051] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 23A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 23A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0052] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 23A6 and 23A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 23A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 23A6 and 23A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0053] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0054] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 23B1, 23B2, and 23B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 23B4 and 23B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 23B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0055] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0056] Embodiment 1 A semiconductor device 10A according to one embodiment of the present invention will be described with reference to the drawings. The semiconductor device 10A can be used for a pixel of a display device.

[0057] 1 shows a circuit configuration example of a semiconductor device 10A. The semiconductor device 10A includes transistors M1 to M5, a transistor M6[1], a transistor M6[2], a transistor M7[1], a transistor M7[2], capacitors C1 to C3, and a light-emitting element 61.

[0058] One of the source or drain of transistor M1 is connected to one electrode of capacitor C1, and the other of the source or drain of transistor M1 is connected to one of the source or drain of transistor M2 and one of the source or drain of transistor M3. The other of the source or drain of transistor M3 is connected to one of the source or drain of transistor M4 and one of the source or drain of transistor M6[2]. The other of the source or drain of transistor M4 is connected to one of the source or drain of transistor M5 and a first terminal of light-emitting element 61. In semiconductor device 10A, the first terminal of light-emitting element 61 functions as an anode, and the second terminal of light-emitting element 61 functions as a cathode.

[0059] The source or drain of transistor M6[1] is connected to the other of the source or drain of transistor M6[2] and one electrode of capacitor C2. The source or drain of transistor M6[1] is connected to the gate of transistor M3, the other electrode of the first capacitor, and the source or drain of transistor M7[1]. The source or drain of transistor M7[1] is connected to the source or drain of transistor M7[2] and one electrode of capacitor C3.

[0060] The gate of transistor M1 is connected to the gate of transistor M4. The gate of transistor M6[1] is connected to the gate of transistor M6[2]. The gate of transistor M7[1] is connected to the gate of transistor M7[2]. The other electrode of capacitor C2 is connected to the other electrode of capacitor C3. The other of the source and drain of transistor M5 is connected to the other of the source and drain of transistor M7[2] and the wiring Vint.

[0061] The first terminal of the transistor M1 and one electrode of the capacitor C1 are connected to a wiring ELVDD. The gates of the transistors M1 and M4 are connected to a wiring EM. The cathode of the light-emitting element is connected to a wiring ELVSS. For example, VDD or a potential H is supplied to the wiring ELVDD, and VSS or a potential L is supplied to the wiring ELVSS.

[0062] The other of the source and drain of transistor M2 is connected to wiring DL. The gate of transistor M2 is connected to wiring GW. The gates of transistor M6[1] and transistor M6[2] are connected to wiring GC. The gates of transistor M7[1] and transistor M7[2] are connected to wiring GI. The other electrodes of capacitor C2 and capacitor C3 are connected to wiring COM. The other electrodes of capacitor C2 and capacitor C3 can be connected to wiring ELVDD, wiring ELVSS, or wiring Vint without being connected to wiring COM. The gate of transistor M5 is connected to wiring GB.

[0063] In addition, in the semiconductor device 10A, the other of the source or drain of the transistor M6[1], the gate of the transistor M3, the other electrode of the first capacitance element, and one of the source or drain of the transistor M7[1] are connected, and the region where these are always at the same potential during circuit operation is referred to as node ND[1].

[0064] In addition, in the semiconductor device 10A, one of the source or drain of the transistor M6[1], the other of the source or drain of the transistor M6[2], and one of the electrodes of the capacitive element C2 are connected, and the region where these are always at the same potential during circuit operation is referred to as node ND[2]a.

[0065] In addition, in the semiconductor device 10A, the other electrode of the source or drain of the transistor M7[1], one electrode of the source or drain of the transistor M7[2], and one electrode of the capacitance element C3 are connected, and the region where these are always at the same potential during circuit operation is referred to as node ND[2]b.

[0066] In addition, in the semiconductor device 10A, the other of the source or drain of the transistor M1, one of the source or drain of the transistor M2, and one of the source or drain of the transistor M3 are connected, and a region where these are always at the same potential during circuit operation is referred to as node ND[3].

[0067] In addition, in the semiconductor device 10A, the other of the source or drain of transistor M3, one of the source or drain of transistor M4, and one of the source or drain of transistor M6[2] are connected, and the region where these are always at the same potential during circuit operation is referred to as node ND[4].

[0068] Some or all of the transistors included in the semiconductor device 10A may have back gates. Fig. 2 shows an example of a circuit configuration in which transistors having back gates are used as the transistors included in the semiconductor device 10A. Fig. 2 shows an example in which, in the semiconductor device 10A, the transistors M1 to M5, the transistor M6[1], the transistor M6[2], the transistor M7[1], and the transistor M7[2] each have a back gate, and the back gate is connected to the gate.

[0069] The gate and back gate of a transistor are arranged to sandwich a channel formation region of a semiconductor layer. Both the gate and the back gate are formed of a conductive layer or a semiconductor layer with low resistivity. The back gate can function in the same way as the gate. When the gate is used to control the on and off states of a transistor, the potential of the back gate can be set to the same potential as the gate.

[0070] For example, when turning on a transistor, supplying a potential that turns on the transistor to both the gate and the back gate can increase the on-state current compared to supplying a potential to only one of them. As shown in Figure 2, by connecting the gate and the back gate, it is possible to keep the gate and the back gate at the same potential. In addition, by controlling the back gate potential independently of the gate, the threshold voltage of the transistor can be adjusted.

[0071] Furthermore, a fixed potential such as GND can be supplied to the back gate. Since the gate and the back gate are formed of a conductive layer or the like, sandwiching the channel formation region of the semiconductor layer between the gate and the back gate makes it difficult for an electric field generated outside the transistor to act on the channel formation region (also referred to as an "electric field shielding effect"). Therefore, providing a back gate in a transistor stabilizes the operation of the transistor. Furthermore, providing a back gate in a transistor reduces variations in characteristics among multiple transistors. Providing a back gate in a transistor can improve the reliability of the transistor. Therefore, the reliability of a semiconductor device including the transistor can be improved. Note that the electric field shielding effect can be obtained even when one or both of the gate and the back gate are electrically floating (also referred to as a "floating state"), but the effect can be enhanced by supplying a potential to the gate and the back gate.

[0072] Furthermore, when a channel formation region of a transistor is irradiated with light, the electrical characteristics of the transistor may fluctuate. Furthermore, when the channel formation region of the transistor is irradiated with light while a voltage is applied to the transistor, the electrical characteristics of the transistor may deteriorate. That is, the reliability of the transistor may decrease. By using a light-blocking conductive material for both the gate and the back gate, deterioration of the electrical characteristics of the transistor can be suppressed and the reliability can be improved.

[0073] N-type transistors can be used for some or all of the transistors included in the semiconductor device 10A. Furthermore, p-type transistors can be used for some or all of the transistors included in the semiconductor device 10A. In FIG. 1 and other figures, transistors M1 to M5 included in the semiconductor device 10A are shown as p-type transistors. Furthermore, transistors M6[1], M6[2], M7[1], and M7[2] are shown as n-type transistors. N-type transistors have higher mobility than p-type transistors, and therefore the operating speed of the semiconductor device 10A can be increased. On the other hand, p-type transistors are easier to realize as normally-off transistors than n-type transistors, and circuit design is relatively easy.

[0074] For example, as shown in Fig. 3, all the transistors included in the semiconductor device 10A can be n-type transistors. When an n-type transistor is used for the transistor M3, the first terminal of the light-emitting element 61 is connected to the wiring ELVDD, and the second terminal of the light-emitting element 61 is connected to the other of the source or drain of the transistor M4 and one of the source or drain of the transistor M5. A potential H is supplied to the wiring Vint.

[0075] In the semiconductor device 10A, the transistor M3 functions as a driving transistor. The transistor M3 determines the amount of current flowing through the light-emitting element 61. The transistors M1, M2, M4, M5, M6[1], M6[2], M7[1], and M7[2] function as switches. Therefore, as shown in FIG. 4 , the transistor M1 can be replaced with a switch SW1, the transistor M2 with a switch SW2, the transistor M4 with a switch SW4, the transistor M5 with a switch SW5, the transistor M6[1] with a switch SW6[1], the transistor M6[2] with a switch SW6[2], the transistor M7[1] with a switch SW7[1], and the transistor M7[2] with a switch SW7[2]. In FIG. 4 , one of the source and drain of the transistor corresponds to a first terminal of the switch, and the other of the source and drain of the transistor corresponds to a second terminal of the switch.

[0076] It is also possible to use mechanical switches as switches SW1, SW2, SW4, SW5, SW6[1], SW6[2], SW7[1], and SW7[2]. An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. The switch has a mechanically movable electrode, and the movement of the electrode selects a conductive state or a non-conductive state.

[0077] Furthermore, the semiconductor device 10A according to one embodiment of the present invention can use transistors with various structures. For example, transistors with various structures such as planar type, FIN type, top gate type, and bottom gate type can be used. Furthermore, as the transistor according to one embodiment of the present invention, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used.

[0078] When an n-channel transistor is used as a transistor included in the semiconductor device 10A, an OS transistor (a transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed) can be used as the transistor. Since an oxide semiconductor has a band gap of 2 eV or more, the off-state current of the OS transistor is extremely small. Specifically, the off-state current of the OS transistor per 1 μm of channel width at room temperature is 1 pA (1×10 −１２ A) Below, 1aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less or 1yA (1 x 10 −２４ A) It can be as follows:

[0079] When an OS transistor is used as a transistor included in the semiconductor device 10A, charge written to each node can be retained for a long period of time. Therefore, for example, when a display device including the semiconductor device 10A displays a still image, degradation in display quality can be suppressed even if the refresh rate is reduced. Reducing the refresh rate can reduce the power consumption of the display device. Furthermore, for example, when a display device including the semiconductor device 10A displays a still image, the image can be continuously displayed even if the operation of the peripheral driver circuit is stopped. Such a driving method of stopping the operation of the peripheral driver circuit while displaying a still image is also called "idling stop driving." By performing idling stop driving, the power consumption of the display device can be further reduced.

[0080] In particular, by using OS transistors for the transistors M6[1] and M7[1], the potential written to the node ND[1] can be held for a long period of time. Furthermore, by using OS transistors for the transistors M6[2] and M7[2], the potential written to the node ND[1] can be held for a long period of time. Furthermore, by connecting one electrode of the capacitor C2 between the transistors M6[1] and M6[2] and connecting one electrode of the capacitor C3 between the transistors M7[1] and M7[2], the potential written to the node ND[1] can be held for a long period of time.

[0081] The node ND[1] holds a potential corresponding to a video signal. Therefore, the node ND[1] is also referred to as a "holding node." The drain current of the transistor M3 is determined by the potential of the node ND[1]. The light emission brightness of the light-emitting element 61 is determined according to the magnitude of the drain current of the transistor M3. By suppressing the potential fluctuation of the node ND[1], the display quality of the display device can be improved.

[0082] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environmental temperature range of room temperature to 200° C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. A semiconductor device including an OS transistor has stable operation and high reliability even in a high-temperature environment.

[0083] Furthermore, transistors using silicon in a semiconductor layer in which a channel is formed (also referred to as "Si transistors") can be used as the transistors M1 to M5. In particular, Si transistors using crystalline silicon in a semiconductor layer have a higher operating speed than OS transistors. By configuring the semiconductor device 10A using OS transistors and Si transistors, the semiconductor device 10A can have a high video signal retention capability and a high operating speed.

[0084] The transistors constituting the semiconductor device 10A can be single-gate transistors having one gate between the source and drain. However, double-gate transistors can also be used. Figure 5A shows the circuit symbol for a double-gate transistor 180A.

[0085] The transistor 180A has a configuration in which a transistor Tr1 and a transistor Tr2 are connected in series. Fig. 5A shows a state in which one of the source or drain of the transistor Tr1 is connected to a terminal S, the other of the source or drain of the transistor Tr1 is connected to one of the source or drain of the transistor Tr2, and the other of the source or drain of the transistor Tr2 is connected to a terminal D. Fig. 5A also shows a state in which the gates of the transistors Tr1 and Tr2 are connected to each other and also to a terminal G.

[0086] The transistor 180A shown in FIG. 5A has a function of switching conduction or non-conduction between the terminal S and the terminal D by changing the potential of the terminal G. Therefore, the transistor 180A, which is a double-gate transistor, has a transistor Tr1 and a transistor Tr2 connected in series and functions as a single transistor. That is, in FIG. 5A , one of the source or the drain of the transistor 180A is connected to the terminal S, the other of the source or the drain is connected to the terminal D, and the gate is connected to the terminal G. Furthermore, since the double-gate transistor has the transistor Tr1 and the transistor Tr2 connected in series, the withstand voltage between the terminal S and the terminal D is high, and therefore the double-gate transistor has high reliability.

[0087] The transistors constituting the semiconductor device 10A may be triple-gate transistors. An example of a circuit symbol for a triple-gate transistor 180B is shown in FIG.

[0088] The transistor 180B has a configuration in which a transistor Tr1, a transistor Tr2, and a transistor Tr3 are connected in series. Fig. 5B shows a state in which one of the source or drain of the transistor Tr1 is connected to a terminal S, the other of the source or drain of the transistor Tr1 is connected to one of the source or drain of the transistor Tr2, the other of the source or drain of the transistor Tr2 is connected to one of the source or drain of the transistor Tr3, and the other of the source or drain of the transistor Tr3 is connected to a terminal D. Fig. 5B also shows a state in which the gates of the transistors Tr1, Tr2, and Tr3 are connected to each other and to a terminal G.

[0089] The transistor 180B shown in FIG. 5B has a function of switching conduction or non-conduction between the terminal S and the terminal D by changing the potential of the terminal G. Therefore, the transistor 180B, which is a triple-gate transistor, has transistors Tr1, Tr2, and Tr3 connected in series and functions as a single transistor. That is, in FIG. 5B, one of the source or the drain of the transistor 180B is connected to the terminal S, the other of the source or the drain is connected to the terminal D, and the gate is connected to the terminal G. Furthermore, the triple-gate transistor has a higher withstand voltage between the terminal S and the terminal D than the double-gate transistor, and therefore has higher reliability.

[0090] 5A and 5B, the transistors Tr1 to Tr3 are shown as n-type transistors, but the same effect can be obtained with p-type transistors.

[0091] A transistor having multiple gates and connected to each other, such as the transistor 180A and the transistor 180B, may be referred to as a "multi-gate transistor" or a "multi-gate transistor."

[0092] A multi-gate transistor is equivalent to a transistor with a long channel length. Therefore, the multi-gate transistor has better electrical characteristics in a saturation region (also called "saturation characteristics") than a single-gate transistor. Therefore, a multi-gate transistor can be used to improve the saturation characteristics of a transistor.

[0093] Specifically, by using a multi-gate transistor for the transistor M3, it is possible to improve the saturation characteristics of the transistor M3. The improved saturation characteristics of the transistor M3 improve the reproducibility of the light-emitting luminance of the light-emitting element 61 in response to a video signal written to the semiconductor device 10A. This improves the display quality of a display device using the semiconductor device 10A. Furthermore, a multi-gate transistor can reduce the off-current compared to a single-gate transistor.

[0094] Furthermore, for transistors functioning as switches, improving their operating speed (switching speed between on and off states, signal transfer speed, etc.) is more important than improving their saturation characteristics. By shortening the channel length L of a transistor functioning as a switch, the operating speed (switching speed between on and off states, signal transfer speed, etc.) can be increased. Therefore, by making the channel lengths L of transistors M1, M2, M4, M5, M6[1], M6[2], M7[1], and M7[2] shorter than the channel length L of transistor M3, the operating speed of semiconductor device 10A and the reproducibility of the light emission luminance of light-emitting element 61 in response to a video signal can be improved.

[0095] The light-emitting element 61 may be a display element such as an EL element (an EL element including organic and inorganic materials, an organic EL element, or an inorganic EL element), an LED (a white LED, a red LED, a green LED, a blue LED, or the like), a micro LED, a QLED (Quantum-dot Light Emitting Diode), or an electron-emitting element.

[0096] <Variation 1> Figure 6 shows an example of the circuit configuration of a semiconductor device 10B, which is a variation of the semiconductor device 10A shown in Figure 1. The semiconductor device 10B shown in Figure 6 differs from the semiconductor device 10A shown in Figure 1 in that an n-type transistor is used as the transistor M5 and no wiring GB is provided. In the semiconductor device 10B, the gate of the transistor M5 is connected to the wiring GI. Therefore, the gates of the transistor M5, the transistor M7[1], and the transistor M7[2] are connected to each other. By not providing the wiring GB, the semiconductor device 10B can occupy a smaller area than the semiconductor device 10A. Furthermore, the resolution and / or definition of a display device using the semiconductor device 10B as a display unit can be improved.

[0097] <Variation 2> FIG. 7 shows an example of a circuit configuration of a semiconductor device 10C, which is a variation of the semiconductor device 10B shown in FIG. 6 . The semiconductor device 10C is also a variation of the semiconductor device 10A. The semiconductor device 10C shown in FIG. 7 differs from the semiconductor device 10B shown in FIG. 6 in that an n-type transistor is used as the transistor M2 and no wiring GW is provided. In the semiconductor device 10C, the gate of the transistor M2 is connected to a wiring GC. Therefore, the gates of the transistor M2, the transistor M6[1], and the transistor M6[2] are connected to each other. By not providing the wiring GW, the semiconductor device 10C can occupy a smaller area than the semiconductor device 10B. Furthermore, the resolution and / or definition of a display device using the semiconductor device 10C as a display unit can be improved.

[0098] <Confirmation of Effects by Simulation> Next, the effects of providing the semiconductor device 10A with the transistor M6[2], the transistor M7[2], the capacitor C2, and the capacitor C3 will be described. As described above, an OS transistor has an extremely low off-state current. For example, as in the semiconductor device 10X shown in FIG. 8, by using OS transistors as the transistors M6[1] and M7[1], it is possible to omit the transistors M6[2], M7[2], the capacitors C2, and the capacitor C3.

[0099] On the other hand, in the semiconductor device 10A of one embodiment of the present invention, the transistor M6[2], the transistor M7[2], the capacitor C2, and the capacitor C3 are provided, which can further increase the retention capability of the node ND[1]. Therefore, the semiconductor device 10A of one embodiment of the present invention has high reliability.

[0100] The retention characteristics of the node ND[1] in the semiconductor device 10A were confirmed using simulation software, such as SPICE (Simulation Program with Integrated Circuit Emphasis).

[0101] First, we confirmed the retention characteristics when there is one transistor between node ND[1] and node ND[4] and when two transistors are connected in series, and when there is one transistor between node ND[1] and wiring Vint and when two transistors are connected in series.

[0102] 9A shows a circuit diagram of a circuit model 901 used in the simulation. The circuit model 901 includes a transistor Tr1 and a capacitor Cs1. In the circuit model 901, one of the source and drain of the transistor Tr1 is connected to one electrode of the capacitor Cs1, and the other of the source and drain is connected to a terminal IN. The gate of the transistor Tr1 is connected to a terminal G.

[0103] 9B shows a circuit diagram of a circuit model 902 used in the simulation. The circuit model 902 has a transistor Tr1, a transistor Tr2, and a capacitance element Cs1. In the circuit model 902, one of the source or drain of the transistor Tr1 is connected to one electrode of the capacitance element Cs1, and the other of the source or drain is connected to one of the source or drain of the transistor Tr2. The other of the source or drain of the transistor Tr2 is connected to a terminal IN. The gates of the transistors Tr1 and Tr2 are connected to each other and to a terminal G.

[0104] In each of the circuit models 901 and 902, a region where one of the source or drain of the transistor Tr1 and one of the electrodes of the capacitor Cs1 are connected and where both are always at the same potential is called a node FN1. In both the circuit model 901 and the circuit model 902, data written from the terminal IN is held in the node FN1.

[0105] Note that the transistor Tr1 corresponds to the transistor M6[1] or the transistor M7[1] of the semiconductor device 10A, the transistor Tr2 corresponds to the transistor M6[2] or the transistor M7[2] of the semiconductor device 10A, and the capacitor Cs1 corresponds to the capacitor C1 of the semiconductor device 10A. The node FN1 corresponds to the node ND[1] of the semiconductor device 10A. The terminal G corresponds to the wiring GC or the wiring GI, and the terminal IN corresponds to the node ND[4] or the wiring Vint.

[0106] Table 1 shows common setting conditions for the circuit models 901 and 902 used in the simulation. The common setting conditions were that the channel length L of each of the transistors Tr1 and Tr2 was 200 nm and the channel width of each of the transistors Tr1 and Tr2 was 60 nm. Furthermore, each of the transistors Tr1 and Tr2 was a normally-off OS transistor. The potential of the other electrode of the capacitor C1 was set to GND. It was assumed that there was no gate leakage of each of the transistors Tr1 and Tr2 and no leakage between one electrode and the other electrode of the capacitor C1.

[0107] Furthermore, −0.95 V is supplied to the terminal G, and the transistors Tr1 and Tr2 are in an off state. In addition, the off current of each of the transistors Tr1 and Tr2 at this time is set to 1×10 −２４ A. In the initial state, 1.2 V is held at the node FN1, and 0 V is supplied to the terminal IN.

[0108]

[0109] The hold time was the time it took for the potential of the node FN1 to decrease by 10% from the initial state. The simulation was performed for a circuit model 901 in which the capacitance of the capacitor Cs1 was set to 5 fF, a circuit model 902 in which the capacitance of the capacitor Cs1 was set to 5 fF, and a circuit model 902 in which the capacitance of the capacitor Cs1 was set to 10 fF.

[0110] The simulation results are shown in FIG. 10 and Table 2. The horizontal axis in FIG. 10 represents time, and the vertical axis represents potential. On the horizontal axis in FIG. 10, the time when the transistor Tr1 is turned off after 1.2 V is written to the node FN1 is set as the reference (0). Note that in the circuit model 902, when the transistor Tr1 is turned off, the transistor Tr2 is also turned off at the same time.

[0111] 10 shows the potential change at the node FN1 of the circuit model 901 in which the capacitance of the capacitive element Cs1 is set to 5 fF. Furthermore, a profile 912a shows the potential change at the node FN1 of the circuit model 902 in which the capacitance of the capacitive element Cs1 is set to 5 fF. Furthermore, a profile 912b shows the potential change at the node FN1 of the circuit model 902 in which the capacitance of the capacitive element C1 is set to 10 fF.

[0112]

[0113] 10 and Table 2, in the circuit model 901, the retention time was estimated to be 151 hours when the capacitance of the capacitance element Cs1 was 5 fF. In addition, in the circuit model 902, the retention time was estimated to be 344 hours when the capacitance of the capacitance element C1 was 5 fF, and 633 hours when the capacitance was 10 fF.

[0114] 10 and Table 2, it was found that, in circuit models 901 and 902, when the capacitance of capacitance element Cs1 is the same, the greater the number of retention transistors connected in series, the longer the retention time. Specifically, when the capacitance of capacitance element C1 is the same, the retention time of circuit model 902 is estimated to be about 2.3 times longer than that of circuit model 901. In addition, it was found that the retention time can be further extended by increasing the capacitance of capacitance element Cs1.

[0115] Next, the retention characteristics of a circuit model 903 in which a capacitive element Cs2 is provided between the transistor Tr1 and the transistor Tr2 of the circuit model 902 were confirmed.

[0116] 11 shows a circuit diagram of a circuit model 903 configured with transistors Tr1, Tr2, and capacitors Cs1 and Cs2. In the circuit model 903, one of the source or drain of transistor Tr1 is connected to one electrode of capacitor Cs1, and the other of the source or drain is connected to one of the source or drain of transistor Tr2 and one electrode of capacitor Cs2. The other of the source or drain of transistor Tr2 is connected to terminal IN. The gates of transistors Tr1 and Tr2 are connected to each other and to terminal G.

[0117] As in the circuit model 902, in the circuit model 903, a region where one of the source or drain of the transistor Tr1 and one electrode of the capacitor Cs1 are connected and where both are always at the same potential is called a node FN1. Data written to the circuit model 903 is held in the node FN1. In the circuit model 903, a region where the other of the source or drain of the transistor Tr1, one of the source or drain of the transistor Tr2, and one electrode of the capacitor Cs2 are connected and where each is always at the same potential is called a node FN2.

[0118] The node FN2 corresponds to the node ND[2]a or ND[2]b of the semiconductor device 10A, and the capacitance element Cs2 corresponds to the capacitance element C2 or C3 of the semiconductor device 10A.

[0119] The retention characteristics of the circuit model 903 were confirmed by simulation. The simulation was performed under four conditions that combined the capacitances of the capacitive element Cs1 and the capacitive element Cs2.

[0120] Table 3 shows the combination conditions of the capacitors Cs1 and Cs2 used in the simulation. Table 3, FIGS. 12A, and 12B show the simulation results. As in FIG. 10, the horizontal axes in FIGS. 12A and 12B represent time, with the time when the transistors Tr1 and Tr2 are turned off after 1.2 V is written to the node FN1 as the reference (0). The vertical axes in FIGS. 12A and 12B represent potential.

[0121]

[0122] 12A shows a potential change at the node FN1 of the circuit model 903 in which the capacitance of the capacitance element Cs1 is set to 5 fF and the capacitance of the capacitance element Cs2 is set to 0 fF. Furthermore, a profile 913b shows a potential change at the node FN1 of the circuit model 903 in which the capacitance of the capacitance element Cs1 is set to 5 fF and the capacitance of the capacitance element Cs2 is set to 5 fF. Furthermore, a profile 913c shows a potential change at the node FN1 of the circuit model 903 in which the capacitance of the capacitance element Cs1 is set to 10 fF and the capacitance of the capacitance element Cs2 is set to 0 fF. Furthermore, a profile 913d shows a potential change at the node FN1 of the circuit model 903 in which the capacitance of the capacitance element Cs1 is set to 5 fF and the capacitance of the capacitance element Cs2 is set to 10 fF.

[0123] The profile 913a shows the same potential change as the profile 912a described above, and the profile 913c shows the same potential change as the profile 912b described above.

[0124] Comparing condition 1 (profile 913a) in which no capacitance is set for the capacitive element Cs2 (capacitance is 0 F) with condition 2 (profile 913b) in which the capacitance of the capacitive element Cs2 is 5 fF, it can be seen that although the slope of the potential decrease at the node FN1 is the same, the time until the potential at the node FN1 starts to decrease is longer under condition 2 in which the capacitive element Cs2 is provided. The retention time under condition 1 was estimated to be 344 hours, and the retention time under condition 2 was estimated to be 1877 hours.

[0125] Furthermore, comparing condition 2 (profile 913b), in which both capacitive element Cs1 and capacitive element Cs2 are provided with a capacitance of 5 fF, with condition 3 (profile 913c), in which capacitive element Cs2 is not provided and capacitive element Cs1 is provided with a capacitance of 10 fF, it can be seen that condition 3 has a shorter retention time than condition 2. This shows that providing capacitive elements with a capacitance of 5 fF each at node FN1 and node FN2 results in a longer retention time than providing a capacitive element with a capacitance of 10 fF only at node FN1. The retention time under condition 3 was estimated to be 633 hours. The retention time under condition 3 was approximately one-third of the retention time under condition 2.

[0126] Furthermore, comparing condition 2 (profile 913b), in which both capacitance elements Cs1 and Cs2 are set to a capacitance of 5 fF, with condition 4 (profile 913d), in which capacitance elements Cs1 and Cs2 are set to a capacitance of 5 fF and 10 fF, respectively, it can be seen that condition 4 requires a longer time until the potential at node FN1 begins to decrease. Furthermore, it can be seen that doubling the capacitance of capacitance element Cs2 also roughly doubles the time until the potential at node FN1 begins to decrease. The retention time under condition 4 was estimated to be 3,404 hours. The retention time under condition 4 was approximately 1.8 times the retention time under condition 2.

[0127] 12B shows a profile 913b that indicates a change in the potential of node FN1 under condition 2, and a profile 913b2 that indicates a change in the potential of node FN2 under condition 2. From FIG. 12B, it can be seen that the potential of node FN2 starts to decrease immediately after transistor Tr1 is turned off. On the other hand, it can be seen that the potential of node FN1 does not change and is maintained at 1.2 V until the potential of node FN2 becomes equal to or lower than approximately 0.1 V at time t.

[0128] From these facts, it can be seen that the magnitude of the capacitance of the capacitor Cs1 connected to node FN1 determines the slope of the potential decrease (the rate at which the potential decreases) of node FN1, and the magnitude of the capacitance of the capacitor Cs2 connected to node FN2 determines the time until the potential of node FN1 starts to decrease. In order to extend the retention time of node FN1, it is more effective to increase the capacitance of the capacitor Cs2 connected to node FN2 than to increase the capacitance of the capacitor Cs1. Therefore, although it is possible to set the capacitance of the capacitor Cs2 to be equal to or smaller than the capacitance of the capacitor Cs1, it is preferable that the capacitance of the capacitor Cs2 be larger than the capacitance of the capacitor Cs1.

[0129] As described above, the off-state current of an OS transistor hardly increases even in a high-temperature environment. On the other hand, depending on the operating conditions of the semiconductor device, the Vth of the transistor may fluctuate, and the drain current may fluctuate accordingly. For example, a fluctuation in the Vth of the transistor Tr1 may cause the potential of the node FN1 to fluctuate. However, even if the Vth fluctuates, the drain current fluctuates only slightly if the potential difference between the source and drain of the transistor is small. With the above configuration, the potential difference between the nodes FN1 and FN2 is prevented from increasing, thereby making it possible to prevent the potential of the node FN1 from fluctuating.

[0130] <<Operation Example>> Next, an operation example of the semiconductor device 10A shown in Fig. 1 will be described with reference to the drawings. Fig. 13 and Fig. 15A are timing charts for describing an operation example of the semiconductor device 10A shown in Fig. 1. Fig. 14 and Fig. 15B and Fig. 16 to Fig. 19 are circuit diagrams for describing an operation example of the semiconductor device 10A shown in Fig. 1.

[0131] In an initial state, a potential L is supplied to the wirings GI, GC, and EM, and a potential H is supplied to the wirings GB and GW. Therefore, the transistors M2, M5, M6[1], M6[2], M7[1], and M7[2] are in an off state, and the transistors M1 and M4 are in an on state. The potential of the node ND[1] is the video signal Vda+Vth, and the transistor M3 is in an on state. Note that the transistor M3 of the semiconductor device 10A shown in FIG. 1 is a p-type transistor, and therefore the Vth of the transistor M3 is a negative potential (a potential lower than the reference potential). Therefore, the video signal Vda+Vth is a potential lower than the video signal Vda.

[0132] The potential of the node ND[3] is assumed to be potential H. The wiring Vint is assumed to be supplied with potential L, and the wiring COM is assumed to be supplied with reference potential (0 V). The wiring DL is assumed to be supplied with video signal Vda. The video signal Vda is assumed to be at a potential higher than potential L. Note that potential H is higher than the reference potential, and potential L is lower than the reference potential. The wiring ELVDD is assumed to be supplied with potential H, and the wiring ELVSS is assumed to be supplied with potential L.

[0133] [Period T11] In the period T11, a potential H is supplied to the wiring GI, and a potential L is supplied to the wiring GB (see FIGS. 13 and 14). When the potential H is supplied to the wiring GI, the transistors M7[1] and M7[2] are turned on, and the potential L is supplied to the node ND[1].

[0134] Furthermore, when a potential L is supplied to the wiring GB, the transistor M5 is turned on. This changes the path of the current that previously flowed to the light-emitting element 61 via the channel formation regions of the transistors M1, M3, and M4. Specifically, the current no longer flows to the light-emitting element 61, but instead flows toward the wiring Vint via the channel formation region of the transistor M5. This causes the light-emitting element 61 to stop emitting light.

[0135] 15A and 15B, a potential H can be supplied to the wiring EM during the period T11. By supplying the potential H to the wiring EM, the transistors M1 and M4 are turned off. This blocks the current flowing from the wiring ELVDD to the wiring Vint, thereby reducing power consumption. Furthermore, since the state is the same as that of the subsequent period T12, the period T12 can be omitted. This increases the operating speed of the semiconductor device 10A.

[0136] [Period T12] In period T12, a potential H is supplied to the wiring EM (see FIGS. 13 and 16). When the potential H is supplied to the wiring EM, the transistors M1 and M4 are turned off. In addition, since the transistor M5 is turned on, a potential L is supplied to the first terminal of the light-emitting element 61.

[0137] [Period T13] During the period T13, a potential L is supplied to the wiring GI, and a potential H is supplied to the wiring GB (see FIGS. 13 and 17). As a result, the transistors M7[1], M7[2], and M5 are turned off. In addition, a potential L is supplied to the wiring GW, and a potential H is supplied to the wiring GC.

[0138] Note that it is preferable to supply the potential L to the wiring GW and the potential H to the wiring GC after supplying the potential L to the wiring GI and the potential H to the wiring GB, which can prevent the wiring DL and the wiring Vint from being electrically connected to each other, thereby reducing the power consumption of the semiconductor device 10A.

[0139] When a potential L is supplied to the wiring GW, the transistor M2 is turned on, and the video signal Vda is supplied to the node ND[3] from the wiring DL. When a potential H is supplied to the wiring GC, the transistors M6[1] and M6[2] are turned on. Because the transistor M3 is also turned on, the video signal Vda begins to be supplied to the node ND[1]. Therefore, the potential of the node ND[1] rises.

[0140] The potential of the node ND[1] continues to rise until it reaches the video signal Vda+Vth at time t13a (see FIGS. 13 and 18). When the potential of the node ND[1] reaches the video signal Vda+Vth, the transistor M3 turns off, and the rise in the potential of the node ND[1] ends. For example, if VSS is -5V, the video signal Vda is -2V, and the Vth of the transistor M3 is -1V, the potential of the node ND[1] becomes -3V.

[0141] [Period T14] In the period T14, a potential H is supplied to the wiring GW, and a potential L is supplied to the wiring GC (see FIGS. 13 and 19). When the potential H is supplied to the wiring GW, the transistor M2 is turned off. When the potential L is supplied to the wiring GC, the transistors M6[1] and M6[2] are turned off, and the potential of the node ND[1] is held. In this way, the potential of the node ND[1] is held at the sum of the video signal Vda and the Vth of the transistor M3. Note that when the transistor M3 functioning as a driving transistor is a p-type transistor, the video signal Vda+Vth is set to a potential equal to or lower than Vth.

[0142] [Period T15] In period T15, a potential L is supplied to the wiring EM (see FIGS. 13 and 20). When the potential L is supplied to the wiring EM, the transistors M1 and M4 are turned on. Furthermore, when the transistor M1 is turned on, the potential of the node ND[3] becomes a potential H. Here, the video signal Vda+Vth held in the node ND[1] is a potential lower than Vth, and the potential H is a potential higher than the video signal Vda+Vth, so the transistor M3 is turned on. In this manner, a current IE flows from the wiring ELVDD to the wiring ELVSS via the transistors M1, M3, M4, and the light-emitting element 61. Furthermore, the current value of the current IE is determined by the potential of the node ND[1]. In the semiconductor device 10A according to one embodiment of the present invention, the video signal Vda corrected by the Vth of the transistor M3 functioning as a driving transistor is held in the node ND[1], so that a current IE having an accurate current value corresponding to the video signal Vda can flow to the light-emitting element 61.

[0143] As shown in the above operation example, a display device using the semiconductor device 10A according to one embodiment of the present invention as a pixel can correct the Vth of the driving transistor for each pixel (also referred to as "internal correction"). Therefore, a display device using the semiconductor device 10A according to one embodiment of the present invention as a pixel can correct Vth variations of the driving transistor between pixels. In addition, the influence of hysteresis of the driving transistor can be suppressed. By using the semiconductor device 10A according to one embodiment of the present invention as a pixel of a display device, the display quality of the display device can be improved.

[0144] Furthermore, in the semiconductor device 10A according to one embodiment of the present invention, the holding of the video signal Vda and the correction of the Vth of the drive transistor are performed simultaneously, and therefore the semiconductor device 10A according to one embodiment of the present invention can operate at a higher speed than a semiconductor device in which the correction of the Vth of the drive transistor and the holding of the video signal Vda are performed in separate operations.

[0145] Furthermore, by using the wiring Vint as a monitor line to measure the current flowing through the transistor M3, it is possible to correct not only the Vth of the transistor M3 between pixels but also variations in the electrical characteristics of the transistor M3 between pixels, such as the mobility of the transistor M3. Specifically, as shown in Figure 21, the transistors M1, M3, M4, and M5 are turned on, the other transistors are turned off, and a potential H is supplied to the wiring ELVSS, thereby measuring the current I M flowing through the transistor M3. The mobility and other electrical characteristics of the transistor M3 can be obtained from the relationship between the potential of the node ND[1] and the current I M at this time.

[0146] Furthermore, by using the wiring Vint as a monitor line to measure the current flowing through the light-emitting element 61, it is possible to correct variations in the electrical characteristics of the light-emitting element 61 between pixels. Specifically, as shown in FIG. 22 , the current-voltage characteristics of the light-emitting element 61 can be obtained by turning off the transistors other than the transistor M5 and supplying a potential H to the wiring Vint.

[0147] The current acquired by using the wiring Vint as a monitor line can be converted into, for example, an analog voltage or a digital signal and output to an external device. The external device can perform correction (also referred to as external correction) of the video signal Vda using the analog voltage or the digital signal.

[0148] By performing not only internal correction but also both internal and external correction, the display quality of the display device can be further improved. Note that internal correction is preferably performed every time an image is rewritten. On the other hand, external correction requires a longer processing time than internal correction, so it does not have to be performed every time an image is rewritten. For example, external correction may be performed only during a predetermined period.

[0149] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0150] Embodiment 2 In this embodiment, a transistor that can be used for a semiconductor device according to one embodiment of the present invention will be described.

[0151] 24A is a plan view of a transistor 200A that can be used for a semiconductor device of one embodiment of the present invention. The transistor 200A is an example of a planar transistor. In this specification, a planar transistor refers to a transistor in which a source electrode and a drain electrode are located at the same height or approximately the same height and a current flowing through a semiconductor has a lateral component.

[0152] Fig. 24B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in Fig. 24A. Fig. 24C is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in Fig. 24A. Note that some elements are omitted from the plan view of Fig. 24A for clarity. Some elements may also be omitted from other plan views.

[0153] The transistor 200A has an insulating layer 202 over a substrate 201 and a semiconductor layer 203 over the insulating layer 202. The transistor 200A also has an insulating layer 204 over the insulating layer 202 and the semiconductor layer 203. The transistor 200A also has a conductive layer 205 over the insulating layer 204. The semiconductor layer 203 and the conductive layer 205 have regions that overlap with each other with the insulating layer 204 interposed therebetween.

[0154] The semiconductor layer 203 has a region 203a, a channel formation region 203b, and a region 203c. The region 203a functions as either a source region or a drain region. The region 203c functions as the other of the source region and the drain region. In the semiconductor layer 203, a region overlapping with the conductive layer 205 functions as the channel formation region 203b. Therefore, the conductive layer 205 functions as the gate electrode of the transistor 200A. The insulating layer 204 functions as a gate insulating layer of the transistor 200A.

[0155] The length of the channel formation region 203b in the X direction is the channel length L of the transistor 200A (see FIG. 24B), and the length of the channel formation region 203b in the Y direction is the channel width W of the transistor 200A (see FIG. 24C).

[0156] An insulating layer 206 is provided over the insulating layer 204 and the conductive layer 205. An opening 207a is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with a region 203a of the semiconductor layer 203. An opening 207b is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with a region 203c of the semiconductor layer 203.

[0157] A conductive layer 208a is provided over the insulating layer 206 and the opening 207a, and a conductive layer 208b is provided over the insulating layer 206 and the opening 207b. The conductive layer 208a is connected to the region 203a of the semiconductor layer 203 at the bottom of the opening 207a. The conductive layer 208b is connected to the region 203c of the semiconductor layer 203 at the bottom of the opening 207b. Thus, the conductive layer 208a functions as one of the source and drain electrodes of the transistor 200A, and the conductive layer 208b functions as the other of the source and drain electrodes of the transistor 200A.

[0158] In addition, an insulating layer 209 is provided over the insulating layer 206 and the conductive layer 208 (the conductive layer 208a and the conductive layer 208b).

[0159] 25A is a plan view of a transistor 200B that can be used for a semiconductor device of one embodiment of the present invention. The transistor 200B is a variation of the transistor 200A. To avoid repetition of description, differences between the transistor 200B and the transistor 200A will be mainly described.

[0160] Fig. 25B is a cross-sectional view taken along the dashed line A1-A2 in Fig. 25A. Fig. 25C is a cross-sectional view taken along the dashed line A3-A4 in Fig. 25A.

[0161] The transistor 200B differs from the transistor 200A in that a conductive layer 219 is provided between the substrate 201 and the insulating layer 202. The conductive layer 219 functions as a backgate electrode of the transistor 200B. Therefore, the conductive layer 219 overlaps with the channel formation region 203b. The conductive layer 219 preferably extends beyond the end of the channel formation region 203b. That is, the conductive layer 219 preferably covers the channel formation region 203b. Covering the channel formation region 203b with the conductive layer 219 can enhance the electric field shielding effect described in the above embodiment.

[0162] 26A is a plan view of a transistor 200C that can be used in a semiconductor device according to one embodiment of the present invention, and FIG. 26B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in FIG. 26A.

[0163] The transistor 200C includes an insulating layer 202 over a substrate 201 and a conductive layer 255 over the insulating layer 202. The transistor 200C also includes an insulating layer 257 over the conductive layer 255, an insulating layer 258 over the insulating layer 257, and an insulating layer 259 over the insulating layer 258. Note that in this specification, the insulating layer 257, the insulating layer 258, and the insulating layer 259 may be collectively referred to as an insulating layer 256 or a spacer layer. The transistor 200C also includes a conductive layer 261 over the insulating layer 259.

[0164] An opening 262 penetrating the conductive layer 261, the insulating layer 259, the insulating layer 258, and the insulating layer 257 is provided in a region overlapping with part of the conductive layer 255. A semiconductor layer 263 is provided to cover the opening 262.

[0165] The semiconductor layer 263 has a region overlapping with the bottom of the opening 262 and a region overlapping with the side surface of the opening 262. That is, the semiconductor layer 263 has a region in contact with the insulating layer 256 inside the opening 262. The semiconductor layer 263 also has a region in contact with the conductive layer 255 and a region in contact with the conductive layer 261 inside the opening 262.

[0166] An insulating layer 264 is provided over the insulating layer 259, the conductive layer 261, and the semiconductor layer 263. A conductive layer 265 is provided over the insulating layer 264. The conductive layer 265 has a region overlapping with the semiconductor layer 263. The conductive layer 265 has a region overlapping with the semiconductor layer 263 with the insulating layer 264 interposed therebetween.

[0167] The insulating layer 264 and the conductive layer 265 each have a region overlapping with the opening 262. The insulating layer 264 and the conductive layer 265 each have a region overlapping with the inside of the opening 262. Inside the opening 262, the semiconductor layer 263 has a region overlapping with the conductive layer 265 with the insulating layer 264 interposed therebetween and a region overlapping with a side surface of the opening 262 (a side surface of the insulating layer 256).

[0168] Furthermore, an insulating layer 266 is provided on the insulating layer 264. Note that the upper surface of the insulating layer 266 is preferably flat. Alternatively, it is preferable that the heights (positions in the Z direction) of the upper surfaces of the insulating layer 266 and the conductive layer 265 are the same or approximately the same. For example, the flatness of the upper surface of the insulating layer 266 can be improved by performing chemical mechanical polishing (CMP) processing or the like. Furthermore, by performing CMP processing, the positions of the upper surfaces of the insulating layer 266 and the conductive layer 265 can be made to be the same or approximately the same. By performing CMP processing, unevenness on the sample surface can be reduced, and the coverage of the insulating layer and conductive layer to be formed subsequently can be improved.

[0169] When an oxide semiconductor is used for the semiconductor layer 263, the conductive layer 255 in contact with the semiconductor layer 263 and the conductive layer 261 in contact with the semiconductor layer 263 are preferably formed using a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Alternatively, another conductive material may be provided over the conductive material containing nitrogen.

[0170] When an oxide semiconductor is used for the semiconductor layer 263, it is preferable to use a material containing oxygen and in which hydrogen is reduced for the insulating layer 258. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like may be used. Since hydrogen is an impurity element in an oxide semiconductor, contact between the semiconductor layer 263, which is an oxide semiconductor, and the insulating layer 258 in which hydrogen is reduced makes it difficult for the semiconductor layer 263 to become n-type. Furthermore, contact between the semiconductor layer 263, which is an oxide semiconductor, and the insulating layer 258 containing oxygen reduces oxygen vacancies in the semiconductor layer 263, thereby stabilizing the characteristics of the transistor and improving its reliability.

[0171] In the case where an oxide semiconductor is used for the semiconductor layer 263, the insulating layer 258 preferably contains excess oxygen. In this specification, excess oxygen refers to oxygen that is released by heating. A material that releases oxygen by heating is a material that releases oxygen in an amount of 1.0×10 converted into oxygen atoms as determined by thermal desorption spectroscopy (TDS) analysis. １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C or 100°C to 400°C.

[0172] When a material containing excess oxygen is used for the insulating layer 258, a material that is impermeable to oxygen may be used for the insulating layers 257 and 259. Examples of the material that is impermeable to oxygen include an oxide containing one or both of aluminum and hafnium, and a silicon nitride. By using a material that is impermeable to oxygen for the insulating layers 257 and 259, the excess oxygen contained in the insulating layer 258 is less likely to be released into the lower or upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a structure in which an insulating layer containing silicon and oxygen (insulating layer 258) is provided between two insulating layers containing silicon and nitrogen (insulating layer 257 and insulating layer 259) is preferable. Silicon nitride, silicon nitride oxide, or the like can be used as the insulating layer containing silicon and oxygen. Silicon oxide, silicon oxynitride, or the like can be used as the insulating layer containing silicon and oxygen.

[0173] When an oxide semiconductor is used for the semiconductor layer 263, by using a material containing hydrogen for the insulating layers 257 and 259, hydrogen is supplied to a region of the semiconductor layer 263 in contact with the insulating layer 257 and a region of the semiconductor layer 263 in contact with the insulating layer 259, and each region of the semiconductor layer 263 becomes n-type. Therefore, the region of the semiconductor layer 263 in contact with the conductive layer 261 and the region of the semiconductor layer 263 in contact with the insulating layer 259 function as one of the source region and the drain region. The region of the semiconductor layer 263 in contact with the conductive layer 255 and the region of the semiconductor layer 263 in contact with the insulating layer 257 function as the other of the source region and the drain region.

[0174] The conductive layer 261 functions as one of the source electrode and the drain electrode of the transistor 200C. The conductive layer 255 functions as the other of the source electrode and the drain electrode of the transistor 200C. The transistor 200C is a transistor in which the source electrode and the drain electrode are arranged in the Z direction. That is, the source and the drain of the transistor 200C are arranged at different heights. In other words, the source and the drain of the transistor 200C are arranged at different positions in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0175] In the above configuration, in the transistor 200C, which is a VFET, the length of the side surface of the insulating layer 158 as viewed from the X direction or the Y direction is the channel length L (channel length L1) (see FIG. 26B ). Therefore, the channel length L of the transistor 200C is determined according to the thickness t1 of the insulating layer 258.

[0176] Furthermore, it is preferable to use a material that does not contain hydrogen or that contains very little hydrogen for the insulating layers 257 and 259. For example, it is preferable to use silicon nitride or silicon nitride oxide that contains very little hydrogen. In this case, the region of the semiconductor layer 263 in contact with the insulating layer 257 and the region of the semiconductor layer 263 in contact with the insulating layer 259 are not made n-type. Therefore, the region of the semiconductor layer 263 in contact with the conductive layer 261 functions as one of the source region and the drain region. The region of the semiconductor layer 263 in contact with the conductive layer 255 functions as the other of the source region and the drain region. The region of the semiconductor layer 263 in contact with the insulating layer 258 functions as a channel formation region.

[0177] In this case, the sum of the lengths of the side surfaces of the insulating layers 257, 258, and 259 as viewed from the X direction or the Y direction is the channel length L (channel length L2). Therefore, the channel length L of the transistor 200C is determined according to the total thickness t2 of the insulating layers 257, 258, and 259. In this manner, the transistor 200C has a channel formation region that extends along the side surface of the insulating layer 256.

[0178] Furthermore, because the semiconductor layer 263 is provided in the opening 262, the perimeter of the opening 262 as viewed in the Z direction corresponds to the channel width W of the transistor 200C (see FIG. 26A ). The perimeter can be determined, for example, at a position halfway between the thickness t1 or the thickness t2 of the insulating layer 258. If necessary, the perimeter of any position on the opening 262 can be used as the channel width W. For example, the perimeter of the bottom of the opening 262 can be used as the channel width W, or the perimeter of the top of the opening 262 can be used as the channel width W. Although FIG. 26A shows the outline (planar shape) of the opening 262 as viewed in the Z direction as a circle, this is not limiting. For example, the outline of the opening 262 as viewed in the Z direction can be an ellipse, a rectangle, or the like.

[0179] In the memory device of one embodiment of the present invention, the channel length L is preferably smaller than at least the channel width W. In one embodiment of the present invention, the channel length L is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W.

[0180] Furthermore, in order to improve the coverage of the semiconductor layer 263, the insulating layer 264, and the conductive layer 265 formed inside the opening 262, the taper angle θ of the side surface of the opening 262, i.e., the taper angle θ of each of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259, is set to 45° or more and 90° or less, preferably 50° or more and 75° or less. The taper angles θ of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259 can be the same or different from each other. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle formed between the bottom surface and the side surface of the layer (see FIG. 26B ).

[0181] A vertical transistor can occupy a smaller area than a transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane (also called a "horizontal transistor"). Therefore, by using a vertical channel transistor in a semiconductor device, the area occupied by the semiconductor device can be reduced. Furthermore, by using a vertical channel transistor in a semiconductor device, high integration of the semiconductor device can be achieved.

[0182] Furthermore, in a lateral transistor, the channel length is limited by the exposure limit of photolithography. In a vertical channel transistor according to one embodiment of the present invention, the channel length can be set by the thickness of the insulating layer 256 or 258. Therefore, the channel length of the transistor can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more). This increases the on-state current of the transistor 200C, thereby improving frequency characteristics. By using a vertical channel transistor, a semiconductor device with high operating speed can be provided.

[0183] 27A is a plan view of a transistor 200D that can be used for a semiconductor device of one embodiment of the present invention. The transistor 200D is a variation of the transistor 200C. To avoid repetition of description, differences between the transistor 200D and the transistor 200C will be mainly described.

[0184] FIG. 27B is a cross-sectional view taken along the dashed line A1-A2 in FIG. 27A.

[0185] The transistor 200D includes an insulating layer 258a and an insulating layer 258b between the insulating layer 257 and the insulating layer 259, and a conductive layer 267 between the insulating layer 258a and the insulating layer 258b. The insulating layer 258a and the insulating layer 258b can be formed using a material and a method similar to those of the insulating layer 258. The opening 262 of the transistor 200D is provided to penetrate the conductive layer 261, the insulating layer 259, the insulating layer 258b, the conductive layer 267, the insulating layer 258a, and the insulating layer 257 in a region overlapping with part of the conductive layer 255.

[0186] In the transistor 200D, an insulating layer 268 is provided along the side surface of the opening 262. Inside the opening 262, the insulating layer 268 has a region overlapping with a side surface of the conductive layer 261, a region overlapping with a side surface of the insulating layer 259, a region overlapping with a side surface of the insulating layer 258b, a region overlapping with a side surface of the conductive layer 267, a region overlapping with a side surface of the insulating layer 258a, and a region overlapping with a side surface of the insulating layer 257.

[0187] Furthermore, inside the opening 262, the semiconductor layer 263 in the transistor 200D has a region that overlaps with a side surface of the conductive layer 261 via the insulating layer 268, a region that overlaps with a side surface of the insulating layer 259 via the insulating layer 268, a region that overlaps with a side surface of the insulating layer 258b via the insulating layer 268, a region that overlaps with a side surface of the conductive layer 267 via the insulating layer 268, a region that overlaps with a side surface of the insulating layer 258a via the insulating layer 268, and a region that overlaps with a side surface of the insulating layer 257 via the insulating layer 268.

[0188] When the conductive layer 265 is used as a gate electrode, the conductive layer 267 functions as a back gate electrode. When the conductive layer 267 is used as a gate electrode, the conductive layer 265 functions as a back gate electrode. One of the insulating layer 264 and the insulating layer 268 functions as a gate insulating layer, and the other functions as a back gate insulating layer. The insulating layer 268 can be formed using a material and a method similar to those of the insulating layer 264.

[0189] <Transistor Structure Example 5> Fig. 28A is a plan view of a transistor 200E that can be used for a semiconductor device of one embodiment of the present invention. Fig. 28B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in Fig. 28A . Fig. 28C is a cross-sectional view taken along the line A3-A4 indicated by a dashed dotted line in Fig. 28A . Note that Fig. 28A is a cross-sectional view of the transistor 200E in the channel length direction, and Fig. 28C is a cross-sectional view of the transistor 200E in the channel width direction.

[0190] 28A to 28C , the transistor 200E includes a semiconductor layer 520a disposed on a substrate 201, a semiconductor layer 520b disposed on the semiconductor layer 520a, conductive layers 542a and 542b disposed spaced apart from each other on the semiconductor layer 520b, an insulating layer 580 disposed on the conductive layers 542a and 542b and having an opening formed between the conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, an insulating layer 550 disposed among the semiconductor layer 520b, the conductive layers 542a, 542b, and the insulating layer 580, and the conductive layer 560, and a semiconductor layer 520c disposed among the semiconductor layer 520b, the conductive layers 542a, 542b, the insulating layer 580, and the insulating layer 550. 28B and 28C , the top surface of the conductive layer 560 is substantially aligned with the top surfaces of the insulating layer 550, the insulating layer 554, the semiconductor layer 520c, and the insulating layer 580. Note that hereinafter, the semiconductor layers 520a, 520b, and 520c may be collectively referred to as the semiconductor layer 520. The conductive layers 542a and 542b may be collectively referred to as the conductive layer 542.

[0191] 28A to 28C , an insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542a, the conductive layer 542b, and the semiconductor layer 520c and the insulating layer 580. The insulating layer 554 is in contact with the side surface of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524.

[0192] Although the transistor 200E has a three-layer structure including the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c in the channel formation region and its vicinity, the present invention is not limited to this. For example, a two-layer structure including the semiconductor layer 520b and the semiconductor layer 520c or a stacked structure of four or more layers may be used. Furthermore, each of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may have a stacked structure of two or more layers.

[0193] For example, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 520, and the semiconductor layer 520c has a stacked structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of the semiconductor layer 520b, and the second metal oxide has a composition similar to that of the semiconductor layer 520a.

[0194] Here, the conductive layer 560 functions as the gate electrode of the transistor, and the conductive layers 542a and 542b function as source and drain electrodes, respectively. As described above, the conductive layer 560 is formed so as to fill the opening of the insulating layer 580 and the region sandwiched between the conductive layers 542a and 542b. Here, the conductive layers 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening of the insulating layer 580. That is, in the transistor 200E, the gate electrode can be arranged between the source and drain electrodes in a self-aligned manner. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 200E. This reduces the area occupied by the semiconductor device. Furthermore, the integration degree of the semiconductor device can be increased.

[0195] 28A to 28C , the conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 550 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a. Although the conductive layer 560 in the transistor 200E has a two-layer stacked structure, the present invention is not limited to this. For example, the conductive layer 560 may have a single-layer structure or a stacked structure of three or more layers.

[0196] The transistor 200E includes an insulating layer 202 disposed on the substrate 201, an insulating layer 514 disposed on the insulating layer 202, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. In addition, a semiconductor layer 520a is disposed on the insulating layer 524.

[0197] Further, insulating layers 574 and 581 functioning as interlayer films are provided over the transistor 200E. The insulating layer 574 is provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, the insulating layer 554, the semiconductor layer 520c, and the insulating layer 580.

[0198] When an oxide semiconductor is used for the semiconductor layer 520, an insulating layer having a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like) is preferably used for the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, an insulating layer having lower hydrogen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 is preferably used for the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, silicon nitride, silicon nitride oxide, or the like can be used.

[0199] Furthermore, an insulating layer having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) is preferably used for the insulating layer 522 and the insulating layer 554. For example, an insulating layer having lower oxygen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 is preferably used for the insulating layer 522 and the insulating layer 554. For example, silicon nitride, silicon nitride oxide, or the like can be used.

[0200] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are separated by the insulating layer 522 and the insulating layer 574. Therefore, impurities such as hydrogen and excess oxygen contained in layers above the insulating layer 574 and below the insulating layer 522 can be prevented from being mixed into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0201] 28B shows an example in which a conductive layer 545 (conductive layer 545a and conductive layer 545b) connected to the transistor 200E and functioning as a plug is provided. Note that an example is shown in which an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided in contact with the side surface of the conductive layer 545 functioning as a plug. That is, the insulating layer 541 is provided in contact with the inner walls of the openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. In addition, in FIG. 28B, a first conductive layer of the conductive layer 545 is provided in contact with the side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided further inside.

[0202] Here, the height of the top surface of the conductive layer 545 and the height of the top surface of the insulating layer 581 can be approximately the same. Note that although the transistor 200E shows a structure in which the first conductive layer of the conductive layer 545 and the second conductive layer of the conductive layer 545 are stacked, the present invention is not limited to this. For example, the conductive layer 545 can also be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0203] Furthermore, the thickness of the semiconductor layer 520b in a region that does not overlap with the conductive layer 542 may be thinner than the thickness of the region that overlaps with the conductive layer 542. This is achieved by removing part of the top surface of the semiconductor layer 520b when forming the conductive layers 542a and 542b. When a conductive film that will become the conductive layer 542 is formed on the top surface of the semiconductor layer 520b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region of the semiconductor layer 520b that is located between the conductive layer 542a and the conductive layer 542b in a plan view, it is possible to prevent a channel from being formed in that region.

[0204] Next, the detailed structure of the transistor 200E that can be used in the semiconductor device of one embodiment of the present invention will be described.

[0205] The conductive layer 505 is arranged to have a region overlapping with the conductive layer 560 with the semiconductor layer 520 interposed therebetween. By providing the conductive layer 505 so as to be embedded in the insulating layer 516, unevenness on the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and coverage with layers formed in later steps can be improved.

[0206] The conductive layer 505 includes a conductive layer 505a, a conductive layer 505b, and a conductive layer 505c. The conductive layer 505a is provided in contact with the bottom surface and sidewalls of an opening provided in the insulating layer 516. The conductive layer 505b is provided so as to fill a recess formed in the conductive layer 505a. The top surface of the conductive layer 505b is lower than the top surfaces of the conductive layer 505a and the insulating layer 516. The conductive layer 505c is provided in contact with the top surface of the conductive layer 505b and the side surface of the conductive layer 505a. The height of the top surface of the conductive layer 505c is equal to or approximately equal to the height of the top surface of the conductive layer 505a and the top surface of the insulating layer 516. In other words, the conductive layer 505b is surrounded by the conductive layers 505a and 505c.

[0207] In the case where an oxide semiconductor is used for the semiconductor layer 520, the conductive layer 505a and the conductive layer 505c can be formed of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N ２ O, NO, NO ２ A conductive material having a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is used.

[0208] By using a conductive material that has a function of reducing hydrogen diffusion for the conductive layers 505a and 505c, it is possible to prevent impurities such as hydrogen contained in the conductive layer 505b from diffusing into the semiconductor layer 520 through the insulating layer 524 or the like. Furthermore, by using a conductive material that has a function of suppressing oxygen diffusion for the conductive layers 505a and 505c, it is possible to prevent the conductive layer 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that have a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 505a can be formed as a single layer or a stack of any of the above conductive materials. For example, titanium nitride can be used for the conductive layer 505a.

[0209] The conductive layer 505b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 505b may be formed using tungsten. When the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a back gate electrode.

[0210] The conductive layer 505 is preferably provided to be larger than the channel formation region in the semiconductor layer 520. In particular, as shown in Fig. 28C, the conductive layer 505 preferably extends to a region outside the end portion intersecting with the channel width direction of the semiconductor layer 520. In other words, the conductive layer 505 and the conductive layer 560 preferably overlap with each other with an insulating layer interposed therebetween on the outside of the side surface of the semiconductor layer 520 in the channel width direction.

[0211] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 functioning as a gate electrode and the electric field of the conductive layer 505 functioning as a back gate electrode.

[0212] The conductive layer 505 can be used as wiring by extending it beyond the end of the semiconductor layer 520. However, the present invention is not limited to this, and a structure in which a conductive layer functioning as wiring is provided under the conductive layer 505 is also possible.

[0213] The insulating layer 514 is preferably formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200E from the substrate side. Therefore, the insulating layer 514 is preferably formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200E from the substrate side. ２ O, NO, NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., copper atoms are difficult to penetrate), or an insulating material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., oxygen is difficult to penetrate).

[0214] For example, aluminum oxide, silicon nitride, or the like is used for the insulating layer 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 514 to the transistor 200E side. Alternatively, it can prevent oxygen contained in the insulating layer 524 or the like from diffusing toward the substrate side of the insulating layer 514.

[0215] The insulating layer 516, the insulating layer 580, and the insulating layer 581, which function as interlayer films, may be formed using an insulating material having a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the insulating layer 516, the insulating layer 580, and the insulating layer 581 may be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0216] When the conductive layer 560 is used as a gate electrode, the insulating layers 522 and 524 function as gate insulating layers.

[0217] Here, the insulating layer 524 in contact with the semiconductor layer 520 preferably contains excess oxygen. For example, silicon oxide, silicon oxynitride, or the like may be used as appropriate for the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 are reduced, and the reliability of the transistor 200E is improved.

[0218] 28C , the thickness of the insulating layer 524 in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b may be thinner than the thickness of the other region. The thickness of the insulating layer 524 in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b is preferably set to a thickness that allows sufficient diffusion of the oxygen.

[0219] As the insulating layer 522, like the insulating layer 514, a material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200E from the substrate side is used. For example, the insulating layer 522 is made of a material that has lower hydrogen permeability than the insulating layer 524. By surrounding the insulating layer 524, the semiconductor layer 520, the insulating layer 550, and the like with the insulating layer 522, the insulating layer 554, and the insulating layer 574, impurities such as water or hydrogen can be prevented from entering the transistor 200E from the outside.

[0220] Furthermore, the insulating layer 522 is preferably made of a material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., the oxygen is less likely to permeate). For example, the insulating layer 522 is made of a material that has lower oxygen permeability than the insulating layer 524. The insulating layer 522 has a function of suppressing the diffusion of oxygen and impurities, so that oxygen diffusing from the semiconductor layer 520 toward the substrate can be reduced. Furthermore, the conductive layer 505 can be prevented from reacting with oxygen contained in the insulating layer 524 or the semiconductor layer 520.

[0221] An insulating layer containing an oxide of one or both of aluminum and hafnium, which are insulating materials, may be used as the insulating layer 522. Examples of the insulating layer containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer that suppresses oxygen release from the semiconductor layer 520 and the intrusion of impurities such as hydrogen into the semiconductor layer 520 from the periphery of the transistor 200E.

[0222] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to the insulating layer 522. Alternatively, the insulating layer 522 can be subjected to nitriding treatment. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride can be stacked as the insulating layer 522. For example, the insulating layer 522 can have a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0223] The insulating layer 522 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ It is possible to use an insulating layer containing a so-called high-k material such as BST in a single layer or a laminated layer. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a high-k material for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0224] Note that each of the insulating layer 522 and the insulating layer 524 can have a stacked structure of two or more layers. In this case, the insulating layer 522 and the insulating layer 524 are not limited to a stacked structure made of the same material, and can have a stacked structure made of different materials.

[0225] The semiconductor layer 520 includes a semiconductor layer 520a, a semiconductor layer 520b on the semiconductor layer 520a, and a semiconductor layer 520c on the semiconductor layer 520b. By providing the semiconductor layer 520a below the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed below the semiconductor layer 520a to the semiconductor layer 520b. Furthermore, by providing the semiconductor layer 520c on the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed above the semiconductor layer 520c to the semiconductor layer 520b.

[0226] When an oxide semiconductor is used for the semiconductor layer 520, the semiconductor layer 520 preferably has a stacked structure of multiple oxide layers with different atomic ratios of metal atoms. For example, when the semiconductor layer 520 includes at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the semiconductor layer 520a to the number of atoms of all elements constituting the semiconductor layer 520a is made higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520a to In is made higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In. Here, the semiconductor layer 520c can use the metal oxide used for the semiconductor layer 520a or the semiconductor layer 520b.

[0227] The energy of the conduction band minimum of the semiconductor layer 520a and the semiconductor layer 520c is preferably higher than the energy of the conduction band minimum of the semiconductor layer 520b. In other words, the electron affinity of the semiconductor layer 520a and the semiconductor layer 520c is preferably lower than the electron affinity of the semiconductor layer 520b. In this case, the semiconductor layer 520c may be made of a metal oxide that can be used for the semiconductor layer 520a. Specifically, the ratio of the number of atoms of the element M contained in the semiconductor layer 520c to the number of atoms of all elements constituting the semiconductor layer 520c is preferably higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520c to In is preferably higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In.

[0228] Here, the energy level of the conduction band minimum changes gradually at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c. In other words, the energy level of the conduction band minimum at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c changes continuously or can be said to be a continuous junction. To achieve this, it is preferable that the defect level density of the mixed layer formed at the interface between the semiconductor layer 520a and the semiconductor layer 520b and the interface between the semiconductor layer 520b and the semiconductor layer 520c is low.

[0229] Specifically, the semiconductor layers 520a and 520b, and the semiconductor layers 520b and 520c, can form a mixed layer with a low defect level density by having a common element other than oxygen (as a main component). For example, when the semiconductor layer 520b is an In—Ga—Zn oxide, the semiconductor layers 520a and 520c can be made of In—Ga—Zn oxide, Ga—Zn oxide, gallium oxide, or the like. The semiconductor layer 520c can also have a stacked structure. For example, a stacked structure of In—Ga—Zn oxide and Ga—Zn oxide on the In—Ga—Zn oxide, or a stacked structure of In—Ga—Zn oxide and gallium oxide on the In—Ga—Zn oxide can be used. In other words, a stacked structure of In—Ga—Zn oxide and an oxide not containing In can be used as the semiconductor layer 520c.

[0230] Specifically, the semiconductor layer 520a may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of 1:1:0.5 or thereabouts. The semiconductor layer 520b may be made of a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of 3:1:2 or thereabouts, or an atomic ratio of 1:1:1 or thereabouts. The semiconductor layer 520c may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of Ga:Zn=2:1 or thereabouts, or an atomic ratio of Ga:Zn=2:5 or thereabouts. Specific examples of the semiconductor layer 520c having a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and Ga:Zn=2:1 [atomic ratio] or the vicinity thereof, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and Ga:Zn=2:5 [atomic ratio] or the vicinity thereof, and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and gallium oxide.

[0231] In this case, the main carrier path is the semiconductor layer 520b. By configuring the semiconductor layers 520a and 520c as described above, the defect state density at the interface between the semiconductor layers 520a and 520b and the interface between the semiconductor layers 520b and 520c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 200E to achieve high on-state current and high frequency characteristics. Note that if the semiconductor layer 520c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the semiconductor layers 520b and 520c, it is expected that the diffusion of constituent elements of the semiconductor layer 520c toward the insulating layer 550 can be suppressed. More specifically, since the semiconductor layer 520c has a stacked structure and an oxide not containing In is located above the stacked structure, it is possible to suppress In diffusion toward the insulating layer 550. The insulating layer 550 functions as a gate insulating layer, and diffusion of In can cause poor transistor characteristics. Therefore, by forming the semiconductor layer 520c into a stacked structure, a highly reliable semiconductor device can be provided.

[0232] A conductive layer 542 (a conductive layer 542a and a conductive layer 542b) functioning as a source electrode and a drain electrode is provided over the semiconductor layer 520b. When an oxide semiconductor is used for the semiconductor layer 520b, the conductive layer 542 is preferably made of a conductive material that is not easily oxidized or that maintains its conductivity even when it absorbs oxygen.

[0233] A region of the semiconductor layer 520 in contact with the conductive layer 542 functions as a source region or a drain region of the transistor 200E. Here, the region between the conductive layer 542a and the conductive layer 542b is formed to overlap with the opening of the insulating layer 580. This allows the conductive layer 560 to be disposed in a self-aligned manner between the conductive layer 542a and the conductive layer 542b.

[0234] The insulating layer 550 functions as a gate insulating layer. The insulating layer 550 is disposed in contact with the top surface of the semiconductor layer 520c. The insulating layer 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. For example, silicon oxide or silicon oxynitride is used as the insulating layer 550.

[0235] The insulating layer 550 is formed using an insulating material in which the concentration of impurities such as water or hydrogen is reduced, similarly to the insulating layer 524. The thickness of the insulating layer 550 is 1 nm to 20 nm.

[0236] A metal oxide may be provided between the insulating layer 550 and the conductive layer 560. The metal oxide suppresses oxygen diffusion from the insulating layer 550 to the conductive layer 560. This can suppress oxidation of the conductive layer 560 due to oxygen contained in the insulating layer 550.

[0237] Although the conductive layer 560 is shown as a two-layer structure in FIGS. 28A to 28C, a single-layer structure or a stacked structure of three or more layers can also be used.

[0238] The conductive layer 560a is formed of the above-mentioned hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive layer having a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0239] The conductive layer 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 550. Examples of conductive materials that can suppress oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0240] The conductive layer 560b can be formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 560 also functions as wiring, it is preferable to use a conductive layer with high conductivity. Furthermore, the conductive layer 560b can have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0241] 28B and 28C , in a region of the semiconductor layer 520b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 520, the side surface of the semiconductor layer 520 is arranged to be covered with the conductive layer 560. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 200E, to act on the side surface of the semiconductor layer 520. This increases the on-state current of the transistor 200E, and improves its frequency characteristics.

[0242] Like the insulating layer 514, the insulating layer 554 is made of an insulating material that prevents impurities such as water or hydrogen from entering the transistor 200E from the insulating layer 580 side. For example, the insulating layer 554 is made of an insulating material that has lower hydrogen permeability than the insulating layer 524. Furthermore, as shown in FIGS. 28B and 28C , the insulating layer 554 is provided in contact with the side surfaces of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524. This structure can prevent hydrogen contained in the insulating layer 580 from entering the semiconductor layer 520 from the top surfaces or side surfaces of the conductive layer 542a, the conductive layer 542b, the semiconductor layer 520a, the semiconductor layer 520b, and the insulating layer 524.

[0243] Furthermore, an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., oxygen is less likely to permeate) is used for the insulating layer 554. For example, an insulating material that has lower oxygen permeability than the insulating layer 580 or the insulating layer 524 is used for the insulating layer 554.

[0244] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layer 554 can be formed by a sputtering method. By forming the insulating layer 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 524 near a region in contact with the insulating layer 554. This allows oxygen to be supplied from this region into the semiconductor layer 520 through the insulating layer 524. The insulating layer 554 has a function of suppressing upward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. The insulating layer 522 has a function of suppressing downward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520, thereby preventing the transistor from becoming normally on.

[0245] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium is formed as the insulating layer 554. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like can be used.

[0246] The insulating layer 580 is provided over the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 with the insulating layer 554 interposed therebetween. For example, the insulating layer 580 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly suitable because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly suitable because they can easily form a region containing oxygen that is released by heating.

[0247] The insulating layer 574, like the insulating layer 514, is formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulating layer 580 from above. The insulating layer 574 is formed using an insulating material that can be used for the insulating layer 514, the insulating layer 554, and the like, for example.

[0248] 28A to 28C show an example in which an insulating layer 581 functioning as an interlayer film is provided over the insulating layer 574. As the insulating layer 581, an insulating material in which the concentration of impurities such as water or hydrogen is reduced is used, similar to the insulating layer 524 and the like.

[0249] The conductive layers 545a and 545b are disposed in openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554. The conductive layers 545a and 545b are provided opposite to each other with the conductive layer 560 interposed therebetween. Note that the top surfaces of the conductive layers 545a and 545b are preferably flush with the top surface of the insulating layer 581.

[0250] Note that an insulating layer 541a is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545a is formed in contact with the side surface of the insulating layer 541a. A conductive layer 542a is located in at least a part of the bottom of the opening, and the conductive layer 545a is in contact with the conductive layer 542a. Similarly, an insulating layer 541b is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545b is formed in contact with the side surface of the insulating layer 541b. A conductive layer 542b is located in at least a part of the bottom of the opening, and the conductive layer 545b is in contact with the conductive layer 542b.

[0251] The conductive layers 545a and 545b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Each of the conductive layers 545a and 545b can have a stacked structure of two or more layers.

[0252] When the conductive layer 545 has a stacked structure, a conductive layer having a function of suppressing diffusion of impurities such as water or hydrogen may be used for the conductive layers in contact with the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542, the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is used. By using such a conductive material, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b. Furthermore, impurities such as water or hydrogen from above the insulating layer 581 can be prevented from entering the semiconductor layer 520 through the conductive layers 545a and 545b.

[0253] The insulating layers 541a and 541b may be, for example, insulating layers that can be used for the insulating layer 554. The insulating layers 541a and 541b are provided in contact with the insulating layer 554, and therefore can prevent impurities such as water or hydrogen from the insulating layer 580 or the like from entering the semiconductor layer 520 through the conductive layers 545a and 545b. Furthermore, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b.

[0254] <Transistor Configuration Example 6> A modification of the transistor 200E shown in FIG. 28 is shown in FIG. 29. FIG. 29A is a plan view of a transistor F which is a modification of the transistor 200E. FIG. 29B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in FIG. 29A. FIG. 29C is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in FIG. 29A. Since the transistor F is a modification of the transistor 200E, differences between the transistor F and the transistor 200E will be mainly described.

[0255] The transistor F has a structure in which the semiconductor layer 520c and the conductive layer 505c are removed from the structure of the transistor 200E. Reducing the number of components of the transistor reduces production costs. Furthermore, reducing the number of components of the transistor shortens the manufacturing process, improving manufacturing yield.

[0256] Furthermore, the transistor F has a region where the insulating layer 554 and the insulating layer 522 are in contact with each other outside the semiconductor layer 520, and the side surface of the insulating layer 524 is covered with the insulating layer 554. When an oxide semiconductor is used for the semiconductor layer 520, covering the side surface of the insulating layer 524 with the insulating layer 554 not only prevents oxygen from diffusing to the outside through the insulating layer 524 but also prevents excessive oxygen from being supplied to the semiconductor layer 520 from the insulating layer 524 side.

[0257] Note that an insulating layer is preferably provided between the insulating layer 580, the insulating layer 554, the conductive layer 542, and the semiconductor layer 520b and the insulating layer 550. Aluminum oxide, hafnium oxide, or the like is preferably used for the insulating layer. By providing the insulating layer, it is possible to suppress desorption of oxygen from the semiconductor layer 520 to the insulating layer 550, excessive supply of oxygen from the insulating layer 550 to the semiconductor layer 520, oxidation of the conductive layer 542, and the like.

[0258] <Transistor Configuration Example 7> FIG. 30A is a plan view of a transistor 200G that can be used in a semiconductor device of one embodiment of the present invention. FIG. 30B is a schematic perspective view of the transistor 200G. FIGS. 30C to 30E are cross-sectional views of the transistor 200G. FIG. 30C is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 30A and is also a cross-sectional view of the transistor 200G in the channel width direction (Y direction). FIG. 30D is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 30A and is also a cross-sectional view of the transistor 200G in the channel width direction. FIG. 30E is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 30A and is also a cross-sectional view of the transistor 200G in the channel length direction (X direction). Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that some components are omitted from the plan view of FIG. 30A and the perspective schematic view of FIG. 30B. Also, FIG. 31A shows an enlarged view of the vicinity of the conductive layer 260 in FIG. 30E. Also, FIG. 31B shows an enlarged view of the vicinity of the semiconductor layer 230 in FIG. 30C.

[0259] The transistor 200G according to this embodiment includes an insulating layer 295 on a substrate (not shown), an insulating layer 296 on the insulating layer 295, an insulating layer 291 on the insulating layer 296, an insulating layer 292 on the insulating layer 291, a semiconductor layer 230 on the insulating layer 292, conductive layers 242a and 242b on the semiconductor layer 230 and the insulating layer 292, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 (conductive layer 260a and conductive layer 260b) on the insulating layer 250. Note that in this specification, the conductive layer 242a and the conductive layer 242b may be collectively referred to as the conductive layer 242.

[0260] An insulating layer 235 is provided on the conductive layer 242, and an insulating layer 280 is provided on the insulating layer 235. The insulating layer 250 and the conductive layer 260 are provided inside a first opening that penetrates the insulating layer 280 and the insulating layer 235 and reaches the semiconductor layer 230. In a plan view, the first opening has a region overlapping with the semiconductor layer 230 and a region extending in the Y direction beyond the edge of the semiconductor layer 230. Therefore, in a plan view, the insulating layer 250 and the conductive layer 260 provided inside the first opening also have a region overlapping with the semiconductor layer 230 and a region extending in the Y direction beyond the edge of the semiconductor layer 230. The conductive layer 260 also functions as wiring. The insulating layer 250 has a region in contact with the semiconductor layer 230 within the first opening. Furthermore, an insulating layer 297 is provided on the insulating layer 280 and the conductive layer 260. Furthermore, an insulating layer 298 is provided on the insulating layer 297.

[0261] Furthermore, insulating layer 241a is provided in contact with the inner wall of the second opening, which penetrates insulating layer 298, insulating layer 297, insulating layer 280, and insulating layer 235 and reaches conductive layer 242a, and conductive layer 245a is provided in contact with insulating layer 241a. Conductive layer 245a has a region in contact with conductive layer 242a at the bottom of the first opening.

[0262] Furthermore, insulating layer 241b is provided in contact with the inner wall of the third opening, which penetrates insulating layer 298, insulating layer 297, insulating layer 280, and insulating layer 235 to reach conductive layer 242b, and conductive layer 245b is provided in contact with insulating layer 241b. Conductive layer 245b has a region in contact with conductive layer 242b at the bottom of the second opening.

[0263] In this specification, the conductive layers 245a and 245b may be collectively referred to as conductive layers 245. The insulating layers 241a and 241b may be collectively referred to as insulating layers 241.

[0264] The semiconductor layer 230 includes a channel formation region of the transistor 200G. The conductive layer 260 has a region that functions as a gate electrode of the transistor 200G. The insulating layer 250 has a region that functions as a gate insulating layer of the transistor 200G. In the transistor 200G, a region of the semiconductor layer 230 that overlaps with the conductive layer 260 functions as a channel formation region. A region of the conductive layer 260 that overlaps with the semiconductor layer 230 functions as a gate electrode. A region of the insulating layer 250 where the insulating layer 250 and the semiconductor layer 230 overlap and where the insulating layer 250 and the conductive layer 260 overlap functions as a gate insulating layer.

[0265] The conductive layer 242a has a region functioning as one of the source electrode and the drain electrode of the transistor 200G. The conductive layer 245a functions as a plug connected to the conductive layer 242a. The conductive layer 242b has a region functioning as the other of the source electrode and the drain electrode of the transistor 200G. The conductive layer 245b functions as a plug connected to the conductive layer 242b.

[0266] The semiconductor layer 230 is formed on the insulating layer 292. As shown in FIG. 31B , the semiconductor layer 230 has a shape with a high aspect ratio when viewed cross-sectionally in the channel width direction. For this reason, the semiconductor layer 230 can also be said to have a fin-like shape. A transistor whose semiconductor layer is fin-shaped is also called a "fin transistor," "fin transistor," or "fin transistor."

[0267] Specifically, a Fin-type transistor is a transistor in which, in a cross-sectional view in the channel width direction (Y direction), the channel formation region of the semiconductor layer has two regions (two surfaces) extending in the Z direction, and has a shape in which a length H (described later) is greater than a length Lx (described later). In a cross-sectional view in the channel width direction, a shape in which the length H is greater than the length Lx is preferable because it allows the channel width per unit area to be increased.

[0268] In this specification, the maximum length of the semiconductor layer 230 in the Y direction in the channel formation region is defined as length Lx, and the maximum length of the semiconductor layer 230 in the channel formation region in a direction perpendicular to the surface on which it is formed (e.g., the top surface of the insulating layer 292) is defined as length H.

[0269] The length Lx can also be considered to be the maximum width of the semiconductor layer 230 in the channel formation region. Therefore, "length Lx" can be read as "width Lx." The length H can also be considered to be the maximum height of the semiconductor layer 230 in the channel formation region. Therefore, "length H" can be read as "height H."

[0270] The ratio of the length H to the length Lx is referred to as the aspect ratio of the semiconductor layer 230. The aspect ratio of the semiconductor layer 230 is preferably as large as possible without causing the semiconductor layer 230 to collapse during the manufacturing process of the transistor 200G. The aspect ratio of the semiconductor layer 230 is preferably greater than 1 and less than 400, more preferably greater than 2 and less than 100, more preferably greater than 5 and less than 40, and even more preferably greater than 10 and less than 20. That is, in the channel formation region of the semiconductor layer 230, the height H of the semiconductor layer 230 is preferably at least longer than the length Lx of the semiconductor layer 230. The height H of the semiconductor layer 230 is preferably greater than 1 and less than 400 times the length Lx of the semiconductor layer 230, more preferably greater than 2 and less than 100 times, more preferably greater than 5 and less than 40 times, and even more preferably greater than 10 and less than 20 times. For example, the height H is preferably greater than 2 and less than 10 times the length Lx. For example, the length Lx is preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 50 nm or less, and even more preferably 10 nm or more and 30 nm or less. Also, for example, the height H is preferably 50 nm or more and 2000 nm or less, and more preferably 100 nm or more and 1000 nm or less. Also, for example, the height H can be 50 nm or more and 100 nm or less.

[0271] 31B , in a cross-sectional view in the channel width direction, it is preferable that the angle θ between the formation surface of the semiconductor layer 230 on the insulating layer 292 and the side surface of the semiconductor layer 230 is perpendicular or approximately perpendicular. For example, it is preferable that the angle θ is 80° or more and 100° or less, and more preferably 85° or more and 95° or less.

[0272] An insulating layer 250, a conductive layer 260, and a conductive layer 242 are provided to cover the semiconductor layer 230 having such an aspect ratio. In the transistor 200G, as shown in FIG. 31B , a portion of the insulating layer 250 and a portion of the conductive layer 260 are provided so as to sandwich the semiconductor layer 230 in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 230 and the conductive layer 260 are provided facing each other with the insulating layer 250 sandwiched between the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 230. In other words, the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 230 each function as a channel formation region. Therefore, compared to when the semiconductor layer 230 is formed in a planar shape, the channel width of the transistor 200G is larger by the amount of the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 230.

[0273] By increasing the channel width as described above, the on-state current, transconductance, frequency characteristics, and the like of the transistor 200G can be improved. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, in the above structure, by providing the semiconductor layer 230, the channel width can be increased without increasing the area occupied by the transistor 200G. This allows for miniaturization or high integration of the semiconductor device.

[0274] Furthermore, as shown in FIG. 31B and other figures, it is preferable that the upper portion of the semiconductor layer 230 has a curved shape. Such a curved shape can prevent defects such as voids from forming in the insulating layer 250 and the conductive layer 242 near the upper portion of the semiconductor layer 230. Note that in FIG. 31B and other figures, a symmetrical structure is shown in which curved shapes are provided on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the semiconductor layer 230, but the present invention is not limited to this. For example, an asymmetrical structure may also be used in which a curved shape is provided on either the A1 side (A3 side) or the A2 side (A4 side) of the upper portion of the semiconductor layer 230.

[0275] When an oxide semiconductor is used as the semiconductor layer 230, as shown in FIGS. 31A and 31B, a configuration including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c disclosed in the third embodiment can be applied.

[0276] 31A and 31B , when an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 250 preferably has a stacked structure of an insulating layer 250a in contact with the semiconductor layer 230, an insulating layer 250b on the insulating layer 250a, an insulating layer 250c on the insulating layer 250b, and an insulating layer 250d on the insulating layer 250c. In this case, the insulating layer 250a and the insulating layer 250c preferably have a function of capturing hydrogen or fixing hydrogen.

[0277] Examples of insulating layers having the function of capturing or fixing hydrogen include metal oxides having an amorphous structure. For the insulating layer 250a and the insulating layer 250c, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0278] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulating layer 250a and the insulating layer 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 250a and the insulating layer 250c makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulating layer that functions as the gate insulating layer.

[0279] For the insulating layer 250a and the insulating layer 250c, an oxide containing one or both of aluminum and hafnium is preferably used, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used.

[0280] In this embodiment, an aluminum oxide film is used as the insulating layer 250a. The aluminum oxide preferably has an amorphous structure. By providing the insulating layer 250a in contact with the semiconductor layer 230, hydrogen contained in the semiconductor layer 230 and the like can be more effectively captured and fixed to the insulating layer 250a.

[0281] In this embodiment, hafnium oxide is used as the insulating layer 250 c. By providing the insulating layer 250 c between the insulating layer 250 b and the insulating layer 250 d, hydrogen contained in the insulating layer 250 b and the like can be more effectively captured and fixed.

[0282] Next, the insulating layer 250b is preferably an insulating layer that is stable to heat, such as silicon oxide or silicon oxynitride. The silicon oxide film used as the insulating layer 250b is preferably formed by a PEALD method.

[0283] In order to suppress oxidation of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260, it is preferable to provide a barrier insulating layer against oxygen in the vicinity of each of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260. In the semiconductor device described in this embodiment, the insulating layer is, for example, the insulating layer 250a, the insulating layer 250d, the insulating layer 250c, and the insulating layer 235.

[0284] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. In this specification and the like, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulating layer having barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulating layer. Furthermore, for example, an insulating layer having barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulating layer.

[0285] Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulating layer 250a, the insulating layer 250c, the insulating layer 250d, and the insulating layer 235 each preferably have a single-layer structure or a stacked-layer structure of the above-mentioned barrier insulating layer against oxygen.

[0286] The insulating layer 250a preferably has a barrier property against oxygen. The insulating layer 250a is preferably at least less permeable to oxygen than the insulating layer 280. The insulating layer 250a has a region in contact with the side surface of the conductive layer 242a and the side surface of the conductive layer 242b. The insulating layer 250a has a barrier property against oxygen, which can prevent the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and forming an oxide film on the side surface. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200G.

[0287] The insulating layer 250a is provided in contact with the top surface and side surfaces of the semiconductor layer 230 and the top surface of the insulating layer 292. The insulating layer 250a has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the semiconductor layer 230 during heat treatment or the like. Therefore, oxygen vacancies can be reduced in the semiconductor layer 230.

[0288] Furthermore, by providing the insulating layer 250a, it is possible to suppress the supply of an excessive amount of oxygen from the insulating layer 280 to the semiconductor layer 230, and to supply an appropriate amount of oxygen to the semiconductor layer 230. Therefore, it is possible to suppress the source region and the drain region from being excessively oxidized, which would result in a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200G.

[0289] An oxide containing one or both of aluminum and hafnium has barrier properties against oxygen and is therefore suitable for the insulating layer 250a.

[0290] The insulating layer 250d also preferably has a barrier property against oxygen. The insulating layer 250d is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260 and between the insulating layer 280 and the conductive layer 260. This structure can prevent oxygen contained in the channel formation region of the semiconductor layer 230 from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, it can prevent oxygen contained in the semiconductor layer 230 and oxygen contained in the insulating layer 280 from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250d is preferably at least less permeable to oxygen than the insulating layer 280. For example, a silicon nitride film is preferably used as the insulating layer 250d. In this case, the insulating layer 250d is an insulating layer containing at least nitrogen and silicon.

[0291] Furthermore, the insulating layer 250d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0292] The insulating layer 235 also preferably has a barrier property against oxygen. The insulating layer 235 is provided between the insulating layer 280 and the conductive layer 242a and between the insulating layer 280 and the conductive layer 242b. The insulating layer 235 is provided in contact with the side surface of the conductive layer 242, the side surface of the semiconductor layer 230, and the top surface of the insulating layer 292. This configuration can prevent oxygen contained in the insulating layer 280 from diffusing into the conductive layer 242. Therefore, it is possible to prevent the conductive layer 242 from being oxidized by the oxygen contained in the insulating layer 280 and its resistivity from increasing. The insulating layer 235 is preferably at least less permeable to oxygen than the insulating layer 280. For example, it is preferable to use silicon nitride as the insulating layer 235. In this case, the insulating layer 235 is an insulating layer containing at least nitrogen and silicon.

[0293] In order to suppress a decrease in the hydrogen concentrations in the source and drain regions in the semiconductor layer 230, it is preferable to provide a barrier insulating layer against hydrogen near each of the source and drain regions. In the semiconductor device described in this embodiment, the barrier insulating layer against hydrogen is, for example, the insulating layer 235.

[0294] Examples of the barrier insulating layer against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulating layer 235 preferably has a single-layer structure or a stacked-layer structure of the above-mentioned barrier insulating layers against hydrogen.

[0295] By providing the insulating layer 235 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions, thereby making the source and drain regions n-type.

[0296] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200G can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0297] The insulating layers 250a to 250d function as part of a gate insulating layer. The insulating layers 250a to 250d, together with the conductive layer 260, are provided in an opening formed in the insulating layer 280. To miniaturize the transistor 200G, the insulating layers 250a to 250d are preferably thin. The thicknesses of the insulating layers 250a to 250d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulating layers 250a to 250d may have a region with the above-described thickness at least in part.

[0298] The thickness of the silicon oxide film used as the insulating layer 250 is preferably 0.7 nm or more and 3 nm or less.

[0299] In order to thin the insulating layers 250a to 250d as described above, it is preferable to form the insulating layers 250a to 250d by using the ALD method. Furthermore, it is preferable to form the insulating layers 250a to 250d by using the ALD method in order to provide the insulating layers 250a to 250d in openings in the insulating layer 280, etc. By forming the insulating layers 250 by using the ALD method, it is possible to form the insulating layer 250 with good coverage on the side surfaces of the first openings formed in the insulating layer 280, the side edges of the conductive layers 242a and 242b, and the like.

[0300] Although the insulating layer 250 has been described above as having a four-layer structure of the insulating layers 250a to 250d, the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250a to 250d. By forming the insulating layer 250 using one, two, or three of the insulating layers 250a to 250d, the manufacturing process of the transistor 200G can be simplified and the productivity of a semiconductor device including the transistor 200G can be improved.

[0301] As shown in FIG. 30A , the shape of the semiconductor layer 230 in a planar view is preferably a circumferential shape (which can also be referred to as a frame shape, an annular shape, a doughnut shape, or a closed curve shape) with both ends coinciding. That is, it is preferable that the semiconductor layer 230 has a structure including a plurality of portions extending in the channel width direction (A1-A2 direction) and a plurality of portions extending in the channel length direction (A5-A6 direction). This can prevent the semiconductor layer 230 from collapsing during the transistor fabrication process when the aspect ratio of the semiconductor layer 230 is increased. Note that the semiconductor layer 230 shown in FIG. 30A can also be described as having a shape with an opening in the center. In FIG. 30A , the shape of the semiconductor layer 230 in a planar view is line-symmetrical about the A1-A2 axis, but the present invention is not limited to this. For example, the shape of the semiconductor layer 230 in a planar view may be asymmetrical.

[0302] The structure shown in Fig. 30A is a structure in which two peripheral semiconductor layers 230 are formed in the Y direction. As shown in Fig. 30A, the semiconductor layer 230 preferably overlaps with the conductive layer 260 at two or more locations in a plan view. Therefore, the conductive layer 260 preferably has two or more regions that overlap with the semiconductor layer 230. In other words, it is preferable that the semiconductor layer 230 and the conductive layer 260 have two or more regions where they overlap with each other.

[0303] With this structure, as shown in FIG. 30B , multiple fin-shaped semiconductor layers 230 are formed in a cross-sectional view in the channel width direction. Each of the multiple fin-shaped semiconductor layers 230 includes a channel formation region. That is, the transistor 200G functions as a multi-channel transistor. Therefore, the channel width of the transistor 200G can be further increased, thereby increasing the on-state current. This allows the operating speed of a semiconductor device including the transistor 200G to be increased.

[0304] Although the above description has been given of a configuration in which two circumferential semiconductor layers 230 are provided, the present invention is not limited to this. For example, a configuration in which one or three or more circumferential semiconductor layers 230 are provided is possible. It is also possible to combine the circumferential semiconductor layers 230 to form a semiconductor layer 230 having a shape with a plurality of openings. It is also possible to use a semiconductor layer 230 that is shaped like a lattice in plan view.

[0305] <Transistor Configuration Example 8> Next, a transistor 200H, which is a variation of the transistor 200G, will be described. FIG. 32A is a plan view of the transistor 200H that can be used in a semiconductor device of one embodiment of the present invention. FIG. 32B is a schematic perspective view of the transistor 200H. FIGS. 32C to 32E are cross-sectional views of the transistor 200H. FIG. 32C is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 32A and is also a cross-sectional view of the transistor 200H in the channel width direction (Y direction). FIG. 32D is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 32A and is also a cross-sectional view of the transistor 200H in the channel width direction. FIG. 32E is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 32A and is also a cross-sectional view of the transistor 200H in the channel length direction (X direction). Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the plan view of Figure 32A and the schematic perspective view of (B), some components are omitted. Also, Figure 33 shows an enlarged view of the semiconductor layer 230 of Figure 32C.

[0306] 32B to 32E , an insulating layer 294 can be provided under the semiconductor layer 230. The planar shape of the insulating layer 294 (the shape when viewed from the Z direction) is the same as that of the semiconductor layer 230. Therefore, in a planar view, the insulating layer 294 overlaps with the semiconductor layer 230. The lower surface of the insulating layer 294 is in contact with the insulating layer 292, the side surface of the insulating layer 294 is in contact with the insulating layer 250 and the conductive layer 242a, and the upper surface of the insulating layer 294 is in contact with the lower surface of the semiconductor layer 230. The insulating layer 294 may be made of an insulating material that can be used for the insulating layer 250b. For example, silicon oxide can be used for the insulating layer 294.

[0307] 32A to 32E correspond to Fig. 30A to 30E. Also, Fig. 33 corresponds to Fig. 31B. Therefore, matters not explained below regarding the configurations according to Fig. 32A to 32E and Fig. 33 can be understood by referring to the explanations given above regarding Fig. 30A to 30E and Fig. 31B.

[0308] 33 , it is preferable that the thickness t2 of the insulating layer 250 at the bottom of the first opening be thinner than the thickness t1 (the length of the insulating layer 294 in the direction perpendicular to the surface on which it is formed) of the insulating layer 294. With this configuration, the lower surface of the conductive layer 260 (conductive layer 260 a) located in the first opening can be positioned lower than the lower surface of the semiconductor layer 230 by the difference (t1 − t2) between the thickness t1 and the thickness t2.

[0309] By positioning the lower surface of the conductive layer 260 below the lower surface of the semiconductor layer 230, a sufficient gate electric field can be applied from the upper end to the lower end of the semiconductor layer 230. In other words, within the opening of the insulating layer 280 or the like, the entire semiconductor layer 230 is electrically surrounded by the electric field of the conductive layer 260, allowing it to function as a channel formation region. This configuration prevents the lower end of the semiconductor layer 230 from functioning as a parasitic channel, thereby reducing leakage current between the source electrode and the drain electrode. Furthermore, it is possible to suppress characteristic defects, such as normally-on transistors, that are caused by the parasitic channel. In other words, the electrical characteristics of the transistor 200H can be improved.

[0310] Furthermore, as described above, the channel width can be increased by making the semiconductor layer 230 function as a channel formation region from the top end to the bottom end, which can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200H.

[0311] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is arranged so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to provide a transistor in which the short channel effect is less likely to occur.

[0312] Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming the transistor 200H in the S-channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between the semiconductor layer 230 and the insulating layer 250, which functions as a gate insulating layer, can be the entire bulk of the semiconductor layer 230. Therefore, the current density flowing through the transistor can be improved, which is expected to improve the on-state current or the field-effect mobility of the transistor. In one embodiment of the present invention, the semiconductor layer 230 has a CAAC structure and a fin-like structure. With this structure, the current paths flowing to the source and drain of the transistor can be parallel to the ab plane of the crystal axis. In other words, an oxide semiconductor having a CAAC structure and a fin-like structure has a conduction path equivalent to that of a two-dimensional semiconductor material, and by using such an oxide semiconductor, a device having two-dimensional conduction can be fabricated.

[0313] <Transistor Configuration Example 9> A transistor 200I, which is a variation of the transistor 200G, is shown in Figures 34A to 34E. The transistor 200I differs from the transistor 200G in that a conductive layer 205 is provided under an insulating layer 291. Figures 34A to 34E correspond to Figures 30A to 30E. Matters not described below regarding the configurations in Figures 34A to 34E can be understood with reference to the description of Figures 30A to 30E above.

[0314] The conductive layer 205 has a region overlapping with the channel formation region of the semiconductor layer 230. Thus, the conductive layer 205 has a region that functions as a gate electrode, similar to the conductive layer 260. The conductive layer 260 may be referred to as a first gate electrode (upper gate electrode) of the transistor 200I, and the conductive layer 205 may be referred to as a second gate electrode (lower gate electrode) of the transistor 200I. When the conductive layer 260 is referred to as a gate electrode of the transistor 200I, the conductive layer 205 may be referred to as a backgate electrode of the transistor 200I.

[0315] When the conductive layer 205 is provided under the insulating layer 291 as in the transistor 200I, each of the insulating layers 292 and 291 has a region that functions as a gate insulating layer, similar to the insulating layer 250. Specifically, a region of each of the insulating layers 292 and 291 that overlaps with the conductive layer 205 functions as a gate insulating layer. The insulating layer 250 may be referred to as a first gate insulating layer (upper gate insulating layer), and the insulating layer 292 and the insulating layer 291 may be referred to as a second gate insulating layer (lower gate insulating layer).

[0316] In the transistor 200I, the conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. In Figures 34C and 34E, the conductive layer 205 is provided inside a fourth opening that penetrates the insulating layer 296 and reaches the insulating layer 295. The fourth opening has, in a plan view, a region that overlaps with the semiconductor layer 230 and a region that extends along the Y direction beyond the end of the semiconductor layer 230. Therefore, the conductive layer 205 provided inside the fourth opening also has, in a plan view, a region that overlaps with the semiconductor layer 230 and a region that extends along the Y direction beyond the end of the semiconductor layer 230. The conductive layer 205 also functions as wiring.

[0317] 34C and 34E , the conductive layer 205 preferably includes a conductive layer 205a and a conductive layer 205b. The conductive layer 205a is provided in contact with the bottom and sidewalls of the fourth opening. The conductive layer 205b is provided so as to fill a recess in the conductive layer 205a formed along the bottom and sidewalls of the fourth opening. Here, it is preferable that the top surface of the conductive layer 205 coincides or substantially coincides with the top surface of the insulating layer 296. That is, when viewed from the Y direction, it is preferable that the shortest distance from the top surface of the substrate (not shown) to the top surface of the insulating layer 296 coincides or substantially coincides with the shortest distance from the top surface of the substrate to the top surface of the conductive layer 205.

[0318] Here, the conductive layer 205a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0319] By using a conductive material that has a function of reducing hydrogen diffusion for the conductive layer 205a, impurities such as hydrogen contained in the conductive layer 205b can be prevented from diffusing into the semiconductor layer 230 via the insulating layer 296 or the like. Furthermore, by using a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 205a, it is possible to suppress oxidation of the conductive layer 205b and a decrease in conductivity. Examples of conductive materials that have a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 205a preferably contains titanium nitride.

[0320] The conductive layer 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0321] As described above, the conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200I can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200I and reduce its off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential of the conductive layer 260 is 0 V compared to not applying a negative potential to the conductive layer 205.

[0322] The electrical resistivity of the conductive layer 205 is designed taking into consideration the potential applied to the conductive layer 205, and the film thickness of the conductive layer 205 is set to match the electrical resistivity. The film thickness of the insulating layer 296 is approximately the same as that of the conductive layer 205. Here, it is preferable to make the film thicknesses of the conductive layer 205 and the insulating layer 296 thin within the range permitted by the design of the conductive layer 205. By making the film thickness of the insulating layer 296 thin, the absolute amount of impurities such as hydrogen contained in the insulating layer 296 can be reduced, and therefore, the diffusion of the impurities into the semiconductor layer 230 can be suppressed.

[0323] Although the above describes a stacked structure of the conductive layer 205a and the conductive layer 205b, the present invention is not limited to this, and the conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductive layer 205 has a three-layer stacked structure, the stacked structure of the conductive layer 205a and the conductive layer 205b may further include a conductive layer made of the same material as the conductive layer 205a on the conductive layer 205b. In this case, the conductive layer can be formed so that the top surface of the conductive layer 205b is lower than the top of the conductive layer 205a, and so as to fill the recess formed by the conductive layer 205a and the conductive layer 205b.

[0324] In addition to the materials disclosed in this embodiment, the materials for conductive layers shown in other embodiments can be used as materials for conductive layer 205, conductive layer 242, conductive layer 245, and conductive layer 260. In addition to the materials disclosed in this embodiment, the materials for insulating layer shown in other embodiments can be used as materials for insulating layer 295, insulating layer 296, insulating layer 291, insulating layer 292, insulating layer 241, insulating layer 250, insulating layer 235, insulating layer 280, insulating layer 297, and insulating layer 298.

[0325] The transistor 200I described in this embodiment can be used as a transistor included in the semiconductor device 10. The transistor 200I can have a large on-state current without increasing the occupation area.

[0326] <Constituent Materials of Transistor> Next, constituent materials that can be used for the transistor 200 (transistor 200A, transistor 200B, transistor 200C, transistor 200D, transistor 200E, transistor 200F, transistor 200G, transistor 200H, and transistor 200I) will be described.

[0327] [Substrate] When a transistor is provided on a substrate, the material used for the substrate is not particularly limited. The material used for the substrate is determined depending on the purpose, taking into consideration the presence or absence of light transparency and heat resistance sufficient to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used as the substrate. Examples of insulating substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates). Furthermore, semiconductor substrates, flexible substrates, resin substrates, and the like can also be used as the substrate.

[0328] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Furthermore, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0329] Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Also, there are substrates having metal nitrides, substrates having metal oxides, etc. Furthermore, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulator substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate.

[0330] Examples of materials that can be used for flexible substrates or resin substrates include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0331] By using the above materials for the substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is less likely to break can be provided. Furthermore, it is also possible to use a substrate on which elements are provided. Elements that can be provided on the substrate include capacitance elements, resistance elements, switching elements, light-emitting elements, memory elements, and the like.

[0332] [Insulating Layer] An inorganic insulating film is used for each of the insulating layers (insulating layer 202, insulating layer 204, insulating layer 206, insulating layer 209, insulating layer 295, insulating layer 296, insulating layer 291, insulating layer 292, insulating layer 294, insulating layer 241, insulating layer 257, insulating layer 250, insulating layer 258, insulating layer 258a, insulating layer 258b, insulating layer 259, insulating layer 264, insulating layer 266, insulating layer 268, insulating layer 516, insulating layer 235, insulating layer 280, insulating layer 297, insulating layer 298, insulating layer 522, insulating layer 524, insulating layer 541, insulating layer 554, insulating layer 580, insulating layer 574, insulating layer 581, etc.). Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminate films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of nitride oxide insulating films include silicon nitride oxide films and aluminum nitride oxide films. Furthermore, organic insulating films can also be used for insulating layers included in semiconductor devices.

[0333] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0334] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for insulating layers that function as gate insulating layers, such as insulating layer 204 and insulating layer 264, enables lower voltages during transistor operation while maintaining the physical film thickness. It also enables thinner equivalent oxide thickness (EOT) for the gate insulating layer. On the other hand, using a material with a low dielectric constant for an insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is important to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0335] Examples of high-dielectric-constant (high-k) materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0336] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0337] [Conductive Layer] For the conductive layers (conductive layer 205, conductive layer 208, conductive layer 219, conductive layer 242, conductive layer 245, conductive layer 255, conductive layer 260, conductive layer 267, conductive layer 261, conductive layer 265, conductive layer 505, conductive layer 545, conductive layer 560, etc.) used in the transistor 200, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. As the alloy containing any of the above metal elements, a nitride of the alloy or an oxide of the alloy can be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. It is also possible to use semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0338] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive layer formed using a conductive material containing oxygen may be referred to as an oxide conductive layer.

[0339] Conductive materials containing tungsten, copper or aluminum as a main component are preferred because they have high conductivity.

[0340] It is also possible to use a plurality of conductive layers formed from the above materials in a stacked state. For example, a stacked structure can be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. It is also possible to use a stacked structure by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. It is also possible to use a stacked structure by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0341] For example, when an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 203 of the transistor 200A or 200B, a conductive layer functioning as a gate electrode, such as the conductive layer 205 or the conductive layer 219, may have a stacked structure in which a material containing the metal element described above and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the semiconductor layer 203 side. By providing the conductive material containing oxygen on the semiconductor layer 203 side, oxygen desorbed from the conductive material is easily supplied to a channel formation region of the semiconductor layer 203.

[0342] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520, the conductive layers 208a, 208b, 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b are conductive layers in contact with the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520, respectively. Therefore, a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion may be used for each of the conductive layers. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b.

[0343] By using a conductive material containing oxygen for the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductivity can be maintained even if the conductive layers 208a, 208b, 255, 261, 542a, and 542b absorb oxygen. For example, even when an insulating layer containing excess oxygen is used as an insulating layer in contact with the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductivity of the conductive layers 208a, 208b, 255, 261, 542a, and 542b can be maintained, which is preferable. For each of the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b, for example, ITO, ITSO, IZO (registered trademark), or the like can be used.

[0344] [Semiconductor Layer] As the semiconductor layer (semiconductor layer 203, semiconductor layer 230, semiconductor layer 263, semiconductor layer 520, etc.), a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. Examples of the semiconductor material that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. Examples of the compound semiconductor include organic materials having semiconductor properties and metal oxides (also referred to as oxide semiconductors) having semiconductor properties. Note that these semiconductor materials can also contain impurities as dopants.

[0345] The semiconductor layer can be made of a semiconductor made of a single element or a compound semiconductor. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that oxide semiconductors are also a type of compound semiconductor. Note that it is also possible to incorporate impurities as dopants into these semiconductor materials.

[0346] When silicon is used for the semiconductor layer, examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0347] For example, by using silicon for the semiconductor layer 203 of the transistor 200A or 200B and adding phosphorus or arsenic as an n-type dopant to the regions 203a and 203c of the semiconductor layer 203, the transistor can function as an n-type transistor. Also, by adding boron as a p-type dopant to the regions 203a and 203c of the semiconductor layer 203, the transistor can function as a p-type transistor. When the regions 203a and 203c of the semiconductor layer 203 contain both an n-type dopant and a p-type dopant, the conductivity type with a higher dopant concentration is more likely to be realized.

[0348] Two-dimensional materials that function as semiconductors can also be used as the semiconductor layer of a transistor. Two-dimensional materials, also known as layered materials, are a general term for a group of materials with a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within a unit layer, i.e., high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the semiconductor layer, a transistor with a large on-state current can be provided.

[0349] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0350] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer, the band gap of the metal oxide is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the semiconductor layer, the off-state current of the transistor can be significantly reduced. Since an OS transistor has a small off-state current, the power consumption of the semiconductor device can be reduced. Note that the oxide semiconductor will be described in detail in Embodiment 3.

[0351] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0352] Embodiment 3 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0353] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of the crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a memory device including the transistor can be improved.

[0354] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0355] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0356] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0357] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide (InOx, where X is an arbitrary number), gallium oxide (GaOx, where X is an arbitrary number), and zinc oxide (ZnOx, where X is an arbitrary number). The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. Note that the element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0358] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO). Examples of the usable oxide include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of the usable oxide include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0359] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics. Note that even when the metal oxide is indium oxide, the transistor can have a large on-state current and high frequency characteristics.

[0360] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field-effect mobility of a transistor may be improved. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0361] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0362] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0363] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0364] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0365] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0366] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using at least two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed using at least two kinds of film formation methods may be referred to as a hybrid OS.

[0367] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by a first deposition method and then forming a metal oxide as a second layer on the first layer by a second deposition method. In this case, it is preferable to use a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed compared to the second deposition method as the first deposition method. By using a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed as the first deposition method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer, thereby increasing the crystallinity of the oxide semiconductor layer.

[0368] Examples of the first film formation method include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). Examples of wet methods include spray coating. The ALD and CVD methods are suitable as the first film formation method because they can reduce damage to the surface to be formed compared to the sputtering method described below.

[0369] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0370] The ALD method can deposit atoms layer by layer, which has the advantages of enabling ultrathin film formation, film formation on high aspect ratio structures or surfaces with large steps, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Furthermore, the PEALD method may be preferable in some cases because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used. However, since the ALD method employs one or both of a high substrate temperature condition during film formation and an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0371] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0372] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0373] Examples of the second film formation method include sputtering, pulsed laser deposition (PLD), etc. Metal oxides formed using the second film formation method tend to have a CAAC structure.

[0374] Note that the first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased using the second layer as a nucleus. This can increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0375] Furthermore, a third layer can be further formed on the second layer. Because the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0376] For example, the oxide semiconductor layer of one embodiment of the present invention can be fabricated by forming a metal oxide as a first layer by a first deposition method, forming a metal oxide as a second layer by a second deposition method, and forming a metal oxide as a third layer by the first deposition method. Specifically, an ALD method can be used as the first deposition method, and a sputtering method can be used as the second deposition method. The ALD method has better coverage than the sputtering method, and the use of the ALD method as the deposition method for the first layer and the third layer can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0377] [Method for Manufacturing Oxide Semiconductor Layer] The semiconductor layer 230, which is an oxide semiconductor layer, can be manufactured by, for example, forming a semiconductor layer 230a on the layer 229, which is a surface to be formed, by an ALD method, forming a semiconductor layer 230b, which is an oxide semiconductor layer, on the semiconductor layer 230a, which is an oxide semiconductor layer, by a sputtering method, and forming a semiconductor layer 230c, which is an oxide semiconductor layer, on the semiconductor layer 230b, by an ALD method. Furthermore, after forming the semiconductor layer 230, which is an oxide semiconductor layer, it is preferable to perform heat treatment. The heat treatment can improve the crystallinity of the semiconductor layer 230. The heat treatment here is not limited to heat treatment. For example, it may be heat applied during the manufacturing process.

[0378] The layer 229 corresponds to the insulating layer 202, the insulating layer 256, the insulating layer 258, or the like described in the above embodiments. The layer 229 does not need to be crystalline. When the layer 229 is crystalline, it may have a crystal structure with low lattice matching with the metal oxide contained in the semiconductor layer 230.

[0379] An example of a method for manufacturing the semiconductor layer 230 will be described with reference to FIGS. 35A to 35D and 36A to 36D.

[0380] When a metal oxide film is formed by a sputtering method, alloying may occur between components contained in the metal oxide film and components contained in the layer on which the film is formed due to damage caused by sputtering particles on the surface on which the film is formed or by energy imparted to the substrate by the sputtering particles, etc. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between components contained in the metal oxide film and components contained in the layer on which the film is formed.

[0381] Therefore, first, a semiconductor layer 230a is formed on the layer 229 by ALD (FIG. 35A), and then a semiconductor layer 230b is formed on the semiconductor layer 230a by sputtering (FIG. 35B).

[0382] In the method for forming an oxide semiconductor layer of one embodiment of the present invention, the semiconductor layer 230a is formed between the semiconductor layer 230b and the layer 229 by a deposition method that causes little damage to a surface on which the semiconductor layer 230a is formed. This suppresses alloying of components contained in the semiconductor layer 230 and components contained in the layer 229, thereby enabling the semiconductor layer 230 to have higher crystallinity.

[0383] By using the above configuration, the thickness of the alloyed region can be reduced, or made so thin that it is difficult to observe. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that Figures 35A and 35B show an example in which no alloyed region is formed between layer 229 and semiconductor layer 230a.

[0384] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0385] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the semiconductor layer 230a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (In, if the semiconductor layer 230a contains In) that is the main component of the semiconductor layer 230a but is not the main component of the layer that will become the surface (here, layer 229) becomes half-value is defined as the depth (position) of the interface between the region and the semiconductor layer 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the semiconductor layer 230a becomes half-value is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0386] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0387] For example, when a silicon oxide layer is used as the layer 229 and SIMS analysis is performed on the semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0×10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0388] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0389] By reducing the alloyed region, it becomes possible to form the CAAC structure near the surface to be formed. Here, "near the surface to be formed" refers to, for example, a region from more than 0 nm to 3 nm, preferably more than 0 nm to 2 nm, more preferably 1 nm to 2 nm, approximately perpendicularly from the surface to be formed of the semiconductor layer 230.

[0390] The CAAC structure near the formation surface can sometimes be confirmed by observation using a TEM. For example, in cross-sectional observation of the semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0391] When the semiconductor layer 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 35A , the semiconductor layer 230a may have a region having lower crystallinity than the semiconductor layer 230b.

[0392] The semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure.

[0393] When the semiconductor layer 230b is formed by sputtering, a mixed layer 231 is formed on or near the surface of the semiconductor layer 230a. Furthermore, when the semiconductor layer 230b is formed, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei, and at least a portion of the semiconductor layer 230a may be crystallized.

[0394] In forming the semiconductor layer 230b by a sputtering method, it is preferable to heat the substrate. In forming the metal oxide, by increasing the substrate temperature (stage temperature) during the formation of the metal oxide, it is possible to form a metal oxide with high crystallinity in some cases.

[0395] Next, a semiconductor layer 230c is formed on the semiconductor layer 230b by ALD (FIG. 35C). For the formation of the semiconductor layer 230c by ALD, the method for forming the semiconductor layer 230a can be referred to.

[0396] When the semiconductor layer 230c is formed on the semiconductor layer 230b having the CAAC structure by the ALD method, the semiconductor layer 230c may grow epitaxially using the semiconductor layer 230b as a nucleus. Therefore, when the semiconductor layer 230c is formed, the semiconductor layer 230c may have a region having the CAAC structure. Furthermore, it is preferable that the region having the CAAC structure is formed over the entire semiconductor layer 230c.

[0397] Next, a heat treatment step may be performed. This heat treatment step may increase the crystallinity of the region having the CAAC structure in the semiconductor layer 230c. Furthermore, if the region is formed only below the semiconductor layer 230c after film formation by the ALD method, this heat treatment step may cause the region to expand upward (FIG. 35D). That is, this heat treatment may cause the region having the CAAC structure to be formed throughout the entire semiconductor layer 230c.

[0398] Furthermore, it is preferable that at least a portion of the semiconductor layer 230a is converted into CAAC by this heat treatment process ( FIG. 35D ). It is expected that the CAAC conversion is facilitated by the mixed layer 231 formed in the semiconductor layer 230a during the deposition of the semiconductor layer 230b, which acts as a nucleus or seed. It is preferable that the region in the semiconductor layer 230a that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the layer 229.

[0399] Furthermore, because the CAAC is formed from the top to the bottom of the semiconductor layer 230a, the CAAC can be formed up to the vicinity of the layer 229 without being limited by the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the semiconductor layer 230a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0400] 35A to 35D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Also, FIGS. 35A to 35D can be regarded as conceptual diagrams illustrating a film formation model of a metal oxide according to one embodiment of the present invention. As shown in FIGS. 35A to 35D , the semiconductor layer 230a and the semiconductor layer 230c each have high crystallinity using the highly crystalline semiconductor layer 230b as a nucleus or seed. Specifically, the crystallinity of the semiconductor layer 230a may be increased by heat treatment during the formation of the semiconductor layer 230b or after the formation of the semiconductor layer 230c. The crystallinity of the semiconductor layer 230c may be increased by heat treatment during the formation of the semiconductor layer 230c or after the formation of the semiconductor layer 230c. The heat treatment has an assisting effect of increasing the crystallinity.

[0401] As described above, in the metal oxide film formation method of one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the semiconductor layer 230a and the semiconductor layer 230c here) can be increased by using the semiconductor layer 230b (i.e., CAAC) with high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown in a solid phase using the semiconductor layer 230b as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, i.e., a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC). Note that although FIGS. 36A to 36D illustrate a structure including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c, the present invention is not limited thereto. For example, the structure including the semiconductor layer 230a and the semiconductor layer 230b can also be an AG CAAC.

[0402] In the semiconductor layer 230, it is preferable that a region having a CAAC structure is widely present throughout the layer. Figure 36A shows the state in which the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c are each crystallized. At this time, the boundary between the semiconductor layer 230a and the semiconductor layer 230b may not be observed. Also, the boundary between the semiconductor layer 230b and the semiconductor layer 230c may not be observed. The semiconductor layer 230 may be expressed as a single layer whose interface is not clearly observed. The semiconductor layer 230 may be expressed as a single layer.

[0403] Furthermore, there are cases where a portion of the semiconductor layer 230a or the semiconductor layer 230c is not crystallized. The example shown in Fig. 36B shows a state in which the vicinity of the interface with the layer 229 in the semiconductor layer 230a is not crystallized. Fig. 36C shows a state in which the vicinity of the surface in the semiconductor layer 230c is not crystallized. Fig. 36D shows a state in which the vicinity of the interface of the semiconductor layer 230a with the layer 229 and the vicinity of the surface of the semiconductor layer 230c are not crystallized.

[0404] By increasing the crystallinity of the oxide semiconductor layer, an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, which is expected to make the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0405] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the semiconductor layer 230, the boundaries between the stacked semiconductor layers 230a, 230b, and 230c may not be visible. In particular, after heat treatment, it may be difficult to identify the boundaries between the stacked films. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, a TEM or the like.

[0406] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to become polycrystalline. The use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the semiconductor layer 230a and the semiconductor layer 230c, crystals that reflect the crystal orientation of the semiconductor layer 230b are formed, and polycrystallization can be suppressed.

[0407] Furthermore, it is preferable that the lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or the semiconductor layer 230c is small. This allows the semiconductor layer 230a or the semiconductor layer 230c to form crystals that reflect the orientation of the crystals of the semiconductor layer 230b. In this case, for example, in cross-sectional observation of the semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the semiconductor layer 230a or the semiconductor layer 230c.

[0408] As long as the lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or 230c is small, the crystal structure of the semiconductor layer 230a or 230c is not particularly limited. The crystal structure of the semiconductor layer 230a or 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0409] [Composition of Oxide Semiconductor Layer] As described above, the semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. The semiconductor layer 230b can be formed by, for example, a sputtering method. The semiconductor layer 230b preferably contains, for example, zinc. By containing zinc, the semiconductor layer 230b becomes a metal oxide with high crystallinity. Furthermore, the semiconductor layer 230b preferably contains an element M in addition to zinc. By containing the element M in the semiconductor layer 230b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, the reliability of a transistor using an oxide semiconductor layer can be improved. Specifically, the semiconductor layer 230b may be made of a metal oxide having an In:M:Zn = 1:1:1 atomic ratio or a composition thereabout, an In:M:Zn = 1:1:1.2 atomic ratio or a composition thereabout, an In:M:Zn = 1:1:0.5 atomic ratio or a composition thereabout, an In:M:Zn = 1:1:2 atomic ratio or a composition thereabout, an In:M:Zn = 4:2:3 atomic ratio or a composition thereabout, an In:M:Zn = 1:3:2 atomic ratio or a composition thereabout, or an In:M:Zn = 1:3:4 atomic ratio or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0410] The semiconductor layer 230b may be configured without the element M. For example, In—Zn oxide may be used. Specifically, the semiconductor layer 230b may have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used. The semiconductor layer 230b may also be configured with a trace amount of the element M. For example, the semiconductor layer 230b may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, the semiconductor layer 230b may have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0411] The semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having a high proportion of In. The semiconductor layer 230a and the semiconductor layer 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0412] The semiconductor layers 230a and 230c may be configured without the element M. For example, an In—Zn oxide may be used. Specifically, the composition may be an In:Zn=1:1 atomic ratio or a composition thereabout, an In:Zn=2:1 atomic ratio or a composition thereabout, or an In:Zn=4:1 atomic ratio or a composition thereabout. Alternatively, an indium oxide may be used. The semiconductor layers 230a and 230c may be configured with a trace amount of the element M. Specifically, the composition may be an In:Ga:Zn=4:0.1:1 atomic ratio or a composition thereabout, an In:Ga:Zn=2:0.1:1 atomic ratio or a composition thereabout, an In:Sn:Zn=4:0.1:1 atomic ratio or a composition thereabout, or an In:Sn:Zn=2:0.1:1 atomic ratio or a composition thereabout.

[0413] Increasing the zinc content of the oxide semiconductor can improve the crystallinity of the oxide semiconductor. It is particularly preferable that the semiconductor layer 230a contains zinc. For example, when the semiconductor layer 230a is formed by an ALD method and the semiconductor layer 230b is formed by a sputtering method, zinc contained in the semiconductor layer 230a may diffuse into the semiconductor layer 230b. This diffusion may occur during sputtering or subsequent heat treatment. The diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b is expected to improve the crystallinity. Alternatively, the diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b is expected to promote the lateral growth of crystal parts having c-axis orientation, thereby facilitating the formation of CAAC.

[0414] The semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having a higher proportion of In than the semiconductor layer 230b.

[0415] Alternatively, for example, a metal oxide having a higher Ga content than the semiconductor layer 230b can be used for the semiconductor layer 230a and the semiconductor layer 230c. For example, it is preferable to use a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout for the semiconductor layer 230a and the semiconductor layer 230c, respectively. Increasing the Ga content may result in the band gaps of the semiconductor layer 230a and the semiconductor layer 230c being larger than those of the semiconductor layer 230b. As a result, the semiconductor layer 230b is sandwiched between the semiconductor layer 230a and the semiconductor layer 230c, which have larger band gaps, and the semiconductor layer 230b functions primarily as a current path (channel). By sandwiching the semiconductor layer 230b between the semiconductor layers 230a and 230c, it is possible to reduce trap levels at the interface of the semiconductor layer 230b and in the vicinity thereof, thereby realizing a buried channel transistor in which the channel is kept away from the insulating layer interface, and thus increasing the field-effect mobility.

[0416] In the oxide semiconductor layer of one embodiment of the present invention, even when the semiconductor layers 230a and 230c are formed using compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the semiconductor layer 230b as a nucleus, so that the entire oxide semiconductor layer including the semiconductor layers 230a and 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the semiconductor layer 230a and the semiconductor layer 230c and the semiconductor layer 230b.

[0417] In particular, even when the semiconductor layers 230 a and 230 c have a high In content, the semiconductor layers can have suitable crystallinity for use as semiconductor layers of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0418] The semiconductor layer 230a and the semiconductor layer 230c may have different compositions.

[0419] The semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having the same composition as the semiconductor layer 230b.

[0420] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0421] The composition of the metal oxide used in the semiconductor layer 230 can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed using a combination of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0422] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0423] The crystal orientation can be obtained from a Fast Fourier Transform (FFT) pattern obtained by performing FFT processing on a TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0424] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystalline portion. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0425] The c-axis orientation rate can be calculated by calculating the proportion of c-axis oriented regions in a map showing crystal orientation. Here, the c-axis oriented regions are defined as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20° or less.

[0426] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be a circle with a diameter of 1.0 nm, for example. Note that the region where FFT is performed is not limited to a circle.

[0427] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0428] The c-axis orientation rates of the region formed as semiconductor layer 230a, the region formed as semiconductor layer 230b, and the region formed as semiconductor layer 230c are defined as Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0429] After the semiconductor layer 230 is fabricated, the boundaries between the semiconductor layers 230a, 230b, and 230c may not be clearly observed.

[0430] The semiconductor layer 230 of one embodiment of the present invention can be divided into three regions, namely, a first region, a second region, and a third region, starting from the top of the layer 229. Each region is a layer-like region.

[0431] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rates of the second region and the third region are each 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher.

[0432] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the semiconductor layer 230 .

[0433] Alternatively, the layer thickness in each region may be approximately the same, for example.

[0434] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0435] Fourth Embodiment In this embodiment, an example of a planar layout and an example of a cross-sectional structure of the semiconductor device 10A shown in FIG. 1 will be described.

[0436] In this embodiment, the case where the transistor 200A (see FIGS. 24A to 24C) described in Embodiment 2 is used as the transistors M1 to M5, the transistor M6[1], the transistor M6[2], the transistor M7[1], and the transistor M7[2] will be described. To reduce repetition of the description, the following mainly describes matters not described in other embodiments. For matters not described in this embodiment, the other embodiments can be used as reference.

[0437] Fig. 37 is a diagram showing an example of a planar layout of the semiconductor device 10A shown in Fig. 1. Fig. 38 is an enlarged view of a portion including transistor M1, transistor M3, and capacitance element C1 in Fig. 37. Fig. 39 is an enlarged view of a portion including transistor M6[1], transistor M6[2], and capacitance element C2 in Fig. 37. Fig. 40 is a cross-sectional view taken along the line A1-A2 indicated by the dashed-dotted line in Fig. 37. Fig. 41A is a cross-sectional view taken along the line A3-A4 indicated by the dashed-dotted line in Figs. 37 and 38. Fig. 41B is a cross-sectional view taken along the line A5-A6 indicated by the dashed-dotted line in Figs. 37 and 39.

[0438] The semiconductor device 10A described in this embodiment includes, over the insulating layer 204, a conductive layer 271, a conductive layer 272, a conductive layer 273, a conductive layer 274, a conductive layer 275, a conductive layer 276, a conductive layer 277, a conductive layer 278, a conductive layer 279, a conductive layer 281, a conductive layer 282, a conductive layer 283, a conductive layer 284, a conductive layer 285, a conductive layer 286, and a conductive layer 287.

[0439] Further, over the insulating layer 206, a conductive layer 211 (conductive layer 211[1], conductive layer 211[2]), a conductive layer 212 (conductive layer 212[1], conductive layer 212[2]), a conductive layer 213 (conductive layer 213[1], conductive layer 213[2]), a conductive layer 214 (conductive layer 214[1], conductive layer 214[2]), a conductive layer 215 (conductive layer 215[1], conductive layer 215[2]), a conductive layer 216 (conductive layer 216[1], conductive layer 216[2]), a conductive layer 217, a conductive layer 238, a conductive layer 220, a conductive layer 221, a conductive layer 222, a conductive layer 223, a conductive layer 224, and a conductive layer 228 are provided.

[0440] These conductive layers can be formed using the materials shown in Embodiment Mode 2.

[0441] The conductive layer 211[1] is connected to the conductive layer 211[2] through the conductive layer 271. Specifically, openings 225 and 226 are provided in parts of the insulating layer 206 in regions overlapping with the conductive layer 271, and the conductive layer 211[1] and the conductive layer 271 are in contact with each other in the region overlapping with the opening 225, and the conductive layer 211[2] and the conductive layer 271 are in contact with each other in the region overlapping with the opening 226 (see FIGS. 37 and 40).

[0442] 37 and 40 show an example in which the conductive layer 211[1] and the conductive layer 271 contact each other at the bottom of one opening 225, but it is possible to provide multiple openings 225. By providing multiple openings 225, the contact area between the conductive layer 211[1] and the conductive layer 271 increases. Therefore, the contact resistance between the conductive layer 211[1] and the conductive layer 271 can be reduced. Similarly, by providing multiple openings 226, the contact area between the conductive layer 211[2] and the conductive layer 271 increases. Therefore, the contact resistance can be reduced. The conductive layer 211[1], the conductive layer 271, and the conductive layer 211[2] function as wiring GW. Therefore, in FIG. 37, the wiring GW extends in the X direction.

[0443] Furthermore, the conductive layer 211[2] is connected to the conductive layer 277. Specifically, an opening 227 is provided in part of the insulating layer 206 in a region overlapping with the conductive layer 277, and the conductive layer 211[2] and the conductive layer 277 are in contact with each other in the region overlapping with the opening 227. A part of the conductive layer 277 functions as the gate electrode of the transistor M2. Therefore, a part of the conductive layer 277 functions as the conductive layer 205 of the transistor M2. Note that although FIGS. 37 and 40 show an example in which the conductive layer 211[2] and the conductive layer 277 are in contact with each other at the bottom of one opening 227, multiple openings 227 can be provided. By providing multiple openings 227, the contact area between the conductive layer 211[2] and the conductive layer 277 increases. Therefore, the contact resistance between the conductive layer 211[2] and the conductive layer 277 can be reduced.

[0444] The conductive layer 212[1] is connected to the conductive layer 212[2] via the conductive layer 272. The conductive layer 212[1], the conductive layer 272, and the conductive layer 212[2] function as the wiring ELVDD. Therefore, in FIG. 37, the wiring ELVDD extends in the X direction. A part of the conductive layer 212[2] functions as one electrode of the capacitor C1. Another part of the conductive layer 212[2] functions as one of the source and drain electrodes of the transistor M1. Therefore, the other part of the conductive layer 212[2] functions as the conductive layer 208a of the transistor M1.

[0445] Another part of the conductive layer 212[2] is connected to the semiconductor layer 203[1] through the opening 207a[1] (see FIGS. 37, 38, and 41A). In this embodiment, the opening 207a of the transistor M1 is referred to as opening 207a[1], and the opening 207b of the transistor M1 is referred to as opening 207b[1]. The semiconductor layer 203 of the transistor M1 is referred to as semiconductor layer 203[1].

[0446] The conductive layer 213[1] is connected to the conductive layer 213[2] via the conductive layer 273. The conductive layer 213[1], the conductive layer 273, and the conductive layer 213[2] function as a wiring GI. Therefore, in FIG. 37, the wiring GI extends in the X direction. The conductive layer 213[2] is connected to the conductive layer 284 and the conductive layer 285. A part of the conductive layer 284 functions as the gate electrode of the transistor M7[1]. Therefore, a part of the conductive layer 284 functions as the conductive layer 205 of the transistor M7[1]. A part of the conductive layer 285 functions as the gate electrode of the transistor M7[2]. Therefore, a part of the conductive layer 285 functions as the conductive layer 205 of the transistor M7[2].

[0447] In addition, the conductive layer 214[1] is connected to the conductive layer 214[2] via the conductive layer 274. The conductive layer 214[1], the conductive layer 274, and the conductive layer 214[2] function as a wiring COM. Therefore, in FIG. 37, the wiring COM extends in the X direction. In addition, the conductive layer 214[2] is connected to the conductive layer 283. A part of the conductive layer 283 functions as the other electrode of the capacitance element C1, and another part functions as the other electrode of the capacitance element C2.

[0448] The conductive layer 215[1] is connected to the conductive layer 215[2] via the conductive layer 275. The conductive layer 215[1], the conductive layer 275, and the conductive layer 215[2] function as the wiring Vint. Therefore, in FIG. 37, the wiring Vint extends in the X direction. The conductive layer 215[2] is connected to the conductive layer 222 via the conductive layer 286.

[0449] In addition, the conductive layer 216[1] is connected to the conductive layer 216[2] via the conductive layer 276. The conductive layer 216[1], the conductive layer 276, and the conductive layer 216[2] function as the wiring GB. Therefore, in FIG. 37, the wiring GB extends in the X direction. The conductive layer 216[2] is connected to the conductive layer 287. A part of the conductive layer 287 functions as the gate electrode of the transistor M5. Therefore, a part of the conductive layer 287 functions as the conductive layer 205 of the transistor M5.

[0450] 37, the conductive layer 279 has a region extending in the X-direction. The conductive layer 279 functions as the wiring GB. A part of the conductive layer 279 functions as the gate electrode of the transistor M1. Therefore, a part of the conductive layer 279 functions as the conductive layer 205 of the transistor M1. The conductive layer 279 is connected to the conductive layer 282 via the conductive layer 222. A part of the conductive layer 282 functions as the gate electrode of the transistor M4. Therefore, a part of the conductive layer 282 functions as the conductive layer 205 of the transistor M4.

[0451] 37, the conductive layer 281 has a region extending in the X direction. The conductive layer 281 functions as a wiring GC. A part of the conductive layer 281 functions as a gate electrode of the transistor M6[1], and another part functions as a gate electrode of the transistor M6[2]. Therefore, a part of the conductive layer 281 functions as a conductive layer 205 of the transistor M6[1], and another part functions as a conductive layer 205 of the transistor M6[2].

[0452] The conductive layer 217 functions as a wiring DL and extends in the Y direction in Fig. 37. A part of the conductive layer 217 functions as the other of the source electrode and the drain electrode of the transistor M2.

[0453] A part of the conductive layer 228 functions as the other of the source and drain electrodes of the transistor M1. Therefore, a part of the conductive layer 228 functions as the conductive layer 208b of the transistor M1. Another part of the conductive layer 228 functions as one of the source and drain electrodes of the transistor M2. Therefore, another part of the conductive layer 228 functions as the conductive layer 208a of the transistor M2. Another part of the conductive layer 228 functions as one of the source and drain electrodes of the transistor M3 (see Figures 37, 38, and 41A). Therefore, another part of the conductive layer 228 functions as the conductive layer 208a of the transistor M3. In this embodiment, the opening 207a of the transistor M3 is referred to as opening 207a[3], and the opening 207b of the transistor M3 is referred to as opening 207b[3]. The semiconductor layer 203 of the transistor M3 is referred to as the semiconductor layer 203[3].

[0454] The conductive layer 278 is connected to the conductive layer 224. A part of the conductive layer 278 functions as the gate electrode of the transistor M1. Therefore, a part of the conductive layer 278 functions as the conductive layer 205 of the transistor M1. Another part of the conductive layer 278 functions as the other electrode of the capacitor C1. Note that a region where the conductive layer 278 and the conductive layer 212[2] overlap functions as the capacitor C1.

[0455] A part of the conductive layer 224 functions as the other of the source electrode and the drain electrode of the transistor M6[1]. Therefore, a part of the conductive layer 224 functions as the conductive layer 208b of the transistor M6[2]. Another part of the conductive layer 224 functions as one of the source electrode and the drain electrode of the transistor M7[1]. Therefore, the other part of the conductive layer 224 functions as the conductive layer 208a of the transistor M7[1].

[0456] A part of the conductive layer 238 functions as one of the source electrode and drain electrode of the transistor M6[1] (see Figures 37, 39, and 41B). Therefore, a part of the conductive layer 238 functions as the conductive layer 208a of the transistor M6[1]. Another part of the conductive layer 238 functions as the other of the source electrode and drain electrode of the transistor M6[2]. Therefore, another part of the conductive layer 238 functions as the conductive layer 208b of the transistor M6[2]. Still another part of the conductive layer 238 functions as one electrode of the capacitor C2. A region where the conductive layer 238 and the conductive layer 283 overlap each other functions as the capacitor C2.

[0457] In this embodiment, the opening 207a of the transistor M6[1] is referred to as opening 207a[6]1, and the opening 207b of the transistor M6[1] is referred to as opening 207b[6]1. The semiconductor layer 203 of the transistor M6[1] is referred to as semiconductor layer 203[6]1. The opening 207a of the transistor M6[2] is referred to as opening 207a[6]2, and the opening 207b of the transistor M6[2] is referred to as opening 207b[6]2. The semiconductor layer 203 of the transistor M6[2] is referred to as semiconductor layer 203[6]2.

[0458] As described in the above embodiment, OS transistors are preferably used as the transistors M6[1], M6[2], M7[1], and M7[2]. This allows the potential written to the node ND[1] to be held for a long period of time. Therefore, an oxide semiconductor is preferably used for the semiconductor layer 203 including the channel formation region of each of the transistors M6[1], M6[2], M7[1], and M7[2].

[0459] A part of the conductive layer 220 functions as the other of the source electrode and the drain electrode of the transistor M3. Therefore, a part of the conductive layer 220 functions as the conductive layer 208b of the transistor M3. Another part of the conductive layer 220 functions as one of the source electrode and the drain electrode of the transistor M4. Therefore, another part of the conductive layer 220 functions as the conductive layer 208a of the transistor M4. Another part of the conductive layer 220 functions as one of the source electrode and the drain electrode of the transistor M6[2]. Another part of the conductive layer 220 functions as the conductive layer 208a of the transistor M6[2].

[0460] A part of the conductive layer 221 functions as the other of the source electrode and the drain electrode of the transistor M7[1]. Therefore, a part of the conductive layer 221 functions as the conductive layer 208b of the transistor M7[1]. Another part of the conductive layer 221 functions as one of the source electrode and the drain electrode of the transistor M7[2]. Therefore, another part of the conductive layer 221 functions as the conductive layer 208a of the transistor M7[2]. Still another part of the conductive layer 221 functions as one electrode of the capacitor C3. A region where the conductive layer 221 and the conductive layer 283 overlap functions as the capacitor C3.

[0461] A part of the conductive layer 222 functions as the other of the source electrode and the drain electrode of the transistor M5. Therefore, a part of the conductive layer 222 functions as the conductive layer 208b of the transistor M5. Another part of the conductive layer 222 functions as the other of the source electrode and the drain electrode of the transistor M7[2]. Therefore, a part of the conductive layer 222 functions as the conductive layer 208b of the transistor M7[2].

[0462] Furthermore, a part of the conductive layer 223 functions as the other of the source electrode and the drain electrode of the transistor M4. Therefore, a part of the conductive layer 223 functions as the conductive layer 208b of the transistor M4. Further, another part of the conductive layer 223 functions as one of the source electrode and the drain electrode of the transistor M5. Therefore, the other part of the conductive layer 223 functions as the conductive layer 208a of the transistor M5. The conductive layer 223 is connected to the first terminal of the light-emitting element 61. Therefore, the other of the source electrode and the drain electrode of the transistor M4 and one of the source electrode and the drain electrode of the transistor M5 are connected to the first terminal of the light-emitting element 61.

[0463] Note that this embodiment shows a structure in which an insulating layer 218 having a flat upper surface is provided above the insulating layer 209 (see FIGS. 40, 41A, and 41B). An insulating layer containing an organic material is suitable for the insulating layer 218. For example, the insulating layer 218 can be formed using an acrylic resin, polyimide, polyamide, polyimideamide, epoxy resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins. Alternatively, the insulating layer 218 may be formed using an inorganic material, and CMP treatment may be performed on the upper surface of the insulating layer 218. Reducing the unevenness on the upper surface of the insulating layer 218 can improve the coverage of insulating layers and conductive layers formed later.

[0464] Furthermore, as described above, by making the channel lengths of transistors M1, M2, M4, M5, M6[1], M6[2], M7[1], and M7[2] that function as switches shorter than the channel length of transistor M3 that functions as a drive transistor, it is possible to improve the operating speed of semiconductor device 10A and the reproducibility of the light emission luminance of light-emitting element 61 in response to a video signal. For example, it is preferable to make the length Ls of the gate electrode of transistor M1 in the channel length direction shorter than the length Ld of the gate electrode of transistor M3 in the channel length direction (see FIG. 38 ).

[0465] The width of a conductive layer used as a power supply line (also referred to as a "power line") is preferably larger than the width of a conductive layer connected to the power line or the width of a portion of the power line branched off to be used as a routing wiring. For example, in the semiconductor device 10A, the width Wp (the length of the conductive layer 212[2] in the Y direction; the length in the direction perpendicular to the direction in which the conductive layer 212[2] extends) of the conductive layer 212[2] functioning as the wiring ELVDD is preferably larger than the width Wr of the conductive layer branched off from the conductive layer 212[2] to connect to the semiconductor layer 203[1] of the transistor M1 (see FIG. 38).

[0466] In other words, it is preferable to set the minimum value of the width Wp in the semiconductor device 10A to be greater than the maximum value of the width Wr. This reduces the degradation of the power supply capability of the conductive layers extending as power lines, enabling the semiconductor device 10A to operate stably. This improves the reliability of the semiconductor device 10A. The same applies to the conductive layers functioning as wiring COM, wiring Vint, etc.

[0467] When a conductive layer used as a signal line is connected to a gate electrode, or when a portion of the conductive layer branches off to form the gate electrode of a transistor, the width of the conductive layer is preferably greater than the length Ls of the gate electrode in the channel length direction. For example, in semiconductor device 10A, the width Wg of conductive layer 281 (the length of conductive layer 281 in the Y direction; the length in the direction perpendicular to the extension direction of conductive layer 281) is preferably greater than the length Ls of the gate electrode of transistor M6[1] in the channel length direction (see FIG. 39).

[0468] In other words, in the semiconductor device 10A, it is preferable that the minimum value of the width Wg is greater than the maximum value of the length Ls. This reduces signal delays that occur when signals are supplied to the transistors via the conductive layer 281. The same applies to the conductive layer 279, the conductive layer 213[2], the conductive layer 216[2], and the like.

[0469] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0470] Embodiment 5 A semiconductor device according to one embodiment of the present invention can be applied to a display device or the like. Furthermore, a semiconductor device according to one embodiment of the present invention can be applied to a module (also referred to as a "display module") including the display device. In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention will be described.

[0471] Examples of the display module include a module in which a connector such as a flexible printed circuit (FPC) or a tape carrier package (TCP) is attached to a display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method or a chip-on-film (COF) method.

[0472] <Structure Example of Display Device> FIG. 42A is a perspective view illustrating a structure example of a display device 400 according to one embodiment of the present invention.

[0473] Display device 400 has a configuration in which substrate 411 and substrate 451 are bonded together. In Fig. 42A, substrate 411 is indicated by a dashed line.

[0474] The display device 400 includes a display portion 452, a circuit portion 454a, a circuit portion 454b, a connection portion 457, and a wiring portion 458. Fig. 42A shows an example in which an IC 456 and an FPC 459 are mounted on the display device 400. Therefore, the configuration shown in Fig. 42A can also be said to be a display module including the display device 400, an IC, and an FPC.

[0475] The circuit portion 454a includes, for example, a scanning line driver circuit (also referred to as a gate driver or a scan driver), and the circuit portion 454b includes, for example, a signal line driver circuit (also referred to as a source driver or a data driver).

[0476] The wiring portion 458 has a function of supplying signals and power to the display portion 452, the circuit portion 454a, and the circuit portion 454b. The signals and power are input to the wiring portion 458 from the outside of the display device 400 via the FPC 459. Alternatively, the signals and power are input to the wiring portion 458 from the IC 456.

[0477] 42A shows an example in which an IC 456 is provided on a substrate 451 by a COG method, a COF method, or the like. For example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 456. Note that the display device 400 and the display module can be configured without an IC. Furthermore, the IC 456 can also be mounted on an FPC by a COF method or the like.

[0478] Note that a scanning line driver circuit can be configured by one or both of the IC 456 and the circuit portion 454a. In this case, the IC 456 may be referred to as a gate driver IC. Also, a signal line driver circuit can be configured by one or both of the IC 456 and the circuit portion 454b. In this case, the IC 456 may be referred to as a source driver IC.

[0479] Display section 452 is a region in display device 400 that displays an image, and has a plurality of periodically arranged pixels 455. Fig. 42A shows an enlarged view of one pixel 455.

[0480] The pixel 455 shown in FIG. 42A includes a pixel 453R that emits red (R) light, a pixel 453G that emits green (G) light, and a pixel 453B that emits blue (B) light. A full-color display can be achieved by configuring one pixel 455 with the pixels 453R, 453G, and 453B. The pixels 453R, 453G, and 453B each function as a subpixel. The display device 400 shown in FIG. 42A illustrates an example in which the pixels 453R, 453B, and 453G that function as subpixels are arranged in a stripe array. Note that the number of subpixels that constitute one pixel 455 is not limited to three and can be four or more. For example, a pixel 455 can have four subpixels that emit R, G, B, and white (W) light, respectively. Alternatively, a pixel 455 can have four subpixels that emit R, G, B, and yellow (Y) light, respectively.

[0481] In this specification, elements relating to red light may be identified by the identification symbol "R," elements relating to green light by the identification symbol "G," and elements relating to blue light by the identification symbol "B," and these elements may be described separately. Furthermore, common elements may be described without identifying the elements. For example, when it is necessary to distinguish between multiple pixels 453, they may be referred to as pixel 453R, pixel 453G, or pixel 453B. Furthermore, when it is not necessary to distinguish between pixel 453R, pixel 453G, and pixel 453B, they may be simply referred to as pixel 453.

[0482] Each of the pixels 453R, 453G, and 453B includes a light-emitting element and a circuit (pixel circuit) that controls the light-emitting luminance of the light-emitting element. The semiconductor device 10 (the semiconductor device 10A, the semiconductor device 10B, the semiconductor device 10C, and the semiconductor device 10X) of one embodiment of the present invention can be used as the pixel 453.

[0483] The connection portion 457 is provided outside the display portion 452. The connection portion 457 can be provided along one side or multiple sides of the display portion 452. The number of connection portions 457 may be single or multiple. FIG. 42A shows an example in which the connection portion 457 is provided so as to surround the four sides of the display portion. The connection portion 457 connects a common electrode of the display element and a wiring portion 458, and can supply a potential to the common electrode.

[0484] Here, for example, the transistor described in any of the above embodiments can be used in at least part of the display portion 452, the circuit portion 454a, and the circuit portion 454b included in the display device 400.

[0485] For example, by using a vertical transistor such as the above-described transistor 200C for one or both of the circuit portions 454a and 454b, the area occupied by the circuit portions 454a and 454b can be reduced, and a display device with a narrow frame can be obtained.

[0486] Furthermore, for example, by using a vertical transistor such as the transistor 200C or the transistor 200D described above for a pixel circuit included in the display portion 452, the area occupied by the pixel circuit can be reduced, and the resolution of the display device can be increased. For example, a display device with a resolution of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be realized.

[0487] Note that the display device of one embodiment of the present invention can also function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0488] Examples of sensor types include capacitance type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.

[0489] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0490] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that the in-cell type touch panel has a configuration in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element (also called a display device) and an opposing substrate.

[0491] [Pixel Array] Figures 42B to 42F are plan views illustrating pixel arrays. In a display device according to one embodiment of the present invention, the pixel array is not particularly limited, and various arrays can be applied. Examples of pixel arrays include a stripe array (see Figure 42B), an S-stripe array (see Figure 42C), a delta array (see Figure 42D), a zigzag array (see Figure 42E), and a pentile array (see Figure 42F). Other examples include a mosaic array, a diamond array, and a Bayer array.

[0492] 42B to 42F, examples of the top surface shape of each subpixel (pixel 453R, pixel 453G, and pixel 453B) include a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, shapes with rounded corners of these polygons, an ellipse, and a circle. Here, the top surface shape of each subpixel corresponds to the top surface shape of the display region of the display element of each subpixel. The top surface shape and size of each subpixel can be determined independently. The arrangements of pixel 453R, pixel 453G, and pixel 453B may be interchanged as appropriate. The display elements and pixel circuits may be arranged in the same or different ways.

[0493] Here, the pentile arrangement is a special pixel arrangement that artificially enhances the resolution. Therefore, a stripe arrangement, for example, can be adopted in a display device. In one embodiment of the present invention, the area occupied by a pixel circuit can be reduced by using vertical transistors such as the transistor 200C or the transistor 200D described above as part or all of the transistors constituting the pixel circuit. Therefore, the pixel arrangement can be changed from the pentile arrangement to, for example, a stripe arrangement without reducing the resolution of the display device.

[0494] [Light-emitting element] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs, organic EL elements (also called OLEDs (organic LEDs)), and semiconductor lasers. As the LED, for example, a mini LED or a micro LED can be used.

[0495] Examples of light-emitting substances that the light-emitting element has include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (quantum dot materials, etc.).

[0496] The light emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light emitting element with a microcavity structure.

[0497] One of a pair of electrodes or a pair of terminals included in the light-emitting element functions as an anode (also referred to as an anode electrode), and the other functions as a cathode (also referred to as a cathode electrode).

[0498] In this embodiment, an example in which an organic EL element is used as a light-emitting element will be described. Therefore, the display device 400 according to one embodiment of the present invention is a display device using an organic EL element.

[0499] The display device 400 according to one embodiment of the present invention is suitable for any of a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed, a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed, and a dual-emission type that emits light on both sides.

[0500] For example, by using a vertical transistor such as the transistor 200C or the transistor 200D described above, the area occupied by the pixel circuit can be reduced, and therefore the aperture ratio of the pixel can be increased, particularly in bottom-emission display devices and dual-emission display devices, and a display device with an aperture ratio of, for example, 50% or more, 55% or more, or 60% or more can be realized.

[0501] In this specification and the like, the aperture ratio refers to the ratio of the area of ​​the region that emits light to the area of ​​the pixel.

[0502] <Structure Example of Light-Emitting Element> A light-emitting element 61 that can be used in a display device according to one embodiment of the present invention will be described.

[0503] 43A , the light-emitting element 61 includes an EL layer 172 between a conductive layer 171 and a conductive layer 173. The EL layer 172 can be composed of a plurality of layers, such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can include, for example, a layer containing a substance with high electron injection properties (electron injection layer) and a layer containing a substance with high electron transport properties (electron transport layer). The light-emitting layer 4411 includes, for example, a light-emitting compound. The layer 4430 can include, for example, a layer containing a substance with high hole injection properties (hole injection layer) and a layer containing a substance with high hole transport properties (hole transport layer).

[0504] A structure including the layer 4420 provided between the electrodes of the conductive layer 171 and the conductive layer 173, the light-emitting layer 4411, and the layer 4430 can function as a single light-emitting unit, and the structure of Figure 43A is called a single structure in this specification and elsewhere.

[0505] 43B shows a modified example of the EL layer 172 included in the light-emitting element 61 shown in Fig. 43A. Specifically, the light-emitting element 61 shown in Fig. 43B includes a layer 4430-1 on the conductive layer 171, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductive layer 173 on the layer 4420-2. For example, when the conductive layer 171 is an anode and the conductive layer 173 is a cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. Alternatively, when the conductive layer 171 is a cathode and the conductive layer 173 is an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. With such a layer structure, carriers can be efficiently injected into the light-emitting layer 4411, and the efficiency of carrier recombination in the light-emitting layer 4411 can be increased.

[0506] Note that a configuration in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 as shown in FIG. 43C is also an example of a single structure.

[0507] 43D , a configuration in which a plurality of light-emitting units (EL layers 172 a and 172 b) are connected in series via an intermediate layer (charge generating layer) 4440 is referred to as a tandem structure or a stack structure in this specification and elsewhere. Note that a tandem structure can realize a light-emitting element capable of emitting light with high brightness.

[0508] 43D, it is preferable that the EL layers 172a and 172b emit light of the same color. For example, it is preferable that the EL layers 172a and 172b emit light of green.

[0509] Note that a full-color display can be achieved by using a light-emitting element 61 emitting red light (R), a light-emitting element 61 emitting green light (G), and a light-emitting element 61 emitting blue light (B) as sub-pixels to form one pixel using these three sub-pixels. When one pixel includes three types of sub-pixels, R, G, and B, it is preferable that the light-emitting elements 61 be arranged in tandem. Specifically, the EL layer 172a and the EL layer 172b of the R sub-pixel each contain a material capable of emitting red light, the EL layer 172a and the EL layer 172b of the G sub-pixel each contain a material capable of emitting green light, and the EL layer 172a and the EL layer 172b of the B sub-pixel each contain a material capable of emitting blue light. In other words, the light-emitting layer 4411 and the light-emitting layer 4412 can be made of the same material. By making the EL layer 172a and the EL layer 172b emit the same light, the current density per unit of light emission luminance can be reduced. Therefore, the reliability of the light emitting element 61 can be improved.

[0510] The light-emitting color of the light-emitting element can be red, green, blue, cyan, magenta, yellow, white, or the like, depending on the material constituting the EL layer 172. Furthermore, the color purity can be further improved by providing the light-emitting element with a microcavity structure.

[0511] The light-emitting layer can contain two or more light-emitting materials that emit light such as R (red), G (green), B (blue), Y (yellow), and O (orange). For example, a light-emitting element that emits white light preferably has a configuration in which the light-emitting layer contains two or more types of light-emitting materials. To obtain white light emission, light-emitting materials are selected such that the emissions of two light-emitting materials have a complementary color relationship, or light-emitting materials are selected such that the emissions of two or more light-emitting materials combine to produce white light. For example, when white light emission is obtained using two light-emitting layers, a light-emitting element that emits white light as a whole can be obtained by adjusting the emission colors of the two light-emitting layers to have a complementary color relationship. Furthermore, when white light emission is obtained using three or more light-emitting layers, a light-emitting element that emits white light as a whole light-emitting device can be obtained by combining the emission colors of the three or more light-emitting layers.

[0512] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0513] Examples of the light-emitting substance include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), etc. As the light-emitting substance contained in the EL element, not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used.

[0514] <Method of Forming Light-Emitting Element> An example of a method of forming the light-emitting element 61 will be described below.

[0515] FIG. 44A shows a schematic top view of a light-emitting element 61. The light-emitting element 61 includes a plurality of light-emitting elements 61R that emit red light, a plurality of light-emitting elements 61G that emit green light, and a plurality of light-emitting elements 61B that emit blue light. In FIG. 44A, the symbols R, G, and B are assigned within the light-emitting region of each light-emitting element to easily distinguish between the light-emitting elements. Also, while FIG. 44A illustrates a configuration having three emitted light colors, red (R), green (G), and blue (B), this is not limiting. For example, a configuration having four or more colors is also possible.

[0516] The light emitting elements 61R, 61G, and 61B are arranged in a matrix. Fig. 44A shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction, but the arrangement of the light emitting elements is not limited to this.

[0517] As the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B, it is preferable to use an organic EL device such as an OLED (organic light-emitting diode) or a QOLED (quantum-dot organic light-emitting diode). Examples of the light-emitting substance contained in the EL element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material). As the light-emitting substance contained in the EL element, not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used.

[0518] FIG. 44B is a schematic cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 44A . FIG. 44B shows cross sections of the light-emitting elements 61R, 61G, and 61B. The light-emitting elements 61R, 61G, and 61B are each provided on an insulating layer 363 and include a conductive layer 171 functioning as a pixel electrode and a conductive layer 173 functioning as a common electrode. The insulating layer 363 can be an inorganic insulating film or an organic insulating film, or both. It is preferable to use an inorganic insulating film as the insulating layer 363. Examples of inorganic insulating films include oxide insulating films and nitride insulating films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film.

[0519] The light-emitting element 61R has an EL layer 172R between a conductive layer 171 functioning as a pixel electrode and a conductive layer 173 functioning as a common electrode. The EL layer 172R contains a light-emitting organic compound that emits light having a peak in at least the red wavelength range. The EL layer 172G of the light-emitting element 61G contains a light-emitting organic compound that emits light having a peak in at least the green wavelength range. The EL layer 172B of the light-emitting element 61B contains a light-emitting organic compound that emits light having a peak in at least the blue wavelength range.

[0520] The EL layer 172R, the EL layer 172G, and the EL layer 172B may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting substance (light-emitting layer).

[0521] The conductive layer 171 functioning as a pixel electrode is provided for each light-emitting element. The conductive layer 173 functioning as a common electrode is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductive layer 171 functioning as a pixel electrode or the conductive layer 173 functioning as a common electrode, and a conductive film that is reflective is used for the other. By making the conductive layer 171 functioning as a pixel electrode light-transmitting and the conductive layer 173 functioning as a common electrode light-reflective, a bottom-emission display device can be obtained. Conversely, by making the conductive layer 171 functioning as a pixel electrode reflective and the conductive layer 173 functioning as a common electrode light-transmitting, a top-emission display device can be obtained. Note that by making both the conductive layer 171 functioning as a pixel electrode and the conductive layer 173 functioning as a common electrode light-transmitting, a dual-emission display device can also be obtained.

[0522] For example, when the light-emitting element 61R is a top-emission type, the light 175R emitted from the light-emitting element 61R is emitted toward the conductive layer 173. When the light-emitting element 61G is a top-emission type, the light 175G emitted from the light-emitting element 61G is emitted toward the conductive layer 173. When the light-emitting element 61B is a top-emission type, the light 175B emitted from the light-emitting element 61B is emitted toward the conductive layer 173.

[0523] An insulator 372 is provided to cover an end portion of the conductive layer 171 functioning as a pixel electrode. The end portion of the insulator 372 preferably has a tapered shape. The insulator 372 can be formed using a material similar to that of the insulating layer 363.

[0524] The insulator 372 is provided to prevent erroneous light emission due to unintentional electrical short circuit between adjacent light-emitting elements 61. In addition, when a metal mask is used to form the EL layer 172, the insulator 372 also functions to prevent the metal mask from coming into contact with the conductive layer 171.

[0525] The EL layer 172R, the EL layer 172G, and the EL layer 172B each have a region in contact with the top surface of the conductive layer 171 that functions as a pixel electrode, and a region in contact with the surface of the insulator 372. Ends of the EL layer 172R, the EL layer 172G, and the EL layer 172B are located on the insulator 372.

[0526] As shown in Figure 44B, a gap is provided between two EL layers between light-emitting elements that emit different colors. In this manner, it is preferable that the EL layers 172R, 172G, and 172B are arranged so as not to be in contact with each other. This can effectively prevent current from flowing through two adjacent EL layers, resulting in unintended light emission (also known as crosstalk). This can improve contrast and realize a display device with high display quality.

[0527] The EL layer 172R, the EL layer 172G, and the EL layer 172B can be separately produced by a vacuum deposition method using a shadow mask such as a metal mask. Alternatively, they can be separately produced by a photolithography method. By using the photolithography method, it is possible to realize a high-definition display device that is difficult to achieve when using a metal mask.

[0528] In this specification and the like, a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification and the like, a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because a display device with an MML structure is fabricated without using a metal mask, it has a higher degree of design freedom in terms of pixel arrangement, pixel shape, and the like than a display device with an MM structure.

[0529] In addition, a protective layer 371 is provided over the conductive layer 173 functioning as a common electrode to cover the light-emitting elements 61R, 61G, and 61B. The protective layer 371 has a function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0530] The protective layer 371 can have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of inorganic insulating films include oxide or nitride films such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, and hafnium oxide. Alternatively, semiconductor materials such as indium gallium oxide and indium gallium zinc oxide (IGZO) can be used for the protective layer 371. The protective layer 371 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or sputtering. While the protective layer 371 includes an inorganic insulating film, the present invention is not limited to this. For example, the protective layer 371 can also have a stacked structure of an inorganic insulating film and an organic insulating film.

[0531] In this specification, "nitride oxide" refers to a compound containing more nitrogen than oxygen. "oxynitride" refers to a compound containing more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

[0532] When indium gallium zinc oxide is used as the protective layer 371, it can be processed by wet etching or dry etching. For example, when IGZO is used as the protective layer 371, a chemical solution such as oxalic acid, phosphoric acid, or a mixed chemical solution (for example, a mixed chemical solution of phosphoric acid, acetic acid, nitric acid, and water (also referred to as a mixed acid aluminum etching solution)) can be used. Note that the mixed acid aluminum etching solution can have a volume ratio of phosphoric acid:acetic acid:nitric acid:water=53.3:6.7:3.3:36.7 or a similar ratio.

[0533] The structure shown in FIG. 44B may be referred to as an SBS structure, which will be described later.

[0534] 44C shows a different example from the above. Specifically, Fig. 44C shows a light-emitting element 61W that emits white light. The light-emitting element 61W has an EL layer 172W that emits white light between a conductive layer 171 that functions as a pixel electrode and a conductive layer 173 that functions as a common electrode.

[0535] The EL layer 172W may be configured by stacking two or more light-emitting layers, each of which is selected so that the emitted light has a complementary color. Alt...

Claims

It has the first to ninth transistors, the first to third capacitive elements, and a light-emitting element. Each of the first to ninth transistors has a gate, a first terminal, and a second terminal. Each of the first to third capacitive elements has a first terminal and a second terminal. The light-emitting element has a first terminal and a second terminal. The first terminal of the first transistor is electrically connected to the first terminal of the first capacitive element. The second terminal of the first transistor is electrically connected to the first terminals of the second transistor and the third transistor. The second terminal of the third transistor is electrically connected to the first terminals of the fourth transistor and the seventh transistor. The second terminal of the fourth transistor is electrically connected to the first terminals of the fifth transistor and the light-emitting element. The first terminal of the sixth transistor is electrically connected to the second terminal of the seventh transistor and the first terminal of the second capacitive element. The second terminal of the sixth transistor is electrically connected to the gate of the third transistor, the second terminal of the first capacitive element, and the first terminal of the eighth transistor. The second terminal of the eighth transistor is electrically connected to the first terminal of the ninth transistor and the first terminal of the third capacitive element. The gate of the first transistor is electrically connected to the gate of the fourth transistor. The gate of the sixth transistor is electrically connected to the gate of the seventh transistor. The gate of the eighth transistor is electrically connected to the gate of the ninth transistor. The second terminal of the second capacitive element is electrically connected to the second terminal of the third capacitive element. A semiconductor device in which the second terminal of the fifth transistor is electrically connected to the second terminal of the ninth transistor. 　 In claim 1, The first terminal of the first transistor and the first terminal of the first capacitive element are electrically connected to a first wiring. The gate of the first transistor and the gate of the fourth transistor are electrically connected to a second wiring. The second terminal of the light-emitting element is electrically connected to a third wiring. The second terminal of the second transistor is electrically connected to a fourth wiring. The gate of the second transistor is electrically connected to a fifth wiring. The gate of the sixth transistor and the gate of the seventh transistor are electrically connected to a sixth wiring. The gate of the eighth transistor and the gate of the ninth transistor are electrically connected to a seventh wiring. The second terminal of the second capacitor element and the second terminal of the third capacitor element are electrically connected to an eighth wiring. The gate of the fifth transistor is electrically connected to a ninth wiring, a semiconductor device. 　 In claim 1 or claim 2, A semiconductor device in which the first to fifth transistors are p-type transistors and the sixth to ninth transistors are n-type transistors. 　 In claim 1 or claim 2, Each of the first to fifth transistors is a semiconductor device including silicon in a semiconductor layer in which a channel is formed. 　 In claim 1 or claim 2, Each of the sixth to ninth transistors is a semiconductor device including an oxide semiconductor in a semiconductor layer in which a channel is formed. 　 In claim 1 or claim 2, The first terminal of the light-emitting element functions as an anode, A semiconductor device in which the second terminal of the light-emitting element functions as a cathode. 　 A semiconductor device having first to third transistors, a capacitor element, and a light-emitting element, Each of the first to third transistors has a gate, a first terminal, and a second terminal, The capacitor element has a first terminal and a second terminal, The light-emitting element has a first terminal and a second terminal, The first terminal of the second transistor is electrically connected to the gate of the first transistor, and the first terminal of the third transistor and the first terminal of the capacitor element are electrically connected to the second terminal of the second transistor, The second terminal of the first transistor is electrically connected to the first terminal of the light-emitting element, The first transistor has a function of supplying a current corresponding to the potential of the gate of the first transistor to the light-emitting element, a semiconductor device. 　 In claim 1, A semiconductor device in which the first transistor is a p-type transistor and each of the second and third transistors is an n-type transistor. 　 In claim 7 or claim 8, The first transistor is a semiconductor device including silicon in a semiconductor layer in which a channel is formed. 　 In claim 7 or claim 8, Each of the second to third transistors is a semiconductor device including an oxide semiconductor in a semiconductor layer in which a channel is formed. 　 In claim 1 or claim 2, The first terminal of the light-emitting element functions as an anode, A semiconductor device in which the second terminal of the light-emitting element functions as a cathode.

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