Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device that has a large on-state current. The semiconductor device includes a first conductive layer, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, an oxide layer, a first oxide semiconductor layer on the oxide layer, a second oxide semiconductor layer on the first oxide semiconductor layer, a second insulating layer on the second oxide semiconductor layer, and a third conductive layer on the second insulating layer. The first conductive layer has a first recess. The first insulating layer and the second conductive layer have a first opening at a position overlapping the first recess. In the first opening, the first oxide semiconductor layer is positioned opposite the first insulating layer with the oxide layer therebetween. In the first opening, the third conductive layer is positioned opposite the first oxide semiconductor layer with the second insulating layer therebetween. The oxide layer includes gallium oxide. The first oxide semiconductor layer includes indium oxide. The second oxide semiconductor layer includes one or both of gallium and indium.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories (storage devices), etc. A CPU is an aggregate of semiconductor elements that have integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (IC chips) such as LSIs, CPUs, or memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with high on-state current.An object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, memory device, or display device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device, memory device, or display device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a display device with high definition or a high aperture ratio.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, memory device, or display device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0013] One embodiment of the present invention is a semiconductor device including first and second oxide semiconductor layers, an oxide layer, first to third conductive layers, and first and second insulating layers. The first insulating layer is located over the first conductive layer. The second conductive layer is located over the first insulating layer. The first conductive layer has a first recess. The first insulating layer and the second conductive layer have a first opening overlapping the first recess. The oxide layer has a portion covering a sidewall of the first opening. The first oxide semiconductor layer has a portion located over the second conductive layer, a portion located over the first conductive layer in the first opening, and a portion facing the first insulating layer in the first opening with the oxide layer sandwiched therebetween. The second oxide semiconductor layer is located over the first oxide semiconductor layer. The second insulating layer is located over the second oxide semiconductor layer. The third conductive layer is located over the second insulating layer. The third conductive layer faces the first oxide semiconductor layer in the first opening with the second insulating layer sandwiched therebetween. The oxide layer contains gallium oxide. The first oxide semiconductor layer contains indium oxide. The second oxide semiconductor layer contains one or both of gallium and indium. The indium content in the first oxide semiconductor layer is higher than the indium content in the second oxide semiconductor layer.

[0014] In the above semiconductor device, the hydrogen concentration in the first oxide semiconductor layer measured by secondary ion mass spectrometry is 1×10 ２０ atoms / cm ３ It is preferable that it is less than 10 ...

[0015] In the above semiconductor device, it is preferable that the second insulating layer has a stack of two or more layers, and that a layer of the second insulating layer that is in contact with the second oxide semiconductor layer contains aluminum oxide.

[0016] In the above semiconductor device, it is preferable that the conduction band minimum of the oxide layer is located closer to the vacuum level than the conduction band minimum of the first oxide semiconductor layer, and the conduction band minimum of the second oxide semiconductor layer is located closer to the vacuum level than the conduction band minimum of the first oxide semiconductor layer.

[0017] In the semiconductor device, it is preferable that the oxide layer contains indium, and that the content of indium in the oxide layer is lower than the content of gallium.

[0018] In the semiconductor device, it is preferable that the oxide layer have a gallium content excluding oxygen of 95% or more, and the first oxide semiconductor layer have an indium content excluding oxygen of 95% or more.

[0019] Another embodiment of the present invention is a semiconductor device including first and second oxide semiconductor layers, an oxide layer, first to fourth conductive layers, and first to third insulating layers. The first insulating layer is located over the first conductive layer. The second conductive layer is located over the first insulating layer. The first conductive layer has a first recess. The first insulating layer and the second conductive layer have a first opening overlapping the first recess. The oxide layer has a portion covering a sidewall of the first opening. The first oxide semiconductor layer has a portion located over the second conductive layer, a portion located over the first conductive layer in the first opening, and a portion facing the first insulating layer in the first opening with the oxide layer sandwiched therebetween. The second oxide semiconductor layer is located over the first oxide semiconductor layer. The second insulating layer is located over the second oxide semiconductor layer. The third insulating layer is located on the second insulating layer and has a second opening at a position overlapping the first opening. The third conductive layer has a portion facing the first oxide semiconductor layer with the second insulating layer interposed therebetween in the first opening and a portion located in the second opening. The fourth conductive layer is located on the third insulating layer and has a region in contact with the third conductive layer. The oxide layer contains gallium oxide. The first oxide semiconductor layer contains indium oxide. The second oxide semiconductor layer contains one or both of gallium and indium. The indium content of the first oxide semiconductor layer is higher than the indium content of the second oxide semiconductor layer.

[0020] In the above semiconductor device, the hydrogen concentration in the first oxide semiconductor layer measured by secondary ion mass spectrometry is 1×10 ２０ atoms / cm ３ It is preferable that it is less than 10 ...

[0021] In the above semiconductor device, it is preferable that the second insulating layer has a stack of two or more layers, and that a layer of the second insulating layer that is in contact with the second oxide semiconductor layer contains aluminum oxide.

[0022] In the above semiconductor device, it is preferable that the conduction band minimum of the oxide layer is located closer to the vacuum level than the conduction band minimum of the first oxide semiconductor layer, and the conduction band minimum of the second oxide semiconductor layer is located closer to the vacuum level than the conduction band minimum of the first oxide semiconductor layer.

[0023] In the semiconductor device, it is preferable that the oxide layer contains indium, and that the content of indium in the oxide layer is lower than the content of gallium.

[0024] In the semiconductor device, it is preferable that the oxide layer have a gallium content excluding oxygen of 95% or more, and the first oxide semiconductor layer have an indium content excluding oxygen of 95% or more.

[0025] Another embodiment of the present invention is a semiconductor device including first and second oxide semiconductor layers, an oxide layer, first to third conductive layers, and first to third insulating layers. The first insulating layer is located over the first conductive layer. The second conductive layer is located over the first insulating layer. The first conductive layer has a first recess. The first insulating layer and the second conductive layer have a first opening overlapping the first recess. The oxide layer has a portion covering a sidewall of the first opening. The first oxide semiconductor layer has a portion located over the second conductive layer, a portion located over the first conductive layer in the first opening, and a portion facing the first insulating layer in the first opening with the oxide layer sandwiched therebetween. The second oxide semiconductor layer is located over the first oxide semiconductor layer. The second insulating layer is located over the second oxide semiconductor layer. The third conductive layer is located over the second insulating layer. The third conductive layer faces the first oxide semiconductor layer in the first opening, with the second insulating layer sandwiched therebetween. The oxide layer contains gallium oxide. The first oxide semiconductor layer contains indium oxide. The second oxide semiconductor layer contains one or both of gallium and indium. The indium content of the first oxide semiconductor layer is higher than the indium content of the second oxide semiconductor layer. The third insulating layer is located between the first insulating layer and the oxide layer. The third insulating layer includes a fourth insulating layer in contact with the first insulating layer and a fifth insulating layer located between the fourth insulating layer and the oxide layer. The fourth insulating layer includes silicon and nitrogen. The fifth insulating layer includes silicon and oxygen.

[0026] In the above semiconductor device, the hydrogen concentration in the first oxide semiconductor layer measured by secondary ion mass spectrometry is 1×10 ２０ atoms / cm ３ It is preferable that it is less than 10 ...

[0027] In the above semiconductor device, it is preferable that the second insulating layer has a stack of two or more layers, and that a layer of the second insulating layer that is in contact with the second oxide semiconductor layer contains aluminum oxide.

[0028] In the above semiconductor device, it is preferable that the conduction band minimum of the oxide layer is located closer to the vacuum level than the conduction band minimum of the first oxide semiconductor layer, and the conduction band minimum of the second oxide semiconductor layer is located closer to the vacuum level than the conduction band minimum of the first oxide semiconductor layer.

[0029] In the semiconductor device, it is preferable that the oxide layer contains indium, and that the content of indium in the oxide layer is lower than the content of gallium.

[0030] In the semiconductor device, it is preferable that the oxide layer have a gallium content excluding oxygen of 95% or more, and the first oxide semiconductor layer have an indium content excluding oxygen of 95% or more.

[0031] In the above semiconductor device, the oxide layer may contain aluminum oxide or yttrium oxide instead of gallium oxide.

[0032] Another embodiment of the present invention includes first and second oxide semiconductor layers, an oxide layer, first to third conductive layers, and first and second insulating layers, wherein the first insulating layer is located over the first conductive layer, the second conductive layer is located over the first insulating layer, the first conductive layer has a first recess, the first insulating layer and the second conductive layer have first openings at positions overlapping with the first recess, the oxide layer has a portion covering a sidewall of the first opening, and the first oxide semiconductor layer has a second insulating layer. a first oxide semiconductor layer located on the first insulating layer, a second oxide semiconductor layer located on the second insulating layer, a third conductive layer located on the second insulating layer, and a third conductive layer located on the second insulating layer, the third conductive layer located on the second insulating layer, the third conductive layer located on the first oxide semiconductor layer, and the third conductive layer located on the second insulating layer, the third conductive layer located on the second insulating layer, and the third oxide semiconductor layer located on the second insulating layer, the third conductive layer located on the first oxide semiconductor layer, and the semiconductor device is subjected to a gate BT stress test in a dark room under measurement conditions of a set temperature of 125° C., a drain potential Vd and a source potential Vs of 0 V, and a gate potential Vg of +1.98 V. When the semiconductor device is subjected to a gate BT stress test in a dark room under measurement conditions of a set temperature of 125° C., a drain potential Vd and a source potential Vs of 0 V, and a gate potential Vg of +1.98 V, a change in threshold voltage calculated from Id-Vg measurement after 100 hours is between −500 mV and 500 mV.

[0033] Another embodiment of the present invention is a method for manufacturing a semiconductor device according to any one of the above. The oxide layer is preferably formed by an ALD method using a first precursor containing gallium and a first oxidizing agent. The first oxide semiconductor layer is preferably formed by an ALD method using a second precursor containing indium and a second oxidizing agent containing ozone. The second oxide semiconductor layer is preferably formed by a sputtering method using a sputtering target containing indium and gallium.

[0034] In the above-described method for manufacturing a semiconductor device, the oxide layer and the first oxide semiconductor layer are preferably formed without exposure to air.

[0035] In the method for manufacturing a semiconductor device, it is preferable that microwave plasma treatment be performed after the second oxide semiconductor layer is formed. In addition, it is preferable that the oxygen flow rate in the microwave plasma treatment be greater than or equal to 0.5% and less than or equal to 5% and that the substrate be heated to a temperature greater than or equal to 300° C. and less than or equal to 450° C.

[0036] In the above method for manufacturing a semiconductor device, the second insulating layer is preferably formed using two or more types of films, and a film in contact with the second oxide semiconductor layer among the two or more types of films preferably contains aluminum oxide.

[0037] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, memory device, or display device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a display device with high definition or a high aperture ratio can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, memory device, or display device can be provided.

[0038] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0039] FIGS. 1A and 1B are perspective views showing an example of a semiconductor device. FIGS. 2A1 and 2A2 are plan views showing an example of a semiconductor device. FIGS. 2B to 2D are cross-sectional views showing an example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views showing an example of a semiconductor device. FIG. 3C is a diagram showing a band diagram. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views showing an example of a semiconductor device. FIG. 6 is a cross-sectional view showing an example of a semiconductor device. FIGS. 7A1 and 7A2 are plan views showing an example of a semiconductor device. FIGS. 7B and 7C are cross-sectional views showing an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing an example of a semiconductor device. FIGS. 9A1 and 9A2 are plan views showing an example of a semiconductor device. FIGS. 9B to 9D are cross-sectional views showing an example of a semiconductor device. FIGS. 10A and 10B are cross-sectional views showing an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIG. 12 is a cross-sectional view showing an example of a semiconductor device. FIGS. 13A and 13B are cross-sectional views showing an example of a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing an example of a semiconductor device. FIGS. 15A1 and 15A2 are plan views showing an example of a semiconductor device. FIGS. 15B to 15D are cross-sectional views showing an example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views showing an example of a semiconductor device. FIGS. 17A to 17D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 18A to 18C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 19A is a plan view showing an example of a memory device. FIGS. 19B and 19C are cross-sectional views showing an example of a memory device. FIG. 20A is a plan view showing an example of a memory device. FIGS. 20B and 20C are cross-sectional views showing an example of a memory device. FIGS. 21A and 21B are cross-sectional views showing an example of a memory device. FIG. 22A is a plan view showing an example of a memory device. FIG. 22B is a cross-sectional view showing an example of a memory device. FIG. 23 is a cross-sectional view showing an example of a memory device. FIG. 24 is a cross-sectional view showing an example of a memory device. FIG. 25 is a block diagram illustrating a configuration example of a semiconductor device. 26A to 26G are diagrams illustrating examples of the circuit configuration of a memory cell.FIGS. 27A and 27B are perspective views illustrating a configuration example of a semiconductor device. FIG. 28 is a block diagram illustrating a CPU. FIGS. 29A and 29B are perspective views of a semiconductor device. FIGS. 30A and 30B are perspective views of a semiconductor device. FIGS. 31A and 31B are circuit diagrams of a semiconductor device according to one embodiment of the present invention, and FIG. 31C is a diagram illustrating an example of an electronic component using a semiconductor device according to one embodiment of the present invention. FIGS. 32A and 32B are perspective views of an example of a display device. FIG. 33 is a cross-sectional view of an example of a display device. FIG. 34 is a cross-sectional view of an example of a display device. FIGS. 35A to 35C are diagrams illustrating a configuration example of a display device. FIGS. 36 are diagrams illustrating an example of an electronic component. FIGS. 37A to 37C are diagrams illustrating an example of a mainframe computer. FIG. 37D is a diagram illustrating an example of space equipment. FIG. 37E is a diagram illustrating an example of a storage system applicable to a data center. FIGS. 38A to 38F are diagrams illustrating examples of electronic devices. FIGS. 39A to 39G are diagrams illustrating examples of electronic devices. FIGS. 40A to 40F are diagrams illustrating examples of electronic devices. FIG. 41 is a graph showing a wet etching rate according to an example. FIG. 42 is a cross-sectional view showing a transistor included in a sample. FIGS. 43A and 43B are results of EDX line analysis of a sample prepared in an example. FIGS. 44A and 44B are results of SIMS analysis of hydrogen concentration of a sample prepared in an example. FIG. 45A is a schematic perspective view of a memory cell, and FIG. 45B is a cross-sectional STEM image of the memory cell. FIG. 46A is a plan view showing an example of a memory device. FIGS. 46B and 46C are cross-sectional views of an example of a memory device. FIG. 47 is a graph showing Id-Vg characteristics of a transistor. FIGS. 48A and 48B are graphs showing Id-Vg characteristics of a transistor. FIG. 49 is a graph showing P-V characteristics according to an example. FIG. 50A is a graph showing an input voltage waveform. FIG. 50B is a graph showing fatigue characteristics. FIGS. 51A and 51B are graphs showing a method of retention measurement. FIG. 51C is a graph showing the results of retention measurement. FIG. 52 is a diagram explaining a memory cell circuit. 53A and 53B are diagrams for explaining a method for evaluating polarization writing and reading, and Fig. 53C is a diagram showing a current waveform.54A and 54B are diagrams showing evaluation results of reliability tests of transistors. FIG. 55 is a diagram showing a band diagram. FIGS. 56A to 56C are diagrams showing calculation results. FIGS. 57A1 to 57C2 are diagrams showing calculation results. FIG. 58 is a diagram showing evaluation results of reliability tests of transistors.

[0040] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0041] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0042] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0043] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0044] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0045] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0046] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0047] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0048] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0049] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0050] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0051] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as AＸ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0052] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0053] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0054] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0055] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0056] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0057] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0058] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0059] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0060] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0061] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0062] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0063] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0064] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0065] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0066] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0067] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0068] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0069] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS. 1A to 18C.

[0070] A semiconductor device according to one embodiment of the present invention includes a transistor, an oxide semiconductor layer, an oxide layer, first to third conductive layers, and first and second insulating layers.

[0071] The oxide semiconductor layer functions as a semiconductor layer of a transistor, the first conductive layer functions as one of a source electrode and a drain electrode of the transistor, the second conductive layer functions as the other of the source electrode and the drain electrode of the transistor, and the third conductive layer functions as a gate electrode of the transistor. The second insulating layer functions as a gate insulating layer of the transistor.

[0072] A first insulating layer is located on the first conductive layer, a second conductive layer is located on the first insulating layer, the first conductive layer has a first recess, and the first insulating layer and the second conductive layer have a first opening at a position overlapping the first recess.

[0073] The oxide layer has a portion covering the sidewall of the first opening. The oxide semiconductor layer has a portion located on the second conductive layer, a portion located on the first conductive layer within the first opening, and a portion facing the first insulating layer within the first opening with the oxide layer sandwiched therebetween. The second insulating layer is located on the oxide semiconductor layer, and the third conductive layer is located on the second insulating layer. Furthermore, in the first opening, the oxide semiconductor layer faces the first insulating layer with the oxide layer sandwiched therebetween, and the third conductive layer faces the oxide semiconductor layer within the first opening with the second insulating layer sandwiched therebetween.

[0074] The oxide semiconductor layer preferably has a two-layer structure including a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, and the Ga content in the second oxide semiconductor layer is preferably higher than the Ga content in the first oxide semiconductor layer.

[0075] Increasing the Ga content in the second oxide semiconductor layer can improve the barrier property of the second oxide semiconductor layer against hydrogen. This can suppress hydrogen diffusion into the first oxide semiconductor layer where a channel is formed. Furthermore, increasing the Ga content in the second oxide semiconductor layer can reduce impurities such as hydrogen and water contained in the oxide semiconductor layer due to heat or the like applied after the formation of the oxide semiconductor layer. This can improve the electrical characteristics and reliability of the transistor.

[0076] Furthermore, by increasing the Ga content in the second oxide semiconductor layer, the barrier property of the second oxide semiconductor layer against oxygen can be improved. Therefore, release of oxygen from the first oxide semiconductor layer where a channel is formed can be suppressed, and the formation of oxygen vacancies in the first oxide semiconductor layer or an increase in the amount of oxygen vacancies in the first oxide semiconductor layer can be suppressed. As a result, the electrical characteristics of the transistor can be improved.

[0077] The In content in the first oxide semiconductor layer is preferably higher than that in the second oxide semiconductor layer, and an increase in the In content in the first oxide semiconductor layer can increase the on-state current and improve the frequency characteristics.

[0078] In a transistor according to one embodiment of the present invention, a first recess is provided in the first conductive layer. This allows the height of the bottom surface of the second insulating layer and the height of the bottom surface of the third conductive layer in the first opening to be lower than in a case where the first recess is not provided. Therefore, a gate electric field can be easily applied to the oxide semiconductor layer, thereby improving the electrical characteristics of the transistor. Here, the height of each surface can be determined, for example, based on the surface on which the transistor is formed.

[0079] Furthermore, if the parasitic capacitance generated between the source electrode or drain electrode and the gate wiring is large, the operation of the transistor may become slow, and the frequency characteristics of a circuit using the transistor may be degraded.

[0080] Therefore, the transistor of one embodiment of the present invention preferably has a structure in which parasitic capacitance generated between the second conductive layer and the third conductive layer is reduced, thereby enabling the transistor to operate at high speed and providing a semiconductor device with favorable electrical characteristics.

[0081] For example, the semiconductor device of one embodiment of the present invention preferably further includes a third insulating layer, wherein the second insulating layer covers a top surface and side surfaces of the oxide semiconductor layer over the first insulating layer, the third insulating layer is located over the second insulating layer and has a second opening at a position overlapping with the first opening, and the third conductive layer preferably has a portion that faces the oxide semiconductor layer in the first opening with the second insulating layer interposed therebetween and a portion that is located in the second opening.

[0082] The third conductive layer has a portion facing the oxide semiconductor layer through the second insulating layer in the first opening and a portion located within the second opening. In this case, the gate wiring is disposed on the third insulating layer, thereby increasing the physical distance between the second conductive layer and the gate wiring. Therefore, the parasitic capacitance generated between the second conductive layer and the gate wiring can be reduced. Note that a portion of the third conductive layer (the portion located on the third insulating layer) may function as the gate wiring, or the gate wiring may be provided on the fourth insulating layer separately from the third conductive layer.

[0083] For example, the semiconductor device of one embodiment of the present invention preferably further includes a fourth insulating layer. The fourth insulating layer is located in the first opening between the first insulating layer and the oxide layer. The fourth insulating layer preferably has a barrier property against hydrogen. With such a structure, the oxide semiconductor layer is surrounded by the fourth insulating layer having a barrier property against hydrogen in a ring shape, which can prevent hydrogen from entering the oxide semiconductor layer. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be increased.

[0084] The fourth insulating layer may be formed of multiple layers. For example, the fourth insulating layer can be formed of two layers: a first layer in contact with the first insulating layer and a second layer between the first layer and the oxide layer. In this case, the first layer has a barrier property against hydrogen, and the second layer has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the oxide semiconductor layer. Alternatively, the first layer has a barrier property against hydrogen, and the second layer has a region containing excess oxygen. This can reduce oxygen vacancies and / or impurities in the oxide semiconductor layer. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be enhanced.

[0085] In the transistor of one embodiment of the present invention, the source electrode and the drain electrode are located at different heights, and a current flows in the semiconductor layer in the height direction. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or a vertical channel transistor.

[0086] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0087] Furthermore, the channel length of the transistor of one embodiment of the present invention can be controlled by the thickness of the first insulating layer, etc. Therefore, a transistor with an extremely short channel length, which is difficult to achieve with a planar transistor, can be realized. Therefore, a transistor with a small occupation area and large on-state current can be realized.

[0088] Furthermore, since a transistor including an oxide semiconductor has a small off-state current, when used in a memory device, for example, stored data can be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. By using the transistor of one embodiment of the present invention in a memory device, the memory device can be highly integrated and has low power consumption.

[0089] <Structural Example 1 of Semiconductor Device> A structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 16B.

[0090] 1A and 1B are perspective views of a semiconductor device having a transistor 200. Fig. 1B is a perspective view with a portion cut away from Fig. 1A. In Fig. 1A and 1B, only the outlines of some components (such as interlayer insulating layers) are indicated by dashed lines.

[0091] 1A and 1B, the X direction, the Y direction, and the Z direction are indicated by arrows. Note that although the same X, Y, and Z symbols are used in both Fig. 1A and Fig. 1B, the directions do not necessarily have to match.

[0092] FIG. 2A1 is a plan view of a semiconductor device having a transistor 200. FIG. 2A2 is a plan view showing an example in which a plurality of transistors 200 are arranged. FIG. 2B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 2A1. FIG. 2C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 2A1. FIG. 2D is a cross-sectional view taken along dashed dotted line A5-A6 in FIG. 2B. Note that some elements are omitted in the plan views of FIGS. 2A1 and 2A2 for clarity. Some elements may also be omitted in the subsequent plan views.

[0093] 2A1。 Figure 3A is a cross-sectional view taken along dashed lines A3-A4 in Figure 2A1. Figure 3B is a cross-sectional view taken along dashed lines A5-A6 in Figure 2B. Figures 3A and 3B correspond to examples of enlarged views of Figures 2C and 2D, respectively.

[0094] 1A to 3B includes an insulating layer 210 over a substrate (not shown), a transistor 200 over the insulating layer 210, and an insulating layer 280 over the insulating layer 210. The insulating layer 210 and the insulating layer 280 function as interlayer films.

[0095] [Transistor 200] The transistor 200 includes a conductive layer 220, a conductive layer 240 over an insulating layer 280, an oxide layer 227, an oxide semiconductor layer 230 over the oxide layer 227, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The insulating layer 280 is located over the conductive layer 220.

[0096] 2B and 2C show an example in which the conductive layer 220 has a two-layer structure of a conductive layer 220_1 and a conductive layer 220_2 over the conductive layer 220_1, the oxide semiconductor layer 230 has a two-layer structure of an oxide semiconductor layer 230_1 and an oxide semiconductor layer 230_2 over the oxide semiconductor layer 230_1, the conductive layer 240 has a two-layer structure of a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1, and the conductive layer 260 has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. The oxide semiconductor layer 230_1 corresponds to the first oxide semiconductor layer described above, and the oxide semiconductor layer 230_2 corresponds to the second oxide semiconductor layer described above.

[0097] In the transistor 200, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and the drain electrode. The conductive layer 260 has a region that functions as a gate wiring.

[0098] As shown in FIGS. 2B and 2C, an opening 290 is provided in the insulating layer 280 and the conductive layer 240, reaching the conductive layer 220.

[0099] The opening 290 includes an opening in the insulating layer 280 and an opening in the conductive layer 240. In other words, the opening in the region where the insulating layer 280 overlaps with the conductive layer 220 is a part of the opening 290, and the opening in the region where the conductive layer 240 overlaps with the conductive layer 220 is another part of the opening 290. The shape and size of the opening 290 in a planar view may differ depending on the layer. Furthermore, when the top surface shape of the opening 290 is circular, the openings in each layer may or may not be concentric.

[0100] At least some of the components of the transistor 200 are disposed in the opening 290. Specifically, the oxide layer 227, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed so that at least a portion thereof is located in the opening 290. Furthermore, the portions of the oxide layer 227, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 that are disposed in the opening 290 are provided so as to reflect the shape of the opening 290.

[0101] The oxide layer 227 is provided so as to cover the bottom and sidewalls of the opening 290. The oxide layer 227 also has a recess that reflects the shape of the opening 290.

[0102] The oxide semiconductor layer 230 is provided so as to cover the oxide layer 227. That is, the oxide semiconductor layer 230 has a region in the opening 290 that faces the insulating layer 280 with the oxide layer 227 sandwiched therebetween. The oxide semiconductor layer 230 also has a recess that reflects the shape of the recess in the oxide layer 227. The oxide semiconductor layer 230 has a portion located on the conductive layer 240 and a portion located on the conductive layer 220 within the opening 290.

[0103] When the oxide semiconductor layer 230 has a two-layer structure of the oxide semiconductor layer 230_1 and the oxide semiconductor layer 230_2, the oxide semiconductor layer 230_1 has a region facing the insulating layer 280 with the oxide layer 227 sandwiched therebetween in the opening 290. The oxide semiconductor layer 230_2 is provided to cover the oxide semiconductor layer 230_1.

[0104] The insulating layer 250 is provided to cover the oxide semiconductor layer 230. The insulating layer 250 is provided on the insulating layer 280 to cover the top surface and side surfaces of the oxide semiconductor layer 230. The insulating layer 250 has a recess that reflects the shape of the recess that the oxide semiconductor layer 230 has.

[0105] The conductive layer 260 is provided so as to fill at least a part of the recessed portion of the insulating layer 250. The conductive layer 260 has a region in the opening 290 that faces the oxide semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0106] The oxide semiconductor layer 230 has a region overlapping with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200. One of a region of the oxide semiconductor layer 230 near the conductive layer 220 and a region of the oxide semiconductor layer 230 near the conductive layer 240 functions as a source region, and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0107] The oxide semiconductor layer 230 is provided inside the opening 290. The transistor 200 has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 here) is located above, so that current flows vertically. That is, a channel is formed along the side surface of the opening 290.

[0108] The transistor 200 includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. That is, the transistor 200 can be said to be an OS transistor.

[0109] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0110] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. ＯThe source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0111] Note that when many defects exist in the oxide semiconductor layer 230, levels due to the defects (also referred to as defect levels) are formed. When a negative voltage is applied to the gate, it is estimated that Fermi level pinning caused by the defect levels suppresses an increase in the energy barrier and makes it easier for electrons to overcome the energy barrier, that is, the threshold voltage is shifted negatively or the off-state current is increased.

[0112] Therefore, it is preferable to provide a layer with high resistivity between the oxide semiconductor layer 230 and the conductive layer 220 or the conductive layer 240. By providing the layer, an energy barrier can be maintained and a negative shift in the threshold voltage or a decrease in the on-state current can be suppressed. Therefore, the threshold voltage of the transistor 200 is shifted in the positive direction, and the transistor 200 can be made normally off. As a result, the electrical characteristics of the transistor 200 can be improved, and the reliability of the transistor 200 can be improved. An example of such a layer is the oxide layer 227 shown in FIGS. 2B and 2C .

[0113] For example, the resistivity of the oxide layer 227 is preferably higher than that of the oxide semiconductor layer 230_1. Specifically, the oxide layer 227 preferably contains at least one of aluminum, gallium, and yttrium, and more preferably contains gallium. For example, the oxide layer 227 preferably has a region in which the gallium content is higher than that of the oxide semiconductor layer 230_1. With such a structure, the oxide layer 227 having higher resistivity than the oxide semiconductor layer 230_1 can be provided.

[0114] When the oxide layer 227 contains gallium, it can be said that the oxide layer 227 contains gallium oxide. When the oxide layer 227 contains aluminum, it can be said that the oxide layer 227 contains aluminum oxide. When the oxide layer 227 contains yttrium, it can be said that the oxide layer 227 contains yttrium oxide.

[0115] Note that an oxide layer containing at least one of aluminum, gallium, and yttrium may have a function of suppressing oxygen transmission. The oxide layer 227 in contact with the oxide semiconductor layer 230_1 has a function of suppressing oxygen transmission, which can suppress release of oxygen from the oxide semiconductor layer 230_1 and suppress formation of oxygen vacancies in the oxide semiconductor layer 230_1 or an increase in the amount of oxygen vacancies in the oxide semiconductor layer 230_1. This can improve the electrical characteristics of the transistor 200.

[0116] When the oxide layer 227 contains at least one of aluminum, gallium, and yttrium, electron traps may be formed at the drain edge, which shifts the threshold voltage in the positive direction and enables the transistor 200 to be normally off.

[0117] On the other hand, the oxide layer 227 preferably has a small thickness. For example, the oxide layer 227 is preferably thinner than the oxide semiconductor layer 230. With such a structure, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 or the conductive layer 240 can be prevented from increasing.

[0118] Specifically, the oxide layer 227 preferably has a region with a thickness of 0.1 nm to 3 nm, more preferably has a region with a thickness of 0.1 nm to 2 nm, or more preferably has a region with a thickness of 0.5 nm to 3 nm, and further preferably has a region with a thickness of 0.5 nm to 2 nm.

[0119] Note that there is no particular limitation on the material that can be used for the oxide layer 227 as long as the resistivity of the oxide layer 227 is higher than that of the oxide semiconductor layer 230_1. The oxide layer 227 may be formed using an insulating material or a semiconductor material. For example, the oxide layer 227 can be formed using a metal oxide material that can be used for the oxide semiconductor layer 230. For example, the oxide layer 227 can contain one or both of gallium and zinc. When the oxide layer 227 contains zinc, the crystallinity of the oxide layer 227 is increased, and the crystallinity of the oxide semiconductor layer 230 provided over the oxide layer 227 can be improved.

[0120] Specifically, the oxide layer 227 can be formed using a single layer or a stack of gallium oxide, zinc oxide, indium gallium oxide (In—Ga oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), or the like. When In—Ga—Zn oxide is used as the oxide layer 227, the indium content in the oxide layer 227 is preferably lower than the gallium content. Specifically, the oxide layer 227 may be formed using a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition similar thereto, or an atomic ratio of In:Ga:Zn=1:3:4 or a composition similar thereto. In this case, the oxide layer 227 contains at least indium and gallium.

[0121] Note that when an oxide layer containing silicon is provided in contact with the oxide semiconductor layer 230, part of silicon in the oxide might be mixed into the oxide semiconductor layer 230, causing oxygen vacancies in the oxide semiconductor layer 230. Therefore, the silicon concentration in the oxide layer 227 is preferably low. For example, the silicon concentration in the oxide layer 227 obtained by SIMS is 1.0×10 ２１ atoms / cm ３ or less, preferably 5.0 × 10 ２０ atoms / cm ３ or less, more preferably 1.0 × 10 ２０ atoms / cm ３The following applies.

[0122] As described above, by providing the oxide layer 227 between the oxide semiconductor layer 230 and the conductive layer 220 or the conductive layer 240, the electrical characteristics of the transistor 200 can be improved and the reliability of the transistor 200 can be improved.

[0123] The oxide semiconductor layer 230_1 preferably contains indium (In), and more preferably has a high In content. For example, the In content in the oxide semiconductor layer 230_1 is preferably higher than that in the oxide semiconductor layer 230_2. By using a metal oxide with a high In content as the oxide semiconductor layer 230_1, the on-state current can be increased and the frequency characteristics can be improved.

[0124] The etching rate of the oxide semiconductor layer 230_1 is preferably low. For example, the etching rate of the oxide semiconductor layer 230_1 in one etchant is preferably lower than the etching rate of the oxide semiconductor layer 230_2. Furthermore, the film density of the oxide semiconductor layer 230_1 is preferably high. For example, the film density of the oxide semiconductor layer 230_1 is preferably higher than the film density of the oxide semiconductor layer 230_2. This can reduce defects contained in the oxide semiconductor layer 230_1. Therefore, the density of defect states in the oxide semiconductor layer 230_1 can be reduced, and a highly reliable transistor can be realized.

[0125] Furthermore, by using an oxide film with a low etching rate for the oxide semiconductor layer 230_1, diffusion of oxygen in the oxide semiconductor layer 230_1 can be suppressed. Therefore, excessive oxygen can be prevented from being mixed into the oxide semiconductor layer 230_1, and oxygen in the oxide semiconductor layer 230_1 can be prevented from diffusing outward. Therefore, a highly reliable transistor can be realized.

[0126] Note that the etching rate of the oxide semiconductor layer 230_1 may be high. In addition, the film density of the oxide semiconductor layer 230_1 may be low. In this way, etching can be performed at a high etching rate, and therefore the time required for etching the oxide semiconductor layer 230_1 can be shortened.

[0127] The film density can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a pale (bright) transmission electron (TE) image. Even when the same material is used for the insulating layer, if the film densities are different, the boundary between the two can sometimes be observed as a difference in contrast in a cross-sectional TEM image.

[0128] For example, the oxide semiconductor layer 230_1 preferably contains indium oxide. Furthermore, indium oxide is preferably used for the oxide semiconductor layer 230_1. Alternatively, an In—Zn oxide may be used for the oxide semiconductor layer 230_1. Specifically, a metal oxide having an atomic ratio of In:Zn=1:1 or a composition thereof, an atomic ratio of In:Zn=2:1 or a composition thereof, or an atomic ratio of In:Zn=4:1 or a composition thereof can be used.

[0129] Alternatively, the oxide semiconductor layer 230_1 may include an In—Zn oxide containing a trace amount of element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin.

[0130] For example, metal oxides having a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or thereabout, In:Ga:Zn=2:0.1:1 (atomic ratio) or thereabout, or In:Ga:Zn=1:0.1:1 (atomic ratio) or thereabout can be used. Furthermore, metal oxides having a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or thereabout, In:Sn:Zn=2:0.1:1 (atomic ratio) or thereabout, or In:Sn:Zn=1:0.1:1 (atomic ratio) or thereabout can be used.

[0131] The oxide semiconductor layer 230_2 is preferably made of a metal oxide having a higher Ga content than that of the oxide semiconductor layer 230_1. Increasing the Ga content can improve the barrier property of the oxide semiconductor layer 230_2 against hydrogen. Therefore, hydrogen can be prevented from diffusing from above the oxide semiconductor layer 230_2 to the oxide semiconductor layer 230_1. Increasing the Ga content can reduce impurities such as hydrogen and water contained in the oxide semiconductor layer 230 due to heat or the like applied after the formation of the oxide semiconductor layer 230. Note that using a metal oxide having a lower In content than that of the oxide semiconductor layer 230_1 for the oxide semiconductor layer 230_2 can sometimes produce the same effect.

[0132] For example, the oxide semiconductor layer 230_2 preferably includes a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereof, an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereof, or an atomic ratio of In:Ga:Zn=1:3:4 or a composition thereof. In this case, the oxide semiconductor layer 230_2 contains indium and gallium.

[0133] Typically, gallium oxide, indium oxide, and a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereof can be used for the oxide layer 227, the oxide semiconductor layer 230_1, and the oxide semiconductor layer 230_2. The thicknesses of the oxide layer 227, the oxide semiconductor layer 230_1, and the oxide semiconductor layer 230_2 are set to 0.5 nm to 1 nm, 5 nm, and 5 nm, respectively.

[0134] When indium oxide, In—Zn oxide, or In—Zn oxide containing a trace amount of element M is used as the oxide semiconductor layer 230_1, the conduction band bottom of the oxide layer 227 might be located closer to the vacuum level than the conduction band bottom of the oxide semiconductor layer 230_1. Furthermore, by increasing the Ga content, the conduction band bottom of the oxide semiconductor layer 230_2 might be located closer to the vacuum level than the conduction band bottom of the oxide semiconductor layer 230_1. In this case, the oxide semiconductor layer 230_1 is sandwiched between the oxide layer 227 and the oxide semiconductor layer 230_2, whose conduction band bottoms are closer to the vacuum level, and can function mainly as a current path (channel).

[0135] By sandwiching the oxide semiconductor layer 230_1 between the oxide layer 227 and the oxide semiconductor layer 230_2, carriers trapped at the interface of the oxide semiconductor layer 230_1 and its vicinity can be reduced. In addition, the channel can be distanced from the surface of the insulating layer 250, and the influence of surface scattering or interface scattering can be reduced. As a result, a buried channel transistor in which the channel is distanced from the insulating layer interface can be realized, and field-effect mobility can be increased.

[0136] FIG. 3C shows a band diagram of the oxide semiconductor layer 230 and its vicinity. In FIG. 3C, the vertical axis represents energy, and the horizontal direction represents the film thickness direction (A5-A6 direction) at the center of the channel formation region. FIG. 3C also shows the valence band maximum (VBM) and conduction band minimum (CBM) of each of the oxide layer 227, the oxide semiconductor layer 230_1, the oxide semiconductor layer 230_2, and the insulating layer 250 when no voltage is applied between the gate and the source. The vacuum level Vac is indicated by a dashed line in FIG. 3C.

[0137] Note that the energy of the upper end of the valence band and the energy of the lower end of the conduction band vary depending on the constituent elements and compositions of the oxide layer 227, the oxide semiconductor layer 230_1, the oxide semiconductor layer 230_2, and the insulating layer 250. Therefore, the relationship in level between the energies of the upper ends of the valence bands and the lower ends of the conduction bands will be mainly described with reference to the band diagram in FIG. 3C .

[0138] Depending on the constituent elements and compositions of the oxide layer 227, the oxide semiconductor layer 230_1, and the oxide semiconductor layer 230_2, the transistor 200 may have a structure in which the oxide semiconductor layer 230_1 is sandwiched between the oxide layer 227 and the oxide semiconductor layer 230_2, whose conduction band minimums are closer to the vacuum level than the oxide semiconductor layer 230_1, as shown in FIG. 3C . This structure can realize a buried channel. That is, this structure forms a path through which more current (electrons are illustrated as carriers in FIG. 3C ) flows in the oxide semiconductor layer 230_1. Therefore, an increase in on-state current or improvement in reliability can be achieved.

[0139] For example, the conduction band bottom of the oxide layer 227 is located closer to the vacuum level than the conduction band bottom of the oxide semiconductor layer 230_1, and the band offset between the oxide layer 227 and the oxide semiconductor layer 230_1 is preferably 0.01 eV to 1.0 eV, more preferably 0.01 eV to 0.7 eV, and still more preferably 0.01 eV to 0.5 eV. Alternatively, the band offset is preferably 0.1 eV to 1.0 eV, more preferably 0.1 eV to 0.7 eV, and still more preferably 0.1 eV to 0.5 eV. Note that in this specification and the like, the band offset between the first layer and the second layer refers to the energy difference between the conduction band bottom of the first layer and the conduction band bottom of the second layer.

[0140] Similarly, the conduction band bottom of the oxide semiconductor layer 230_2 is located closer to the vacuum level than the conduction band bottom of the oxide semiconductor layer 230_1, and the band offset between the oxide semiconductor layer 230_2 and the oxide semiconductor layer 230_1 is preferably 0.01 eV to 1.0 eV, more preferably 0.01 eV to 0.7 eV, and still more preferably 0.01 eV to 0.5 eV, or preferably 0.1 eV to 1.0 eV, more preferably 0.1 eV to 0.7 eV, and still more preferably 0.1 eV to 0.5 eV.

[0141] The band gap of a metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS). Furthermore, a combination of these techniques can be used for analysis. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the energy difference between the vacuum level and the top of the valence band, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0142] 3A, a recess is provided in the conductive layer 220_2. In other words, the conductive layer 220 has a recess, the bottom surface of which corresponds to the bottom surface of the recess of the conductive layer 220_2, and the side surface of which corresponds to the side surface of the recess of the conductive layer 220_2.

[0143] The opening 290 overlaps with the recess of the conductive layer 220_2. Here, the bottom of the opening 290 includes the bottom surface of the recess of the conductive layer 220_2, and the sidewall of the opening 290 includes the side surface of the recess of the conductive layer 220_2, the side surface of the insulating layer 280, and the side surface of the conductive layer 240.

[0144] By providing a recess in the conductive layer 220_2 at a position overlapping with the opening 290, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be lower than the height of the top surface of the conductive layer 220_2 in contact with the insulating layer 280, relative to the top surface of the insulating layer 210, as compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the top surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0145] The oxide layer 227 is in contact with the bottom surface and side surfaces of the recessed portion of the conductive layer 220_2 and the top surface of the conductive layer 240_2. The recessed portion of the conductive layer 220_2 can increase the area where the oxide semiconductor layer 230 and the conductive layer 220_2 overlap with each other through the oxide layer 227. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220_2 can be reduced.

[0146] 2B illustrates a structure in which the end portions of the conductive layer 240, the oxide layer 227, and the oxide semiconductor layer 230 are aligned outside the opening 290. The conductive layer 240, the oxide layer 227, and the oxide semiconductor layer 230 can be manufactured by processing using the same mask. This is preferable because the number of masks required for manufacturing a semiconductor device can be reduced. Note that the present invention is not limited to this. For example, a structure may be employed in which any one of the end portions of the oxide semiconductor layer 230, the oxide layer 227, the conductive layer 240_1, and the conductive layer 240_2 is located inside or outside the other end portions in the X or Y direction.

[0147] The conductive layer 240 is preferably not located inside the opening 290 of the insulating layer 280. That is, the conductive layer 240 preferably does not have a region in contact with the side surface of the insulating layer 280 inside the opening 290. With this configuration, the opening 290 can be formed in the conductive layer 240 and the insulating layer 280 at the same time. Furthermore, if the side surface of the conductive layer 240 and the side surface of the insulating layer 280 are aligned inside the opening 290, the film thickness distribution of the oxide layer 227, the oxide semiconductor layer 230, and the like provided inside the opening 290 can be made uniform. Furthermore, it is possible to prevent the oxide layer 227, the oxide semiconductor layer 230, and the like from being separated by a step or the like between the conductive layer 240 and the insulating layer 280.

[0148] As described above, the channel formation region, the source region, and the drain region can be formed in the opening 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.

[0149] 2A2 shows an example in which a plurality of transistors 200 are arranged in a matrix. Specifically, FIG. 2A2 shows an example in which 4×4 transistors are arranged in the X and Y directions. As shown in FIG. 2A2, the transistor 200 is provided at the intersection of a conductive layer 260 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in FIG. 2A2, the diameter of the opening 290 can be made smaller than both the width of the short side of the conductive layer 240 and the width of the short side of the conductive layer 260. In this way, the transistor 200 can be said to have a structure that allows for high integration and miniaturization.

[0150] As shown in FIG. 3B , the oxide layer 227, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 located at the center faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, the entire periphery of the oxide semiconductor layer 230 becomes a channel formation region in a plan view. In this case, for example, the channel width of the transistor 200 is determined by the outer periphery of the oxide semiconductor layer 230. That is, the channel width of the transistor 200 can be determined by the width of the opening 290 (or the diameter when the opening 290 is circular in a plan view). In FIGS. 3A and 3B , the width D of the opening 290 is shown, and in FIG. 3B , the channel width W of the transistor 200 is shown. Because the oxide layer 227 is thin, the channel width W can be considered as the length of the outline of the opening 290 in a plan view.

[0151] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. On the other hand, the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view, is roughly determined by the width of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200, thereby enabling a semiconductor device to be highly integrated.

[0152] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the conductive layer 240 on the opening 290 side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening 290 in the conductive layer 240 is used as the width D of the opening 290. Alternatively, the width of the opening 290 at the highest position in the conductive layer 240, the width of the opening 290 at the lowest position, the width of the opening 290 at a midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D is determined using the width of the opening 290 in the conductive layer 240, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280 on the opening 290 side may be used as the width D. Alternatively, the width of the opening 290 at the highest position in the insulating layer 280, the width of the opening 290 at the lowest position, the width of the opening 290 at a midpoint between these, or the average value of these three widths may be used as the width D.

[0153] When the opening 290 is formed using photolithography, the width D of the opening 290 is set by the exposure limit of photolithography. The width D of the opening 290 is set by the film thickness of each of the oxide layer 227, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0154] The channel length of the transistor 200 is the distance between the source region and the drain region. In other words, the channel length of the transistor 200 can be determined by the thickness of the insulating layer 280 on the conductive layer 220. In FIG. 3A , the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. Note that because the oxide layer 227 is thin, the channel length L can be considered to be the distance between the end of the region where the oxide semiconductor layer 230 and the conductive layer 220 face each other across the oxide layer 227 in a cross-sectional view and the end of the region where the oxide semiconductor layer 230 and the conductive layer 240 face each other across the oxide layer 227 in a cross-sectional view. In this case, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side in a cross-sectional view.

[0155] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 200 can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor 200 can be made into a very fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, thereby improving its frequency characteristics.

[0156] Note that the channel length of the transistor 200 is determined by the thickness of the insulating layer 280 over the conductive layer 220, and therefore the channel length does not affect the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view. Setting the channel length of the transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less can improve productivity and yield in forming the insulating layer 280, forming the opening 290 in the insulating layer 280, and the like.

[0157] From the above, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0158] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0159] As described above, by forming the opening 290 so as to have a circular shape in a plan view, the oxide layer 227, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. This makes the distance between the conductive layer 260 and the oxide semiconductor layer 230 approximately uniform, so that a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0160] Although the present embodiment illustrates an example in which the opening 290 is circular in plan view, the present invention is not limited thereto. In plan view, the opening 290 may be, for example, a circle or a substantially circular shape such as an oval, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygonal shape with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 2A1 and other figures, the opening 290 is preferably circular in plan view. By using a circular shape, the processing accuracy during the formation of the opening can be improved, allowing for the formation of openings of minute sizes. In this specification and other figures, the term "circular" is not limited to a perfect circle.

[0161] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0162] [Oxide Semiconductor Layer 230] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a stacked structure of two or more layers.

[0163] The crystallinity of a semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0164] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the oxide semiconductor layer 230, the off-state current of the transistor 200 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the OS transistor has high frequency characteristics, the semiconductor device can operate at high speed.

[0165] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, refer to the description in Embodiment 2. Detailed description thereof will be omitted here.

[0166] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material for a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0167] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0168] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0169] In addition, a transistor in which a layer material functioning as a semiconductor is used for a channel formation region may be applied to the semiconductor device of this embodiment mode. Note that the layer material will be described in detail in Embodiment Mode 5.

[0170] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layers included in the semiconductor device.

[0171] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, it also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0172] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0173] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0174] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to 1:1. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0175] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above-mentioned metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0176] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0177] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0178] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in the third embodiment can have a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0179] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0180] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0181] Ferroelectricity is believed to be exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals having an orthorhombic crystal structure is preferred because it exhibits ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0182] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, if the amount of Group 3 element added is too large, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0183] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0184] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include nitrides such as aluminum nitride, aluminum titanium nitride, and silicon nitride. Other examples include nitride oxides such as silicon nitride oxide.

[0185] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0186] An insulating layer provided in contact with or near the oxide semiconductor layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer.

[0187] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and silicon (hafnium silicate), etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium.

[0188] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0189] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0190] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0191] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0192] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. −Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0193] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0194] Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0195] Since the insulating layer 210 functions as an interlayer film, it is preferable to use the above-mentioned material having a low relative dielectric constant. By using a material having a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0196] A barrier insulating layer against hydrogen is preferably used for the insulating layer 210. When the insulating layer 210 provided below the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200 to the oxide semiconductor layer 230 can be suppressed. For example, a silicon nitride film is preferably used as the insulating layer 210.

[0197] An insulating layer having a function of capturing or fixing hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 210 through the conductive layer 220, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0198] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced, which can prevent impurities such as hydrogen or water from entering a channel formation region of the oxide semiconductor layer 230.

[0199] 3A shows an example in which the insulating layer 210 has a single-layer structure. Note that the insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable to use a barrier insulating layer against hydrogen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0200] Since the insulating layer 280 functions as an interlayer film, it is preferable to use the above-mentioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0201] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of the oxide semiconductor layer 230.

[0202] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least some of the layers constituting the insulating layer 280 by sputtering, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and V. Ｏ H can be reduced.

[0203] Note that the thickness of the insulating layer 280 on the conductive layer 220 affects the channel length of the transistor 200 , and therefore the thickness of the insulating layer 280 is set appropriately in accordance with the design value of the channel length of the transistor 200 .

[0204] FIG. 3A shows an example in which the insulating layer 280 has a single-layer structure. Note that the insulating layer 280 can have a stacked structure of two or more layers. For example, as shown in FIG. 4A, the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2. In this case, it is preferable to use the above-described material with a low relative dielectric constant for the insulating layer 280_2, and to use barrier insulating layers against oxygen for the insulating layers 280_1 and 280_3. This can suppress oxidation of the conductive layer 220 and the conductive layer 240 and prevent high resistance.

[0205] For example, it is preferable to use a silicon nitride film or an aluminum oxide film for the insulating layer 280_1 and the insulating layer 280_3, and a silicon oxide film for the insulating layer 280_2. Note that each of the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0206] A barrier insulating layer against hydrogen is preferably used for the insulating layer 250. When the insulating layer 250 provided over the oxide semiconductor layer 230 has a barrier property against hydrogen, hydrogen contained in the conductive layer 260 can be prevented from diffusing into the oxide semiconductor layer 230. For example, a silicon nitride film is suitable as the insulating layer 250 because it has a high barrier property against hydrogen.

[0207] Furthermore, since the insulating layer 250 is in contact with the oxide semiconductor layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0208] An insulating layer having a region containing excess oxygen is preferably used as the insulating layer 250. In this way, oxygen can be supplied from the insulating layer 250 to the oxide semiconductor layer 230, and oxygen vacancies in the oxide semiconductor layer 230 can be reduced. A silicon oxide film, a silicon oxynitride film, or the like is suitable for the insulating layer 250 because it has a structure that is stable against heat.

[0209] 3A shows an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed using two or more types of films. By using two or more types of films as the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the oxide semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230.

[0210] For example, the insulating layer 250 can have a two-layer structure including a first insulating layer and a second insulating layer over the first insulating layer. In this case, the first insulating layer is in contact with the oxide semiconductor layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0211] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be provided.

[0212] Furthermore, for example, the insulating layer 250 can have a third insulating layer between the oxide semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure including the third insulating layer, the first insulating layer on the third insulating layer, and the second insulating layer on the first insulating layer.

[0213] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having a barrier property against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the oxide semiconductor layer 230, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, a decrease in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230 can be suppressed.

[0214] Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the oxide semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure including the fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer. The fourth insulating layer is a layer in contact with the oxide semiconductor layer 230 among the two or more stacked layers included in the insulating layer 250.

[0215] An insulating layer having a barrier property against oxygen is preferably used as the fourth insulating layer. Note that the first to third insulating layers can have the same structure as the layers used in the above-described three-layer structure. The fourth insulating layer is a layer in contact with the oxide semiconductor layer 230 and the conductive layer 240. The fourth insulating layer having a barrier property against oxygen can prevent oxygen from being released from the oxide semiconductor layer 230. Furthermore, the side surfaces of the conductive layer 240 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 200.

[0216] For example, an aluminum oxide film may be used as the fourth insulating layer. The aluminum oxide film has a function of capturing or adhering hydrogen or a barrier property against hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side.

[0217] In addition, when an aluminum oxide film is used as the fourth insulating layer and an In—Zn oxide film is used as the oxide semiconductor layer 230_2, diffusion of hydrogen into the oxide semiconductor layer 230_1 can be suppressed in some cases.

[0218] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage kept constant in the subthreshold region.

[0219] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0220] Typically, the thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0221] Note that the insulating layer 250 having a four-layer structure may not include the second insulating layer. For example, an insulating layer having a barrier property against oxygen can be used as the fourth insulating layer, an insulating layer containing a material with a low dielectric constant can be used as the third insulating layer, and an insulating layer having a function of capturing or fixing hydrogen can be used as the first insulating layer. Specifically, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side can be used.

[0222] In addition, in forming the insulating layer 250 having a stacked structure of multiple insulating films, it is preferable to use an atomic layer deposition (ALD) process two or more times. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, it is possible to increase productivity by successively forming two or more types of films, for example, two or more types of insulating films, using the ALD process.

[0223] [Conductive Layer] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0224] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (In—Sn oxide, also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also referred to as ITSO), indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0225] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0226] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0227] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0228] The conductive layer 220 and the conductive layer 240 are each a conductive layer in contact with the oxide layer 227, and therefore are preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0229] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 210, the conductive layer 220 is preferably able to maintain its conductivity. For example, ITO, ITSO, In—Zn oxide, or the like is preferably used for each of the conductive layer 220 and the conductive layer 240.

[0230] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, by using a conductive material containing oxygen for the layer in the stacked structure that has the largest contact area with the oxide layer 227, the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230 and between the conductive layer 240 and the oxide semiconductor layer 230 can be reduced.

[0231] 4A shows an example in which the conductive layer 220_1 has a two-layer structure including a conductive layer 220_11 and a conductive layer 220_12 over the conductive layer 220_11. In other words, the conductive layer 220 shown in FIG. 4A has a three-layer structure including a conductive layer 220_11, a conductive layer 220_12 over the conductive layer 220_11, and a conductive layer 220_2 over the conductive layer 220_12. In this case, for example, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 220_11, a material with high conductivity as the conductive layer 220_12, and a conductive material containing oxygen (more preferably an oxide conductor) as the conductive layer 220_2. Specifically, it is preferable to use titanium nitride for the conductive layer 220_11, tungsten for the conductive layer 220_12, and an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 220_2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the oxide semiconductor layer 230. Furthermore, the oxide conductor is used for the layer closest to the channel formation region of the oxide semiconductor layer 230. Compared to tungsten, the oxide conductor has lower contact resistance with the oxide semiconductor layer 230, so that the current path between the source and drain can be shortened and the on-state current of the transistor 200 can be increased. With such a structure, the conductive layer 220 can maintain conductivity even when in contact with the oxide layer 227. Furthermore, when an oxide insulating layer is used for the insulating layer 210, the insulating layer 210 can prevent the conductive layer 220 from being excessively oxidized. Furthermore, when a metal material (tungsten here) having higher conductivity than an oxide conductor and titanium nitride is used for the conductive layer 220_12, the conductivity of the conductive layer 220 can be increased.

[0232] The conductive layer 240 shown in FIG. 3A has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240_2 and a material having higher conductivity than the conductive layer 240_2 for the conductive layer 240_1. Specifically, for example, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240_2 and tungsten for the conductive layer 240_1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240_1. By using an oxide conductor for the conductive layer 240_2 that is mainly in contact with the oxide layer 227, the contact resistance with the oxide semiconductor layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240, the conductivity of the conductive layer 240 can be increased.

[0233] Note that the conductive layer 240_1 may be formed using a conductive material containing oxygen, and the conductive layer 240_2 may be formed using a material having higher conductivity than the conductive layer 240_1. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the oxide semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0234] The conductive layer 260 has a region that functions as a gate wiring. The conductive layer 260 is preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 260 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0235] Furthermore, the conductive layer 260 preferably uses a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer may be captured.

[0236] 3A has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, it is preferable to use a titanium nitride film as the conductive layer 260_1 and a tungsten film as the conductive layer 260_2. Alternatively, it is preferable to use a tantalum nitride film as the conductive layer 260_1 and a copper film as the conductive layer 260_2. Such a structure can increase the conductivity of the conductive layer 260.

[0237] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0238] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0239] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0240] 4A , the semiconductor device of one embodiment of the present invention may include an insulating layer 283 over the transistor 200. Specifically, the insulating layer 283 may be provided over the conductive layer 260 and the insulating layer 250.

[0241] A barrier insulating layer against hydrogen is preferably used for the insulating layer 283. With such a structure, diffusion of hydrogen from above the transistor 200 to the oxide semiconductor layer 230 can be suppressed.

[0242] 3A , both the conductive layer 260_1 and the conductive layer 260_2 are located in the opening 290. Note that as the transistor 200 is miniaturized and the width of the opening 290 becomes smaller, it becomes more difficult to arrange all of the layers that form the conductive layer 260 in the opening 290. Depending on the width of the opening 290 and the thicknesses of the oxide layer 227, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260_1, the conductive layer 260_1 may be provided in the opening 290 and the conductive layer 260_2 may be provided so as to overlap with the opening 290 (see FIG. 4B ).

[0243] 4A shows a configuration in which the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 are flush (aligned or approximately aligned), but the present invention is not limited to this. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 may be discontinuous. Furthermore, the inclination of the side surface of the conductive layer 240 in the opening 290 and the inclination of the side surface of the insulating layer 280 in the opening 290 may differ from each other. In this case, part of the side wall of the opening 290 has a tapered shape.

[0244] 5A and 5B show examples in which at least a portion of the sidewall of the opening 290 is tapered. Fig. 5A shows an example in which the side surface of the conductive layer 240 in the opening 290 is tapered, and Fig. 5B shows an example in which the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 are both tapered.

[0245] By tapering the sidewall of the opening 290, the coverage of the oxide layer 227, the oxide semiconductor layer 230, the insulating layer 250, and the like can be improved, and defects such as voids can be reduced. When the sidewall of the opening 290 is tapered, for example, the taper angle (angle θ240) of the side surface of the conductive layer 240 in the opening 290 and the taper angle (angle θ280) of the side surface of the insulating layer 280 in the opening 290 are preferably 45 degrees or more and less than 90 degrees. Specifically, a taper angle of 80 degrees or more and less than 90 degrees is preferable, as described above, because this allows for miniaturization or high integration of the semiconductor device. Furthermore, a taper angle of 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable, because this improves the coverage of the film formed in the opening 290.

[0246] Furthermore, for example, it is preferable that angle θ240 is smaller than angle θ280. With such a configuration, coverage of the side surface of conductive layer 240 in opening 290 by oxide layer 227, oxide semiconductor layer 230, etc. is improved, and defects such as voids can be reduced. Furthermore, when insulating layer 280 has a stacked structure, the inclination of the side surface of each layer in opening 290 may be different. Similarly, when conductive layer 240 has a stacked structure, the inclination of the side surface of each layer in opening 290 may be different.

[0247] 6 , the oxide semiconductor layer 230 may have a different ratio between the film thickness (hereinafter referred to as the first film thickness) of a portion where the top surface of the conductive layer 240 or the conductive layer 220 is to be formed and the film thickness (hereinafter referred to as the second film thickness) of a portion where the sidewall of the opening 290 is to be formed. For example, when a portion of the oxide semiconductor layer 230 is formed by a sputtering method, the oxide semiconductor layer 230 may have a different ratio between the first film thickness and the second film thickness. For example, as shown in FIG. 6 , the ratio of the second film thickness to the first film thickness may be less than 1, less than 0.8, or less than 0.5. In particular, the closer the angle θ 280 is to 90 degrees, the smaller the ratio of the second film thickness to the first film thickness in the oxide semiconductor layer 230 tends to be.

[0248] 7A1 to 16B, examples of the configuration of a transistor that is partially different from the configuration of transistor 200 will be described. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0249] [Transistor 200A] Fig. 7A1 is a plan view of a semiconductor device including a transistor 200A. Fig. 7A2 is a plan view showing an example of arranging a plurality of transistors 200A. Fig. 7B is a cross-sectional view taken along dashed line A1-A2 in Fig. 7A1. Fig. 7C is a cross-sectional view taken along dashed line A3-A4 in Fig. 7A1. For a cross-sectional view taken along dashed line A5-A6 in Fig. 7B, refer to Fig. 2D. An enlarged view of Fig. 7C is shown in Fig. 8A.

[0250] 7A1 to 7C includes an insulating layer 210 over a substrate (not shown), a transistor 200A over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 284, an insulating layer 285 over the insulating layer 284, and a conductive layer 265 over the transistor 200A, the insulating layer 284, and the insulating layer 285. The insulating layer 210, the insulating layer 280, the insulating layer 284, and the insulating layer 285 function as interlayer films.

[0251] The semiconductor device shown in FIGS. 7A1 to 7C differs from the semiconductor device shown in FIGS. 2A1 to 2D in that it includes a conductive layer 265, an insulating layer 284, and an insulating layer 285.

[0252] The conductive layer 265 functions as a gate wiring. The conductive layer 265 can be formed using a material that can be used for the conductive layer 260. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 265. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0253] The transistor 200A includes a conductive layer 220, a conductive layer 240 over an insulating layer 280, an oxide layer 227, an oxide semiconductor layer 230 over the oxide layer 227, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The conductive layer 265 has a region in contact with the conductive layer 260. Note that the conductive layer 265 may be considered a component of the transistor 200A. The insulating layer 284 is provided over the insulating layer 250.

[0254] In the transistor 200A, the stacked structure from the conductive layer 220 to the insulating layer 250 is similar to that of the above-described transistor 200, and therefore detailed description thereof will be omitted.

[0255] 7B and 7C , insulating layer 284 is provided so as to be located on insulating layer 250. Furthermore, insulating layer 284 is provided with openings 270 that reach insulating layer 250 at positions overlapping openings 290. Conductive layer 260 is disposed so that at least a portion thereof is located within opening 270. Conductive layer 260 contacts insulating layer 250 within opening 270.

[0256] The conductive layer 260 is provided to fill the openings 290 and 270. The conductive layer 260 has a portion that faces the oxide semiconductor layer 230 in the opening 290 with the insulating layer 250 interposed therebetween, and a portion that is located in the opening 270.

[0257] 7B and 7C show an example in which both the conductive layer 260_1 and the conductive layer 260_2 are provided in the opening 290. Note that as transistors are miniaturized and the widths of the openings 290 and 270 become smaller, it becomes more difficult to arrange all of the layers constituting the conductive layer 260 in the openings 290 and 270. For example, there is a case in which only the conductive layer 260_1 is provided in the opening 290, and the conductive layer 260_1 and the conductive layer 260_2 are provided in the opening 270. There is also a case in which only the conductive layer 260_1 is provided in the opening 270.

[0258] The portion of the conductive layer 265 that does not overlap with the opening 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layers 284 and 285. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240, and to reduce the parasitic capacitance that occurs between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have an overlapping portion without the insulating layer 285 being therebetween.

[0259] 8A shows an example in which the width of the opening 270 is smaller than the width D of the opening 290. The smaller the width of the opening 270, the greater the physical distance between the conductive layer 240 and the conductive layer 260 can be, and the smaller the parasitic capacitance that occurs between the conductive layer 240 and the conductive layer 260 can be, which is preferable. For example, the width of the opening 270 is preferably the same as or smaller than the width of the opening 290.

[0260] It is preferable that the height of the top surface of the conductive layer 260 and the height of the top surface of the insulating layer 285 are the same or approximately the same. The conductive layer 265 is provided over the insulating layer 285, the insulating layer 284, and the conductive layer 260, and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other.

[0261] That is, the transistor 200A has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0262] In this embodiment, an example in which the opening 270 is circular in plan view has been shown, but the present invention is not limited to this. Shapes that can be applied to the opening 270 are the same as the shapes that can be applied to the opening 290 described above.

[0263] The width of the opening 270 may vary in the depth direction. In particular, the width of the opening 270 used here is the maximum width of the opening 270 provided in the insulating layer 284 in a cross-sectional view.

[0264] An insulating layer having a function of capturing or fixing hydrogen is preferably used as the insulating layer 284. With such a structure, diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230 can be suppressed, and further, hydrogen contained in the oxide semiconductor layer 230 can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. As the insulating layer 284, an aluminum oxide film, a hafnium oxide film, a hafnium silicate film, or the like can be used.

[0265] Furthermore, a barrier insulating layer against hydrogen can be used as the insulating layer 284. This can suppress diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film each have characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 284.

[0266] When a silicon nitride film is used as the insulating layer 284, the silicon nitride film is preferably formed by a sputtering method. The sputtering method does not require the use of molecules containing hydrogen in the film formation gas, and therefore can reduce the hydrogen concentration in the insulating layer 284. Furthermore, by forming the insulating layer 284 by a sputtering method, a silicon nitride film with high density can be formed.

[0267] Alternatively, the insulating layer 284 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may be a stacked film of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0268] The insulating layer 285 functions as an interlayer film, and therefore is preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably includes a silicon oxide film.

[0269] Note that a structure similar to that of the transistor 200 can also be applied to the transistor 200A. For example, as shown in FIG. 8B , the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 over the insulating layer 280_1, and an insulating layer 280_3 over the insulating layer 280_2. An insulating layer 283 can be provided over the insulating layer 285 and the conductive layer 265. The conductive layer 220_1 can have a two-layer structure including a conductive layer 220_11 and a conductive layer 220_12 over the conductive layer 220_11.

[0270] [Transistor 200B] Fig. 9A1 is a plan view of a semiconductor device having transistor 200B. Fig. 9A2 is a plan view showing an example of arranging a plurality of transistors 200B. Fig. 9B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 9A1. Fig. 9C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 9A1. Fig. 9D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 9B. Fig. 9D can also be considered a cross-sectional view of the XY plane including insulating layer 280.

[0271] 9C and 9D are shown in Fig. 10A and Fig. 10B, respectively. Also, Fig. 11A and Fig. 11B are cross-sectional views taken along dashed line A3-A4 in Fig. 9A1. Fig. 11A and Fig. 11B are examples of the enlarged view of Fig. 9C, showing examples of the configuration of each layer in more detail.

[0272] The semiconductor device shown in FIGS. 9A1 to 9D includes an insulating layer 210 on a substrate (not shown), a transistor 200B on the insulating layer 210, and an insulating layer 280 on the insulating layer 210.

[0273] The transistor 200B includes a conductive layer 220, a conductive layer 240 on the insulating layer 280, an insulating layer 225, an oxide layer 227, an oxide semiconductor layer 230 on the oxide layer 227, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0274] The transistor 200B shown in FIGS. 9A1 to 9D differs from the transistor 200 shown in FIGS. 2A1 to 2D in that it includes an insulating layer 225.

[0275] As shown in FIG. 9D, the transistor 200B has a configuration in which the insulating layer 225 is disposed between the insulating layer 280 and the oxide layer 227 in a plan view.

[0276] The insulating layer 225 is provided along at least a part of the sidewall of the opening 290. The insulating layer 225 has at least a region located between the oxide semiconductor layer 230 and the insulating layer 280. The insulating layer 225 can also be called a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0277] As described above, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region of the oxide semiconductor. In particular, it is preferable that hydrogen be reduced as much as possible in the channel formation region of the oxide semiconductor.

[0278] Therefore, a barrier insulating layer against hydrogen is preferably used as the insulating layer 225 provided outside the oxide semiconductor layer 230. This can suppress diffusion of hydrogen into the oxide semiconductor layer 230 and improve the reliability of the transistor 200. For example, a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film is preferably used as the insulating layer 225, and a silicon nitride film is more preferably used.

[0279] Note that a silicon nitride film also has a barrier property against oxygen. Therefore, by using a silicon nitride film for the insulating layer 225, oxygen can be prevented from being extracted from the oxide semiconductor layer 230, which can prevent oxygen vacancies from being formed in the oxide semiconductor layer 230. Furthermore, by using a silicon nitride film for the insulating layer 225, excessive oxygen can be prevented from being supplied to the oxide semiconductor layer 230. Therefore, the channel formation region of the oxide semiconductor layer 230 can be prevented from becoming oxygen-excessive, thereby improving the reliability of the transistor 200B. Furthermore, the insulating layer 225 may be in contact with the side surface of the conductive layer 240 in the opening 290. In this case, by using a silicon nitride film for the insulating layer 225, it is possible to prevent the side surface of the conductive layer 240 in the opening 290 from being oxidized and an oxide film from being formed on the side surface.

[0280] The silicon nitride film of the insulating layer 225 is preferably formed using the PEALD method, which can improve the coverage of the insulating layer 225 on the sidewall of the opening 290 and form an insulating layer 225 with a uniform thickness.

[0281] The insulating layer 225 may be made of the above-mentioned material that can have ferroelectricity.

[0282] As shown in FIG. 9B and other figures, the conductive layer 220_2 has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located lower (closer to the insulating layer 210) than the bottom surface of the second recess. When forming the opening 290, the second recess is formed in the conductive layer 220_2, and then, when processing the insulating layer 225, the first recess is formed in the conductive layer 220_2. Therefore, in FIG. 9B and other figures, the side surface of the second recess is aligned with the side surface of the insulating layer 280 at the opening 290, and the side surface of the first recess is aligned with the surface of the insulating layer 225 facing the oxide layer 227. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0283] 9B and other drawings, the insulating layer 225 is in contact with the bottom surface and side surfaces of the recess (specifically, the second recess) of the conductive layer 220, and is in contact with the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 240_1, and the side surfaces of the conductive layer 240_2 within the opening 290. The oxide layer 227 is in contact with the bottom surface and side surfaces of the recess (specifically, the first recess) of the conductive layer 220, the insulating layer 225, and the top surface of the conductive layer 240_2. The oxide semiconductor layer 230 is located inside the oxide layer 227 within the opening 290, the insulating layer 250 is located inside the oxide semiconductor layer 230 within the opening 290, and the conductive layer 260 is located inside the insulating layer 250 within the opening 290.

[0284] 10A , the shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220_2 that is in contact with the insulating layer 280 is preferably longer than the shortest distance Ta from the top surface of the insulating layer 210 to the bottom surface of the insulating layer 250. This increases the area where the side surface of the conductive layer 220_2 faces the oxide semiconductor layer 230 with the oxide layer 227 sandwiched therebetween, thereby reducing the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230. Therefore, a decrease in the on-state current of the transistor 200B due to the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230 can be suppressed. Note that the shortest distance Ta can be determined based on the bottom surface of the insulating layer 250 in the opening 290.

[0285] 10A , the shortest distance Tc is preferably equal to or greater than the shortest distance Tb from the top surface of the insulating layer 210 to the bottom surface of the conductive layer 260, and more preferably longer than the shortest distance Tb. This makes it easier to apply a gate electric field to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200B. Furthermore, a gate electric field is also easier to apply to a region of the oxide semiconductor layer 230 that faces the conductive layer 220_2 across the oxide layer 227, thereby increasing the on-state current of the transistor 200B. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200B can be improved. Note that the shortest distance Tb can be determined based on the bottom surface of the conductive layer 260 in the opening 290.

[0286] Here, as shown in FIG. 10A, the width (film thickness) of the insulating layer 225 is set to width T ＳＷ Width T ＳＷ It is preferable that the width T ＳＷ By reducing the width T ＳＷ By increasing the width T ＳＷ is, for example, preferably 1 nm or more and 20 nm or less, more preferably 2 nm or more and 15 nm or less, and even more preferably 3 nm or more and 10 nm or less.

[0287] 10B also shows the channel width W of the transistor 200B. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W is "(D-2×T ＳＷ ) × π”.

[0288] The channel length of transistor 200B can be considered to be the distance between the source region and the drain region. In other words, it can be said that the channel length of transistor 200B is determined by the height of insulating layer 225. It can also be said that the channel length of transistor 200B is determined by the depth of the recess (specifically, the second recess) in conductive layer 220, the thickness of insulating layer 280 on conductive layer 220, and the thickness of conductive layer 240. When the channel length of transistor 200B is considered to be the distance between the source region and the drain region, it can be said that the channel length of transistor 200B is the length L shown in FIG. 10A .

[0289] 10A illustrates a configuration in which the conductive layer 220_2 has a first recess and a second recess, but the present invention is not limited to this. For example, as illustrated in FIG. 11A , the transistor 200B may have a configuration in which only one recess is provided in the conductive layer 220_2.

[0290] A recess can be formed in the conductive layer 220_2 in one or both of the steps of forming the opening 290 and forming the insulating layer 225. The transistor 200B illustrated in Figure 10A shows an example in which a recess is formed in the conductive layer 220_2 in both steps, whereas the transistor 200B illustrated in Figure 11A shows an example in which a recess is not formed in the conductive layer 220_2 in the step of forming the opening 290 but is formed in the step of forming the insulating layer 225.

[0291] 11A , the insulating layer 225 is in contact with the side surface of the insulating layer 280, the side surface of the conductive layer 240_1, the side surface of the conductive layer 240_2, and the top surface of the conductive layer 220_2 in the opening 290. The oxide layer 227 is in contact with the bottom and side surfaces of the recess of the conductive layer 220_2.

[0292] When a recess is formed in the conductive layer 220_2 in at least one of the steps of forming the opening 290 and forming the insulating layer 225, the height of the bottom surface of the conductive layer 260_1 in the opening 290 can be reduced, which makes it easier for a gate electric field to be applied to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200B.

[0293] When a recess is formed in the conductive layer 220_2 in the process of forming the insulating layer 225, the oxide layer 227 can be in contact with the bottom and side surfaces of the recess of the conductive layer 220_2, and the overlap area between the oxide semiconductor layer 230 and the conductive layer 220_2 with the oxide layer 227 sandwiched therebetween is increased, which is preferable because the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 can be reduced.

[0294] For example, as shown in FIG. 11B, a transistor 200B may have a structure in which the insulating layer 225 does not cover the side surfaces of the conductive layer 240_2.

[0295] 11B is in contact with the bottom and side surfaces of the recess of the conductive layer 220, and is in contact with the side surface of the insulating layer 280 within the opening 290. The insulating layer 225 is in contact with a portion of the side surface of the conductive layer 240_1, but is not in contact with the side surface of the conductive layer 240_2. The insulating layer 225 may be in contact with one or more of the side surface of the insulating layer 280, the side surface of the conductive layer 240_1, and the side surface of the conductive layer 240_2 within the opening 290, or may cover part or all of each side surface.

[0296] When at least a part of the side surface of the conductive layer 240_2 is not covered with the insulating layer 225, the part is in contact with the oxide layer 227. This can increase the overlapping area between the oxide semiconductor layer 230 and the conductive layer 240 with the oxide layer 227 sandwiched therebetween, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced. Similarly, when the insulating layer 225 does not cover the side surface of the conductive layer 240_2 and also does not cover at least a part of the side surface of the conductive layer 240_1, the part is in contact with the oxide layer 227. This can increase the overlapping area between the oxide semiconductor layer 230 and the conductive layer 240 with the oxide layer 227 sandwiched therebetween, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0297] 10A shows an example in which the insulating layer 225 has a single-layer structure. Note that the insulating layer 225 can have a stacked structure of two or more layers. For example, as shown in FIG. 12, the insulating layer 225 can have a two-layer structure of an insulating layer 225_1 and an insulating layer 225_2.

[0298] 12 shows an example in which the insulating layer 225 has a two-layer structure including an insulating layer 225_1 in contact with the insulating layer 280 and an insulating layer 225_2 located between the insulating layer 225_1 and the oxide layer 227. The insulating layer 225 shown in FIG. 12 can be said to have a two-layer structure including the insulating layer 225_1 and the insulating layer 225_2 over the insulating layer 225_1.

[0299] It is preferable that the insulating layer 225_1 provided in contact with the side surface of the insulating layer 280 in the opening 290 be a barrier insulating layer against hydrogen, and the insulating layer 225_2 provided in contact with the oxide layer 227 be an insulating layer having a function of capturing or fixing hydrogen. With such a structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced through the oxide layer 227. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved. For example, it is preferable that a silicon nitride film be used for the insulating layer 225_1, and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film be used for the insulating layer 225_2. In this case, the insulating layer 225_1 contains silicon and nitrogen, and the insulating layer 225_2 contains one or both of hafnium and aluminum, and oxygen.

[0300] Furthermore, the insulating layer 225_1 can be a barrier insulating layer against hydrogen, and the insulating layer 225_2 can be an insulating layer having a region containing excess oxygen. With such a structure, one or both of oxygen vacancies and hydrogen in the oxide semiconductor layer 230 can be reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved. For example, it is preferable to use a silicon nitride film for the insulating layer 225_1 and a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film for the insulating layer 225_2. In this case, the insulating layer 225_1 contains silicon and nitrogen, and the insulating layer 225_2 contains one or both of silicon and aluminum, and oxygen. In particular, when a silicon oxide film is used for the insulating layer 225_2, the insulating layer 225_2 contains silicon and oxygen.

[0301] Typically, a silicon nitride film and a silicon oxide film can be used as the insulating layer 225_1 and the insulating layer 225_2, respectively. The thicknesses of the insulating layer 225_1 and the insulating layer 225_2 are set to 2 nm and 2 nm, respectively.

[0302] As described above, by wrapping the oxide semiconductor layer 230 in a ring shape with a barrier insulating layer against hydrogen and providing an insulating layer having a function of capturing or fixing hydrogen or an insulating layer including a region containing excess oxygen near the oxide semiconductor layer 230, it is possible to reduce one or both of oxygen vacancies and impurities in the oxide semiconductor layer 230. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0303] The insulating layer 225 can have a three-layer structure including a first insulating layer, a second insulating layer, and a third insulating layer. For example, it is preferable that one of the first to third insulating layers is a barrier insulating layer against hydrogen, another is an insulating layer having a function of capturing or fixing hydrogen, and the others are insulating layers having a region containing excess oxygen. With such a structure, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be enhanced.

[0304] Another example of the structure of the insulating layer 225 shown in FIG. 12 is shown in FIGS. 13A and 13B.

[0305] In the transistor 200B shown in Figure 13A, an example is shown in which the insulating layer 225_1 is provided in contact with a portion of the bottom surface and the side surface of the recess formed by the conductive layer 220_2, and the insulating layer 225_2 is located inside the insulating layer 225_1 in the opening 290 and is provided in contact with another portion of the bottom surface of the recess formed by the conductive layer 220_2.

[0306] 13B , the conductive layer 220_2 has a first recess, a second recess located outside the first recess, and a third recess located outside the second recess. The first recess is deeper than the second recess, and the second recess is deeper than the third recess. The third recess is provided in the conductive layer 220_2 when the opening 290 is formed, and then the second recess is provided in the conductive layer 220_2 when the insulating layer 225_1 is processed, and then the first recess is provided in the conductive layer 220_2 when the insulating layer 225_2 is processed. Therefore, in Figure 13B, the side of the third recess is aligned with the side of the insulating layer 280 at the opening 290, the side of the second recess is aligned with the surface of the insulating layer 225_1 facing the insulating layer 225_2, and the side of the first recess is aligned with the surface of the insulating layer 225_2 facing the oxide layer 227.

[0307] In the transistor 200B shown in Figure 13B, the insulating layer 225_1 is provided in contact with the bottom and side surfaces of the third recess of the conductive layer 220_2, and the insulating layer 225_2 is provided in contact with the bottom and side surfaces of the second recess of the conductive layer 220_2.

[0308] 13A or 13B can be formed by providing the insulating layer 225_1 on the sidewall of the opening 290 and then forming and processing an insulating film to be the insulating layer 225_2. Compared to the transistor 200B shown in FIG. 12, the region where the insulating layer 225_1 is in contact with the oxide layer 227 is reduced, and a configuration in which the insulating layer 225_2 is in contact with the oxide layer 227 can be realized.

[0309] Note that a structure similar to that of at least one of the transistors 200 and 200A can also be applied to the transistor 200B. For example, as shown in FIG. 14A , in the semiconductor device shown in FIG. 10A , the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 over the insulating layer 280_1, and an insulating layer 280_3 over the insulating layer 280_2. Furthermore, an insulating layer 283 can be provided over the insulating layer 250 and the conductive layer 260. Furthermore, the conductive layer 220_1 can have a two-layer structure including a conductive layer 220_11 and a conductive layer 220_12 over the conductive layer 220_11. Furthermore, FIG. 14B shows an example in which the above structure is applied to the semiconductor device shown in FIG. 12 .

[0310] [Transistor 200C] Fig. 15A1 is a plan view of a semiconductor device having transistor 200C. Fig. 15A2 is a plan view showing an example of arranging a plurality of transistors 200C. Fig. 15B is a cross-sectional view taken along dashed line A1-A2 in Fig. 15A1. Fig. 15C is a cross-sectional view taken along dashed line A3-A4 in Fig. 15A1. Fig. 15D is a cross-sectional view taken along dashed line A5-A6 in Fig. 15B. Fig. 15D can also be considered a cross-sectional view of the XY plane including insulating layer 280. Fig. 16A shows an enlarged view of Fig. 15C.

[0311] The semiconductor device shown in Figures 15A1 to 15D has an insulating layer 210 on a substrate (not shown), a transistor 200C on the insulating layer 210, an insulating layer 280 on the insulating layer 210, and an insulating layer 281 on the insulating layer 280.

[0312] The transistor 200C includes a conductive layer 220, a conductive layer 255 on the insulating layer 280, a conductive layer 240 on the insulating layer 281, an insulating layer 225, an oxide layer 227, an oxide semiconductor layer 230 on the oxide layer 227, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0313] 2A1 to 2D in that the semiconductor device illustrated in Figures 15A1 to 15D includes a conductive layer 255 and an insulating layer 281. The transistor 200C illustrated in Figures 15A1 to 15D also differs from the transistor 200B illustrated in Figures 9A1 to 9D in that the transistor 200C includes a conductive layer 255.

[0314] The conductive layer 255 is located over the insulating layer 280, and the insulating layer 281 is located over the conductive layer 255 and the insulating layer 280. In addition, the conductive layer 240_1 is located over the insulating layer 281.

[0315] As shown in FIG. 16A, an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280 , the conductive layer 255 , the insulating layer 281 , and the conductive layer 240 .

[0316] In transistor 200C, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, the conductive layer 240 functions as the other of the source electrode and the drain electrode, the conductive layer 255 functions as a second gate electrode, and the insulating layer 225 functions as a second gate insulating layer.

[0317] The oxide semiconductor layer 230 has a region that overlaps with the conductive layer 255 with the oxide layer 227 and the insulating layer 225 interposed therebetween and with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200C.

[0318] Since the transistor 200C includes a conductive layer that functions as a backgate electrode, the threshold voltage of the transistor 200C can be controlled by the potential applied to the conductive layer. Therefore, by controlling the threshold voltage, a normally-off transistor can be easily realized.

[0319] In the transistor 200C, one of the conductive layer 255 and the conductive layer 260 may be used as a gate electrode and the other as a back gate electrode. The transistor 200C may have a particularly preferable structure in which the conductive layer 260 is used as a gate electrode and the conductive layer 255 is used as a back gate electrode. When the conductive layer 260, which has a wider region facing the oxide semiconductor layer 230 than the conductive layer 255, is used as the gate electrode, a gate electric field is applied to the oxide semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor. When the conductive layer 260 functions as a gate electrode and the conductive layer 255 functions as a back gate electrode, the insulating layer 250 functions as a gate insulating layer and the insulating layer 225 functions as a back gate insulating layer.

[0320] The conductive layer 255 can be made of a conductive material that can be used for the conductive layer 260 .

[0321] The insulating layer 281 functions as an interlayer film. The insulating layer 281 can be formed using an insulating material that can be used for the insulating layer 280.

[0322] 16A shows an example in which the insulating layer 281 has a single-layer structure. Note that the insulating layer 281 can have a stacked structure of two or more layers. For example, as shown in FIG. 16B, the insulating layer 281 can have a three-layer structure including an insulating layer 281_1, an insulating layer 281_2 on the insulating layer 281_1, and an insulating layer 281_3 on the insulating layer 281_2. In this case, it is preferable to use the above-described material with a low relative dielectric constant for the insulating layer 281_2, and to use barrier insulating layers against oxygen for the insulating layers 281_1 and 281_3. This can suppress oxidation of the conductive layer 255 and the conductive layer 240 and prevent high resistance.

[0323] Note that a structure similar to that of at least one of the transistors 200, 200A, and 200B can also be applied to the transistor 200C. For example, as shown in FIG. 16B , in the semiconductor device shown in FIG. 16A , the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 over the insulating layer 280_1, and an insulating layer 280_3 over the insulating layer 280_2. An insulating layer 283 can be provided over the insulating layer 250 and the conductive layer 260. The conductive layer 220_1 can have a two-layer structure including a conductive layer 220_11 and a conductive layer 220_12 over the conductive layer 220_11.

[0324] 17A to 18C , a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of elements, descriptions of parts that are similar to those described above may be omitted.

[0325] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0326] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0327] CVD methods can be further classified into plasma-enhanced CVD (PECVD), which utilizes plasma, thermal CVD (TCVD), which utilizes heat, and photo-CVD (photo-CVD), which utilizes light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0328] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0329] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0330] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of the following conditions: a high substrate temperature during film formation and / or an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these conditions.

[0331] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0332] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0333] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0334] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0335] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0336] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0337] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0338] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0339] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0340] An example of a manufacturing method for the semiconductor device including the above-described transistor 200B (see FIGS. 9A to 9D) will be described with reference to FIGS. 17A to 18C. Note that the insulating layer 225 has a two-layer structure of an insulating layer 225_1 and an insulating layer 225_2, as shown in FIG.

[0341] First, as shown in FIG. 17A, an insulating layer 210 is formed on a substrate (not shown), a conductive layer 220_1 is formed on the insulating layer 210, a conductive layer 220_2 is formed on the conductive layer 220_1, and an insulating layer 280 is formed on the conductive layer 220_2.

[0342] The insulating layer 280 can be formed using two types of film formation methods. For example, a silicon nitride film can be formed as the insulating layer 280 by the ALD method, and then a silicon nitride film can be formed by the sputtering method. The ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for forming thin films and for covering the surfaces of openings or layers with high aspect ratios. The sputtering method has a higher film formation rate than the ALD method, so it can improve productivity.

[0343] Note that after the insulating layer 280 is formed, planarization treatment is preferably performed to planarize the top surface of the insulating layer 280. As the planarization treatment, planarization treatment (also referred to as CMP treatment) using a chemical mechanical polishing (CMP) method is preferable. Alternatively, planarization treatment using etching (also referred to as etch-back treatment) may be performed. By performing the planarization treatment on the insulating layer 280, the surface on which the conductive layer 240a is to be formed can be flattened, and discontinuity of the conductive layer 240a can be suppressed. Note that the planarization treatment is not necessarily performed, and in that case, manufacturing costs can be reduced.

[0344] Subsequently, as shown in FIG. 17A, a conductive layer 240_1 is formed over the insulating layer 280, and a conductive layer 240_2 is formed over the conductive layer 240_1.

[0345] 17B , openings 290 are formed in the conductive layer 240_2, the conductive layer 240_1, and the insulating layer 280 at positions overlapping with the conductive layer 220_1. At this time, a recess is preferably provided in the conductive layer 220_2 at a position overlapping with the opening 290. By forming the opening 290, the bottom and side surfaces of the recess of the conductive layer 220_2 are preferably exposed.

[0346] To facilitate microfabrication and reduce the size of the transistor, it is preferable to use anisotropic etching to process part of the conductive layer 220_2, part of the conductive layer 240_1, part of the conductive layer 240_2, and part of the insulating layer 280 when forming the opening 290. Dry etching is particularly preferable because it is suitable for microfabrication. The opening 290 may be formed under different processing conditions depending on the layer. Note that the inclination of the side surface of the conductive layer 220_2, the side surface of the conductive layer 240_1, the side surface of the conductive layer 240_2, and the side surface of the insulating layer 280 may differ within the opening 290 depending on the materials and processing conditions of the conductive layer 220_2, the conductive layer 240_1, the conductive layer 240_2, and the insulating layer 280.

[0347] Furthermore, by a process of forming the opening 290 or the like, a region containing a halogen element may be provided on at least one of the bottom and side surfaces of the recess of the conductive layer 220_2, the side surface of the insulating layer 280, the side surface of the conductive layer 240_1, and the top and side surface of the conductive layer 240_2. Examples of such a region include a region containing fluorine, a region containing chlorine, or a region containing fluorine and chlorine. For example, a halogen element derived from the etching gas used in the dry etching may remain in the region.

[0348] Subsequently, heat treatment is preferably performed at a temperature of, for example, 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower.

[0349] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above heat treatment, impurities such as hydrogen or water contained in the insulating layer 280 or the like can be reduced before the formation of the oxide semiconductor layer 230.

[0350] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulating layer 280 and the like as much as possible.

[0351] 17C , an insulating layer 225_1 and an insulating layer 225_2 are formed in this order to cover the opening 290. The insulating layer 225_1 is provided in contact with the bottom and side surfaces of the recess of the conductive layer 220_2, the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 240_1, and the top and side surfaces of the conductive layer 240_2. The insulating layer 225_2 is provided on the insulating layer 225_1.

[0352] The insulating layers 225_1 and 225_2 are preferably formed by a CVD method or an ALD method, and more preferably by an ALD method, because they are layers provided in the opening 290. This allows the insulating layers 225_1 and 225_2 to be formed with good coverage.

[0353] In this embodiment, a silicon nitride film is deposited as the insulating layer 225_1 by a PEALD method, and a silicon oxide film is deposited as the insulating layer 225_2 by a PEALD method.

[0354] Note that the insulating layers 225_1 and 225_2 are preferably formed in succession without exposure to the air. By forming the insulating layers 225_1 and 225_2 in succession without exposure to the air, productivity can be improved. Furthermore, impurities (typically, moisture and the like) introduced into the interface between the insulating layers 225_1 and 225_2 and the vicinity thereof can be reduced.

[0355] 17D , the insulating layer 225_1 and the insulating layer 225_2 are processed to expose the top surface of the conductive layer 240_2 and to expose the conductive layer 220_2 in the opening 290. In the opening 290, it is preferable that the bottom surface of the recess of the conductive layer 220_2 is exposed.

[0356] By processing the insulating layer 225_1 and the insulating layer 225_2 by anisotropic etching, a region of the insulating layer 225_1 and the insulating layer 225_2 located on the top surface of the conductive layer 240_2 and a region of the insulating layer 225_1 and the insulating layer 225_2 located on the bottom surface of the opening 290 can be removed, and the insulating layer 225_1 and the insulating layer 225_2 can be left only on the side surface of the opening 290. The insulating layer 225_1 and the insulating layer 225_2 are preferably processed by highly anisotropic etching using a dry etching method.

[0357] As shown in FIG. 17D, when the insulating layer 225_1 and the insulating layer 225_2 are processed, a portion of the conductive layer 220_2 may be removed to provide a recess (the first recess described above) in the conductive layer 220_2.

[0358] Treatment for supplying oxygen is preferably performed after the insulating layer 225_2 is formed and before the insulating layer 225_2 is processed (see FIG. 17C ). Oxygen is thereby supplied to the insulating layer 225_2, and oxygen can be supplied from the insulating layer 225_2 to the oxide semiconductor layer 230 by heat or the like applied after the formation of the oxide semiconductor layer 230. Furthermore, by providing the insulating layer 225_1 having a barrier property against oxygen, diffusion of oxygen into the conductive layer 220 and the conductive layer 240 can be suppressed, and a decrease in the conductivity of the conductive layer 220 and the conductive layer 240 can be suppressed. Therefore, the range of materials that can be selected for the conductive layer 220 and the conductive layer 240 can be broadened.

[0359] Alternatively, treatment to supply oxygen may be performed after the insulating layer 225_2 is processed (see FIG. 17D ). As a result, oxygen is supplied to the insulating layer 225_2, and oxygen can be supplied from the insulating layer 225_2 to the oxide semiconductor layer 230 by heat or the like applied after the formation of the oxide semiconductor layer 230. Furthermore, by using an oxide conductor for the conductive layer 220_2 and the conductive layer 240_2, a decrease in the conductivity of the conductive layer 220_2 and the conductive layer 240_2 can be suppressed even in the case where treatment to supply oxygen is performed after the insulating layer 225_2 is processed.

[0360] Examples of treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere or plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer 225_2 by depositing an oxide film (preferably a metal oxide film) by a sputtering method in an oxygen-containing atmosphere. The deposited oxide film may be removed immediately after deposition or may be left as it is. In the case where the deposited oxide film is left as it is, the oxide film can be used as the oxide layer 227. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes a gas containing a compound containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0361] 18A , an oxide layer 227 is formed to cover the opening 290. The oxide layer 227 is provided in contact with the bottom and side surfaces of the recess of the conductive layer 220_2, the side surfaces of the insulating layer 225_2, the side surfaces of the conductive layer 240_1, and the top and side surfaces of the conductive layer 240_2.

[0362] Since the oxide layer 227 is a layer provided in the opening 290, it is preferably formed by the CVD method or the ALD method, and more preferably by the ALD method, so that the oxide layer 227 can be provided with good coverage.

[0363] 18A , an oxide semiconductor layer 230_1 and an oxide semiconductor layer 230_2 are formed in this order on the oxide layer 227. The oxide semiconductor layer 230_1 is preferably formed as a film with as uniform a thickness as possible along the top surface of the oxide layer 227. By forming the oxide semiconductor layer 230_1 using the ALD method, a thin film can be formed with good controllability. Therefore, the oxide semiconductor layer 230_1 is preferably formed using the ALD method.

[0364] Furthermore, when the oxide semiconductor layer 230 has high crystallinity, diffusion of impurities in the oxide semiconductor layer 230 is suppressed, which makes it difficult for the electrical characteristics of the transistor to fluctuate and improves reliability. When the oxide semiconductor layer 230_2 is formed by a sputtering method, it is easier to form a layer with high crystallinity than when an ALD method is used, which is preferable.

[0365] When the oxide semiconductor layer 230_2 is deposited by a sputtering method, oxygen or a mixed gas of oxygen and a noble gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be deposited can be increased. When the oxide film is deposited by a sputtering method, an In-M-Zn oxide target or the like can be used.

[0366] When the oxide semiconductor layer 230_2 is formed by a sputtering method, an oxygen-excess oxide semiconductor is formed when the percentage of oxygen contained in a sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor for a channel formation region has relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient oxide semiconductor is formed when the percentage of oxygen contained in a sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region has relatively high field-effect mobility. Furthermore, the crystallinity of the oxide semiconductor layer can be improved by performing film formation while heating the substrate.

[0367] Furthermore, when the oxide semiconductor layer 230_2 is formed by a sputtering method, an element contained in the conductive layer 220 may be mixed into a region of the oxide semiconductor layer 230 near the conductive layer 220 due to damage to the surface where the oxide semiconductor layer 230 is formed. If the element is tin, carriers are generated when tin is mixed into a region of the oxide semiconductor layer 230 near the conductive layer 220, and contact between the conductive layer 220 and the oxide semiconductor layer 230 is established, thereby realizing a transistor with excellent electrical characteristics. Similarly, an element contained in the conductive layer 240 may be mixed into a region of the oxide semiconductor layer 230 near the conductive layer 240. This allows contact between the conductive layer 240 and the oxide semiconductor layer 230 to be established, thereby realizing a transistor with excellent electrical characteristics.

[0368] For a method for manufacturing the oxide semiconductor layer 230, the description in Embodiment 2 can be referred to.

[0369] In this embodiment, a gallium oxide film is formed as the oxide layer 227 by a thermal ALD method, an indium oxide film is formed as the oxide semiconductor layer 230_1 by a thermal ALD method, and an In—Ga—Zn oxide film is formed as the oxide semiconductor layer 230_2 by a sputtering method. At this time, the oxide layer 227 can be formed by the ALD method using a precursor containing gallium and an oxidizer, the oxide semiconductor layer 230_1 can be formed by the ALD method using a precursor containing indium and an oxidizer containing ozone, and the oxide semiconductor layer 230_2 can be formed by the sputtering method using a sputtering target containing indium and gallium.

[0370] Since an indium oxide film formed by an ALD method has a low etching rate, a highly reliable transistor can be realized by using an indium oxide film for the oxide semiconductor layer 230_1.

[0371] Note that the oxide layer 227 and the oxide semiconductor layer 230_1 are preferably formed in succession without exposure to the air. By forming the oxide layer 227 and the oxide semiconductor layer 230_1 in succession without exposure to the air, productivity can be improved. Furthermore, impurities (typically, moisture and the like) introduced into the interface between the oxide layer 227 and the oxide semiconductor layer 230_1 and the vicinity thereof can be reduced.

[0372] After the oxide semiconductor layer 230_1 is formed, treatment for supplying oxygen to the oxide semiconductor layer 230_1 may be performed. By this treatment, oxygen can be supplied to the oxide semiconductor layer 230 by heat or the like applied after the treatment. Note that the above description can be referred to for details of the treatment for supplying oxygen.

[0373] Next, heat treatment is preferably performed. By performing the heat treatment, impurities such as hydrogen or water contained in the oxide semiconductor layer 230 (particularly the oxide semiconductor layer 230_1) can be reduced. The temperature of the heat treatment is preferably 100° C. to 650° C., more preferably 250° C. to 600° C., and still more preferably 300° C. to 500° C. or 350° C. to 550° C. For details of the heat treatment, refer to the above description.

[0374] The gas used in the heat treatment is preferably highly purified. When the heat treatment is performed using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor layer 230 as much as possible.

[0375] The heat treatment can reduce impurities such as carbon, hydrogen, or water in the oxide semiconductor layer 230. Reducing the impurities in the film in this manner can improve the crystallinity of the oxide semiconductor layer 230, resulting in a denser and more compact structure. This increases the crystalline regions in the oxide semiconductor layer 230, reducing in-plane variations in the crystalline regions in the oxide semiconductor layer 230. Therefore, in-plane variations in the electrical characteristics of the transistor can be reduced.

[0376] In addition, in the case where at least one of the insulating layer 225_2 and the oxide layer 227 contains oxygen, oxygen is preferably supplied from the insulating layer containing oxygen to the channel formation region of the oxide semiconductor layer 230 by the heat treatment. Ｏ H can be reduced.

[0377] In this manner, excess oxygen may be supplied to the oxide semiconductor layer 230 from an insulating layer in contact with the oxide semiconductor layer 230 or an oxide layer located near the oxide semiconductor layer 230. The excess oxygen has a function of trapping electrons, which makes it easier for negative charges to be formed. Therefore, the threshold voltage of the transistor is shifted in the positive direction, and a normally-off transistor can be realized.

[0378] Note that microwave plasma treatment may be performed after the oxide semiconductor layer 230_1 or the oxide semiconductor layer 230_2 is formed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer 230 can be reduced. Furthermore, a crystalline region of the oxide semiconductor layer 230 might grow. Note that details of the microwave plasma treatment will be described in Embodiment 2.

[0379] 18B , the oxide semiconductor layer 230_2, the oxide semiconductor layer 230_1, the oxide layer 227, the conductive layer 240_2, and the conductive layer 240_1 are processed into island shapes to expose part of the top surface of the insulating layer 280. The oxide semiconductor layer 230_2, the oxide semiconductor layer 230_1, the oxide layer 227, the conductive layer 240_2, and the conductive layer 240_1 can be processed using the same mask. This is preferable because it reduces the number of masks required to manufacture a semiconductor device.

[0380] Cleaning treatment is preferably performed to remove impurities or the like attached to the surface of the oxide semiconductor layer 230 during the above processing. Examples of the cleaning method include wet cleaning using a cleaning solution or the like (also referred to as wet etching treatment), plasma treatment using plasma, and cleaning by heat treatment. The above cleaning methods may be combined as appropriate.

[0381] Wet cleaning may be performed using an aqueous solution prepared by diluting one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid with pure water or carbonated water. Wet cleaning may also be performed using pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0382] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water or carbonated water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration or temperature of the aqueous solution may be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0383] The ultrasonic cleaning is preferably performed at a frequency of 200 kHz or higher, more preferably 900 kHz or higher, because damage to the oxide semiconductor layer 230 and the like can be reduced by using such a frequency.

[0384] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0385] 18C , an insulating layer 250 is formed to cover the opening 290. Furthermore, a conductive layer 260_1 is formed over the insulating layer 250, and a conductive layer 260_2 is formed over the conductive layer 260_1. The insulating layer 250 is provided in contact with the oxide semiconductor layer 230. The conductive layer 260_1 and the conductive layer 260_2 are preferably provided to fill the opening 290. Note that depending on the diameter of the opening 290, the thickness of the conductive layer 260_1, and the like, the conductive layer 260_2 may not be provided in the opening 290.

[0386] The insulating layer 250, the conductive layer 260_1, and the conductive layer 260_2 are each formed in the opening 290 with a large aspect ratio. Therefore, the insulating layer 250, the conductive layer 260_1, and the conductive layer 260_2 are each preferably formed by a film formation method with good coverage, and more preferably by a CVD method, an ALD method, or the like.

[0387] Microwave plasma treatment is preferably performed after the insulating layer 250 is formed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer 230 can be reduced. Furthermore, a crystalline region of the oxide semiconductor layer 230 might grow. Note that the details of the microwave plasma treatment will be described in Embodiment 2.

[0388] In addition, when the insulating layer 250 has a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer, microwave plasma treatment may be performed after the formation of the third insulating layer. Furthermore, microwave plasma treatment may be performed again after the formation of the first insulating layer. In this way, microwave plasma treatment in an oxygen-containing atmosphere may be performed multiple times (at least twice or more).

[0389] After the third insulating layer is formed, treatment for supplying oxygen to the third insulating layer may be performed, thereby making it possible to supply oxygen to the oxide semiconductor layer 230. Note that the above description can be referred to for details of the treatment for supplying oxygen.

[0390] In this embodiment, the insulating layer 250 is formed by depositing an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film in this order using an ALD method.

[0391] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0392] In this embodiment, a structure in which at least part of the insulating layer 225, the oxide layer 227, the oxide semiconductor layer 230_1, and at least part of the insulating layer 250 are formed by an ALD method is exemplified. Also, a structure in which at least part of the insulating layer 225, the oxide layer 227, the oxide semiconductor layer 230_1, and at least part of the insulating layer 250 are formed by using silicon oxide, gallium oxide, indium oxide, aluminum oxide, or hafnium oxide is exemplified. That is, at least part of the insulating layer 225, the oxide layer 227, the oxide semiconductor layer 230_1, and at least part of the insulating layer 250 are formed using oxide films formed by an ALD method. Furthermore, the oxide films contain oxygen and one element other than oxygen.

[0393] In this specification and the like, an oxide film containing oxygen and one element other than oxygen may be referred to as a simple oxide film, which refers to an oxide film in which the content of the element other than oxygen is 95% or more.

[0394] In the ALD process, a precursor is introduced into a chamber and adsorbed onto the substrate surface. The adsorption of the precursor onto the substrate surface activates a self-limiting mechanism for the surface chemical reaction, preventing further adsorption of the precursor onto the precursor layer on the substrate. The appropriate substrate temperature range within which the self-limiting mechanism for the surface chemical reaction operates is also referred to as the ALD window. The ALD window is determined by the precursor's temperature characteristics, vapor pressure, decomposition temperature, and other factors. In other words, the ALD window varies depending on the precursor. Therefore, when depositing an oxide film containing multiple elements other than oxygen, it is necessary to adjust the film formation conditions taking into account the ALD window of each precursor. On the other hand, when depositing a single oxide film, the film formation conditions can be adjusted by taking into account only the ALD window of one precursor, making it easier to adjust the film formation conditions and resulting in the formation of a high-quality oxide film.

[0395] For example, a gallium oxide film used for the oxide layer 227 is preferably a simple oxide film. For example, an indium oxide film used for the oxide semiconductor layer 230_1 is preferably a simple oxide film.

[0396] In the semiconductor device of one embodiment of the present invention, an oxide layer having higher resistivity than an oxide semiconductor layer is provided between a source electrode or a drain electrode and the oxide semiconductor layer, whereby the electrical characteristics of the transistor can be improved and the reliability of the transistor can be improved.

[0397] In a semiconductor device according to one embodiment of the present invention, an oxide semiconductor layer is surrounded by a barrier insulating layer against hydrogen, and one or both of an insulating layer having a function of capturing or adhering hydrogen and an insulating layer having a region containing excess oxygen are provided near the oxide semiconductor layer, whereby oxygen vacancies and / or impurities in the oxide semiconductor layer can be reduced, thereby improving the electrical characteristics and reliability of the transistor.

[0398] The semiconductor device according to one embodiment of the present invention has a structure in which parasitic capacitance between the other of the source electrode and the drain electrode and between the gate electrode and the other of the source electrode and the drain electrode and between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit using the semiconductor device.

[0399] This embodiment mode can be combined with other embodiment modes or examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0400] In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described. The oxide semiconductor layer of one embodiment of the present invention has a stacked-layer structure. Note that, as will be described later, it may be difficult to identify boundaries between stacked films.

[0401] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (poly-crystalline) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0402] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution TEM image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0403] For example, the CAAC structure is formed so that the c-axis is perpendicular or substantially perpendicular to the surface or surface of the oxide semiconductor layer on which the oxide semiconductor layer is to be formed. In the CAAC structure, metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor layer is to be formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the oxide semiconductor layer is to be formed.

[0404] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0405] When the oxide semiconductor layer has a CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms is observed in a cross section of the oxide semiconductor layer observed using a TEM image. Specifically, the bright spots are observed to be arranged in layers in a direction parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed.

[0406] When electron diffraction is performed on an oxide semiconductor layer having a CAAC structure, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern.

[0407] Furthermore, an FFT pattern obtained by performing a fast Fourier transform (FFT) process on a TEM image reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0408] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. Regions in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0409] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to a surface on which the oxide semiconductor layer is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the oxide semiconductor layer has crystallinity.

[0410] Note that the crystallinity of the metal oxide included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0411] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide may contain indium and zinc as the main components and may further contain element M. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more elements selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0412] Examples of metal oxides that can be used according to one embodiment of the present invention include In—Zn oxide, ITO, indium titanium oxide (In—Ti oxide), In—Ga oxide, indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), In—Ga—Zn oxide, ITSO, indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, Ga—Zn oxide, Al—Zn oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like can be used. Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, or the like can be used as the metal oxide according to one embodiment of the present invention.

[0413] By increasing the content of indium in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0414] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0415] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0416] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0417] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0418] In the present embodiment, an In-M-Zn oxide may be used as an example of the metal oxide.

[0419] [Method for Forming Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide by two film formation methods, for example. That is, the oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide by a first film formation method and a second film formation method.

[0420] For example, when the oxide semiconductor layer has a two-layer structure of a first layer and a second layer over the first layer, the oxide semiconductor layer can be manufactured by forming the first layer on a surface to be formed by the second film formation method and then forming the second layer above the first layer by the first film formation method.

[0421] For example, when the oxide semiconductor layer has a three-layer structure including a first layer, a second layer over the first layer, and a third layer over the second layer, the oxide semiconductor layer can be manufactured by forming the first layer on a surface to be formed by the second film formation method, then forming the second layer by the first film formation method, and then forming the third layer by the second film formation method.

[0422] The second film formation method is preferably a film formation method that causes less damage to the surface on which the oxide semiconductor layer is formed than the first film formation method. This can suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on which the oxide semiconductor layer is formed. Furthermore, since impurities such as silicon can be prevented from being mixed into the second layer formed on the first layer, the crystallinity of the oxide semiconductor layer can be further improved in some cases.

[0423] Examples of the second film formation method include ALD, CVD, and MBE. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and MOCVD. The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and can be considered one of the film formation methods that cause less damage to the surface on which the film is formed. A wet method can also be used as the second film formation method. The wet method is one of the film formation methods that cause less damage to the surface on which the film is formed. Examples of the wet method include spray coating.

[0424] The first film formation method is preferably a method capable of forming a crystalline metal oxide film. In this case, it is particularly preferable that the metal oxide film formed has a CAAC structure. Examples of the first film formation method include a sputtering method and a PLD method. Since a metal oxide film formed by a sputtering method is likely to have crystallinity, the sputtering method is suitable as the first film formation method.

[0425] When a metal oxide is formed on a surface to be formed using the first film formation method, damage to the surface to be formed may cause alloying between components contained in the metal oxide and components contained in the layer on the surface to be formed. This alloying may result in the formation of a mixed layer at the interface between the metal oxide and the layer on the surface to be formed. This mixed layer may also be referred to as an alloyed region. The formation of the mixed layer may also be referred to as alloying.

[0426] For example, when a sputtering method is used as the first film-forming method, a mixed layer may be formed by particles (also referred to as sputtering particles) emitted from a target or the like, or by energy imparted to a substrate by the sputtering particles or the like. Specifically, when a metal oxide film is formed by the first film-forming method using a silicon-containing insulating layer, such as a silicon oxide film, as a formation surface, silicon may be mixed into the metal oxide. There is a concern that the inclusion of impurities such as silicon into the metal oxide may inhibit the crystallization of the metal oxide. Furthermore, there is a concern that using an oxide semiconductor layer containing impurities in a transistor may adversely affect the initial characteristics or reliability of the transistor. Furthermore, even when heat treatment, which will be described later, is performed, it is difficult to enhance the crystallinity of the alloyed region.

[0427] Therefore, as described above, by forming a metal oxide by the second film formation method before forming a metal oxide by the first film formation method, it is possible to prevent impurities from being mixed into the oxide semiconductor layer. Furthermore, alloying can be suppressed. Therefore, the initial characteristics and reliability of the transistor can be improved. Furthermore, the crystallinity of the oxide semiconductor layer can be further increased.

[0428] The ALD method is suitable as the second film formation method because it can suppress damage to the formation surface compared to the sputtering method. Furthermore, the ALD method is a film formation method with better coverage than the sputtering method, and by using the ALD method as the film formation method for the first layer and the third layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, etc. with a high aspect ratio.

[0429] Here, a method for forming an In-M-Zn oxide as the first layer or the third layer by ALD will be described.

[0430] First, a source gas containing an indium precursor is introduced into a reaction chamber, and the precursor is adsorbed onto the surface to be formed. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby removing components other than indium while leaving indium adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are combined.

[0431] Next, a source gas containing a precursor having element M is introduced into the reaction chamber and is adsorbed onto the layer in which indium and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0432] Next, a source gas containing a zinc-containing precursor is introduced into the reaction chamber and adsorbed onto the layer in which the element M and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0433] By repeating the above-described method, an In-M-Zn oxide can be formed as an oxide semiconductor layer on a layer that is a formation surface by an ALD method.

[0434] When an oxide semiconductor layer is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ ) or the like is used as an oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor layer can be reduced.

[0435] Here, the temperature to which the substrate is heated when the precursor is introduced into the reaction chamber is defined as a first temperature, and the temperature to which the substrate is heated when the oxidizing agent is introduced into the reaction chamber is defined as a second temperature.

[0436] The first temperature is preferably a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium (TEI) as the indium-containing precursor, triethylgallium (TEG) as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the first temperature is, for example, 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0437] Note that the second temperature is preferably higher than the first temperature. For example, when the oxidizing agent contains ozone, the second temperature is preferably higher than 200° C. and lower than 450° C., more preferably higher than or equal to 250° C. and lower than or equal to 400° C., and further preferably higher than or equal to 300° C. and lower than or equal to 350° C. With such a configuration, the hydrogen concentration in the oxide semiconductor layer can be reduced. Furthermore, by setting the first temperature lower than the second temperature, particles generated by decomposition of the precursor can be suppressed.

[0438] It is preferable that the reaction chamber into which the precursor is introduced and the reaction chamber into which the oxidizing agent is introduced are the same. This configuration allows for film formation without the need to load and unload the substrate, thereby improving productivity. It is also possible to use different reaction chambers for the introduction of the precursor and the introduction of the oxidizing agent. By providing a first reaction chamber set to a first temperature and a second reaction chamber set to a second temperature, the first temperature and the second temperature can be maintained, respectively. This facilitates temperature control, improving work efficiency and safety.

[0439] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the reaction chamber, and then discharge excess precursor, reaction products, etc. from the reaction chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the reaction chamber, and then discharge excess reactant, reaction products, etc. from the reaction chamber.

[0440] Furthermore, in the present specification and elsewhere, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or oxidant, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, and ion state.

[0441] By using the above-described configuration, the thickness of the mixed layer can be reduced, or the thickness can be reduced to such an extent that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0442] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0443] For example, EDX line analysis is performed on the alloyed region and its periphery, with the direction perpendicular to the surface on which the first layer is formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal that is the main component of the first layer and is not the main component of the layer that will become the surface on which the layer is formed (In if the first layer contains In) becomes half-value is defined as the depth (position) of the interface between the region and the first layer. Furthermore, the depth at which the quantitative value of an element that is the main component of the layer that will become the surface on which the layer is formed and is not the main component of the first layer (e.g., Si) becomes half-value is defined as the depth (position) of the interface between the region and the layer that will become the surface on which the layer is formed. From the above, the thickness of the alloyed region can be calculated.

[0444] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0445] For example, when SIMS analysis is performed on an oxide semiconductor layer formed on a silicon oxide film that is a surface to be formed, the depth at which the silicon concentration is 50% of the maximum concentration of the silicon oxide film is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0×10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0446] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0447] Note that by reducing the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region that is more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, more preferably 1 nm or more and not more than 2 nm, approximately perpendicularly from the formation surface of the oxide semiconductor layer.

[0448] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of an oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0449] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure. The crystallinity of the first layer may be increased by forming a second layer with high crystallinity on the first layer with low crystallinity or by performing heat treatment after forming the second layer, with the second layer acting as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which the oxide semiconductor layer is formed.

[0450] Since the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0451] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0452] When the oxide semiconductor layer is used as a semiconductor layer of a transistor, the third layer, which is the uppermost layer of the oxide semiconductor layer, may be in contact with a gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is on.

[0453] The oxide semiconductor layer in this embodiment can be used as the oxide semiconductor layer 230 or the like included in each transistor described in Embodiment 1. The layer serving as a formation surface corresponds to one or more of the conductive layer 220, the insulating layer 280, the conductive layer 240, the insulating layer 225, or the like described in Embodiment 1.

[0454] The layer serving as the formation surface is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film, or a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. The layer serving as the formation surface does not need to have crystallinity. When the layer has crystallinity, it may have a crystal structure with low lattice matching with a metal oxide contained in the oxide semiconductor layer.

[0455] Furthermore, after the oxide semiconductor layer is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor layer. The heat treatment here is not limited to heat treatment. For example, heat applied during a manufacturing process may be used.

[0456] After the formation of the first layer, a microwave plasma treatment is preferably carried out.

[0457] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0458] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the oxide semiconductor layer 230 can be reduced. Examples of impurities include hydrogen and carbon. Although the above example illustrates a structure in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor layer.

[0459] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0460] When microwave plasma treatment is performed, the substrate may be heated. The substrate is preferably heated to a temperature above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C or below 450°C. For example, the substrate is preferably heated to a temperature above room temperature and below 500°C, more preferably above 100°C and below 450°C, more preferably above 200°C and below 450°C, more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0461] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In the microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( ３ P ｊ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋ ) can take three states. Note that oxygen ions act effectively in reducing the hydrogen concentration in the oxide film by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge, and that the oxide film may be etched. Therefore, for example, when the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0462] The shorter the processing time of the microwave plasma treatment, the more the oxidation of the conductive layer 220 or the conductive layer 240, etc. can be suppressed. Also, the productivity increases. Therefore, for example, the processing time of the microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0463] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor layer. By the action of plasma, microwaves, oxygen radicals, or the like, defects in which hydrogen has entered oxygen vacancies in the oxide semiconductor layer (hereinafter referred to as V Ｏ By splitting V (sometimes referred to as H) into oxygen vacancies and hydrogen, the hydrogen impurities can be removed from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0464] Furthermore, microwave plasma treatment can improve the crystallinity of the first layer. Here, the principle of how microwave plasma treatment improves the crystallinity of an oxide semiconductor layer will be described. First, active species such as oxygen radicals excited by microwaves arrive at the surface of the oxide semiconductor layer, and a substitution reaction occurs between the active species and oxygen in the oxide semiconductor layer. At this time, nuclei or seeds are formed. Furthermore, lateral growth of the nuclei or seeds is induced. Note that it is preferable that the active species excited by microwaves contain oxygen (typically, oxygen ions), which is easily adsorbed to the side surfaces of the nuclei or seeds, because this lateral growth is promoted. Microwave plasma treatment causes the formation of nuclei or seeds and the lateral growth of the nuclei or seeds, thereby improving the crystallinity of the oxide semiconductor layer.

[0465] On the other hand, a reaction occurs between part of the oxygen in the oxide semiconductor that exists before the microwave plasma treatment and hydrogen in the oxide semiconductor. In other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove O from the oxide semiconductor. ２ The hydrogen concentration in the oxide semiconductor can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor can be further reduced by increasing the temperature during the microwave plasma treatment.

[0466] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0467] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0468] The increased crystallinity of the first layer can further increase the crystallinity of the second layer formed over the first layer, thereby increasing the crystallinity of the entire oxide semiconductor layer.

[0469] Oxygen supplied to the oxide semiconductor layer can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0470] The second layer is preferably formed by sputtering.

[0471] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0472] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0473] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0474] When forming a metal oxide using a sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during metal oxide formation, a metal oxide with high crystallinity may be formed. When forming a metal oxide using a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0475] When a third layer is formed on a second layer having a CAAC structure by ALD, the third layer may grow epitaxially using the second layer as a nucleus. Therefore, during the formation of the third layer, the third layer may have a region having the CAAC structure. Furthermore, the region having the CAAC structure is preferably formed throughout the entire third layer.

[0476] After forming the third layer, a heat treatment step may be performed.

[0477] The heat treatment temperature can be, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, and more preferably 350°C or higher and 550°C or lower. Typically, it can be 400°C±25°C (375°C or higher and 425°C or lower). The treatment time can be 10 hours or shorter, for example, 1 minute or higher and 5 hours or lower, or 1 minute or higher and 2 hours or lower. When an RTA apparatus is used, the treatment time can be, for example, 1 second or higher and 5 minutes or lower. It is expected that this heat treatment will repair atomic-level crystalline gaps in the CAAC structure of the second layer with the third layer.

[0478] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0479] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the third layer. Furthermore, if the region is formed only below the third layer after film formation by the ALD method, the heat treatment step may cause the region to expand upward. That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire third layer.

[0480] Furthermore, it is preferable that at least a portion of the first layer is converted into CAAC by the heat treatment process. It is expected that the CAAC conversion is facilitated by the mixed layer formed in the first layer during the formation of the second layer acting as a nucleus or seed. It is preferable that the region in the first layer that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the surface to be formed.

[0481] Furthermore, because the CAAC is formed from the top to the bottom of the first layer, the CAAC can be formed up to the vicinity of the layer regardless of the material or crystallinity of the layer on which the CAAC is formed. For example, even if the layer has an amorphous structure, the first layer can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer on which the CAAC is formed has an amorphous structure.

[0482] After the third layer is formed, microwave plasma treatment may be performed.

[0483] Further, by performing one or both of the above heat treatment and microwave plasma treatment, the crystallinity of the entire oxide semiconductor layer can be increased.

[0484] In this manner, the impurities in the oxide semiconductor layer can be reduced. When crystal growth is performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.

[0485] Note that one or both of the heat treatment and the microwave plasma treatment may be performed directly on the oxide semiconductor layer or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0486] The first layer and the third layer each have high crystallinity using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer may be increased by heat treatment during the deposition of the second layer or after the deposition of the third layer. The crystallinity of the third layer may be increased by heat treatment during the deposition of the third layer or after the deposition of the third layer. The heat treatment has an assisting effect of increasing the crystallinity.

[0487] As described above, in the method for forming a metal oxide film according to one embodiment of the present invention, the crystallinity of the upper and lower metal oxides (the first layer and the third layer in this case) can be increased by using the second layer having a highly crystalline metal oxide (i.e., CAAC) as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower metal oxides can be grown in a solid phase using the second layer as a nucleus or seed to form an oxide semiconductor layer with high crystallinity. An oxide semiconductor layer formed by such a film formation method, i.e., a CAAC film in this case, can be referred to as an axial growth CAAC (AG CAAC).

[0488] In the oxide semiconductor layer, a region having a CAAC structure is preferably present widely throughout the layer. The region having the CAAC structure in the first layer is crystallinely connected to the region having the CAAC structure in the second layer. The region having the CAAC structure in the third layer is crystallinely connected to the region having the CAAC structure in the second layer. As a result, the boundary between the first layer and the second layer may not be observed. Furthermore, the boundary between the second layer and the third layer may not be observed. The oxide semiconductor layer may be expressed as a single layer whose interface is not clearly observed. The oxide semiconductor layer may be expressed as a single layer.

[0489] In each of the first to third layers, in a region having the CAAC structure, for example, bright spots aligned parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed are observed in cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in each of the first to third layers is preferably parallel or substantially parallel to the normal direction of the surface on which the oxide semiconductor layer is formed.

[0490] Furthermore, a portion of the first layer or the third layer may not be crystallized.

[0491] By increasing the crystallinity of the oxide semiconductor layer, it is expected that an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0492] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the oxide semiconductor layer, the boundaries between the stacked films of the first to third layers may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional scanning transmission electron microscope (STEM), or the like.

[0493] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to have a cubic crystal structure. Therefore, by using an oxide semiconductor with a high In content in one or both of the first layer and the third layer in contact with the second layer, a crystal that reflects the crystal orientation of the second layer can be formed.

[0494] Furthermore, it is preferable that the lattice mismatch between the crystals of the second layer and the crystals of the first layer or the third layer is small. This allows the first layer or the third layer to have crystals that reflect the orientation of the crystals of the second layer. In this case, for example, in cross-sectional observation of the oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the first layer or the third layer.

[0495] The crystal structure of the first layer or the third layer is not particularly limited as long as the lattice mismatch between the crystals of the second layer and the crystals of the first layer or the third layer is small. The crystal structure of the first layer or the third layer may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0496] Furthermore, the oxide semiconductor layer of one embodiment of the present invention can be formed without forming the first layer in some cases by providing the oxide layer 227 described in Embodiment 1 between the layer on which the oxide semiconductor layer is to be formed and the oxide semiconductor layer. In this case, the oxide semiconductor layer has a two-layer structure including the second layer and the third layer. For example, by forming the oxide layer 227 by an ALD method, the oxide layer 227 can suppress alloying between components contained in the oxide semiconductor layer and components contained in the layer on which the oxide semiconductor layer is to be formed in some cases. Therefore, the crystallinity of the entire oxide semiconductor layer can be increased in some cases.

[0497] As described above, even in a structure in which the first layer is not provided, the oxide semiconductor layer above can be grown by solid-phase growth using the second layer as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a deposition method can also be called an AG CAAC.

[0498] Note that when a metal oxide applicable to the first layer is used as the oxide layer 227 , the first layer can be referred to as the oxide layer 227 .

[0499] In the above structure, typically, the oxide layer 227 can be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition close thereto, or a gallium oxide, the second layer can be a metal oxide containing a trace amount of element M, and the third layer can be an In—Zn oxide.

[0500] The oxide semiconductor layer of one embodiment of the present invention can be formed by using the second film formation method and one or both of microwave plasma treatment and heat treatment. In other words, the oxide semiconductor layer of one embodiment of the present invention can be formed without forming a second layer. In this case, the oxide semiconductor layer has a two-layer structure including a first layer and a third layer. For example, by performing one or both of microwave plasma treatment and heat treatment after forming the first layer, the crystallinity of the first layer can be increased, and the crystallinity of the third layer can be increased using the first layer as a nucleus or seed. Furthermore, by performing one or both of microwave plasma treatment and heat treatment after forming the third layer, the crystallinity of the oxide semiconductor layer can be increased. Therefore, a CAAC structure can be formed in the oxide semiconductor layer.

[0501] Furthermore, for example, by providing the oxide layer 227 described in Embodiment 1 between a layer on which the first layer is to be formed and the oxide semiconductor layer, the crystallinity of the first layer can be improved by using the oxide layer 227 as a nucleus or a seed. Furthermore, by performing microwave plasma treatment and / or heat treatment after forming the first layer and / or the third layer, the crystallinity of the oxide semiconductor layer can be improved. Therefore, a CAAC structure can be formed in the oxide semiconductor layer.

[0502] As described above, even in a structure in which the second layer is not provided, the oxide semiconductor layer above can be grown by solid-phase growth using the first layer as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a deposition method can also be called an AG CAAC.

[0503] As described in Embodiment 1, the oxide semiconductor layer may have a two-layer structure including a first layer formed by the second deposition method and a second layer formed over the first layer by the first deposition method, and the oxide layer 227 may be provided between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed. In this case, the first layer corresponds to the oxide semiconductor layer 230_1 described in Embodiment 1, and the second layer corresponds to the oxide semiconductor layer 230_2 described in Embodiment 1.

[0504] [Composition of Oxide Semiconductor Layer] The second layer preferably has a different composition from the first layer. The second layer preferably has a different composition from the third layer. The first layer may have the same composition as the third layer. Alternatively, the first layer and the third layer may have different compositions.

[0505] The second layer preferably contains In, and more preferably has a high content of In. By using a metal oxide with a high content of In as the second layer, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0506] As described above, the second layer preferably has a composition suitable for forming a CAAC structure. The second layer preferably contains, for example, zinc. By containing zinc, the second layer becomes a metal oxide with high crystallinity.

[0507] The second layer may be, for example, an In-Zn oxide. Specifically, the second layer may have a composition of In:Zn=1:1 (atomic ratio) or a composition close thereto, an In:Zn=2:1 (atomic ratio) or a composition close thereto, or an In:Zn=4:1 (atomic ratio) or a composition close thereto. Alternatively, an indium oxide may be used. Note that a composition close thereto includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0508] The second layer preferably contains the element M. When the second layer contains the element M, for example, oxygen vacancies can be suppressed from being formed in the metal oxide. Therefore, the reliability of a transistor using the oxide semiconductor layer can be improved. Specifically, the second layer may be formed of a metal oxide having a composition of In:M:Zn=1:1:1 (atomic ratio) or a composition therearound, an In:M:Zn=1:1:1.2 (atomic ratio) or a composition therearound, an In:M:Zn=1:1:0.5 (atomic ratio) or a composition therearound, an In:M:Zn=1:1:2 (atomic ratio) or a composition therearound, an In:M:Zn=4:2:3 (atomic ratio) or a composition therearound, an In:M:Zn=1:3:2 (atomic ratio) or a composition therearound, or an In:M:Zn=1:3:4 (atomic ratio) or a composition therearound.

[0509] The second layer may also be configured to contain a trace amount of element M. For example, the second layer may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout, or In:Ga:Zn=1:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, the second layer may have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout, or In:Sn:Zn=1:0.1:1 (atomic ratio) or a composition thereabout.

[0510] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease by up to about 50% compared to the sputtering target.

[0511] The first and third layers may each use a metal oxide that can be used for the second layer.

[0512] For example, the first layer and the third layer can be made of a metal oxide having a higher In content than the second layer. By using a metal oxide having a higher In content, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0513] Furthermore, for example, metal oxides having a higher Ga content than the second layer can be used for the first layer and the third layer. For example, it is preferable to use a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition thereabout, a metal oxide having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or a composition thereabout, or a metal oxide having a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or a composition thereabout for the first layer and the third layer, respectively. By increasing the Ga content, for example, the band gaps of the first layer and the third layer can be made larger than that of the second layer in some cases. As a result, the second layer is sandwiched between the first layer and the third layer, which have larger band gaps, and the second layer functions mainly as a current path (channel). By sandwiching the second layer between the first layer and the third layer, it is possible to reduce trap levels at the interface of the second layer and its vicinity. This allows for a buried-channel transistor in which the channel is located away from the insulating layer interface, thereby increasing the field-effect mobility. Furthermore, the influence of interface states that may form on the back channel side is reduced, suppressing light degradation (e.g., negative-bias light degradation) of the transistor and improving its reliability.

[0514] Alternatively, one of the first layer and the third layer may be a metal oxide having a higher In content than the second layer, and the other may be a metal oxide having a higher Ga content than the second layer.

[0515] The first layer, the second layer, and the third layer may each have a plurality of layers having the above-described composition stacked together. For example, the third layer may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0516] When forming a metal oxide film containing multiple metal elements, such as In—Ga—Zn oxide, using the ALD method, the ratio of the number of cycles of precursors containing each metal element can be set to match the target composition. For example, when forming an In—Ga—Zn oxide film with an atomic ratio of In:Ga:Zn=1:3:2, one cycle of forming an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of forming a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of forming a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element and the atomic ratio of each metal element in the formed metal oxide film may not necessarily match.

[0517] In the oxide semiconductor layer of one embodiment of the present invention, even when the first layer and the third layer are formed using compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the second layer as a nucleus, so that the entire oxide semiconductor layer including the first layer and the third layer can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of each of the first layer and the third layer and the second layer.

[0518] In particular, even when the first layer and the third layer have a high In content, the oxide semiconductor layer can have suitable crystallinity for a semiconductor layer of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0519] The first and third layers may be made of a metal oxide having the same composition as that of the second layer. Using the same composition may make it easier for the first and third layers to become CAAC after heat treatment.

[0520] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness or both than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0521] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0522] The composition of the metal oxide used in the oxide semiconductor layer can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0523] [Oxide Semiconductor Layer of Transistor] The oxide semiconductor layer of this embodiment can be used as a semiconductor layer of a transistor.

[0524] The oxide semiconductor layer of this embodiment has a CAAC structure. In the oxide semiconductor layer having the CAAC structure, metal atoms are arranged in a layered manner in a direction parallel or substantially parallel to a surface on which the oxide semiconductor layer is formed in a crystal portion.

[0525] It is estimated that an oxide semiconductor layer having a CAAC structure exhibits current anisotropy. For example, in an IGZO crystal, current flows more easily in the a-axis direction than in the c-axis direction. That is, it is estimated that in an oxide semiconductor layer having a CAAC structure, current flows more easily in the horizontal direction than in the vertical direction.

[0526] In the semiconductor device described in the above embodiment, the oxide semiconductor layer 230 has metal atoms arranged in a layered manner in a direction parallel to or substantially parallel to the surface where the oxide semiconductor layer 230 is formed. It can also be expressed as the a-b plane of the CAAC structure being provided in a direction parallel to or substantially parallel to the surface where the oxide semiconductor layer 230 is formed. Here, the oxide semiconductor layer 230 is provided along the sidewall of the opening 290 with the oxide layer 227, which is part of the surface where the oxide semiconductor layer 230 is formed, sandwiched therebetween. Thus, in the oxide semiconductor layer 230, the metal atoms are arranged in a layered manner in a direction parallel to or substantially parallel to the sidewall of the opening 290. With this structure, the a-b plane of the CAAC structure can be provided along the direction of current flow in the channel of the transistor. This can increase the on-state current of the transistor.

[0527] When the oxide semiconductor layer of this embodiment is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. In a transistor used in a smaller semiconductor device, the thickness of the oxide semiconductor layer 230 is preferably 1 nm to 20 nm, further preferably 3 nm to 15 nm, further preferably 5 nm to 12 nm, and further preferably 5 nm to 10 nm. The average thickness of the oxide semiconductor layer in a channel formation region of the transistor is particularly preferably, for example, 2 nm to 15 nm.

[0528] The second layer preferably has a thickness of, for example, 200 nm or less. When the second layer is lamellar, the thickness is preferably, for example, 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and more preferably 2 nm or more and 100 nm or less.

[0529] Alternatively, if the second layer can function as a crystal nucleus, the second layer may not exist in a layered structure but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the second layer exist discretely.

[0530] The first layer and the third layer each preferably have a thickness of 0.5 nm to 50 nm, more preferably 0.5 nm to 30 nm, more preferably 0.5 nm to 20 nm, more preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and more preferably 2 nm to 20 nm. The first layer is further preferably 0.5 nm to 3 nm.

[0531] [Impurities in Oxide Semiconductor] Here, the influence of each impurity in an oxide semiconductor will be described.

[0532] As described in the above embodiment, in a transistor including an oxide semiconductor for a semiconductor layer, oxygen vacancies (V Ｏ The presence of impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen.

[0533] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0534] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5 × 10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0535] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Note that the lower limit of the hydrogen concentration in the channel formation region of the oxide semiconductor is not particularly limited, but is, for example, less than 1×10 １６ atoms / cm ３ It can be more than that.

[0536] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0537] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0538] This embodiment mode can be combined with other embodiment modes or examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0539] 19A to 24. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0540] 19A to 19C , the structure of a memory device including a transistor and a capacitor will be described. Fig. 19A is a plan view of a memory device including a transistor 200 and a capacitor 100. Fig. 19B is a cross-sectional view taken along dashed line A1-A2 in Fig. 19A . Fig. 19C is a cross-sectional view taken along dashed line A3-A4 in Fig. 19A .

[0541] 19A to 19C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, and an insulating layer 180 and an insulating layer 280 over the conductive layer 110. The insulating layer 140, the insulating layer 180, and the insulating layer 280 function as interlayer films. The conductive layer 110 functions as a wiring.

[0542] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0543] The capacitor 100 includes a conductive layer 115 over the conductive layer 110, an insulating layer 130 over the conductive layer 115, and a conductive layer 220_1 over the insulating layer 130. The conductive layer 220_1 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. That is, the capacitor 100 forms a metal-insulator-metal (MIM) capacitor. Note that the conductive layer 220_2 provided over the conductive layer 220_1 can also be considered as part of the upper electrode of the capacitor 100.

[0544] As shown in FIGS. 19B and 19C , an opening 190 reaching the conductive layer 110 is provided in the insulating layer 180. At least a portion of the conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region in contact with the top surface of the conductive layer 110 in the opening 190, a region in contact with the side surface of the insulating layer 180 in the opening 190, and a region in contact with at least a portion of the top surface of the insulating layer 180. The insulating layer 130 is disposed so that at least a portion of it is located in the opening 190. The conductive layer 220_1 is disposed so that at least a portion of it is located in the opening 190. Note that, as shown in FIGS. 19B and 19C , the conductive layer 220_1 is preferably provided so as to fill the opening 190. Note that the films provided inside the opening 190 are preferably formed using an ALD method. This improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220_1 are preferably formed by an ALD method.

[0545] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched between them on the side surfaces as well as the bottom surface within the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, this can promote miniaturization or high integration of memory devices.

[0546] 19B and 19C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a structure, miniaturization or high integration of the memory device can be achieved.

[0547] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the top surface of the conductive layer 110. In addition, a conductive layer 220_1 is provided on the insulating layer 130 so as to fill the opening 190. The capacitor 100 having such a configuration may be called a trench capacitor.

[0548] In addition, an insulating layer 280 is disposed over the capacitor 100. The insulating layer 280 has a portion located over the insulating layer 130 and a portion located over the conductive layer 220_2.

[0549] The transistor 200 includes a conductive layer 220 having a conductive layer 220_1 and a conductive layer 220_2, a conductive layer 240 over an insulating layer 280, an oxide layer 227, an oxide semiconductor layer 230 over the oxide layer 227, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250.

[0550] In the transistor 200, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and the drain electrode.

[0551] The detailed description of the transistor 200 will be omitted because the description in Embodiment 1 ( FIG. 3A ) can be referred to. The transistor included in the memory cell 150 is not limited to the transistor 200, and any of the transistors exemplified in Embodiment 1 can be applied.

[0552] As shown in FIGS. 19A to 19C , the transistor 200 is provided to overlap with the capacitor 100. Furthermore, an opening 290 where part of the structure of the transistor 200 is provided overlaps with an opening 190 where part of the structure of the capacitor 100 is provided. In particular, the conductive layer 220 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100. Therefore, the transistor 200 and the capacitor 100 share part of their structures. With this structure, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be densely arranged and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated. FIGS. 19B and 19C show an example in which the width of the opening 190 is smaller than the width of the opening 290. The relationship between the width of the opening 190 and the width of the opening 290 is not particularly limited. From the viewpoint of miniaturization, it is preferable that the width of the opening 190 be equal to or smaller than the width of the opening 290 .

[0553] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics, can be suppressed.

[0554] 20A to 20C illustrate a memory device in which the transistor 200A described in Embodiment 1 is used as a transistor included in the memory cell 150. FIG. 20A is a plan view of a memory device including the transistor 200A and a capacitor 100. FIG. 20B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 20A. FIG. 20C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 20A.

[0555] 20B and 20C , a structure may be used in which the side edges of the insulating layer 130 and the conductive layer 220 coincide with each other. By using such a structure, the insulating layer 130 and the conductive layer 220 can be formed using the same mask, and the manufacturing process of the memory device can be simplified.

[0556] 26A shows a circuit diagram of the memory device described in this embodiment. As shown in FIG. 26A, the configurations shown in FIGS. 19A to 19C function as memory cells. A memory cell 951 includes a transistor M1 and a capacitor CA. Here, the transistor M1 corresponds to the transistor 200, and the capacitor CA corresponds to the capacitor 100.

[0557] One of the source and drain of the transistor M1 is connected to one of a pair of electrodes of the capacitor CA. The other of the source and drain of the transistor M1 is connected to a wiring BIL. The gate of the transistor M1 is connected to a wiring WOL. The other of the pair of electrodes of the capacitor CA is connected to a wiring CAL.

[0558] Here, the wiring BIL corresponds to the conductive layer 240, the wiring WOL corresponds to the conductive layer 260, and the wiring CAL corresponds to the conductive layer 110. As shown in FIGS. 19A to 19C , it is preferable that the conductive layer 260 is provided extending in the X direction, and the conductive layer 240 is provided extending in the Y direction. With this configuration, the wiring BIL and the wiring WOL are provided intersecting each other. Also, in FIG. 19A , the wiring CAL (conductive layer 110) is provided parallel to the wiring WOL (conductive layer 260). However, the present invention is not limited to this. The wiring CAL may be provided parallel to the wiring BIL (conductive layer 240), for example.

[0559] The memory cells will be described in detail in a later embodiment.

[0560] [Capacitor 100] The capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 220_1. The conductive layer 110 is provided below the conductive layer 115. The conductive layer 115 has a region in contact with the conductive layer 110.

[0561] The conductive layer 110 is provided on the insulating layer 140. The conductive layer 110 functions as wiring CAL and can be provided, for example, in a strip shape. Note that a strip shape refers to a shape having an area extending in a certain direction (for example, the X direction, Y direction, or Z direction).

[0562] The conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in the section [Conductive Layer] of Embodiment 1. For example, a conductive material with high conductivity, such as tungsten, can be used as the conductive layer 110. By using such a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can function sufficiently as a wiring CAL.

[0563] The conductive layer 115 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion, and is used in a single layer or a stacked layer. For example, titanium nitride or ITSO may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can suppress oxidation of the conductive layer 110. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can suppress oxidation of the conductive layer 110.

[0564] The insulating layer 130 is provided on the conductive layer 115. The insulating layer 130 is provided so as to be in contact with the top surface and side surfaces of the conductive layer 115. In other words, the insulating layer 130 preferably has a structure that covers the side end portions of the conductive layer 110. This can prevent a short circuit between the conductive layer 115 and the conductive layer 220_1.

[0565] Alternatively, a structure may be used in which the side edges of the insulating layer 130 coincide with the side edges of the conductive layer 115. With such a structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, which can simplify the manufacturing process of the memory device.

[0566] It is preferable to use a material with a high relative dielectric constant (high-k) for the insulating layer 130. By using a high-k material for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitive element 100 can be sufficiently ensured.

[0567] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of a high-k material, and preferably by using a stack structure of a high-dielectric-constant (high-k) material and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0568] Furthermore, a material that can have ferroelectricity may be used as the insulating layer 130. For details of the material that can have ferroelectricity, the description in the first embodiment can also be referred to.

[0569] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when they are as thin as a few nanometers, and are therefore preferred as the insulating layer 130. The film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the film thickness is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0570] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor element 100 can be reduced.

[0571] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor element 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0572] The conductive layer 220_1 is provided in contact with a part of the upper surface of the insulating layer 130. The side end of the conductive layer 220_1 is preferably located inside the side end of the conductive layer ...

Claims

It has a first and a second oxide semiconductor layer, an oxide layer, first to third conductive layers, and first and second insulating layers. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first conductive layer has a first recess. The first insulating layer and the second conductive layer have a first opening at a position overlapping the first recess. The oxide layer has a portion covering the sidewall of the first opening. The first oxide semiconductor layer has a portion located on the second conductive layer, a portion located on the first conductive layer within the first opening, and a portion facing the first insulating layer with the oxide layer interposed therebetween within the first opening. The second oxide semiconductor layer is located on the first oxide semiconductor layer. The second insulating layer is located on the second oxide semiconductor layer. The third conductive layer is located on the second insulating layer. The third conductive layer faces the first oxide semiconductor layer with the second insulating layer interposed therebetween within the first opening. The oxide layer contains gallium oxide. The first oxide semiconductor layer contains indium oxide. The second oxide semiconductor layer contains one or both of gallium and indium. A semiconductor device in which the indium content in the first oxide semiconductor layer is higher than the indium content in the second oxide semiconductor layer. 　 In claim 1, The hydrogen concentration in the first oxide semiconductor layer obtained by secondary ion mass spectrometry is less than 1×10 ２０ atoms / cm ３ . A semiconductor device. 　 In claim 2, The second insulating layer has a laminate of two or more layers. A semiconductor device in which, among the layers of the second insulating layer, the layer in contact with the second oxide semiconductor layer contains aluminum oxide. 　 In claim 1, The lower end of the conduction band of the oxide layer is located closer to the vacuum level side than the lower end of the conduction band of the first oxide semiconductor layer. A semiconductor device in which the lower end of the conduction band of the second oxide semiconductor layer is located closer to the vacuum level side than the lower end of the conduction band of the first oxide semiconductor layer. 　 In claim 1, The oxide layer contains indium. A semiconductor device in which, in the oxide layer, the indium content is lower than the gallium content. 　 In claim 1, The gallium content excluding oxygen in the oxide layer is 95% or more. A semiconductor device in which the indium content excluding oxygen in the first oxide semiconductor layer is 95% or more. 　 It has a first and a second oxide semiconductor layer, an oxide layer, first to fourth conductive layers, and first to third insulating layers. The first insulating layer is located on the first conductive layer, The second conductive layer is located on the first insulating layer, The first conductive layer has a first recess, The first insulating layer and the second conductive layer have a first opening at a position overlapping the first recess, The oxide layer has a portion covering the sidewall of the first opening, The first oxide semiconductor layer has a portion located on the second conductive layer, a portion located on the first conductive layer within the first opening, and a portion facing the first insulating layer with the oxide layer interposed therebetween within the first opening, The second oxide semiconductor layer is located on the first oxide semiconductor layer, The second insulating layer is located on the second oxide semiconductor layer, The third insulating layer is located on the second insulating layer and has a second opening at a position overlapping the first opening, The third conductive layer has a portion facing the first oxide semiconductor layer through the second insulating layer within the first opening and a portion located within the second opening, The fourth conductive layer is disposed on the third insulating layer and has a region in contact with the third conductive layer, The oxide layer contains gallium oxide, The first oxide semiconductor layer contains indium oxide, The second oxide semiconductor layer contains one or both of gallium and indium, A semiconductor device in which the indium content in the first oxide semiconductor layer is higher than the indium content in the second oxide semiconductor layer. 　 In claim 7, The hydrogen concentration in the first oxide semiconductor layer obtained by secondary ion mass spectrometry is less than 1×10 ２０ atoms / cm ３ . A semiconductor device. 　 In claim 8, The second insulating layer has a laminate of two or more layers, Among the layers of the second insulating layer, the layer in contact with the second oxide semiconductor layer contains aluminum oxide. A semiconductor device. 　 In claim 7, The lower end of the conduction band of the oxide layer is located closer to the vacuum level side than the lower end of the conduction band of the first oxide semiconductor layer, The lower end of the conduction band of the second oxide semiconductor layer is located closer to the vacuum level side than the lower end of the conduction band of the first oxide semiconductor layer. A semiconductor device. 　 In claim 7, The oxide layer contains indium, In the oxide layer, the indium content is lower than the gallium content. A semiconductor device. 　 In claim 7, The gallium content excluding oxygen in the oxide layer is 95% or more, The indium content excluding oxygen in the first oxide semiconductor layer is 95% or more. A semiconductor device. 　 It has a first and a second oxide semiconductor layer, an oxide layer, first to third conductive layers, and first to third insulating layers. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first conductive layer has a first recess. The first insulating layer and the second conductive layer have a first opening at a position overlapping with the first recess. The oxide layer has a portion covering the side wall of the first opening. The first oxide semiconductor layer has a portion located on the second conductive layer, a portion located on the first conductive layer within the first opening, and a portion facing the first insulating layer with the oxide layer interposed therebetween within the first opening. The second oxide semiconductor layer is located on the first oxide semiconductor layer. The second insulating layer is located on the second oxide semiconductor layer. The third conductive layer is located on the second insulating layer. The third conductive layer faces the first oxide semiconductor layer with the second insulating layer interposed therebetween within the first opening. The oxide layer contains gallium oxide. The first oxide semiconductor layer contains indium oxide. The second oxide semiconductor layer contains one or both of gallium and indium. The indium content in the first oxide semiconductor layer is higher than the indium content in the second oxide semiconductor layer. The third insulating layer is located between the first insulating layer and the oxide layer. The third insulating layer has a fourth insulating layer in contact with the first insulating layer and a fifth insulating layer located between the fourth insulating layer and the oxide layer. The fourth insulating layer contains silicon and nitrogen. The fifth insulating layer contains silicon and oxygen, a semiconductor device. 　 In claim 13, The hydrogen concentration in the first oxide semiconductor layer obtained by secondary ion mass spectrometry is less than 1×10 ２０ atoms / cm ３ . A semiconductor device. 　 In claim 14, The second insulating layer has a laminate of two or more layers. Among the layers of the second insulating layer, the layer in contact with the second oxide semiconductor layer contains aluminum oxide, a semiconductor device. 　 In claim 13, The lower end of the conduction band of the oxide layer is located closer to the vacuum level side than the lower end of the conduction band of the first oxide semiconductor layer. The lower end of the conduction band of the second oxide semiconductor layer is located closer to the vacuum level side than the lower end of the conduction band of the first oxide semiconductor layer, a semiconductor device. 　 In claim 13, The oxide layer contains indium. In the oxide layer, the indium content is lower than the gallium content, a semiconductor device. 　 In claim 13, the content rate of gallium excluding oxygen in the oxide layer is 95% or more, and the content rate of indium excluding oxygen in the first oxide semiconductor layer is 95% or more. A semiconductor device. 　 A semiconductor device having first and second oxide semiconductor layers, an oxide layer, first to third conductive layers, and first and second insulating layers, wherein the first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the first conductive layer has a first recess, the first insulating layer and the second conductive layer have a first opening at a position overlapping the first recess, the oxide layer has a portion covering the side wall of the first opening, the first oxide semiconductor layer has a portion located on the second conductive layer, a portion located on the first conductive layer within the first opening, and a portion facing the first insulating layer with the oxide layer interposed therebetween within the first opening, the second oxide semiconductor layer is located on the first oxide semiconductor layer, the second insulating layer is located on the second oxide semiconductor layer, the third conductive layer is located on the second insulating layer, the third conductive layer faces the first oxide semiconductor layer with the second insulating layer interposed therebetween within the first opening, when a gate BT stress test under a dark room is performed on the semiconductor device under measurement conditions where the set temperature is 125°C, the drain potential Vd and the source potential Vs are 0V, and the gate potential Vg is +1.98V, the change amount of the threshold voltage calculated from the Id-Vg measurement after 100 hours has elapsed is -500 mV or more and 500 mV or less. A semiconductor device. 　 A method for manufacturing a semiconductor device according to any one of claims 1 to 19, forming the oxide layer by ALD using a first precursor containing gallium and a first oxidant, forming the first oxide semiconductor layer by ALD using a second precursor containing indium and a second oxidant containing ozone, A method for manufacturing a semiconductor device, comprising forming the second oxide semiconductor layer by sputtering using a sputtering target containing indium and gallium. 　 In claim 20, A method for manufacturing a semiconductor device, wherein the oxide layer and the first oxide semiconductor layer are formed without exposure to the atmosphere. 　 In claim 20, After forming the second oxide semiconductor layer, microwave plasma treatment is performed, The oxygen flow rate ratio in the microwave plasma treatment is 0.5% or more and 5% or less, A method of manufacturing a semiconductor device, wherein the heating temperature of the substrate when performing the microwave plasma treatment is 300°C or more and 450°C or less. In claim 22, The second insulating layer is formed of two or more kinds of films, Among the two or more kinds of films, the film in contact with the second oxide semiconductor layer has aluminum oxide. A method of manufacturing a semiconductor device.

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