RFID analog conditioner circuit, RFID digital block initialization circuit and RFID voltage reference

Abstract

An RFID analog conditioner circuit (ANL) comprises an antenna input (RF1) connected to an antenna input of a carrier frequency divider (FD16), to an antenna input of a demodulator (Dmd), and a first antenna input of a harvester with modulator (HM). A power output of the harvester with modulator (HM) is connected to a power input of the carrier frequency divider (FD16), to a power input of the demodulator (Dmd), and to a reference voltage circuit (Vref), whose output is connected to a reference input of the demodulator (Dmd), whose output is connected to a demodulation output (o-Dmd) of the RFID analog conditioner circuit (ANL). The RFID analog conditioner circuit (ANL) also comprises a modulation input (i-Mod) connected to a modulation input of the harvester with modulator (HM). The RFID analog conditioner circuit (ANL) comprises a voltage hold circuit (VH) and an initialization circuit (Int), whose inputs are connected to the power output of the harvester with modulator (HM), an output of the voltage hold circuit (VH) is connected to a holding output (o-VH) of the RFID analog conditioner circuit (ANL), and an output of the initialization circuit (Int) is connected to an initialization output (o-Int) of the RFID analog conditioner circuit (ANL).

Description

[0001] RFID analog conditioner circuit, RFID digital block initialization circuit and RFID voltage reference

[0002] The invention concerns an RFID analog conditioner circuit, an RFID digital block initialization circuit, and an RFID voltage reference, intended especially for flexible integrated circuits for nearfield communication (NFC) and in NFC tags.

[0003] There is known from publication titled „A Thin Elastic NFC Forum Type 1 Compatible RFID Tag” in IEEE Journal of Solid-State Circuits (Early Access), DOI: 10.1109 / JSSC.2023.3300256, an NFC RFID tag, whose architecture has been divided into an analog part and a digital part. The analog part consists of the following circuits: harvester with modulator, frequency divider, AM demodulator, reference voltage circuit, and symbol detector. The digital part consists of the following circuits: symbol decoder, NFC core, and NFC response circuit. In this tag, the antenna is connected to the harvester with modulator, the frequency divider, and the AM demodulator. The supply voltage from the harvester with modulator is connected to each analog and digital tag circuit. The output of the frequency divider is connected to the symbol decoder, the NFC core, the NFC response circuit, and the symbol detector. The output of the reference voltage circuit is connected to the AM demodulator and the symbol detector. The output of the AM demodulator is connected to the symbol detector and the frequency divider. Two other outputs of the AM demodulator are connected to the symbol detector. The output of the symbol detector is connected to the symbol decoder. The outputs of the symbol decoder are connected to the NFC core. The outputs of the NFC core are connected to the NFC response circuit. At least one output of the NFC response circuit is connected to the frequency divider, while the modulation output of the NFC response circuit is connected to the harvester with modulator. The symbol detector consists of a pulse counter made of a cascade of four flip-flops, a synchronizer of two flip-flops, and a delay circuit of five inverters. The NFC response circuit contains a 73 -bit shift register made of flip-flops. The digital part of the tag uses two clock signals with frequencies resulting from dividing the antenna signal frequency by 16 and 64.

[0004] There is known from the Korean patent description KR101839081B1, an NFC integrated circuit, which includes a rectifier for rectifying an ASK-modulated RF input signal and outputting a rectified signal; an offset calibrator for tracking the rectified signal outputted from the rectifier in response to control signals and generating a first input signal in accordance with a result of tracking; and a comparator for receiving and comparing the first input signal and a reference signal, and outputting a comparison signal. It is possible to automatically calibrate the offset of the comparator. In particular, an architecture is known from this invention in which part of the RF interface contains the following circuits: a rectifier, a modulator / demodulator, and a clock signal extractor. Moreover, the entire circuit contains a power management circuit, an internal oscillator, and a control circuit.

[0005] There are known from the European patent application EP2680458A2 an apparatus and method to provide improved NFC communications. A first NFC device antenna transmits information to a second NFC device by driving an antenna module with a current to generate a magnetic field. The magnetic field is modulated and the information is transmitted according to a first set of operating parameters. A second NFC device harvests power from the magnetic field and communicates information to the first NFC device by modulating the magnetic field according to a second set of operating parameters, which is received by the first NFC device. The first NFC device recovers a signal metric from the modulated magnetic field. The first NFC device uses the signal metric to provide feedback regarding the second set of operating parameters. Various systems are presented to utilize the signal metric feedback and provide efficient and reliable communications between the first and second NFC devices.

[0006] In particular, a system is known for this solution: an antenna module, an antenna driver, a modulator, a demodulator, a detection module, and an NFC controller module.

[0007] There are known from European invention EP2749050A1, methods and apparatus for improving management of NFC logical connections, which relate to improving mechanisms for managing logical connection establishment between a NFCC and a DH. In one example, with a NFC device a NFCC may be configured to receive a core initialization command, from a DH, as part of an initialization and activation procedure. The NFCC may be configured to transmit a core initialization response to the DH without information associated with a static RF connection. Thereafter, the NFC device may detect one or more remote NFC endpoints. In particular, the system known from this invention comprises an initialization module. The initialization module can initiate and activate internal communication between the system blocks - i.e., NFCC and DH. Such initialization can be performed via basic initialization messages between NFCC and DH.

[0008] There is known from American invention US3522454A a pulse control circuit comprising (a) a series connection extending from a first voltage supply terminal through the current electrodes of a first MOS transistor, then through the current electrodes of a second MOS transistor and then through a load resistance to a second voltage supply terminal; (b) a timing branch including a series circuit of a capacitance and a resistance and extending from the junction between said second MOS transistor and said load resistance to said second supply terminal; (c) the gate of said first MOS transistor being connected to the junction between said capacitance and resistance of said timing branch; (d) means for supplying to the gate of said first MOS transistor a clamping potential within the on condition of said first MOS transistor, said means being such as to limit the difference between said clamping potential and the threshold potential at said gate to a value small in comparison with the voltage across said first and second supply terminals; (e) input means connected to the gate of said second MOS, transistor; and (f) output means connected to the junction between said first and said second MOS transistors.

[0009] There is known from German invention DE2620187A1 monostable multivibrator circuit with a capacitor, a charging arrangement for charging the capacitor, an input arrangement for controlling the charging arrangement in dependence on an input signal and with an output arrangement for generating an output pulse, characterized in that the charging arrangement contains a first, second and third field effect transistor, that the first and second field effect transistor are each connected in series with their source-drain path and form a path between two terminals of an energy source, that the gate and the drain electrode of the first two transistors are connected to one another, that the gate electrode of the third field effect transistor is connected to a point in said path, that the first and second field effect transistor are each connected with their source-drain path between the first terminal of the energy source and a first terminal of the capacitor, that said input arrangement is connected to a second terminal of the capacitor, that the output arrangement is connected to the first terminal of the capacitor, and that the circuit is constructed such that during operation, in response to an input signal applied to said input arrangement, an output pulse is generated in the output arrangement, and that the source-drain path of the third transistor supplies a substantially constant current, whereby the charging of the capacitor begins, and that the output pulse is terminated when the voltage at the capacitor reaches a predetermined value.

[0010] There is known from American invention description US5315230A a reference voltage generator which compensates for temperature and VCC variations includes a constant current source and a MOS P-channel transistor. The constant current source provides a constant current over a wide range of VCC that corresponds to biasing a p-channel transistor in a region where its resistance is constant. The output of the current source is supplied to the P-channel transistor, which is in saturation. The constant current provides a constant voltage drop across the P-channel transistor. Hence, a stable reference voltage is generated. Temperature compensation is provided by biasing the P-channel transistor to saturation and supplying a constant current that the corresponds to biasing a p-channel transistor where the resistance is substantially constant over a temperature range. The current causes a voltage drop across the P-channel transistor to maintain a stable reference voltage. Also, temperature compensation is further provided by utilizing the negative temperature coefficients of the resistors included in the constant current source.

[0011] In particular, the feedback current source design is known from this invention, which has a resistor and two transistors coupled together in such a way that the gate of one transistor is connected to the source of the second transistor and the gate of the second transistor is connected to the drain of the first transistor, whereas the resistor is connected between one of the transistors and the supply voltage node. This design was implemented using p-MOS transistors.

[0012] There is known from American invention description US5955874A a reference voltage circuit that is independent of the voltage supply as well as substantially insensitive to process and temperature variations. The reference voltage circuit includes an intrinsic transistor circuit which includes a plurality of intrinsic transistors of equal size. The intrinsic transistor circuit is coupled to a current mirror circuit, and a plurality of threshold transistors. In so doing, a reference voltage circuit is provided that is substantially independent of process and temperature variations. In addition, by grounding the source connections of the plurality of threshold transistors, the reference voltage circuit output voltage also is substantially independent of supply voltage variations.

[0013] In particular, a solution using an n-MOS transistor having the gate connected with the drain and the source connected to the ground is known from this invention, providing the transistor's threshold voltage in the circuit. Such a structure performs a current-voltage conversion in the circuit.

[0014] There is known from American invention description US4975631A a constant current source circuit, which comprises a first FET connected to a first voltage line at its drain region and to a second voltage line through an impedance circuit at its source region and gate in common; a second FET connected to the first voltage line at its drain region and its source region and gate being connected to each other; a third FET connected to the source region of the second FET at its drain region, to the second voltage line at its source region and to the source region of the first FET at its gate; and a fourt FET connected to a current output node of the circuit at its drain region, to the second voltage line at its source region and to the source region of the second FET at its gate. Every FET is operated at the saturation state. In particular, a solution using an n-MOS transistor with the gate connected to the source and the drain connected to the power supply is known from this invention. This structure acts as a current source in the circuit.

[0015] In state-of-the-art electronics engineering, there are known (remote) radio-frequency identification (RFID) systems, and in particular near-field communication (NFC). There are known in the art field-effect transistors (FETs) with an insulated gate, thin-film transistors (TFTs), as well as transistors based on indium-gallium zinc oxide (IGZO or InGaZnO - from indium (In), gallium (Ga), zinc (Zn), oxygen (O)). It is also known that the designation of the drain and source of these transistors is conventional because, due to the symmetrical structure of the transistor, changing these designations does not affect the functionality of the transistor or the circuit in which it is located; however, this nomenclature is of an ordering nature.

[0016] The aim of the invention is to create a small, in terms of area occupied, and fast circuit for NFC RFID in a-IGZO technology, which is characterized by large TFT transistors with a relatively low cut-off frequency. There is therefore a need to solve the problem of implementation with too large an area, meeting critical time parameters and providing sufficient power, which are necessary for the correct operation of the entire NFC RFID tag circuit.

[0017] In addition, the aim of the invention is to properly initialize the digital blocks of the NFC tag using an implementationally economical, dedicated electronic circuit, which will solve the problem of excessive complexity of the digital implementation and the analog subcircuit of the RFID tag system.

[0018] Moreover, the aim of the invention is to provide a constant reference voltage, independent from the supply voltage, for the digital blocks of the NFC tag using an implementationally economical, dedicated electronic circuit, which will solve the problem of providing a repeatable reference voltage in circuits with large technological spreads, where it is problematic to obtain electronic components with constant parameters, and where is also a possibility of changing these parameters over time.

[0019] The essence of the solution is that an RFID analog conditioner circuit having an antenna input connected to an antenna input of a carrier frequency divider, to an antenna input of a demodulator and to a first antenna input of a harvester with modulator, whose power output is connected to a power input of the carrier frequency divider, to a power input of the demodulator and to a reference voltage circuit, whose output is connected to a reference input of the demodulator, whose output is connected to a demodulation output of the RFID analog conditioner circuit, as well as having a modulation input connected to a modulation input of the harvester with modulator, according to the invention, it comprises a voltage hold circuit and an initialization circuit, whose inputs are connected to the power output of the harvester with modulator. Furthermore, an output of the voltage hold circuit is connected to a holding output of the RFID analog conditioner circuit, and an output of the initialization circuit is connected to an initialization output of the RFID analog conditioner circuit. The technical advantage of using the voltage hold circuit is to maintain a constant voltage at the holding output of the conditioner circuit, even in the event of a short-term lack of a high-frequency signal at the antenna input. However, as a result of the initialization circuit, it is possible to reset several digital circuits connected to this circuit through the initialization output and synchronously trigger their operation at the correct time.

[0020] Advantageously, the reference voltage circuit is connected to the demodulator via a ripple rejection circuit, which has a power input connected to the power output of the harvester with modulator. This makes the demodulator less susceptible to errors caused by momentary fluctuations in the DC voltage coming from the harvester with modulator.

[0021] Advantageously, the RFID analog conditioner circuit comprises a shunt regulator circuit connected to the power output of the harvester with modulator. For that reason, the voltage at the harvester's output with modulator and the entire power supply line cannot exceed the maximum voltage value, which protects the other circuits from destruction or incorrect operation, even with high signal amplitudes at the antenna input.

[0022] Advantageously, the RFID analog conditioner circuit comprises a second antenna input connected to a second antenna input of the harvester with modulator. By using the second complementary antenna signal input, it is possible to provide a much attenuated high-frequency signal than in the case without this input, which is beneficial to the efficiency of the harvester with modulator and reduces the risk of overloading the demodulator and carrier frequency divider.

[0023] Advantageously, the second antenna input is connected to a ground of the RFID analog conditioner circuit. For that reason, the entire conditioner has asymmetric inputs and outputs, significantly reducing the number of nodes and the level of complexity of the construction of particular conditioner components.

[0024] Advantageously, the RFID analog conditioner circuit operates substantially at a frequency of 13.56 MHz of the input signal. For that reason, it is possible to use the circuit to implement the NFC standard.

[0025] Advantageously, all transistors in the circuit are the FETs of "n" type. The use of one type of FETs with insulated gates simplifies the technological process of implementing a circuit.

[0026] Advantageously, all transistors in the circuit are TFT-type transistors. TFTs allow to manufacture cheap and / or flexible integrated circuits.

[0027] Advantageously, the transistor channels are made of amorphous semiconductor material. The use of amorphous semiconductor material ensures low cost of manufacturing transistors (at relatively low temperatures).

[0028] Advantageously, the transistors contain indium-gallium zinc oxide. The use of indium gallium zinc oxide (IGZO) provides a relatively high carrier mobility parameter.

[0029] Advantageously, the voltage hold circuit contains a diode and a capacitor connected in series between the input and ground of this circuit, and the output is connected to the connection point of the diode and the capacitor. For that reason, temporary drops in signal amplitude at the antenna input or inputs caused by modulation during communication or spikes caused by supply voltage surges are eliminated.

[0030] Advantageously, the diode used in the voltage hold circuit is made of a transistor with its gate connected to its source and connected to the input of the circuit, and the drain of the transistor connected to the capacitor and the output of the circuit. For that reason, it is possible to implement the circuit in a technological process that does not allow the creation of a P-N or M-S semi conductor j uncti on .

[0031] Advantageously, the width-to-length ratio of the transistor channel used to construct the diode in the voltage hold circuit ranges from 5 to 20. For that reason, a proper current efficiency of the transistor is provided, ensuring a suitably short charging time of the capacitance connected to the transistor.

[0032] Advantageously, the capacitance of the capacitor used in the voltage hold circuit ranges from 5 pF to 20 pF. F or that reason, a sufficient electric charge is provided to momentarily maintain the voltage in the case of signal decays at the antenna input or inputs.

[0033] Advantageously, the ripple rejection circuit has its input and output connected inside the circuit and connected to the power input of the circuit via a resistor, and to the ground of the circuit via a capacitor or capacitors connected in parallel. This allows the capacitor charging current to be limited by the resistor, and the parallelly connected capacitors increase the stored charge.

[0034] Advantageously, the resistance of the resistor used in the ripple rejection circuit ranges from 2 MQ to 5 MQ. This allows the discharge time constant of the charge-holding capacitor to initialize the demodulator on subsequent input signal frames properly. Advantageously, the cumulative capacitance of capacitors used in the ripple rejection circuit ranges from 3 pF to 50 pF. Therefore, the level of interference at the demodulator supply voltage does not cause errors during signal demodulation.

[0035] Furthermore, according to the invention, a first transistor has the source connected to a circuit ground; the drain of the first transistor is connected to the initialization output, to a power supply input via a first resistor, to the gate of a second transistor, and to the drain of a third transistor, while the gate of the first transistor is connected to the drain of the second transistor. Moreover, the source of the second transistor is connected to the circuit ground, while the drain of the second transistor is connected to the power supply input via a second resistor. Moreover, the source of the third transistor is connected to the circuit ground, while the gate of the third transistor is connected to the circuit ground via a capacitor and to the power supply input via a third resistor. The technical advantage of such a structure is its bistable behavior conditioned by the mutual coupling of the first two transistors, while the switching time of the bistable circuit depends on the time constant resulting from the value of the capacitor and the third resistor.

[0036] Advantageously, the width-to-length ratio of the channel of the first transistor in relation to the width-to-length ratio of the channel of the second transistor is either significantly smaller or significantly larger. For that reason, the bistable circuit is conditioned to initialize in one of two states.

[0037] Advantageously, the value of the first resistor in relation to the value of the second resistor is significantly either smaller or significantly larger. This causes the bistable circuit to initialize in one of two states, particularly when the first two transistors are of similar size.

[0038] Advantageously, the gate of the first transistor is connected to the circuit ground via a second capacitor. For that reason, the bistable circuit is conditioned to initialize in one of two states due to the time constant resulting from the values of the second capacitor and the second resistor - especially in the case where the first two transistors and the first two resistors are of similar size.

[0039] Advantageously, the gate of the third transistor is connected to the source and the gate of a fourth transistor, whose drain is connected to the power supply input. Due to the fourth transistor, the initial state of the circuit is quickly restored after a power failure.

[0040] Advantageously, the power supply input is connected directly to an output of an RFID harvester. The direct power supply signal from the harvester, without power holding circuits, allows the generation of an initialization signal at the beginning of RFID communication and independently of power drops resulting from modulation.

[0041] Advantageously, all transistors in the circuit are the FETs of "n" type. The use of one type of FETs with insulated gates simplifies the technological process of implementing a circuit.

[0042] Advantageously, all transistors in the circuit are TFT-type transistors. TFTs allow the manufacture of cheap and / or flexible integrated circuits.

[0043] Advantageously, the transistor channels are made of amorphous semiconductor material. The use of amorphous semiconductor material ensures low cost of manufacturing transistors (at relatively low temperatures).

[0044] Advantageously, the transistors contain indium-gallium zinc oxide. The use of indium gallium zinc oxide (IGZO) provides a relatively high carrier mobility parameter.

[0045] Advantageously, the capacitance of the capacitor ranges from 3 to 5 picofarads, while the value of the third resistor ranges from 15 to 25 megaohms. For that reason, the bistable circuit composed of the elements: the first transistor, the second transistor, the first resistor, the second resistor, and the second capacitor, can reach a stable balance point corresponding to the power supply input voltage, and the pulse on the initialization output lasts at least a few microseconds.

[0046] Advantageously, the capacitance of the second capacitor ranges from 20 to 30 femtofarads, the value of the second resistor ranges from 5 to 15 megaohms, and the value of the first resistor is substantially half of the value of the second resistor, with the first two transistors being substantially of the same size. Therefore, the probability of achieving a stable state in the first phase of the circuit's operation is close to one.

[0047] Furthermore, the essence of the solution is that, in an RFID voltage reference having a feedback current source comprising two coupled transistors in the way that the first transistor is connected to the drain of the second transistor, and the gate of the second transistor is connected to the source of the first transistor, while a resistor is connected between the gate and the source of the second transistor, according to the invention, a low-precision subthreshold current source is connected between the feedback current source and a power supply input, at least one additional feedback current source is connected between the feedback current source and a reference voltage output, while a current-voltage converter is connected between the reference voltage output and a circuit ground. The technical advantage of this solution is to provide a mechanism for stabilizing the voltage between the gate and the source of the second transistor of the feedback current source thus stabilizing the drain current of the first transistor of the feedback current source.

[0048] Advantageously, the low-precision subthreshold current source comprises a transistor, whose drain is connected to the power supply input and whose gate is connected to its source and to the drain of the second transistor of the feedback current source. For that reason, a constant current from a few nanoamps to several nanoamps is obtained, depending on the supply voltage, geometric dimensions, and the specimen of the transistor of the low-precision subthreshold current source, while this transistor keeps the properties of a non-ideal current source.

[0049] Advantageously, an additional feedback current source comprises two coupled transistors in the way that the gate of the first transistor is connected to the drain of the second transistor, and the gate of the second transistor is connected to the source of the first transistor, while a resistor is connected between the gate and the source of the second transistor, whereas the drain of the second transistor is connected to the source of the second transistor of the feedback current source, the drain of the first transistor is connected to the power supply input, and the source of the second transistor is connected to the reference voltage output. For that reason, a stable voltage is obtained on the resistor of the additional feedback current source, independent of the supply voltage connected to the power supply input of the circuit, which results in a stable current flowing through this resistor, which comes from the reference voltage output node.

[0050] Advantageously, the current-voltage converter comprises a transistor, whose source is connected to the circuit ground, and whose gate is connected to its drain and to the reference voltage output. This voltage can be regulated by the current of the feedback current source and the geometrical dimensions of the transistor of the current-voltage converter, performing the function of converting the current value to the voltage value.

[0051] Advantageously, the first transistor in the feedback current source is implemented as multiple transistors connected in parallel. For that reason, it is possible to control the current of the feedback current source by changing the number of transistors. Furthermore, the impact of technological spreads on the values of generated currents is reduced, and the effects resulting from the imperfections of transistors’ physical models are reduced.

[0052] Advantageously, the number of transistors connected in parallel in the feedback current source in place of the first transistor ranges from 2 to 4. This makes it possible to obtain the minimum current of the feedback current source necessary to polarize the gate of the first transistor of the additional feedback current source.

[0053] Advantageously, the transistor in the low-precision subthreshold current source is implemented as multiple transistors connected in parallel. For that reason, the current in the subthreshold operating range of the transistor in the subthreshold current source is more significant than in the second transistor in the feedback current source in a similar range, which provides the surplus current needed to charge the gate capacitance of the first transistor in the feedback current source.

[0054] Advantageously, the number of parallelly connected transistors in the low-precision subthreshold current source ranges from 2 to 4. This makes it possible to obtain the minimum current of the low-precision subthreshold current source necessary to polarize the gate of the first transistor of the feedback current source.

[0055] Advantageously, the transistors in the additional feedback current source are implemented as multiple transistors connected in parallel. For that reason, it is possible to control the current of the feedback current source by changing the number of transistors. Furthermore, the impact of technological spreads on obtained currents is reduced, and the effects resulting from the imperfections of the transistors’ physical models are reduced. Moreover, as a result, the additional feedback current source can generate significantly higher currents than the feedback current source.

[0056] Advantageously, the numbers of parallelly connected transistors in the additional feedback current source in the places of the transistors of this source range from 3 to 12. For that reason, the entire circuit ensures obtaining stable voltages in the range from 0.7 V to 1.5 V.

[0057] Advantageously, the transistor in the current-voltage converter is implemented as multiple transistors connected in parallel. This reduces the influence of intra-class variations on the voltage at the reference voltage output. For that reason, the impact of inter-specimen spreads on the voltage value on the reference voltage output is reduced.

[0058] Advantageously, the number of parallelly connected transistors in the current-voltage converter ranges from 2 to 4. This produces the desired output voltage of the source.

[0059] Advantageously, the power supply input is connected directly to an output of an RFID harvester, or indirectly via a ripple rejection circuit. This provides a constant and stable reference voltage for ripple voltage ranging from 3 V to 7 V.

[0060] Advantageously, all transistors in the circuit are the FETs of "n" type. The use of one type of FETs with insulated gates simplifies the technological process of implementing a circuit.

[0061] Advantageously, all transistors in the circuit are TFT-type transistors. TFTs allow to manufacture cheap and / or flexible integrated circuits.

[0062] Advantageously, the transistor channels are made of amorphous semiconductor material. The use of amorphous semiconductor material ensures low cost of manufacturing transistors (at relatively low temperatures).

[0063] Advantageously, the transistors contain indium-gallium zinc oxide. The use of indium gallium zinc oxide (IGZO) provides a relatively high carrier mobility parameter.

[0064] Advantageously, the width-to-length ratio of the channel of the second transistor in the feedback current source ranges from 1 to 2, and the resistance value of the resistor in this source ranges from 1.5 to 2.5 megaohms. Due to this, the subthreshold current of the second transistor in the feedback current source is smaller than the one of the transistor of the low-precision subthreshold current source, and the feedback current source establishes a small current needed only to polarize the additional feedback current source.

[0065] Advantageously, the width-to-length ratio of the channel of the transistor of the lowprecision subthreshold current source ranges from 2 to 3. Due to this, the current of the low- precision subthreshold current source in the subthreshold range is larger than the current of the drain of the second transistor of the feedback current source, which allows for proper operation of the entire circuit.

[0066] Advantageously, the resistance value of the resistor in the additional feedback current source ranges from 100 to 150 kiloohms. This provides a polarity current for the current-voltage converter in a range of transition characteristics, allowing small manufacturing spreads. Furthermore, the essence of the solution is that, in an RFID voltage reference having a feedback current source comprising two coupled transistors in the way that the first transistor is connected to the drain of the second transistor, and the gate of the second transistor is connected to the source of the first transistor, while a resistor is connected between the gate and the source of the second transistor, according to the invention, a low-precision subthreshold current source is connected between the feedback current source and a power supply input. Moreover, between the feedback current source and a circuit ground a reference voltage output circuit is connected, from which reference voltage output is derived. The technical advantage of this solution is to provide a mechanism for stabilizing the voltage between the gate and the source of the second transistor of the feedback current source thus stabilizing the drain current of the first transistor of the feedback current source.

[0067] Advantageously, the low-precision subthreshold current source comprises a transistor, whose drain is connected to the power supply input, and whose gate is connected to its source and to the drain of the second transistor of the feedback current source. For that reason, a constant current from a few nanoamps to several nanoamps is obtained, depending on the supply voltage, geometric dimensions, and the specimen of the transistor of the low-precision subthreshold current source, while this transistor keeps the properties of a non-ideal current source.

[0068] Advantageously, the reference voltage output circuit comprises two coupled transistors in the way that the gate of the first transistor is connected to the drain of the second transistor, and the gate of the second transistor is connected to the source of the first transistor, and in that comprises a third transistor connected between the source of the first transistor and the circuit ground, whereas the gate of the third transistor is connected to its drain, to the source of the first transistor and to the reference voltage output, the drain of the second transistor is connected to the source of the second transistor of the feedback current source, the drain of the first transistor is connected to the power supply input, while the source of the second transistor is connected to the circuit ground. For that reason, a stable voltage is obtained between the drain and the source of the third transistor of the reference voltage output circuit, independent of the supply voltage connected to the power supply input of the circuit, which results in a stable current flow from the source of the third transistor, whereas this current depends on the voltage-current transient characteristic of the third transistor.

[0069] Advantageously, the first transistor in the feedback current source is implemented as multiple transistors connected in parallel. For that reason, it is possible to control the current of the feedback current source by changing the number of the transistors. Furthermore, the impact of technological mismatches on the values of generated currents is reduced and the effects resulting from the imperfections of the transistors’ physical models are reduced.

[0070] Advantageously, the number of parallelly connected transistors in the feedback current source in place of the first transistor ranges from 2 to 4. This makes it possible to obtain the minimum current of the feedback current source necessary to polarize the gate of the first transistor of the reference voltage output circuit.

[0071] Advantageously, the transistor in the low-precision subthreshold current source is implemented as multiple transistors connected in parallel. For that reason, the current in the subthreshold operating range of the transistor in the subthreshold current source is greater than in the second transistor in the feedback current source in the similar range, which provides the surplus current needed to charge the gate capacitance of the first transistor in the feedback current source, and therefore the correct operation of the feedback current source.

[0072] Advantageously, the number of parallelly connected transistors in the low-precision subthreshold current source ranges from 2 to 4. This makes it possible to obtain the minimum current of the low-precision subthreshold current source necessary to polarize the gate of the first transistor of the feedback current source.

[0073] Advantageously, the transistors in the reference voltage output circuit are implemented as multiple transistors connected in parallel. This enables discrete regulation of the current flowing from the source of the third transistor of the reference voltage output circuit to the ground, by changing the number of transistors in the places of the first and the third transistor. Moreover, an additional change in the number of transistors in the place of the second transistor of the reference voltage output circuit allows for more precise voltage regulation at the reference voltage output. The increase of the number of transistors used in the reference voltage output circuit reduces the impact of technological mismatches on the voltage obtained at the reference voltage output. Furthermore, it reduces the contribution of effects resulting from the imperfections of the transistors’ physical models.

[0074] Advantageously, the numbers of parallelly connected transistors in the reference voltage output circuit (VR), in the places of the first two transistors of this circuit range from 3 to 12, and the number of parallelly connected transistors in the reference voltage output circuit in place of the third transistor of this circuit ranges from 2 to 4. For that reason, the entire circuit ensures obtaining stable voltages in the range from 0.3 V to 1.5 V.

[0075] Advantageously, the power supply input is connected directly to an output of an RFID harvester, or indirectly via a ripple rejection circuit. This provides a constant and stable reference voltage for ripple voltage ranging from 3 V to 7 V.

[0076] Advantageously, all transistors in the circuit are the FETs of "n" type. The use of one type of FETs with insulated gates simplifies the technological process of implementing a circuit.

[0077] Advantageously, all transistors in the circuit are TFT-type transistors. TFTs allow to manufacture cheap and / or flexible integrated circuits.

[0078] Advantageously, the transistor channels are made of amorphous semiconductor material. The use of amorphous semiconductor material ensures low cost of manufacturing transistors (at relatively low temperatures).

[0079] Advantageously, the transistors contain indium-gallium zinc oxide. The use of indium gallium zinc oxide (IGZO) provides a relatively high carrier mobility parameter.

[0080] Advantageously, the width-to-length ratio of the channel of the second transistor in the feedback current source ranges from 1 to 2, and the resistance value of the resistor in this source ranges from 1.5 to 2.5 megaohms. Due to this, the subthreshold current of the second transistor in the feedback current source is smaller than the one of the transistor of the low-precision subthreshold current source, and the feedback current source establishes a small current needed only to polarize the reference voltage output circuit.

[0081] Advantageously, the width-to-length ratio of the channel of the transistor of the low- precision subthreshold current source ranges from 2 to 3. Due to this, the current of the low- precision subthreshold current source in the subthreshold range is larger than the current of the drain of the second transistor of the feedback current source, which allows for proper operation of the entire circuit.

[0082] The invention has been described below in detail, with reference to the attached figures. Fig. 1 presents a schematic diagram of a basic RFID analog conditioner circuit, fig. 2 presents a schematic diagram of an RFID analog conditioner circuit with supporting circuits, fig. 3 presents a schematic diagram of an RFID digital block initialization circuit, fig. 4 presents a schematic diagram of an RFID voltage reference with a feedback current source with single transistors, fig. 5 presents a schematic diagram of an RFID voltage reference with a feedback current source with multiple transistors connected in parallel, fig. 6 presents a schematic diagram of an RFID voltage reference with a reference voltage output circuit with single transistors, and fig. 7 - a schematic diagram of an RFID voltage reference with a reference voltage output circuit with multiple transistors connected in parallel.

[0083] The RFID analog conditioner circuit in the embodiment shown in fig. 1 contains the following circuits: a harvester with modulator HM, an initialization circuit Int, a reference voltage circuit Vref, a voltage hold circuit VH, a demodulator Dmd and an analog subcircuit of carrier frequency divider FD16. Moreover, the RFID analog conditioner circuit ANL has: an antenna input RF1, a demodulation output o-Dmd, a holding output o-VH, a modulation input i-Mod, and an initialization output o-Int.

[0084] The antenna input RF1 is connected to: the first antenna input harvester with modulator HM, the antenna input of the carrier frequency divider FD16, and the antenna input of the demodulator Dmd. The power output of the harvester with modulator HM is connected to: the power input of the carrier frequency divider FD16, the reference voltage circuit Vref, the power input of the demodulator Dmd, the input of the voltage hold circuit VH, and the input of the initialization circuit Int. The output of the reference voltage circuit Vref is connected to the reference input of the demodulator Dmd. The output of the demodulator Dmd is connected to the demodulation output o-Dmd. The voltage hold circuit VH output is connected to the holding output o-VH. The modulation input i-Mod is connected to the modulation input of the harvester with modulator HM. The output of the initialization circuit Int is connected to the initialization output o-Int.

[0085] The RFID analog conditioner circuit in the embodiment shown in fig. 2 contains the following circuits: a harvester with modulator HM, a shunt regulator circuit SR, an initialization circuit Int, a reference voltage circuit Vref, a ripple rejection circuit RR, a voltage hold circuit VH, a demodulator Dmd, and an analog subcircuit of carrier frequency divider FD16. Moreover, the RFID analog conditioner circuit ANL has: an antenna input RF1, a second antenna input RF2, a demodulation output o-Dmd, a holding output o-VH, a modulation input i-Mod, an initialization output o-Int, and a ground gnd.

[0086] The antenna input RF1 is connected to: the first antenna input harvester with modulator HM, the antenna input of the carrier frequency divider FD16, and the antenna input of the demodulator Dmd. The second antenna input RF1 is connected to the second antenna input of the harvester with modulator HM and the ground gnd. The power output of the harvester with modulator HM is connected to: the power input of the carrier frequency divider FD16, the reference voltage circuit Vref, the shunt regulator circuit SR, the power input of the ripple rejection circuit RR, the power input of the demodulator Dmd, the input of the voltage hold circuit VH, and the input of the initialization circuit Int. The output of the reference voltage circuit Vref is connected to the input of the ripple rejection circuit RR, and the output of the ripple rejection circuit RR is connected to the reference input of the demodulator Dmd. The output of the demodulator Dmd is connected to the demodulation output o-Dmd. The voltage hold circuit VH output is connected to the holding output o-VH. The modulation input i-Mod is connected to the modulation input of the harvester with modulator HM. The output of the initialization circuit Int is connected to the initialization output o-Int.

[0087] The harvester with modulator HM circuit converts the high-frequency voltage signal from the antenna input RF1 or the antenna inputs RF1 and RF2 to a constant voltage that supplies a number of components of the ANL conditioner circuit that are connected to the power output of the harvester with modulator HM. The maximum value of this voltage is limited by the shunt regulator circuit SR (to about 6 V), which ensures the correct operation of the ANL conditioner components at a high level of the high-frequency signal amplitude at the antenna input RF1 or the antenna inputs RF1 and RF2 while reducing the risk of damage caused by a too high voltage level. In addition to the power-delivering function, the harvester with modulator HM loads or unloads the antenna inputs RF1 and RF2, depending on the voltage level on the modulation input i-Mod supplied externally to the ANL conditioner, thus affecting the total impedance at the antenna inputs RF1 and RF2, which performs the return communication of the NFC tag. The high-frequency alternating voltage from the antenna input RF1, after being provided to the carrier frequency divider FD16, is converted into a signal with a sixteen-time lower frequency with preserved phase synchronism, which can additionally be regulated from the digital side of the circuit. Due to the use of the reference voltage circuit Vref, it is possible to obtain a reference voltage independent of the temporary amplitude of the high-frequency signal at the input or inputs of the ANL conditioner and, consequently, at the power output of the harvester with modulator HM. Moreover, the voltage from the antenna input RF1 is fed to the input of the demodulator Dmd, which, by comparing the temporary values of the amplitude from the antenna input RF1 with the voltage from the reference voltage circuit Vref, converts the temporary values of this amplitude into a binary sequence assigning respectively high and low amplitude values to low and high logical levels on the demodulation output o-Dmd. The ripple rejection circuit RR has an additional beneficial effect on the operation of the demodulator Dmd by reducing its vulnerability to errors caused by unusual voltage interferences at the output of the reference voltage circuit Vref. The high-frequency alternating voltage from the antenna input RF1, after conversion to a constant voltage in the harvester with modulator HM, is also used to accumulate electrical energy in the voltage hold circuit VH, whose goal is to maintain a constant voltage at the holding output o-VH during shortterm decays of the high-frequency signal, and for that reason, the circuits connected there, sensitive to the supply voltage declining, can operate correctly.

[0088] The invention allows for a small area and frequency efficient circuit implementation of the RFID analog conditioner circuit, and the power from the antenna RF signal is obtained efficiently enough to power all conditioner subcircuits. The industrial application of the invention is in the industry and market of products requiring individual electronic markings.

[0089] The RFID digital block initialization circuit in the embodiment shown in fig. 3 contains four transistors Tl, T2, T3, and Tr, three resistors Rl, R2, and Rr, two capacitors Cr and C2, a power supply input HRV, an initialization output Int, and a circuit ground gnd.

[0090] The source of the first transistor Tl is connected to the circuit ground gnd. The drain of the first transistor Tl is connected to the initialization output Int, to the power supply input HRV via the first resistor Rl, the gate of the second transistor T2, and the drain of the third transistor T3. The gate of the first transistor Tl is connected to the drain of the second transistor T2 and to the circuit ground gnd via the second capacitor C2. The source of the second transistor T2 is connected to the circuit ground gnd. The drain of the second transistor T2 is connected to the power supply input HRV via the second resistor R2. The source of the third transistor T3 is connected to the circuit ground gnd. The gate of the third transistor T3 is connected to the circuit ground gnd via capacitor Cr, to the power supply input HRV via the third resistor Rr, and to the source and the gate of the fourth transistor Tr. The drain of the fourth transistor Tr is connected to the power supply input HRV.

[0091] The operation of the RFID digital block initialization circuit takes place in two phases. In the first phase, after switching on the circuit's power supply, i.e., when a voltage of about 2 V appears between the HRV power supply input and the circuit ground gnd, the process of charging the capacitor Cr through the resistance of the third resistor Rr begins. This voltage is initially too low to drive the third transistor T3. However, this allows the first and the second transistor, Tl and T2, to operate with positive feedback. In this case, the first two transistors, the first two resistors, and the second capacitor Tl, T2, R2, Rl, and C2 form a bistable circuit, which always allows obtaining one of two stable states at the initialization output Int. These states correspond to voltages close to the level of the circuit ground gnd and the power supply input HRV. In general, the states would be accidental, i.e., it would be impossible to determine whether the initialization output Int potential will converge in time to the potential of the power supply input HRV or the circuit ground gnd. This is typical for bistable circuits with a symmetrical structure. However, due to the use of additionally increased capacitance between the gate and source electrodes of the first transistor Tl, by switching on the second capacitor C2, the stable voltage at the initialization output Int, after starting the system, is always close to the power supply input HRV voltage.

[0092] In the second phase of the circuit operation, i.e., when the capacitance of the capacitor Cr is charged to the voltage allowing the third transistor T3 to enter the triode range of operation, the drain of the third transistor T3 lowers the voltage of the gate of the second transistor T2 to approximately 0 V, switching the bistable circuit Tl, T2, R2, Rl, and C2 to the opposite state, which means that the voltage at the initialization output Int close to the voltage level at the power supply input HRV switches to the opposite value, and a state corresponding to the voltage close to 0 V appears.

[0093] The invention allows the digital blocks of the RFID NFC tag to be initialized with a signal occurring at the right moment for the proper duration, ensuring the correct operation of the digital part of the tag. The industrial application of the invention is found in the industry and the market of products requiring individual electronic markings.

[0094] The RFID voltage reference in the embodiment shown in fig. 4 contains, between a power supply input Vhrv and a circuit ground gnd, a cascade connection of: a low-precision subthreshold current source IT, a feedback current source IF, an additional feedback current source IR and a current- voltage converter VT. A reference voltage output Vref of the RFID voltage reference has been connected between the additional feedback current source IR and the current-voltage converter VT.

[0095] The low-precision subthreshold current source IT is implemented as the transistor Tit, which drain is connected to power supply input Vhrv, and its gate is connected to its source and connected to the feedback current source IF.

[0096] The feedback current source IF is implemented based on two transistors, Tia and Tib, and the resistor Rif. The gate of the first transistor Tia is connected to the drain of the second transistor Tib. The gate of the second transistor Tib is connected to the source of the first transistor Tia. The resistor Rif is connected between the gate and the source of the second transistor Tib. The drain of the first transistor Tia is connected to the power supply input Vhrv. The drain of the second transistor Tib is connected to the low-precision subthreshold current source IT. The source of the second transistor Tib is connected to the additional feedback current source IR.

[0097] The additional feedback current source IR was implemented based on two transistors, Tra and Trb, and the resistor Rr. The gate of the first transistor Tra is connected to the drain of the second transistor Trb. The gate of the second transistor Trb is connected to the source of the first transistor Tra. The resistor Rr is connected between the gate and the source of the second transistor Trb. The drain of the first transistor Tra is connected to the power supply input Vhrv. The drain of the second transistor Trb is connected to the feedback current source IF. Whereas the source of the second transistor Trb is connected to the current-voltage converter VT and the reference voltage output Vref of the RFID voltage reference circuit.

[0098] The current-voltage converter VT is implemented in the form of a Tvt transistor, the source of which is connected to the circuit ground gnd, and the gate is connected to the drain, and connected to the additional feedback current source IR and to the reference voltage output Vref of the RFID voltage reference circuit.

[0099] The RFID voltage reference in the embodiment shown in fig. 5 is substantially the same as the circuit in the embodiment of fig. 4, with the difference that: the transistor Tit was made as a parallel connection of two transistors Titl and Tit2, the transistor Tia was made as a parallel connection of two transistors Tial and Tia2, the transistor Tra was made as a parallel connection of five transistors Tral, Tra2, Tra3, Tra4 and Tra5, the transistor Trb was made as a parallel connection of five transistors Trbl, Trb2, Trb3, Trb4 and Trb5, while the transistor Tvt was made as a parallel connection of three transistors Tvtl, Tvt2 and Tvt3.

[0100] In the presented solution, the low-precision subthreshold current source IT uses the subthreshold operation region of transistor Tit to increase the gate potential of the transistor Tia by charging the gate capacitance of the transistor Tia. The channel of the transistor Tit forces a current in the range of 1 nA to 15 nA through the drain of the transistor Tib and the gate capacitance of transistor Tia, which causes transistor Tia to enter the saturation range of operation. The pentode range of the transistor Tia causes current flow through its source and drain, and a voltage directly proportional to this current is applied to the resistor Rif. The increase of the voltage on the resistor Rif, caused by charging the gate capacitance of the transistor Tia by the current source IT, is stopped by the transistor Tib at a moment when the voltage on the resistor Rif causes transistor Tib to enter the triode range of operation from a cut-off state. This occurs when approximately the voltage on the resistor Rif exceeds the threshold voltage of the transistor Tib, then the drain of the transistor Tib begins to limit the voltage across the gate capacitance of the transistor Tia, leading to a stabilization of the current of the drain of the transistor Tia and the voltage on the resistor Rif. The stabilized current of the transistor Tia is also a current of the feedback current source IF, which forces a stable current flow into the gate of the first transistor Tra of the additional feedback current source IR.

[0101] The additional source IRuses transistors Tra and Trb to stabilize the voltage on the resistor Rr by limiting the voltage of the gate capacitance of the transistor Tra, which is charged by the source IF. The stabilization mechanism results from the opposite nature of the operation of transistors Tra and Trb. The gate of the transistor Tra is charged with current from the source IF, leading to an increase of current in the source of the transistor Tra and thus the voltage on the resistor Rr; however, after exceeding the voltage on the resistor Rr above the threshold voltage of the transistor Trb, the source IF current no longer charges the gate capacitance of the transistor Tra, but is discharged by the drain of the transistor Trb.

[0102] The constant current of the source IR provides the stable voltage on the resistor Rr. In this solution, this current simultaneously sets the operating point of the transistor Tvt, forcing its active operation, which, according to a DC characteristic of the transistor Tvt, results in a constant voltage at the reference voltage output Vref.

[0103] The invention provides a reference voltage, which is constant and independent from the state of the reference circuit, for the digital blocks of the NFC RFID tag. The industrial application of the invention is in the industry and market for products requiring individual electronic markings.

[0104] The RFID voltage reference in the embodiment shown in fig. 6 contains, between a power supply input Vhrv and a circuit ground gnd, a cascade connection of: a low-precision subthreshold current source IT, a feedback current source IF, and a reference voltage output circuit VR, from which a reference voltage output Vref of the RFID voltage reference is derived.

[0105] The low-precision subthreshold current source IT is implemented as the transistor Tit, which drain is connected to the power supply input Vhrv, and its gate is connected to its source and connected to the feedback current source IF.

[0106] The feedback current source IF is implemented based on two transistors, Tia and Tib, and the resistor Rif. The gate of the first transistor Tia is connected to the drain of the second transistor Tib. The gate of the second transistor Tib is connected to the source of the first transistor Tia. The resistor Rif is connected between the gate and the source of the second transistor Tib. The drain of the first transistor Tia is connected to the power supply input Vhrv. The drain of the second transistor Tib is connected to the low-precision subthreshold current source IT. The source of the second transistor Tib is connected to the reference voltage output circuit VR.

[0107] The reference voltage output circuit VR is implemented based on three transistors Tva, Tvb, and Tvc. The gate of the first transistor Tva is connected to the drain of the second transistor Tvb. The gate of the second transistor Tvb is connected to the source of the first transistor Tva. The third transistor Tvc is connected between the ground of the circuit gnd and the source of the first transistor Tva, to which the drain of the third transistor Tvc is connected and to its gate. The drain of the first transistor Tva is connected to the power supply input Vhrv. The drain of the second transistor Tvb is connected to the feedback current source IF. However, the source of the second transistor Tvb is connected to the circuit ground gnd. The reference voltage output Vref of the RFID voltage reference circuit is connected to the source of the first transistor Tva also.

[0108] The RFID voltage reference in the embodiment shown in fig. 7 is substantially the same as the circuit in the embodiment of fig. 6, with the difference that: the transistor Tit was made as a parallel connection of two transistors Titl and Tit2, the transistor Tia was made as a parallel connection of two transistors Tial and Tia2, the transistor Tva was made as a parallel connection of five transistors Tval, Tva2, Tva3, Tva4 and Tva5, the transistor Tvb was made as a parallel connection of five transistors Tvbl, Tvb2, Tvb3, Tvb4 and Tvb5, while the transistor Tvc was made as a parallel connection of three transistors Tvcl, Tvc2 and Tvc3.

[0109] In this solution, the low-precision subthreshold current source IT uses the subthreshold operation of the transistor Tit to increase the gate potential of the transistor Tia by charging the gate capacitance of the transistor Tia. The channel of the transistor Tit forces a current ranging from 1 nA to 15 nA through the drain of the transistor Tib and the gate capacitance of the transistor Tia, which causes the transistor Tia to enter the saturation range of operation. The saturation range of the transistor Tia causes current to flow through its source and drain, and a voltage directly proportional to this current is applied to the resistor Rif. The voltage increase on the resistor Rif, caused by charging the gate capacitance of the transistor Tia by the current source IT, is stopped by the transistor Tib at the moment when the voltage on the resistor Rif causes the transistor Tib to enter the triode range of operation from a cut-off state. This occurs when the voltage on the resistor Rif exceeds approximately the threshold voltage of the transistor Tib, then the drain of the transistor Tib begins to limit the voltage on the gate capacitance of the transistor Tia, leading to a current stabilization of the drain of the transistor Tia and the voltage on the resistor Rif. A stabilized current of the transistor Tia is also a current of the feedback current source IF, which forces a stable current flow into the gate of the first transistor Tva of the reference voltage output circuit VR.

[0110] The reference voltage output circuit VR uses the transistors Tva and Tvb to stabilize voltage between the drain and the source of the transistor Tvc operating in the non-saturated range of operation. This stabilization is achieved by limiting the voltage of the gate capacitance of the transistor Tva, which is charged by the current source IF. The stabilization mechanism results from the opposite nature of operation of the transistors Tva and Tvb. The gate of the transistor Tva is charged with the current from the current source IF, leading to an increase in the current of the source of the transistor Tva, and thus an increase in voltage between the drain and the source of the transistor Tvc. After exceeding the value of threshold voltage of the transistor Tvb by the drain-source voltage of the transistor Tvc, the current of the source IF no longer charges the gate capacitance of the transistor Tva, but is discharged by the drain of the transistor Tvb to the ground gnd voltage.

[0111] The drain-source voltage of the transistor Tvc is also the gate-source voltage of the transistor Tvb, which, together with the transistor Tva maintains the reference voltage at the output Vref at a stable level, near the Tvb threshold voltage. In this solution, the voltage at the reference voltage output Vref mainly depends on the parameters of the transistor Tvb, while the transistor Tvc acts only as a non-linear load that converts the gate-source voltage of the transistor Tvb to the drain current of the transistor Tvc, following its transfer characteristics.

[0112] The invention provides a reference voltage, which is constant and independent from the operation of the reference circuit of the digital blocks of the NFC RFID tag. The industrial application of the invention is in the industry and market for products requiring individual electronic markings.

Claims

Claims1. An RFID analog conditioner circuit (ANL) having an antenna input (RF 1 ) connected to the antenna input of a carrier frequency divider (FD16), to an antenna input of a demodulator (Dmd) and to a first antenna input of a harvester with modulator (HM), whose power output is connected to a power input of the carrier frequency divider (FD16), to a power input of the demodulator (Dmd) and to a reference voltage circuit (Vref), whose output is connected to a reference input of the demodulator (Dmd), whose output is connected to a demodulation output (o-Dmd) of the RFID analog conditioner circuit (ANL), as well as having a modulation input (i-Mod) connected to a modulation input of the harvester with modulator (HM), characterized in that comprises a voltage hold circuit (VH) and an initialization circuit (Int), whose inputs are connected to the power output of the harvester with modulator (HM), an output of the voltage hold circuit (VH) is connected to a holding output (o-VH) of the RFID analog conditioner circuit (ANL), and an output of the initialization circuit (Int) is connected to an initialization output (o-Int) of the RFID analog conditioner circuit (ANL).

2. The RFID analog conditioner circuit according to claim 1, characterized in that the reference voltage circuit (Vref) is connected to the demodulator (Dmd) via a ripple rejection circuit (RR), which has a power input connected to the power output of the harvester with modulator (HM).

3. The RFID analog conditioner circuit according to claim 1 or 2, characterized in that comprises a shunt regulator circuit (SR) connected to the power output of the harvester with modulator (HM).

4. The RFID analog conditioner circuit according to claim 1 or 2 or 3, characterized in that comprises a second antenna input (RF2) connected to a second antenna input of the harvester with modulator (HM).

5. The RFID analog conditioner circuit according to any of the claims from 1 to 4, characterized in that the second antenna input (RF2) is connected to a ground (gnd) of the RFID analog conditioner circuit (ANL).

6. The RFID analog conditioner circuit according to any of the claims from 1 to 5, characterized in that it operates substantially at a frequency of 13.56 MHz of the input signal.

7. The RFID analog conditioner circuit according to any of the claims from 1 to 6, characterized in that all transistors in the circuit are the FETs of "n" type.

8. The RFID analog conditioner circuit according to any of the claims from 1 to 7, characterized in that all transistors in the circuit are TFT-type transistors.

9. The RFID analog conditioner circuit according to any of the claims from 1 to 8, characterized in that the transistor channels are made of amorphous semiconductor material.

10. The RFID analog conditioner circuit according to any of the claims from 1 to 9, characterized in that the transistors contain indium-gallium zinc oxide.

11. The RFID analog conditioner circuit according to any of the claims from 1 to 10, characterized in that the voltage hold circuit (VH) contains a diode and a capacitor connected in series between the input and the ground of this circuit, and the output is connected to the connection point of the diode and the capacitor.

12. The RFID analog conditioner circuit according to claim 11, characterized in that the diode used in the voltage hold circuit (VH) is made of a transistor with its gate connected to its source and connected to the input of the circuit, and the drain of the transistor connected to the capacitor and the output of the circuit.

13. The RFID analog conditioner circuit according to claim 12, characterized in that the width-to-length ratio of transistor channel used to construct the diode in the voltage hold circuit (VH) ranges from 5 to 20.

14. The RFID analog conditioner circuit according to claim 11 or 12 or 13, characterized in that the capacitance of the capacitor used in the voltage hold circuit (VH) ranges from 5 pF to 20 pF.

15. The RFID analog conditioner circuit according to any of the claims from 2 to 14, characterized in that the ripple rejection circuit (RR) has its input and output connected inside the circuit and connected to the power input of the circuit via a resistor, and to the ground of the circuit via a capacitor or capacitors connected in parallel.

16. The RFID analog conditioner circuit according to claim 15, characterized in that the resistance of the resistor used in the ripple rejection circuit (RR) ranges from 2 M.Q to 5 MQ.

17. The RFID analog conditioner circuit according to claim 15 or 16, characterized in that the cumulative capacitance of capacitors used in the ripple rejection circuit (RR) ranges from 3 pF to 50 pF.

18. An RFID digital block initialization circuit having an initialization output (Int), characterized in that a first transistor (Tl) has the source connected to a circuit ground (gnd), the drain of the first transistor (Tl) is connected to the initialization output (Int), to a power supply input (HRV) via a first resistor (Rl), to the gate of a second transistor (T2), and to the drain of a third transistor (T3), while the gate of the first transistor (Tl) is connected to the drain of the second transistor (T2), and in that the source of the second transistor (T2) is connected to the circuit ground (gnd), while the drain of the second transistor (T2) is connected to the power supply input (HRV) via a second resistor (R2), and in that the source of the third transistor (T3) is connected to the circuit ground (gnd), while the gate of the third transistor (T3) is connected to the circuit ground (gnd) via a capacitor (Cr) and to the power supply input (HRV) via a third resistor (Rr).

19. The RFID digital block initialization circuit according to claim 18, characterized in that the width-to-length ratio of the channel of the first transistor (Tl) in relation to the width-to- length ratio of the channel of the second transistor (T2) is either significantly smaller or significantly larger.

20. The RFID digital block initialization circuit according to claim 18 or 19, characterized in that the value of the first resistor (Rl) in relation to the value of the second resistor (R2) is either significantly smaller or significantly larger.

21. The RFID digital block initialization circuit according to claim 18 or 19 or 20, characterized in that the gate of the first transistor (Tl) is connected to the circuit ground (gnd) via a second capacitor (C2).

22. The RFID digital block initialization circuit according to any of the claims from 18 to 21, characterized in that the gate of the third transistor (T3) is connected to the source and the gate of a fourth transistor (Tr), whose drain is connected to the power supply input (HRV).

23. The RFID digital block initialization circuit according to any of the claims from 18 to 22, characterized in that the power supply input (HRV) is connected directly to an output of an RFID harvester.

24. The RFID digital block initialization circuit according to any of the claims from 18 to 23, characterized in that all transistors in the circuit are the FETs of "n" type.

25. The RFID digital block initialization circuit according to any of the claims from 18 to 24, characterized in that all transistors in the circuit are TFT-type transistors.

26. The RFID digital block initialization circuit according to any of the claims from 18 to 25, characterized in that the transistor channels are made of amorphous semiconductor material.

27. The RFID digital block initialization circuit according to any of the claims from 18 to 26, characterized in that the transistors contain indium-gallium zinc oxide.

28. The RFID digital block initialization circuit according to any of the claims from 18 to 27, characterized in that the capacitance of the capacitor (Cr) ranges from 3 to 5 picofarads, while the value of the third resistor (Rr) ranges from 15 to 25 megaohms.

29. The RFID digital block initialization circuit according to any of the claims from 21 to 28, characterized in that the capacitance of the second capacitor (C2) ranges from 20 to 30 femtofarads, the value of the second resistor (R2) ranges from 5 to 15 megaohms, and the value of the first resistor (Rl) is substantially half of the value of the second resistor (R2), with the first two transistors (Tl, T2) being substantially of the same size.

30. An RFID voltage reference having a feedback current source (IF) comprising two coupled transistors in the way that the first transistor (Tia) is connected to the drain of the second transistor (Tib), and the gate of the second transistor (Tib) is connected to the source of the first transistor (Tia), while a resistor (Rif) is connected between the gate and the source of the second transistor (Tib), characterized in that a low-precision subthreshold current source (IT) is connected between the feedback current source (IF) and a power supply input (Vhrv), at least one additional feedback current source (IR) is connected between the feedback current source (IF) and a reference voltage output (Vref), while a current-voltage converter (VT) is connected between the reference voltage output (Vref) and a circuit ground (gnd).

31. The RFID voltage reference according to claim 30, characterized in that the low- precision subthreshold current source (IT) comprises a transistor (Tit), whose drain is connected to the power supply input (Vhrv) and whose gate is connected its source and to the drain of the second transistor (Tib) of the feedback current source (IF).

32. The RFID voltage reference according to claim 30 or 31, characterized in that an additional feedback current source (IR) comprises two coupled transistors in the way that thegate of the first transistor (Tra) is connected to the drain of the second transistor (Trb), and the gate of the second transistor (Trb) is connected to the source of the first transistor (Tra), while a resistor (Rr) is connected between the gate and the source of the second transistor (Trb), whereas the drain of the second transistor (Trb) is connected to the source of the second transistor (Tib) of the feedback current source (IF), the drain of the first transistor (Tra) is connected to the power supply input (Vhrv), and the source of the second transistor (Trb) is connected to the reference voltage output (Vref).

33. The RFID voltage reference according to claim 30 or 31 or 32, characterized in that the current-voltage converter (VT) comprises a transistor (Tvt), whose source is connected to the circuit ground (gnd), and whose gate is connected to its drain and to the reference voltage output (Vref).

34. The RFID voltage reference according to any of the claims from 30 to 33, characterized in that the first transistor (Tia) in the feedback current source (IF) is implemented as multiple transistors connected in parallel (Tial, Tia2).

35. The RFID voltage reference according to claim 34, characterized in that the number of transistors connected in parallel (Tial, Tia2) in the feedback current source (IF) in place of the first transistor (Tia) ranges from 2 to 4.

36. The RFID voltage reference according to any of the claims from 31 to 35, characterized in that the transistor (Tit) in the low-precision subthreshold current source (IT) is implemented as multiple transistors connected in parallel (Titl , Tit2).

37. The RFID voltage reference according to claim 36, characterized in that the number of parallelly connected transistors (Titl, Tit2) in the low-precision subthreshold current source (IT) ranges from 2 to 4.

38. The RFID voltage reference according to any of the claims from 32 to 37, characterized in that the transistors (Tra, Trb) in the additional feedback current source (IR) are implemented as multiple transistors connected in parallel (Tral, Tra2, Tra3, Tra4, Tra5), (Trbl, Trb2, Trb3, Trb4, Trb5).

39. The RFID voltage reference according to claim 38, characterized in that the numbers of parallelly connected transistors (Tral, Tra2, Tra3, Tra4, Tra5), (Trbl, Trb2, Trb3, Trb4, Trb5) in the additional feedback current source (IR) in the places of the transistors of this source (Tra, Trb) range from 3 to 12.

40. The RFID voltage reference according to any of the claims from 33 to 39, characterized in that the transistor (Tvt) in the current-voltage converter (VT) is implemented as multiple transistors connected in parallel (Tvtl, Tvt2, Tvt3).

41. The RFID voltage reference according to claim 40, characterized in that the number of parallelly connected transistors (Tvtl, Tvt2, Tvt3) in the current-voltage converter (VT) ranges from 2 to 4.

42. The RFID voltage reference according to any of the claims from 30 to 41, characterized in that the power supply input (HRV) is connected directly to an output of an RFID harvester, or indirectly via a ripple rejection circuit.

43. The RFID voltage reference according to any of the claims from 30 to 42, characterized in that all transistors in the circuit are the FETs of "n" type.

44. The RFID voltage reference according to any of the claims from 30 to 43, characterized in that all transistors in the circuit are TFT-type transistors.

45. The RFID voltage reference according to any of the claims from 30 to 44, characterized in that the transistor channels are made of amorphous semiconductor material.

46. The RFID voltage reference according to any of the claims from 30 to 45, characterized in that the transistors contain indium-gallium zinc oxide.

47. The RFID voltage reference according to any of the claims from 30 to 46, characterized in that the width-to-length ratio of the channel of the second transistor (Tib) in the feedback current source (IF) ranges from 1 to 2, and the resistance value of the resistor (Rif) in this source (IF) ranges from 1.5 to 2.5 megaohms.

48. The RFID voltage reference according to any of the claims from 31 to 47, characterized in that the width-to-length ratio of the channel of the transistor (Tit) of the low-precision subthreshold current source (IT) ranges from 2 to 3.

49. The RFID voltage reference according to any of the claims from 32 to 48, characterized in that the resistance value of the resistor (Rr) in the additional feedback current source (IR) ranges from 100 to 150 kiloohms.

50. An RFID voltage reference having a feedback current source (IF) comprising two coupled transistors in the way that the first transistor (Tia) is connected to the drain of the second transistor (Tib), and the gate of the second transistor (Tib) is connected to the source of the first transistor (Tia), while a resistor (Rif) is connected between the gate and the source of the second transistor (Tib), characterized in that a low-precision subthreshold current source (IT) is connected between the feedback current source (IF) and a power supply input (Vhrv), and in that between the feedback current source (IF) and a circuit ground (gnd) a reference voltage output circuit (VR) is connected, from which reference voltage output (Vref) is derived.

51. The RFID voltage reference according to claim 50, characterized in that the low- precision subthreshold current source (IT) comprises a transistor (Tit), whose drain is connected to the power supply input (Vhrv), and whose gate is connected to its source and to the drain of the second transistor (Tib) of the feedback current source (IF).

52. The RFID voltage reference according to claim 50 or 51, characterized in that the reference voltage output circuit (VR) comprises two coupled transistors in the way that the gate of the first transistor (Tva) is connected to the drain of the second transistor (Tvb), and the gate of the second transistor (Tvb) is connected to the source of the first transistor (Tva), and in that comprises a third transistor (Tvc) connected between the source of the first transistor (Tva) and the circuit ground, whereas the gate of the third transistor (Tvc) is connected to its drain, to the source of the first transistor (Tva) and to the reference voltage output (Vref), the drain of the second transistor (Tvb) is connected to the source of the second transistor (Tib) of the feedback current source (IF), the drain of the first transistor (Tva) is connected to the power supply input (Vhrv), while the source of the second transistor (Tvb) is connected to the circuit ground (gnd).

53. The RFID voltage reference according to claim 50 or 51 or 52, characterized in that the first transistor (Tia) in the feedback current source (IF) is implemented as multiple transistors connected in parallel (Tial, Tia2).

54. The RFID voltage reference according to claim 53, characterized in that the number of parallelly connected transistors (Tial, Tia2) in the feedback current source (IF) in place of the first transistor (Tia) ranges from 2 to 4.

55. The RFID voltage reference according to any of the claims from 51 to 54, characterized in that the transistor (Tit) in the low-precision subthreshold current source (IT) is implemented as multiple transistors connected in parallel (Titl , Tit2).

56. The RFID voltage reference according to claim 55, characterized in that the number of parallelly connected transistors (Titl, Tit2) in the low-precision subthreshold current source (IT) ranges from 2 to 4.

57. The RFID voltage reference according to any of the claims from 52 to 56, characterized in that the transistors (Tva, Tvb, Tvc) in the reference voltage output circuit (VR) are implemented as multiple transistors connected in parallel (Tval, Tva2, Tva3, Tva4, Tva5), (Tvbl, Tvb2, Tvb3, Tvb4, Tvb5), (Tvcl, Tvc2, Tvc3).

58. The RFID voltage reference according to claim 57, characterized in that the numbers of parallelly connected transistors (Tval, Tva2, Tva3, Tva4, Tva5), (Tvbl, Tvb2, Tvb3, Tvb4, Tvb5) in the reference voltage output circuit (VR), in the places of the first two transistors of this circuit (Tva, Tvb) range from 3 to 12, and the number of parallelly connected transistors (Tvcl, Tvc2, Tvc3) in the reference voltage output circuit (VR) in place of the third transistor of this circuit (Tvc) ranges from 2 to 4.

59. The RFID voltage reference according to any of the claims from 50 to 58, characterized in that the power supply input (HRV) is connected directly to an output of an RFID harvester, or indirectly via a ripple rejection circuit.

60. The RFID voltage reference according to any of the claims from 50 to 59, characterized in that all transistors in the circuit are the FETs of "n" type.

61. The RFID voltage reference according to any of the claims from 50 to 60, characterized in that all transistors in the circuit are TFT-type transistors.

62. The RFID voltage reference according to any of the claims from 50 to 61, characterized in that the transistor channels are made of amorphous semiconductor material.

63. The RFID voltage reference according to any of the claims from 50 to 62, characterized in that the transistors contain indium-gallium zinc oxide.

64. The RFID voltage reference according to any of the claims from 50 to 63, characterized in that the width-to-length ratio of the channel of the second transistor (Tib) in the feedback current source (IF) ranges from 1 to 2, and the resistance value of the resistor (Rif) in this source (IF) ranges from 1.5 to 2.5 megaohms.

65. The RFID voltage reference according to any of the claims from 51 to 64, characterized in that the width-to-length ratio of the channel of the transistor (Tit) of the low-precision subthreshold current source (IT) ranges from 2 to 3.

Images