Semiconductor apparatus and method for manufacturing semiconductor apparatus

Abstract

The present invention provides a semiconductor device including a first semiconductor element and a second semiconductor element on a substrate. The first semiconductor element includes: a first laminate in which a Si layer and a SiGe layer are laminated; a first source / drain region formed on side surfaces of the first laminate in the gate length direction; a first gate electrode formed on the upper side and side surfaces in the gate width direction of the first laminate via a first gate insulation film; and insulation film regions formed between the SiGe layer and the first source / drain regions.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002] In a semiconductor device having a nanosheet FET (Field Effect Transistor), an input / output transistor (TFT) for an input / output device is required near a logic device using the nanosheet FET. The input / output transistor needs to operate at a voltage higher than that of the nanosheet FET that constitutes the logic device. For this reason, if an input / output transistor is to be formed using a nanosheet FET, the gate insulating film must be thicker than conventional ones. However, with conventional methods for manufacturing nanosheet FETs, it is difficult to form a gate insulating film thick enough to withstand high voltages.

[0003] As a method for manufacturing a thick gate insulating film compatible with the manufacturing method of nanosheet FETs, a semiconductor device has been proposed in which an element capable of withstanding high-voltage operation due to a special FinFET (FinFET) structure is formed on the same wafer as the nanosheet FET (see Patent Document 1). In this semiconductor device, the EG-FET (Extended Gate Field Effect Transistor) serving as the input / output transistor is composed of a FinFET processed with a laminated structure of Si and SiGe. The SG-FET (Suspended Gate Field Effect Transistor) for the logic device is formed of a conventional nanosheet FET (NS-FET). Because the input / output transistor has a FinFET shape, this structure allows for the application of a thick gate insulating film independently of the gate insulating film for the logic device. As a result, this semiconductor device can ensure the required current characteristics even at high gate voltages.

[0004] US Patent Application Publication No. 2023 / 0178547

[0005] However, in the semiconductor device described in Patent Document 1, both the Si and SiGe layers stacked below the gate electrode contact the source and drain regions. In this structure, when a gate voltage (Vg) is applied to the pFET, the FET in the SiGe layer region, which has a smaller bandgap, turns on first, forming an inversion layer in the SiGe layer, which has a smaller |Vth|. As a result, when the gate voltage (Vg) increases further and the FET in the Si layer region turns on, a characteristic bend (hump) occurs in the Id-Vg characteristic, which deviates from a smooth curve. Having such an Id-Vg characteristic can potentially reduce the reliability of the semiconductor device.

[0006] In order to solve the above-mentioned problems, the present invention provides a semiconductor device and a method for manufacturing the semiconductor device that can suppress a decrease in reliability.

[0007] The semiconductor device of the present invention includes a first semiconductor element and a second semiconductor element on a substrate. The first semiconductor element includes a first stacked body including a Si layer and a SiGe layer, first source / drain regions formed on side surfaces of the first stacked body in the gate length direction, a first gate electrode formed above the first stacked body and on side surfaces of the first stacked body in the gate width direction via a first gate insulating film, and an insulating film region formed between the SiGe layer and the first source / drain regions. The second semiconductor element includes a second stacked body including a Si layer and a second gate electrode, and second source / drain regions formed on side surfaces of the second stacked body in the gate length direction. The second gate electrode is formed between the Si layers and above the second stacked body via a second gate insulating film.

[0008] The present invention also provides a semiconductor device having a configuration in which a first semiconductor device including a first semiconductor element and a second semiconductor element are stacked on a first substrate, and a second semiconductor device including a third semiconductor element and a fourth semiconductor element are stacked on a second substrate. The first semiconductor element and the third semiconductor element each include a first stacked body including a Si layer and a SiGe layer, first source / drain regions formed on side surfaces of the first stacked body in the gate length direction, a first gate electrode formed above the first stacked body and on side surfaces of the first stacked body in the gate width direction with a first gate insulating film interposed therebetween, and an insulating film region formed between the SiGe layer and the first source / drain regions. The second semiconductor element and the fourth semiconductor element each include a second stacked body including a Si layer and a second gate electrode stacked with a gate insulating film interposed therebetween, and second source / drain regions formed on side surfaces of the second stacked body in the gate length direction. The second gate electrode is formed between the Si layers and above the second stacked body via a second gate insulating film.

[0009] a step of selectively etching the SiGe layer exposed on the side surfaces of the first stack and the second stack in the gate length direction to form recesses on the side surfaces of the SiGe layer relative to the side surfaces of the Si layer; a step of forming an insulating film region in the recesses; a step of forming first source / drain regions on the side surfaces of the first stack in the gate length direction and second source / drain regions on the side surfaces of the second stack in the gate length direction; a step of forming a first gate insulating film and a first gate electrode above the first stack and on the side surfaces of the first stack in the gate width direction; a step of selectively removing the SiGe layer from the second stack; and a step of forming a second gate insulating film and a second gate electrode between the Si layers of the second stack and above the second stack.

[0010] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress a decrease in reliability.

[0011] 5 is a diagram illustrating a schematic configuration of a conventional semiconductor device; FIG. 6 is an equivalent circuit diagram of the conventional semiconductor device; FIG. 7 is a diagram illustrating Id-Vg characteristics when the conventional semiconductor device is a pFET; FIG. 8 is a diagram illustrating Id-Vg characteristics when the conventional semiconductor device is an nFET; FIG. 9 is a diagram (plan view) illustrating a schematic configuration of a semiconductor device of a first embodiment; FIG. 10 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 5; FIG. 11 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 10; FIG. 11 is an equivalent circuit diagram of the semiconductor device of the first embodiment; FIG. 12 is a diagram illustrating Id-Vg characteristics when the semiconductor device of the first embodiment is a pFET; FIG. 13 is a diagram illustrating Id-Vg characteristics when the semiconductor device of the first embodiment is an nFET; FIG. 14 is a diagram illustrating a manufacturing process of the semiconductor device of the first embodiment; FIG. 15 is a diagram illustrating a manufacturing process of the semiconductor device of the first embodiment; FIG. 16 is a diagram illustrating a manufacturing process of the semiconductor device of the first embodiment; 1 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 2 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 3 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 4 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 5 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 6 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 7 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 8 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 9 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 10 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 11 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 12 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 13 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 14 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment;1 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; FIG. 2 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; FIG. 3 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; FIG. 4 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; FIG. 5 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; FIG. 6 is a diagram for explaining a configuration of the semiconductor device of the second embodiment; FIG. 7 is a diagram for explaining a configuration of the semiconductor device of the second embodiment; FIG. 8 is a diagram for explaining a configuration of the semiconductor device of the third embodiment; FIG. 9 is a diagram for explaining a configuration of the semiconductor device of the third embodiment; FIG. 10 is a diagram for explaining a configuration of the semiconductor device of the fourth embodiment; FIG. 11 is a diagram for explaining a configuration of the semiconductor device of the fourth embodiment; FIG. 12 is a diagram for explaining a configuration of the semiconductor device of the fifth embodiment; FIG. 13 is a diagram for explaining a configuration of the semiconductor device of the fifth embodiment;

[0012] Hereinafter, examples of embodiments for carrying out the present invention will be described, but the present invention is not limited to the following examples. The description will be given in the following order: 1. Overview of a semiconductor device with a conventional configuration 2. First embodiment of the semiconductor device 3. Manufacturing method of the semiconductor device 4. Other embodiments of the semiconductor device

[0013] 1. Overview of a semiconductor device with a conventional configuration [Configuration of a conventional semiconductor device] As a conventional semiconductor device, the configuration and problems of the semiconductor device described in the above-mentioned Patent Document 1 will be mainly described. The configuration of the conventional semiconductor device is shown in Fig. 1. Note that Fig. 1 only shows a cross-sectional view of the semiconductor device in the gate length direction.

[0014] The semiconductor device shown in FIG. 1 includes an EG-FET (Extended Gate Field Effect Transistor) serving as an input / output device and an SG-FET (Suspended Gate Field Effect Transistor) for a logic device, both of which are formed on a substrate 305. The EG-FET and SG-FET are formed adjacent to each other on the substrate 305 via an STI (Shallow Trench Isolation) 310. The EG-FET serving as an input / output device is composed of a FinFET having a processed laminated structure of Si and SiGe. The SG-FET (Suspended Gate Field Effect Transistor) for a logic device is formed of a normal nanosheet FET (NS-FET).

[0015] The EG-FET serving as an input / output device includes a nanosheet laminate for an EG pillar formed by stacking Si and SiGe nanosheets, source / drain regions 390a, 390c formed on both sides of the nanosheet laminate, an EG gate insulating film 325a formed on the nanosheet laminate, an EG gate electrode 335a formed on the EG gate insulating film 325a, and sidewall spacers 330c, 330e formed on the EG gate insulating film 325a and around the EG gate electrode 335a. Furthermore, each nanosheet layer constituting the nanosheet laminate and the source / drain regions 390a, 390c are formed on a first dielectric layer 330a. The nanosheet laminate for the EG pillar includes a first barrier layer 340a, a first semiconductor layer 350a, a third barrier layer 340c, a third semiconductor layer 360a, a fifth barrier layer 340e, a fifth semiconductor layer 350c, a seventh barrier layer 340g, a seventh semiconductor layer 360c, a ninth barrier layer 340i, a ninth semiconductor layer 350e, an eleventh barrier layer 340k, and an eleventh semiconductor layer 360e stacked together. Here, the nanosheet layers, the third semiconductor layer 360a, the seventh semiconductor layer 360c, and the eleventh semiconductor layer 360e, are formed of Si nanosheet layers. Furthermore, the first semiconductor layer 350a, the fifth semiconductor layer 350c, and the ninth semiconductor layer 350e are formed of SiGe nanosheet layers. These semiconductor layers are stacked with a third barrier layer 340c, a fifth barrier layer 340e, a seventh barrier layer 340g, a ninth barrier layer 340i, and an eleventh barrier layer 340k interposed therebetween.

[0016] The SG-FET logic device includes an SG pillar formed by stacking a Si nanosheet layer and a metal electrode, source / drain regions 390b, 390d formed on both sides of the nanosheet layer, an SG gate insulating film 325b formed on the SG pillar, an SG gate electrode 335b formed on the SG gate insulating film 325b, and sidewall spacers 330d, 330f formed around the SG gate insulating film 325b and the SG gate electrode 335b thereon. The nanosheet layers, metal electrodes, and source / drain regions 390b, 390d constituting the SG pillar are formed on a second dielectric layer 330b. The SG pillar includes a stack of a first metal electrode 335e, a second semiconductor layer 360b, a second metal electrode 335d, a fourth semiconductor layer 360d, a third metal electrode 335c, and a sixth semiconductor layer 360f. The first metal electrode 335e is surrounded by inner spacers 315a and 315b and interfacial layers (IL) 325g and 325h. The second metal electrode 335d is surrounded by inner spacers 315c and 315d and interfacial layers 325e and 325f. The third metal electrode 335c is surrounded by inner spacers 315e and 315f and interfacial layers 325c and 325d.

[0017] [Equivalent Circuit Diagram of Conventional Input / Output Device] In the semiconductor device having the above configuration, the EG-FET serving as the input / output device has an eleventh semiconductor layer 360e made of a Si nanosheet layer formed directly below the EG gate electrode 335a, and a ninth semiconductor layer 350e made of a SiGe nanosheet layer, both of which are in contact with source / drain regions 390a, 390c. Therefore, an equivalent circuit of the EG gate electrode 335a, the eleventh semiconductor layer 360e, the ninth semiconductor layer 350e, and the source / drain regions 390a, 390c in the EG-FET can be shown as in FIG.

[0018] 2, Tr_1 is an eleventh semiconductor layer 360e made of a Si nanosheet layer, and Tr_2 is a ninth semiconductor layer 350e made of a SiGe nanosheet layer. The source / drain regions 390a, 390c of Tr_1 are R1_s and R1_d, and the source / drain regions 390a, 390c of Tr_2 are R2_s and R2_d. The gate threshold voltage (Vth) of the eleventh semiconductor layer 360e (Tr_1) made of a Si nanosheet layer is |Vth_1|, and the gate threshold voltage (Vth) of the ninth semiconductor layer 350e (Tr_2) made of a SiGe nanosheet layer is |Vth_2|.

[0019] When the EG-FET is a p-channel FET (pFET), it is known that, assuming the same gate insulating film thickness, [|Vth_2|<|Vth_1|] due to the difference in band gap between Si and SiGe. For this reason, in the equivalent circuit of the EG-FET shown in Figure 2, Tr_1 and Tr_2, which have different gate threshold voltages (Vth), are connected in parallel.

[0020] [Id-Vg Characteristics of a Conventional Semiconductor Device] Figure 3 shows the Id-Vg characteristics when the EG-FET is a pFET. In the Id-Vg characteristics shown in Figure 3, when a gate voltage (Vg) is applied and the gate voltage exceeds |Vth_2|, the FET Tr_2, which is made of a SiGe layer region with a low gate threshold voltage, turns on, and current flows only through Tr_2. This state continues in the region where the gate voltage is [|Vth_2| < Vg < |Vth_1|]. Then, when the gate voltage exceeds |Vth_1|, the FET Tr_1, which is made of a Si layer region with a high gate threshold voltage, turns on, and current also flows through Tr_1. Therefore, when the gate voltage is less than |Vth_1|, the pFET EG-FET exhibits Id-Vg characteristics due to Tr_2 alone. However, when the gate voltage exceeds |Vth_1|, it exhibits Id-Vg characteristics due to the combined Id-Vg characteristics of Tr_1 and Tr_2. For this reason, a steep change occurs in the Id-Vg characteristics at the boundary of |Vth_1|, and a characteristic bend (hump) occurs in the Id-Vg characteristics curve. If such a characteristic hump occurs in the Id-Vg characteristics, there is a possibility that a malfunction will occur in a circuit that performs a specific operation, and there is a possibility that the reliability of the semiconductor device will decrease.

[0021] When the EG-FET is an n-channel FET (nFET), it is known that |Vth_1| of Tr_1 and |Vth_2| of Tr_2 are almost the same. Therefore, in the equivalent circuit of the EG-FET shown in FIG. 2, Tr_1 and Tr_2, which have almost the same gate threshold voltage (Vth), are connected in parallel. The Id-Vg characteristics when the EG-FET is an nFET are shown in FIG. 4. In the Id-Vg characteristics shown in FIG. 4, in the region [|Vth_2| to |Vth_1| < Vg], the FET channels are in the off state in both Tr_1 and Tr_2. Therefore, in this region, no on-current flows through the entire EG-FET. On the other hand, in the region [|Vth_2| to |Vth_1| ≦ Vg], the nFET is inverted almost simultaneously in both the channel of the SiGe layer of Tr_2 and the channel of the Si layer of Tr_1. Therefore, when the EG-FET is an nFET, no hump occurs.

[0022] 2. First Embodiment of Semiconductor Device A specific embodiment of the semiconductor device of the present invention will now be described. Schematic configuration diagrams of a semiconductor device according to a first embodiment are shown in Fig. 5, Fig. 6, and Fig. 7. [Configuration of Semiconductor Device] Fig. 5 is a plan view (top view) of the semiconductor device. Fig. 6 is a cross-sectional view of the semiconductor device shown in Fig. 5 taken along line A-A (cross-sectional view in the gate length direction). Fig. 7 is a cross-sectional view of the semiconductor device shown in Fig. 5 taken along line B-B (cross-sectional view in the gate width direction).

[0023] The semiconductor device 10 shown in Figure 5 includes a first semiconductor element 100 and a second semiconductor element 200 on a substrate 11. The first semiconductor element 100 is an input / output transistor (I / O transistor) that serves as an I / O device. The first semiconductor element 100 that serves as an I / O device is composed of a FinFET having a processed laminated structure of Si and SiGe. The second semiconductor element 200 is a nanosheet FET that serves as a logic device.

[0024] 5, the first semiconductor element 100 includes a gate electrode 112 (first gate electrode), a source region 108, and a drain region 109 (first source / drain region) formed on a substrate 11. The second semiconductor element 200 includes a gate electrode 212 (second gate electrode) formed on the substrate 11, and a source region 208 and a drain region 209 (second source / drain region).

[0025] 5, the first semiconductor element 100 has a larger gate length than the second semiconductor element 200. Because the first semiconductor element 100 is an input / output transistor for an input / output device, a higher voltage is applied to the gate electrode 112 than to the second semiconductor element 200. For this reason, it is preferable that the first semiconductor element 100 have a larger gate length than the second semiconductor element 200 in order to suppress a through current, or so-called punch-through, between the source region 108 and the drain region 109. On the other hand, it is preferable that the second semiconductor element 200, which will be a logic device, has a shorter gate length in order to improve switching speed.

[0026] 6 and 7 , the first semiconductor element 100 is a FinFET formed by a first stack of Si layers 101, 102, 103, and 104 and SiGe layers 105, 106, and 107. The second semiconductor element 200 is a Gate All Around (GAA) FET formed by a second stack of Si layers 201, 202, 203, and 204 and gate electrodes 205, 206, and 207. The Si layers 101, 102, 103, and 104 of the first semiconductor element 100 and the Si layers 201, 202, 203, and 204 of the second semiconductor element 200 are both formed by nanosheet layers. The first semiconductor element 100 and the second semiconductor element 200 are mounted on a substrate 11, and their entire surfaces are sealed by an insulating layer 18.

[0027] The first semiconductor element 100 has a bottom Si layer 101 on a PTS (punch through stopper) layer 13 formed on the top layer of a substrate 11. The first semiconductor element 100 has a first stacked body having a stacked structure including the Si layer 101, that is, Si layer 101 / SiGe layer 105 / Si layer 102 / SiGe layer 106 / Si layer 103 / SiGe layer 107 / Si layer 104.

[0028] 6 , the first semiconductor element 100 includes a source region 108 and a drain region 109 on the side surfaces of a first stack of Si layers 101, 102, 103, and 104 and SiGe layers 105, 106, and 107. The Si layers 101, 102, 103, and 104 are connected to the source region 108 and the drain region 109. Inner spacers 110 (first inner spacers) made of insulating film regions are formed between the SiGe layers 105, 106, and 107 and the source region 108 and the drain region 109. Therefore, the side surfaces of the SiGe layers 105, 106, and 107 are recessed toward the center of the first semiconductor element 100 relative to the Si layers 101, 102, 103, and 104 by the amount of the inner spacers 110. The side surfaces of the SiGe layers 105, 106, and 107 are not directly connected to the source region 108 and the drain region 109. The first semiconductor element 100 shown in FIG. 6 has inner spacers 110 formed between the SiGe layers 105, 106, and 107 and both the source region 108 and the drain region 109. However, the first semiconductor element 100 only needs to have the inner spacers 110 formed between the SiGe layers 105, 106, and 107 and either the source region 108 or the drain region 109. Forming the inner spacer 110 in at least one of these regions can suppress direct carrier movement between the SiGe layers 105, 106, and 107 and the source region 108 or the drain region 109. Therefore, even when a gate voltage is applied to the first semiconductor element 100 and channels are formed in the SiGe layers 105, 106, and 107, movement of carriers between the source region 108 and the drain region 109 can be suppressed.

[0029] 6 , the first semiconductor element 100 includes a gate insulating film 111 (first gate insulating film) and an insulating film 117 thinner than the gate insulating film 111 above the uppermost Si layer 104. The gate insulating film 111 is formed in the center of the Si layer 104, and the insulating film 117 is formed around the gate insulating film 111. The gate insulating film 111 is thicker than the insulating film 117 and a gate insulating film 211 (second gate insulating film) of the second semiconductor element 200 (described later). This ensures that the gate insulating film 111 has a thickness sufficient to withstand high voltages in the first semiconductor element 100, which is an input / output transistor of an input / output device.

[0030] A gate electrode 112 is formed on the gate insulating film 111. Sidewalls 116 of the gate electrode 112 are formed on the insulating film 117. The gate electrode 112 is formed of a high-dielectric constant (high-k) material layer 113, a first metal layer 114, and a second metal layer 115. The bottom and side surfaces of the gate electrode 112, i.e., the contact surfaces with the gate insulating film 111 and the sidewalls 116, are covered with a thin high-dielectric constant material layer 113. The first metal layer 114 is filled inside the high-dielectric constant material layer 113, and the second metal layer 115 is further filled in the central upper part of the first metal layer 114. An insulating layer 12 is formed on the side surfaces of the sidewalls 116 and on the side surfaces of the source region 108 and the drain region 109. The insulating layer 12 covers the side surfaces of the first semiconductor element 100, the side surfaces of the second semiconductor element 200, and the top surface of the substrate 11.

[0031] 6, the second semiconductor element 200 has a lowermost Si layer 201 on a PTS layer 13 formed on the uppermost layer of a substrate 11. The second semiconductor element 200 also has a second stacked body having a stacked structure including the Si layer 201, that is, [Si layer 201 / gate electrode 205 / Si layer 202 / gate electrode 206 / Si layer 203 / gate electrode 207 / Si layer 204].

[0032] 6 , the second semiconductor element 200 includes a gate insulating film 211 and an insulating film 217 above the uppermost Si layer 204. The gate insulating film 211 is formed in the center of the Si layer 204, and the insulating film 217 is formed around the gate insulating film 211. The gate insulating film 211 is formed thinner than the gate insulating film 111 of the first semiconductor element 100. A gate electrode 212 is formed on the gate insulating film 211. Sidewalls 216 of the gate electrode 212 are formed on the insulating film 217. The gate electrode 212 is formed of a high-dielectric-constant material layer 213, a first metal layer 214, and a second metal layer 215. The gate electrode 212 includes a thin high-dielectric-constant material layer 213 covering its bottom and side surfaces, i.e., the contact surfaces between the gate insulating film 211 and the sidewalls 216. A first metal layer 214 is filled in the high-dielectric-constant material layer 213 , and a second metal layer 215 is further filled in the central upper portion of the first metal layer 214 .

[0033] A gate insulating film 211 is formed between the gate electrodes 205, 206, and 207 and the Si layers 201, 202, 203, and 204. The gate insulating film 211 is formed only between the gate electrodes 205, 206, and 207 and the Si layers 201, 202, 203, and 204. The second semiconductor element 200 includes a source region 208 and a drain region 209 on the side surfaces of a second stack of the Si layers 201, 202, 203, and 204 and the gate electrodes 205, 206, and 207. The Si layers 201, 202, 203, and 204 are connected to the source region 208 and the drain region 209. An inner spacer 210 (second inner spacer) made of an insulating film region is formed between the gate electrodes 205, 206, and 207 and the source region 208 and the drain region 209. Therefore, the gate electrodes 205, 206, and 207 are not directly connected to the source region 208 and the drain region 209. In addition, an inner spacer 210 made of an insulating film region is also formed between the gate insulating film 211 and the source region 208 and the drain region 209.

[0034] Furthermore, gate electrodes 205, 206, and 207 formed between the Si layers 201, 202, 203, and 204 are formed of a high-dielectric-constant material layer 213 and a first metal layer 214. The high-dielectric-constant material layer 213 covers the contact surfaces between the gate electrodes 205, 206, and 207 and the gate insulating film 211 and inner spacer 210. The first metal layer 214 is filled inside the high-dielectric-constant material layer 213. The first metal layer 214 is formed continuously with the gate electrodes 205, 206, and 207 and the gate electrode 212 (see FIG. 7 ). Therefore, in the cross-sectional view in the gate length direction shown in FIG. 6 , the Si layers 202, 203, and 204, except for the bottommost Si layer 201, are surrounded by the gate electrodes 205, 206, 207, and the gate electrode 212. Gate electrodes 205, 206, 207 and gate electrode 212 are formed between the Si layers 201, 202, 203, and 204 and above the second stacked body, with a gate insulating film 211 interposed therebetween. That is, in the second semiconductor element 200, the entire cross section in the gate length direction of the Si layers 202, 203, and 204, which form channel portions, is surrounded by the gate electrodes 205, 206, 207, and 212. An insulating layer 12 is formed on the side surfaces of the sidewall 216 and on the side surfaces of the source region 208 and the drain region 209. The insulating layer 12 is continuously formed from the side surface of the first semiconductor element 100 to the side surface of the second semiconductor element 200, via the upper surface of the substrate 11.

[0035] 7 , an STI (Shallow Trench Isolation) 14 is formed as an element isolation region on the surface of a substrate 11. The STI 14 is composed of an insulating film 15 buried in the substrate 11, an insulating film 16 formed on the insulating film 15, and an insulating layer 17 buried on the insulating film 16. The STI 14 is formed between a first semiconductor element 100 and a second semiconductor element 200. The STI 14 is formed in an area other than the area where the first stack of Si layers 101, 102, 103, and 104 and SiGe layers 105, 106, and 107 of the first semiconductor element 100 and the Si layers 201, 202, 203, and 204 of the second semiconductor element 200 are formed.

[0036] In the cross-sectional view in the gate width direction shown in FIG. 7 , the first semiconductor element 100 has a gate insulating film 111 covering the side and top surfaces of a stacked structure of Si layers 101, 102, 103, and 104 and SiGe layers 105, 106, and 107. In the cross-sectional view in the gate width direction, the side surfaces of the Si layers 101, 102, 103, and 104 and the SiGe layers 105, 106, and 107 are formed flush with each other without any interlayer steps. Also, in the cross-sectional view in the gate width direction, the first semiconductor element 100 has a gate electrode 112 and a high-dielectric-constant material layer 113 covering the side and top surfaces of the gate insulating film 111. The thin high-dielectric-constant material layer 113 covers the contact surfaces between the gate electrode 112 and the gate insulating film 111, the STI 14, and the insulating layer 12. A first metal layer 114 is filled inside the high-dielectric-constant material layer 113 , and a second metal layer 115 is further filled above the center of the first metal layer 114 .

[0037] 7, the second semiconductor element 200 has a lowermost Si layer 201 on the PTS layer 13 formed on the uppermost layer of the substrate 11. The top and side surfaces of the Si layer 201 are covered with a gate insulating film 211. Furthermore, in the cross-sectional view in the gate width direction shown in FIG. 7, the second semiconductor element 200 has Si layers 202, 203, and 204 stacked above the Si layer 201, with a high-dielectric-constant material layer 213 and a first metal layer 214 constituting a gate electrode 212 interposed therebetween. The Si layers 202, 203, and 204 are each covered at their peripheries by a gate insulating film 211. The periphery of the gate insulating film 211 is covered with a high-dielectric-constant material layer 213. The high-dielectric-constant material layer 213 covers the entire contact surface between the gate insulating film 211 and the gate electrode 212, as well as the side and bottom surfaces of the gate electrode 212. A first metal layer 214 is filled inside the high-dielectric-constant material layer 213 , and a second metal layer 215 is further filled above the center of the first metal layer 214 .

[0038] [Equivalent Circuit Diagram of Semiconductor Device] Next, FIG. 8 shows an equivalent circuit diagram of the first semiconductor element 100, which serves as an input / output device in the semiconductor device 10 shown in FIGS. 5-7 described above. As shown in FIG. 6, in the first semiconductor element 100, the Si layer 104 made of a nanosheet layer formed directly below the gate electrode 112 is in contact with the source region 108 and the drain region 109. In contrast, the SiGe layer 107 formed directly below the gate electrode 112 is not in contact with the source region 108 and the drain region 109 due to the interposition of the inner spacer 110. Therefore, the equivalent circuit of the gate electrode 112, Si layer 104, SiGe layer 107, source region 108, and drain region 109 in the first semiconductor element 100 can be shown as in FIG. 8.

[0039] 8, Tr_1 is a FET including a Si layer 104. Tr_2 is a FET including a SiGe layer 107. R1_s is a source region 108, and R1_d is a drain region 109. The gate threshold voltage (Vth) of the FET (Tr_1) including the Si layer 104 is |Vth_1|, and the gate threshold voltage (Vth) of the FET (Tr_2) including the SiGe layer 107 is |Vth_2|.

[0040] As shown in FIG. 6 , the SiGe layer 107 is not in contact with the source region 108 and the drain region 109. Therefore, in the equivalent circuit shown in FIG. 8 , Tr_2 is not directly connected to R1_s and R1_d. As shown in FIG. 6 , the SiGe layer 107 is connected to the source region 108 and the drain region 109 via an inversion layer formed in the Si layer 104. Therefore, in the equivalent circuit shown in FIG. 8 , the source / drain of Tr_2 is connected to the inside of the source / drain of Tr_1 (under the gate electrode) and is connected to R1_s and R1_d via the source / drain of Tr_1. In this way, unlike the conventional EG-FET shown in FIG. 2 in which Tr_1 and Tr_2 are connected in parallel, the first semiconductor element 100 does not directly contact the source / drain of Tr_1 and Tr_2. Therefore, in the first semiconductor element 100, an inversion layer is formed in Tr_1, and then Tr_2 is connected to the source / drain region.

[0041] [Id-Vg Characteristics of Semiconductor Device] FIG. 9 shows the Id-Vg characteristics when the first semiconductor element 100 is a pFET. In the Id-Vg characteristics shown in FIG. 9, when a gate voltage (Vg) is applied and the gate voltage exceeds |Vth_2|, an inversion layer is formed in the SiGe layer 107. However, no inversion layer is formed in the Si layer 104, and the channel of Tr_1 remains in an off state. Therefore, even if an inversion layer is formed in the SiGe layer 107, Tr_2 does not turn on as a parasitic transistor, and no current flows through Tr_2. As a result, it can be considered that no on-current flows overall in the first semiconductor element 100.

[0042] When the gate voltage exceeds |Vth_1|, an inversion layer is formed in the Si layer 104, which has a high gate threshold voltage, the FET of Tr_1 is turned on, and a current also flows through Tr_1. At this time, since Tr_2 (SiGe layer 107) is disposed in contact with Tr_1 (Si layer 104), when the channel of Tr_1 is turned on, carriers gradually flow into Tr_2, which has already been inverted and has formed a channel.

[0043] Therefore, the first semiconductor element 100 of the pFET exhibits Id-Vg characteristics dependent on Tr_1 even when the gate voltage is less than |Vth_2|. Furthermore, when the gate voltage exceeds |Vth_2|, the Id-Vg characteristics are affected by the inversion layer formed in the SiGe layer 107. However, since Tr_1 is in the off state, no current flows through the first semiconductor element 100, and the Id-Vg characteristics remain a smooth curve. Furthermore, when the gate voltage exceeds |Vth_1|, Tr_1 is turned on, and carriers are injected into the parallel SiGe layer 107, which functions as a channel. Therefore, the first semiconductor element 100 of the pFET has a lower overall channel resistance than Tr_1 alone, and a larger current can be obtained. As a result, the first semiconductor element 100 of the pFET exhibits an Id characteristic without the characteristic bend (hump) in the Id-Vg characteristic curve.

[0044] Also, the Id-Vg characteristics when the first semiconductor element 100 is an nFET are shown in FIG. 10. In the Id-Vg characteristics shown in FIG. 10, in the region where [|Vth_2| to |Vth_1| > Vg], the channels of the FETs are in the off state in both Tr_1 and Tr_2. Therefore, in this region, no on-current flows through the entire EG-FET. On the other hand, when it becomes the region where [|Vth_2| to |Vth_1| ≤ Vg], the nFETs invert almost simultaneously in both the channel of the SiGe layer of Tr_2 and the channel of the Si layer of Tr_1. Therefore, in the first semiconductor element 100 of the nFET, the Id characteristic rises without the occurrence of a characteristic bend (hump) in the curve of the Id-Vg characteristics.

[0045] Therefore, in the semiconductor device 10 described above, the Id characteristic rises without the occurrence of a characteristic bend (hump) in the curve of the Id-Vg characteristics. For this reason, the semiconductor device 10 can suppress the occurrence of defects even in a circuit that performs a specific operation, and can suppress a decrease in reliability.

[0046] 〈3. Manufacturing method of semiconductor device〉 Next, a method for manufacturing the semiconductor device 10 shown in FIGS. 5 to 7 described above will be described. FIGS. 11 to 41 show manufacturing process diagrams of the semiconductor device 10. In the manufacturing process of the semiconductor device 10 shown in FIGS. 11 to 41, on the left side (a) of the drawing, a cross-sectional view taken along line A-A (a cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 5 is shown, and on the right side (b) of the drawing, a cross-sectional view taken along line B-B (a cross-sectional view in the gate width direction) is shown.

[0047] First, as shown in FIG. 11, impurities are implanted into the outermost surface of the substrate 11, and a PTS layer 13 having a gentle concentration gradient from the surface of the substrate 11 toward the inside is formed. When the PTS layer 13 is formed as a p-type, boron is implanted as an impurity, and when the PTS layer 13 is formed as an n-type, phosphorus is implanted as an impurity.

[0048] 12, a Si layer 19, a SiGe layer 20, a Si layer 21, a SiGe layer 22, a Si layer 23, a SiGe layer 24, and a Si layer 25 are stacked on the substrate 11. The Si layers 19, 21, 23, 25, and the SiGe layers 20, 22, 24 are formed by epitaxial growth of Si and SiGe. The Si layer 19, the Si layer 21, the Si layer 23, and the Si layer 25 are formed to a thickness of, for example, about 5 nm. The SiGe layer 20, the SiGe layer 22, and the SiGe layer 24 are formed to a thickness of about 10-15 nm.

[0049] 13, hard mask layers 26 and 27 are formed on the Si layer 25. The hard mask layer 26 is made of, for example, SiN. The hard mask layer 27 is made of, for example, SiO. ２ or the like. Furthermore, the hard mask layers 26, 27 are patterned into a predetermined shape. To pattern the hard mask layers 26, 27, first, the hard mask layer 26 and the hard mask layer 27 are formed in a stacked manner over the entire surface of the Si layer 25. Then, a resist layer (not shown) is formed on the hard mask layer 27. The formed resist layer is exposed to light using a photomask on which a pattern has been formed, and developed to be patterned. Then, using the patterned resist layer as a mask, the hard mask layers 26, 27 are etched to form a predetermined pattern in the hard mask layers 26, 27. The patterns of the hard mask layers 26, 27 here are formed into the shapes of the stacked body of Si layers 101, 102, 103, and 104 in the first semiconductor element 100 and the stacked body of Si layers 201, 202, 203, and 204 in the second semiconductor element 200.

[0050] 14 , the patterned hard mask layers 26 and 27 are used to etch the stack of the Si layer 19, the SiGe layer 20, the Si layer 21, the SiGe layer 22, the Si layer 23, the SiGe layer 24, and the Si layer 25, thereby forming a Si / SiGe stack 28. Furthermore, the surface of the substrate 11 is etched to a predetermined depth. Reactive ion etching (RIE), for example, is used to etch the Si layer, the SiGe layer, and the substrate 11.

[0051] 15, after removing the hard mask layer 27, an insulating film 15 is formed to cover the side surfaces of the Si / SiGe stack 28, the side surfaces and top surface of the hard mask layer 26, the surface of the substrate 11, and the side surfaces of the PTS layer 13. Furthermore, an insulating film 16 is formed to cover the insulating film 15. The insulating film 15 is made of, for example, SiO ２ The insulating film 16 is made of, for example, SiN. The insulating films 15 and 16 are formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0052] 16, an insulating layer 17 is deposited on the entire surface of the substrate 11, and then the insulating layer 17 is polished and planarized until the upper surface of the hard mask layer 26 is exposed. ２ For example, CVD or the like is used to deposit the insulating layer 17. Furthermore, chemical mechanical polishing (CMP) or the like is used to polish and flatten the insulating layer 17.

[0053] Next, the hard mask layer 26, the insulating films 15 and 16 formed on the side surfaces of the Si / SiGe stack 28, and the insulating layer 17 formed on the side surfaces of the Si / SiGe stack 28 are removed. The insulating films 15 and 16 and the insulating layer 17 are removed up to the same height as the surface of the PTS layer 13 formed on the surface of the substrate 11. As a result, as shown in FIG. 17 , the top and side surfaces of the Si / SiGe stack 28 are exposed, and an STI 14 is formed by the insulating films 15 and 16 and the insulating layer 17 at the same height as the top surface of the PTS layer 13. Anisotropic etching such as RIE is used to remove the hard mask layer 26, the insulating films 15 and 16, and the insulating layer 17.

[0054] 18, a dummy gate insulating film 30 is formed to cover the side and upper surfaces of the Si / SiGe stack 28 and the upper surface of the STI 14. Furthermore, a dummy gate layer 31 is deposited to cover the dummy gate insulating film 30, and then the dummy gate layer 31 is polished and planarized. The dummy gate insulating film 30 is formed using, for example, SiO ２The dummy gate layer 31 is formed using polysilicon (p-Si), amorphous silicon (α-Si), or the like. The dummy gate insulating film 30 is formed and the dummy gate layer 31 is deposited using, for example, CVD, or the like. The dummy gate layer 31 is polished using, for example, CMP, or the like.

[0055] Next, hard mask layers 32 and 33 are formed on the dummy gate layer 31. The hard mask layer 32 is made of, for example, SiN. The hard mask layer 33 is made of, for example, SiO. ２ or the like. Then, as shown in FIG. 19 , the hard mask layers 32 and 33 are patterned into a predetermined shape. To pattern the hard mask layers 32 and 33, first, the hard mask layers 32 and 33 are formed by stacking them over the entire surface of the dummy gate layer 31. Then, a resist layer (not shown) is formed on the hard mask layers 32 and 33. The formed resist layer is exposed to light using a photomask on which a pattern has been formed, and developed to be patterned. Then, using the patterned resist layer as a mask, the hard mask layers 32 and 33 are etched to form a predetermined pattern in the hard mask layers 32 and 33. The patterns of the hard mask layers 32 and 33 here are formed into the shapes of the gate electrode 112 of the first semiconductor element 100 and the gate electrode 212 of the second semiconductor element 200.

[0056] 20 , the dummy gate layer 31 is etched using the patterned hard mask layers 32 and 33. As a result, a dummy gate 34 is formed in the first semiconductor element 100. Furthermore, a dummy gate 35 is formed in the second semiconductor element 200. Here, the dummy gate 34 is formed in a shape similar to that of the gate electrode 112 of the first semiconductor element 100. Similarly, the dummy gate 35 is formed in a shape similar to that of the gate electrode 212 of the second semiconductor element 200. For example, reactive ion etching (RIE) is used to etch the dummy gate layer 31.

[0057] 21 , sidewalls 116 are patterned on the side surfaces of the dummy gate 34 and the hard mask layers 32 and 33 of the first semiconductor element 100. Furthermore, sidewalls 216 are formed on the side surfaces of the dummy gate 35 and the hard mask layers 32 and 33 of the second semiconductor element 200. Furthermore, the Si / SiGe stacked body 28 and the dummy gate insulating film 30 are etched using the dummy gates 34 and 35, the hard mask layer 33, and the sidewalls 116 and 216 as masks.

[0058] To pattern the sidewalls 116, first, a material layer (e.g., SiN) constituting the sidewalls 116, 216 is formed to a predetermined thickness on the entire surface of the substrate 11. Then, the formed material layer is subjected to anisotropic etching such as RIE, thereby leaving the sidewalls 116, 216 on the side surfaces of the dummy gates 34, 35 and the hard mask layers 32, 33. The thickness of the material layer to be formed is adjusted depending on the thickness of the sidewalls 116, 216 to be left on the side surfaces of the dummy gates 34, 35 and the hard mask layers 32, 33. The sidewalls 116 are formed in an area where the stack of Si layers 101, 102, 103, and 104 of the first semiconductor element 100 will be formed. The sidewalls 216 are also formed in an area where the stack of Si layers 201, 202, 203, and 204 of the second semiconductor element 200 will be formed. By etching the Si / SiGe stack 28 and the dummy gate insulating film 30, an independent first stack 36 consisting of a stack of the Si layer 101, the SiGe layer 20, the Si layer 102, the SiGe layer 22, the Si layer 103, the SiGe layer 24, and the Si layer 104 is formed in the first semiconductor element 100. Similarly, an independent second stack 37 consisting of a stack of the Si layer 201, the SiGe layer 20, the Si layer 202, the SiGe layer 22, the Si layer 203, the SiGe layer 24, and the Si layer 204 is formed in the second semiconductor element 200.

[0059] Next, in the first stack 36 shown in FIG. 21 , the side surfaces of the SiGe layers 20, 22, and 24 exposed in the gate length direction are selectively etched to partially remove the side surfaces of the SiGe layers 20, 22, and 24. As a result, as shown in FIG. 22 , SiGe layers 105, 106, and 107 are formed, and recesses 38 are formed in the side surfaces of the SiGe layers 105, 106, and 107 relative to the side surfaces of the Si layers 101, 102, 103, and 104. As a result, steps are formed between the side surfaces of the SiGe layers 105, 106, and 107 and the side surfaces of the Si layers 101, 102, 103, and 104 due to the recesses 38. Similarly, in the second stack 37 shown in FIG. 21 , the side surfaces of the SiGe layers 20, 22, and 24 exposed in the gate length direction are selectively etched to partially remove the side surfaces of the SiGe layers 20, 22, and 24. As a result, as shown in FIG. 22 , recesses 39 are formed on the side surfaces of the SiGe layers 20, 22, and 24 relative to the side surfaces of the Si layers 201, 202, 203, and 204. Therefore, a step is formed between the side surfaces of the SiGe layers 20, 22, and 24 and the side surfaces of the Si layers 201, 202, 203, and 204 due to the recesses 39. At this time, the side surfaces in the gate width direction are covered by the dummy gates 34 and 35. Therefore, the side surfaces of the SiGe layers 20, 22, and 24 in the gate width direction are not etched. The SiGe layers 20, 22, and 24 are etched using isotropic etching such as atomic layer etching (ALE), quasi-ALE, or selective vapor-phase etching. These techniques have selectivity for Si relative to SiGe and inverse selectivity for SiGe relative to Si during the etching process. Therefore, these techniques can selectively etch the side surfaces of the SiGe layers 20, 22, and 24 of the first stacked bodies 36 and 37 to form the recesses 38 and 39. The depths of the recesses 38 and 39 are adjusted taking into consideration the thickness of the inner spacer 110 of the first semiconductor element 100 and the thickness of the inner spacer 210 of the second semiconductor element 200.

[0060] 23 , an insulating layer 40 is formed to selectively cover the first stacked bodies 36 and 37, the dummy gates 34 and 35, the hard mask layers 32 and 33, and the sidewalls 116 and 216. The insulating layer 40 is formed as follows. First, a resist layer (not shown) that opens the first stacked body 36, the dummy gate 34, the hard mask layers 32 and 33, the sidewalls 116 and 216, and the peripheries thereof, is patterned. Then, SiN or the like is stacked using CVD or the like. Then, the resist layer and the SiN on the resist layer are removed.

[0061] Next, anisotropic etching such as RIE is performed to remove the insulating layer 40 exposed from the side surfaces of the first stacked bodies 36 and 37. That is, the portions of the insulating layer 40 protruding from the Si layers 101, 102, 103, and 104 are removed, thereby leaving inner spacers 110 as insulating film regions in the recesses 38 on the side surfaces of the SiGe layers 105, 106, and 107, as shown in Fig. 24. Also, the portions of the insulating layer 40 protruding from the Si layers 201, 202, 203, and 204 are removed, thereby leaving inner spacers 210 as insulating film regions in the recesses 39 on the side surfaces of the SiGe layers 20, 22, and 24, as shown in Fig. 24.

[0062] 25 , a source region 108 and a drain region 109 are formed on the side surfaces of the first stacked body 36. A source region 208 and a drain region 209 are formed on the side surfaces of the second stacked body 37. The source regions 108, 208 and the drain regions 109, 209 are formed, for example, by epitaxial growth of the Si layers 101, 102, 103, and 104 and the Si layers 201, 202, 203, and 204. When forming the source regions 108, 208 and the drain regions 109, 209 by epitaxial growth of the Si layers, impurities are implanted. For example, boron is implanted as an impurity when the first semiconductor element 100 is formed as a p-type, and phosphorus is implanted as an impurity when the first semiconductor element 100 is formed as an n-type. Similarly, when the second semiconductor element 200 is formed as a p-type, boron is implanted as an impurity, and when the second semiconductor element 200 is formed as an n-type, phosphorus is implanted as an impurity.

[0063] Next, as shown in FIG. 26, an insulating layer 12 is formed on the entire surface of the substrate 11. The insulating layer 12 is made of, for example, SiN. The insulating layer 12 is formed by CVD. Furthermore, as shown in FIG. 27, an insulating layer 18 is formed on the entire surface of the substrate 11. The insulating layer 18 is deposited to a position higher than the insulating layer 12 formed on the hard mask layers 32 and 33. The insulating layer 18 is made of, for example, SiO ２ The insulating layer 18 is formed by, for example, CVD.

[0064] 28 , the surface of the insulating layer 18 is polished from above using CMP or the like to expose the hard mask layer 32 and the sidewalls 116 and 216. As a result, the hard mask layer 33, the insulating layer 12, and the sidewalls 116 and 216 formed above the hard mask layer 32 are removed.

[0065] Next, the hard mask layer 32, the sidewalls 116 and 216 on the side surfaces of the hard mask layer 32, and the insulating layer 12 are selectively removed. The hard mask layer 32, the sidewalls 116 and 216, and the insulating layer 12 are made of, for example, SiN. For this reason, the hard mask layer 32, the sidewalls 116 and 216, and the insulating layer 12 are selectively etched using a chemical such as hydrogen fluoride that can selectively wet etch SiN relative to SiO and Si. This exposes the dummy gates 34 and 35 while leaving the shape of the insulating layer 18 intact, as shown in FIG. 29 .

[0066] Next, the dummy gates 34 and 35 are removed, thereby exposing the dummy gate insulating film 30, as shown in Fig. 30. The dummy gates 34 and 35 are removed using, for example, plasma etching, which is capable of selectively etching the polysilicon (p-Si) and amorphous silicon (α-Si) that make up the dummy gates 34 and 35.

[0067] 31, the entire surface of the substrate 11 is filled with an insulating layer 18, the surface of the insulating layer 18 is planarized, and then a resist layer 42 is patterned to open only the area inside the insulating layer 12 of the second semiconductor element 200. Furthermore, using the resist layer 42 as a mask, the insulating layer 18 is etched to expose the insulating layer 12 and the second stacked body 37. When etching the insulating layer 18, the dummy gate insulating film 30 of the second semiconductor element 200 is also removed. The insulating layer 18 is made of, for example, SiO ２ The insulating layer 18 is planarized by CMP or the like. The insulating layer 18 and the dummy gate insulating film 30 are etched by RIE or the like.

[0068] Next, the resist layer 42 is stripped, and the SiGe layers 20, 22, and 24 of the second stack 37 of the second semiconductor element 200 are selectively etched. As a result, as shown in FIG. 32 , the interlayer spaces between the Si layers 201, 202, 203, and 204 of the second semiconductor element 200 are exposed. Plasma etching or the like is used to strip the resist layer 42. The SiGe layers 20, 22, and 24 are selectively etched, for example, by dry etching using a mixed gas containing hydrogen fluoride and oxygen, or by wet etching using a mixed solution of hydrogen fluoride and hydrogen peroxide.

[0069] 33, a gate insulating film 211 is formed on the entire surface, and a high-dielectric-constant material layer 213 is further formed on the gate insulating film 211. The gate insulating film 211 is formed, for example, by thermal oxidation of the exposed surfaces of the Si layers 201, 202, 203, and 204. The high-dielectric-constant material layer 213 is formed, for example, by thermal oxidation of hafnium dioxide (HfO ２ The high dielectric constant material layer 213 is formed of, for example, hafnium oxynitride (HfON), etc. The high dielectric constant material layer 213 is formed by, for example, ALD (Atomic Layer Deposition) or the like.

[0070] 34 , a first metal layer 214 is filled on the high-dielectric-constant material layer 213, and a second metal layer 215 is further filled on the first metal layer 214. The first metal layer 214 is formed of, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), niobium, or the like. The second metal layer 215 is formed of, for example, tungsten (W), or the like. The first metal layer 214 and the second metal layer 215 are formed by, for example, CVD.

[0071] 35 , the first metal layer 214 and the second metal layer 215 located above the sidewall 216 are removed. The first metal layer 214 and the second metal layer 215 are removed by, for example, CMP and RIE. As a result, a gate electrode 212 made of the high-dielectric-constant material layer 213, the first metal layer 214, and the second metal layer 215 is formed in the second semiconductor element 200.

[0072] Next, as shown in FIG. 36 , the entire surface of the substrate 11 is filled with an insulating layer 18, the surface of the insulating layer 18 is planarized, and then a region where the gate electrode of the first semiconductor element 100 will be formed is opened. For example, a resist layer is patterned on the insulating layer 18 to open the region where the gate electrode will be formed. Furthermore, using the resist layer as a mask, the insulating layer 18 is etched to expose the insulating layer 12 and the first stacked body 36. When etching the insulating layer 18, the dummy gate insulating film 30 of the first semiconductor element 100 and a portion of the insulating layer 12 in the gate width direction are also removed. CMP or the like is used to planarize the insulating layer 18. RIE or the like is used to etch the insulating layer 18 and the dummy gate insulating film 30. Plasma etching or the like is used to remove the resist layer.

[0073] 37, a gate insulating film 111 is formed on the exposed surface of the first stack 36, and further, a high-dielectric-constant material layer 113 is formed on the entire surface of the substrate 11. The gate insulating film 111 is formed, for example, by epitaxial growth of Si layers 101, 102, 103, and 104, followed by thermal oxidation of the formed Si layers. The high-dielectric-constant material layer 113 is formed, for example, by epitaxial growth of hafnium dioxide (HfO ２The high dielectric constant material layer 113 is formed by, for example, CVD or the like.

[0074] 38 , a first metal layer 114 is filled on the high-dielectric-constant material layer 113, and a second metal layer 115 is further filled on the first metal layer 114. The first metal layer 114 is formed of, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), niobium, or the like. The second metal layer 115 is formed of, for example, tungsten (W), or the like. The first metal layer 114 and the second metal layer 115 are formed by, for example, CVD.

[0075] 39 , the high dielectric constant material layer 113, the first metal layer 114, and the second metal layer 115 above the insulating layer 18 are removed. The high dielectric constant material layer 113, the first metal layer 114, and the second metal layer 115 are removed by, for example, CMP.

[0076] 40 , the high-dielectric-constant material layer 113, the first metal layer 114, and the second metal layer 115 located above the sidewalls 116 are removed. The high-dielectric-constant material layer 113, the first metal layer 114, and the second metal layer 115 are removed by, for example, RIE. As a result, a gate electrode 112 made of the high-dielectric-constant material layer 113, the first metal layer 114, and the second metal layer 115 is formed in the first semiconductor element 100.

[0077] Next, an insulating layer 18 is formed over the entire surface of the substrate 11, and the surface is planarized. The insulating layer 18 is formed by, for example, CVD. The insulating layer 18 is planarized by, for example, CMP. As a result, the first semiconductor element 100 and the second semiconductor element 200 are sealed by the insulating layer 18, as shown in FIG. 41. Through the above steps, the semiconductor device 10 can be manufactured, in which the first semiconductor element 100 and the second semiconductor element 200 are formed on the substrate 11, as shown in FIGS. 5-7.

[0078] 4. Other Embodiments of the Semiconductor Device Next, as another embodiment of the semiconductor device, the configuration of a semiconductor device of embodiment 2-5 will be described. The semiconductor device of embodiment 2-5 described below has a configuration similar to that of the semiconductor device of embodiment 1 described above. Therefore, a description of the configuration similar to that of the semiconductor device of embodiment 1 described above will be omitted.

[0079] [Semiconductor Device of Second Embodiment] Figures 42 and 43 show the configuration of a semiconductor device of the second embodiment. Figure 42 corresponds to a cross-sectional view taken along line A-A (cross-sectional view in the gate length direction) of the semiconductor device shown in Figure 5. Figure 43 corresponds to a cross-sectional view taken along line B-B (cross-sectional view in the gate width direction) of the semiconductor device shown in Figure 5. A semiconductor device 50 shown in Figures 42 and 43 has a configuration in which a first semiconductor device 51 and a second semiconductor device 52, each having a configuration similar to that of the semiconductor device 10 shown in Figures 5 and 6 described above, are stacked in the vertical direction (the stacking direction of the Si layers).

[0080] The first semiconductor device 51 stacked in the upper layer includes, on a substrate 55 (first substrate), a first semiconductor element 150 configured with a FinFET to serve as an input / output device, and a second semiconductor element 152 configured with a GAAFET to serve as a logic device. The second semiconductor device 52 stacked in the lower layer includes, on a substrate 11 (second substrate), a third semiconductor element 151 configured with a FinFET to serve as an input / output device, and a fourth semiconductor element 153 configured with a GAAFET to serve as a logic device.

[0081] In the semiconductor device 50 having the above configuration, for example, the first semiconductor element 150 and the second semiconductor element 152 in the upper layer are formed as pFETs, and the third semiconductor element 151 and the fourth semiconductor element 153 in the lower layer are formed as nFETs. The semiconductor device 50 can form a CFET (Complementary Field Effect Transistor: 3D sequential integration) in which a first semiconductor device 51 including the first semiconductor element 150 and the second semiconductor element 152 on a substrate 55 and a second semiconductor device 52 including the third semiconductor element 151 and the fourth semiconductor element 153 formed on a substrate 11 are stacked.

[0082] [Semiconductor Device of Third Embodiment] Figures 44 and 45 show the configuration of a semiconductor device of the third embodiment. Figure 44 corresponds to a cross-sectional view taken along line A-A (cross-sectional view in the gate length direction) of the semiconductor device shown in Figure 5. Figure 45 corresponds to a cross-sectional view taken along line B-B (cross-sectional view in the gate width direction) of the semiconductor device shown in Figure 5. A semiconductor device 60 shown in Figures 44 and 45 has a configuration in which a first semiconductor device 61 and a second semiconductor device 62 are stacked in the vertical direction (stacking direction of Si layers).

[0083] The upper first semiconductor device 61 has a configuration similar to that of the semiconductor device 10 shown in Figures 5 and 6 above, except that the first semiconductor element 100 is removed. Therefore, the first semiconductor device 61 includes a second semiconductor element 162, which is a GAAFET and serves as a logic device, on a substrate 65 (first substrate). The lower second semiconductor device 62 has the same configuration as the semiconductor device 10 shown in Figures 5 and 6 above. Therefore, the lower second semiconductor device 62 includes, on a substrate 11 (second substrate), a third semiconductor element 161, which is a FinFET and serves as an input / output device, and a fourth semiconductor element 163, which is a GAAFET and serves as a logic device.

[0084] In the semiconductor device 60 having the above configuration, for example, the second semiconductor element 162 in the upper layer is formed as a pFET, and the third semiconductor element 161 and the fourth semiconductor element 163 in the lower layer are formed as nFETs. The semiconductor device 60 can form a CFET (Complementary Field Effect Transistor: 3D sequential integration) in which a first semiconductor device 61 including the second semiconductor element 152 on a substrate 65 and a second semiconductor device 62 including the third semiconductor element 161 and the fourth semiconductor element 163 formed on a substrate 11 are stacked.

[0085] [Semiconductor Device of Fourth Embodiment] Figures 46 and 47 show the configuration of a semiconductor device of the fourth embodiment. Figure 46 corresponds to a cross-sectional view taken along line A-A (cross-sectional view in the gate length direction) of the semiconductor device shown in Figure 5. Figure 47 corresponds to a cross-sectional view taken along line B-B (cross-sectional view in the gate width direction) of the semiconductor device shown in Figure 5. A semiconductor device 70 shown in Figures 46 and 47 has a configuration in which a first semiconductor device 71 and a second semiconductor device 72 are stacked in the vertical direction (stacking direction of Si layers).

[0086] The first semiconductor device 71 in the upper layer has a configuration similar to that of the semiconductor device 10 shown in Figures 5 and 6 described above. Therefore, the first semiconductor device 71 stacked in the upper layer includes, on a substrate 75 (first substrate), a first semiconductor element 170 configured as a FinFET serving as an input / output device, and a second semiconductor element 172 configured as a GAAFET serving as a logic device. The second semiconductor device 72 in the lower layer has a configuration similar to that of the semiconductor device 10 shown in Figures 5 and 6 described above, except that the first semiconductor element 100 is removed. Therefore, the second semiconductor device 72 stacked in the lower layer includes, on a substrate 11 (second substrate), a fourth semiconductor element 173 that is a GAAFET serving as a logic device.

[0087] In the semiconductor device 70 having the above configuration, for example, the first semiconductor element 170 and the second semiconductor element 172 in the upper layer are formed as pFETs, and the fourth semiconductor element 173 in the lower layer is formed as an nFET. The semiconductor device 70 can form a CFET (Complementary Field Effect Transistor: 3D sequential integration) in which a first semiconductor device 71 including the first semiconductor element 170 and the second semiconductor element 172 on a substrate 75 and a second semiconductor device 72 including the fourth semiconductor element 173 formed on a substrate 11 are stacked.

[0088] [Semiconductor Device of Fifth Embodiment] Figures 48 and 49 show the configuration of a semiconductor device of a fifth embodiment. Figure 48 corresponds to a cross-sectional view of the semiconductor device shown in Figure 5 taken along line A-A (cross-sectional view in the gate length direction). Figure 49 corresponds to a cross-sectional view of the semiconductor device shown in Figure 5 taken along line B-B (cross-sectional view in the gate width direction). A semiconductor device 80 shown in Figures 48 and 49 has a configuration in which a first semiconductor device 81 and a second semiconductor device 82, each having a configuration similar to that of the semiconductor device 10 shown in Figures 5 and 6, are stacked in the vertical direction (the stacking direction of the Si layers). In the semiconductor device 80 of the fifth embodiment, the first semiconductor device 81 and the second semiconductor device 82 are connected face-to-face by bonding electrodes 92, 94 and bonding electrodes 97, 99 formed on the surfaces opposite to the substrate 85 (first substrate) and the substrate 11 (second substrate), respectively.

[0089] The first semiconductor device 81 stacked in the upper layer includes a first semiconductor element 180, which is an input / output transistor (I / O transistor) serving as an I / O device, and a second semiconductor element 182, which is a GAAFET (GaAs-Alternating-Mode Field Effect Transistor) serving as a logic device, on a substrate 85. The first semiconductor device 81 also includes a bonding electrode 92 and a bonding electrode 94 on the surface of the insulating layer 18. The gate electrode 112 of the first semiconductor element 180 is electrically connected to the bonding electrode 92 via a through electrode 91 that penetrates the insulating layer 18. The gate electrode 212 of the second semiconductor element 182 is electrically connected to the bonding electrode 94 via a through electrode 93 that penetrates the insulating layer 18.

[0090] The second semiconductor device 82 stacked in the lower layer includes, on the substrate 11, a third semiconductor element 181 which is an input / output transistor (I / O transistor) that serves as an I / O device, and a fourth semiconductor element 183 which is a GAAFET that serves as a logic device. The second semiconductor device 82 also includes a bonding electrode 97 and a bonding electrode 99 on the surface of the insulating layer 18. The gate electrode 112 of the third semiconductor element 181 is electrically connected to the bonding electrode 97 via a through electrode 96 that penetrates the insulating layer 18. The gate electrode 212 of the fourth semiconductor element 183 is electrically connected to the bonding electrode 99 via a through electrode 98 that penetrates the insulating layer 18.

[0091] The through electrodes 91, 93, 96, 98 and the bonding electrodes 92, 94, 97, 99 are formed from copper (Cu) or the like. The through electrodes 91, 93, 96, 98 and the bonding electrodes 92, 94, 97, 99 are formed, for example, by first forming openings in the insulating layer 18 using a patterned resist layer as a mask. Then, copper is filled into the openings using CVD or the like to form the through electrodes 91, 93, 96, 98 and the bonding electrodes 92, 94, 97, 99. The surfaces of the insulating layer 18 and the bonding electrodes 92, 94, 97, 99 are polished and planarized using CMP or the like. The formed bonding electrodes 92, 94, 97, 99 are then heated while facing each other and in contact with each other, thereby bonding the bonding electrodes 92, 94, 97, 99 to each other.

[0092] In the semiconductor device 80 having the above configuration, for example, the first semiconductor element 180 and the second semiconductor element 182 in the upper layer are formed as pFETs, and the third semiconductor element 181 and the fourth semiconductor element 183 in the lower layer are formed as nFETs. This method makes it possible to form a structure that makes it easy to form a BSPDN (Backside Power Delivery Network) or the like.

[0093] The present invention is not limited to the configurations described in the above-described embodiments, and various modifications and changes are possible without departing from the scope of the present invention.

[0094] 10, 50, 60, 62, 70, 80... Semiconductor device, 11, 55, 65, 75, 85, 305... Substrate, 12, 15, 16, 117, 217... Insulating film, 13... PTS layer, 14, 310... STI, 17, 18, 40... Insulating layer, 19, 21, 23, 25, 101, 102, 103, 104, 201, 202, 203, 204... Si layer, 20, 22, 24, 105, 106, 107... SiGe layer, 26, 27, 32, 33... Hard mask layer, 28... Si / SiGe stacked body, 30... dummy gate insulating film, 31... dummy gate layer, 34, 35... dummy gate, 36... first stacked body, 37... second stacked body, 38, 39... recess, 42... resist layer, 51, 61, 71, 81... first semiconductor device, 52, 62, 72, 82... second semiconductor device, 153, 163, 173, 183... fourth semiconductor element, 91, 93, 96, 98... through electrode, 92, 94, 97, 99... Bonding electrodes, 100, 150, 170, 180... First semiconductor element, 108, 208... Source region, 109, 209... Drain region, 110, 210, 315a, 315b, 315c, 315d, 315e, 325f... Inner spacers, 111, 211... Gate insulating film, 112, 205, 206, 207, 212... Gate electrode, 113, 213... High dielectric constant material layer, 114, 214... First Metal layer, 115, 215... second metal layer, 116, 216... sidewall, 151, 161, 181... third semiconductor element, 152, 162, 172, 182, 200... second semiconductor element, 325a... EG gate insulating film, 325b... SG gate insulating film, 325c, 325d, 325e, 325f, 325g, 325h... IL layer, 330a... first dielectric layer, 330b... second dielectric layer, 330c, 330d, 330e,330f: Sidewall spacer, 335a: EG gate electrode, 335b: SG gate electrode, 335c: third metal electrode, 335d: second metal electrode, 335e: first metal electrode, 340a: first barrier layer, 340c: third barrier layer, 340e: fifth barrier layer, 340g: seventh barrier layer, 340i: ninth barrier layer, 340k: th 11 barrier layers, 350a... first semiconductor layer, 350c... fifth semiconductor layer, 350e... ninth semiconductor layer, 360a... third semiconductor layer, 360b... second semiconductor layer, 360c... seventh semiconductor layer, 360d... fourth semiconductor layer, 360e... eleventh semiconductor layer, 360f... sixth semiconductor layer, 390a, 390b, 390c, 390d... source / drain regions,

Claims

1. A semiconductor device including a first semiconductor element and a second semiconductor element on a substrate, wherein the first semiconductor element includes: a first laminate in which an Si layer and an SiGe layer are laminated; a first source / drain region formed on a side surface in the gate length direction of the first laminate; a first gate electrode formed above the first laminate and on a side surface in the gate width direction via a first gate insulating film; and an insulating film region formed between the SiGe layer and the first source / drain region, and the second semiconductor element includes: a second laminate in which an Si layer and a second gate electrode are laminated; and a second source / drain region formed on a side surface in the gate length direction of the second laminate, and the second gate electrode is formed via a second gate insulating film between the Si layers and above the second laminate.

2. The semiconductor device according to claim 1, wherein the SiGe layer is connected to the first source / drain region via the Si layer and the insulating film region.

3. The semiconductor device according to claim 1, wherein the first gate insulating film of the first semiconductor element has a greater thickness than the second gate insulating film of the second semiconductor element.

4. The semiconductor device according to claim 1, wherein the first semiconductor element has a greater gate length than the second semiconductor element.

5. The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are composed of a metal layer and a high-k dielectric layer, and the high-k dielectric layer contacts the first gate insulating film and the second gate insulating film.

6. The semiconductor device according to claim 1, wherein the first semiconductor element is either a p-channel type FET (Field Effect Transistor) or an n-channel type FET.

7. A semiconductor device having a structure in which a first semiconductor device including a first semiconductor element and a second semiconductor element is stacked on a first substrate, and a second semiconductor device including a third semiconductor element and a fourth semiconductor element is stacked on a second substrate, wherein the first semiconductor element and the third semiconductor element include: a first laminate in which an Si layer and an SiGe layer are stacked; a first source / drain region formed on a side surface in the gate length direction of the first laminate; a first gate electrode formed above the first laminate and on a side surface in the gate width direction via a first gate insulating film; and an insulating film region formed between the SiGe layer and the first source / drain region, and the second semiconductor element and the fourth semiconductor element include: a second laminate in which an Si layer and a second gate electrode are stacked via a gate insulating film; and a second source / drain region formed on a side surface in the gate length direction of the second laminate, and the second gate electrode is formed via a second gate insulating film between the Si layers and above the second laminate.

8. The semiconductor device according to claim 7, wherein the SiGe layer contacts the first source / drain region via the Si layer and the insulating film region.

9. The semiconductor device according to claim 7, wherein the first semiconductor device and the second semiconductor device are joined by joining electrodes formed on the first substrate and the second substrate, the first semiconductor element and the third semiconductor element are electrically connected by the joining electrodes, and the second semiconductor element and the fourth semiconductor element are electrically connected by the joining electrodes.

10. A step of forming a Si / SiGe laminate formed by laminating a Si layer and a SiGe layer; a step of etching the Si / SiGe laminate to form a first laminate and a second laminate; a step of selectively etching the SiGe layer exposed on the side surfaces in the gate length direction of the first laminate and the second laminate to form a recess on the side surface of the SiGe layer with respect to the side surface of the Si layer; a step of forming an insulating film region in the recess; a step of forming a first source / drain region on the side surface in the gate length direction of the first laminate and forming a second source / drain region on the side surface in the gate length direction of the second laminate; a step of forming a first gate insulating film and a first gate electrode above the first laminate and on the side surface in the gate width direction; a step of selectively removing the SiGe layer from the second laminate; and a step of forming a second gate insulating film and a second gate electrode between the Si layers of the second laminate and above the second laminate. A method for manufacturing a semiconductor device.

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