Semiconductor device and power conversion device

Abstract

The present invention can suppress current concentration in an end portion of an active region while suppressing an increase in the surface area of a chip, and increases cut-off resistance. In a semiconductor device (30), a diode (33) of an active region (31) includes a second electrode (12), a drift layer (5) of a first conductivity type, and a second semiconductor layer (2) of a second conductivity type that is in contact with the drift layer (5) and electrically connected to the second electrode (12). The active region (31) is in contact with the drift layer (5) between the diode (33) and a termination region (32), and includes a third semiconductor layer (3) of the second conductivity type positioned closer to the second semiconductor layer (2) than the drift layer (5), and a fourth semiconductor layer (4) positioned between the second semiconductor layer (2) and the third semiconductor layer (3). The third semiconductor layer (3) and the fourth semiconductor layer (4) are not directly connected to the second electrode (12), the third semiconductor layer (3) has a higher impurity concentration than the second semiconductor layer (2), and the fourth semiconductor layer (4) is of the second conductivity type or the first conductivity type and has a lower impurity concentration than the second semiconductor layer (2).

Description

Semiconductor device and power conversion device

[0001] The present invention relates to a semiconductor device and a power conversion device.

[0002] The global trend toward realizing a decarbonized society is driving steady market growth in electric vehicles (EVs), power grids, and railways. Applications in these markets use power conversion devices that convert DC power supplied from a DC power source into AC current to control inductive loads such as electric motors. Key components of power conversion devices include semiconductor devices and the gate drive circuits that drive them.

[0003] Semiconductor devices are required to have low loss and high breakdown voltage, so that they can interrupt large currents flowing through them without damaging the semiconductor elements inside the semiconductor device. In inverter devices, which are a type of power conversion device, freewheeling diodes (freewheeling diodes) are used as semiconductor devices for circulating currents flowing through inductive loads. It has been reported that in order to achieve high breakdown voltage in such diodes, it is necessary to suppress current concentration at the anode termination, and an element structure that achieves this is disclosed, for example, in Patent Document 1.

[0004] Patent Document 1 describes a diode element structure in which the carrier concentration injected from the end of the anode layer in the planar direction into the n-drift layer in the termination region is reduced by ensuring a certain distance or more between the end of the anode layer in the planar direction of the contact region between the anode layer and the anode electrode and the end of the junction between the anode layer and the n-drift layer in the planar direction.

[0005] Japanese Patent Application Publication No. 9-232597

[0006] Patent Document 1 describes a technology in which, by ensuring a certain or greater distance (L) between the end in the planar direction of the contact region between the anode layer (p+ conductivity type semiconductor layer (11)) and the anode electrode (16) and the end in the planar direction of the junction (J1) between the anode layer and the n-drift layer (n- conductivity type semiconductor region (14)), the concentration of carriers injected from the end in the planar direction of the anode layer into the n-drift layer in the termination region can be reduced, and the di / dt (critical di / dt) at which breakdown occurs during diode recovery can be increased.

[0007] However, the higher the breakdown voltage of a semiconductor device, the longer the distance (L) required to suppress the concentration of hole current during recovery becomes, which poses a problem of increasing the chip area.

[0008] The problem to be solved by the present invention is to provide a semiconductor device that can suppress current concentration at the end of the active region while suppressing an increase in chip area, and has high interruption resistance, and a power conversion device using the same.

[0009] In order to solve the above-mentioned problems, a semiconductor device of the present invention is a semiconductor device having an active region having a diode and a termination region surrounding the active region, wherein the diode has a first electrode, a second electrode, a first semiconductor layer of a first conductivity type electrically connected to the first electrode, a drift layer of the first conductivity type having an impurity concentration lower than that of the first semiconductor layer, and a second semiconductor layer of a second conductivity type in contact with the drift layer and electrically connected to the second electrode, the active region has, between the diode and the termination region, a third semiconductor layer of the second conductivity type in contact with the drift layer and arranged on a side of the drift layer closer to the second semiconductor layer, and a fourth semiconductor layer arranged between the second semiconductor layer and the third semiconductor layer, the third semiconductor layer and the fourth semiconductor layer are not directly connected to the second electrode, the third semiconductor layer has a higher impurity concentration than the second semiconductor layer, and the fourth semiconductor layer is of the second conductivity type or the first conductivity type and has a lower impurity concentration than the second semiconductor layer.

[0010] The power conversion device of the present invention is characterized by including a free wheel diode using the semiconductor device described above.

[0011] According to the present invention, it is possible to suppress current concentration at the edge of the active region while suppressing an increase in chip area, and it is possible to realize a semiconductor device with high interruption resistance and a power conversion device using the same.

[0012] 1 is a diagram showing the overall configuration of an electric motor control system using a power conversion device of Example 1. FIG. 2 is a plan view of a semiconductor device of Example 1. FIG. 3 is a cross-sectional view of the semiconductor device of Example 1. FIG. 4 is a diagram showing the relationship between impurity concentrations along C-D in FIG. 3. FIG. 5 is a schematic diagram showing the flow of holes during forward conduction in the semiconductor device of Example 1. FIG. 6 is a schematic diagram showing the flow of holes during reverse recovery in the semiconductor device of Example 1. FIG. 7 is a cross-sectional view of a semiconductor device of a modified example of Example 1. FIG. 8 is a cross-sectional view of a semiconductor device of Example 2. FIG. 9 is a cross-sectional view of a semiconductor device of a modified example of Example 2. FIG. 10 is a cross-sectional view of a semiconductor device of Example 3. FIG. 11 is a cross-sectional view of a semiconductor device of Example 4. FIG. 12 is a cross-sectional view illustrating the structure of a MOS control diode used in a semiconductor device of a modified example of Example 4. FIG. 13 is a timing chart illustrating a method of controlling a semiconductor device and a power conversion device in a modified example of Example 4.

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0014] FIG. 1 is a diagram showing the overall configuration of an electric motor control system using a power conversion device according to a first embodiment.

[0015] The power conversion device 130 is a device that converts electric power using a power semiconductor device. Here, an example in which an inverter device is used as the power conversion device 130 will be described.

[0016] The motor control system 100 includes a DC power supply 110 , a power conversion device 130 , and an electric motor 120 .

[0017] The power conversion device 130 has a smoothing capacitor 131, inverter units 135 for three phases, UVW (U-phase inverter unit 135U, V-phase inverter unit 135V, and W-phase inverter unit 135W), and a command logic unit 132. The power conversion device 130 converts DC power supplied from the DC power supply 110 into AC power, outputs the AC power, and drives the electric motor 120. The smoothing capacitor 131 is provided between the DC power supply 110 (power supply voltage = Vcc) and the positive electrode connecting line 133 and negative electrode connecting line 134 of the power conversion device 130.

[0018] In each phase, the inverter unit 135 has an upper arm, a lower arm, and a gate driver 139. The upper arm and lower arm each have a semiconductor switching element 136 and a freewheeling diode 137. The upper arm semiconductor switching element 136 and the lower arm semiconductor switching element 136 are connected in series. In this embodiment, the semiconductor switching element 136 is configured as an insulated gate bipolar transistor (IGBT). Gate signals (G1, G2) are sent to the gate of the semiconductor switching element 136 from the gate driver 139. The high-potential side terminal of the upper arm semiconductor switching element 136 is connected to the first end of the smoothing capacitor 131 via the positive electrode connection line 133. The low-potential side terminal of the upper arm semiconductor switching element 136 is connected to the high-potential side terminal of the lower arm semiconductor switching element 136. The low potential side terminal of the semiconductor switching element 136 of the lower arm is connected to the second end side of the smoothing capacitor 131 via the negative electrode connecting line 134 .

[0019] In each phase, a connection point 138 between the low potential side terminal of the semiconductor switching element 136 of the upper arm and the high potential side terminal of the semiconductor switching element 136 of the lower arm is connected to one end of the winding of the corresponding phase of the motor 120. The other end of the winding of each phase of the motor 120 is connected to the neutral point of the motor 120. The motor 120 is, for example, an induction motor.

[0020] A freewheel diode 137 (freewheel diode) is connected in antiparallel to each semiconductor switching element 136. As the freewheel diode 137, various types of diodes can be used, such as a pn junction diode, a diode using both a pn junction and a Schottky junction, or a MOS controlled diode.

[0021] The command logic unit 132 outputs an ON command instructing an ON state or an OFF command instructing an OFF state to the gate driver 139 as a drive command signal (P1, P2) for the semiconductor switching element 136. The command logic unit 132 alternately controls the upper arm semiconductor switching element 136 and the lower arm semiconductor switching element 136 to the ON state in each phase in order to control the control variable of the electric motor 120 to the command value. The control variable of the electric motor 120 is, for example, the torque of the electric motor.

[0022] The gate driving devices 139 are provided corresponding to the respective semiconductor switching elements 136, acquire drive command signals (P1, P2) from the command logic unit 132, and output gate signals (G1, G2) based on the acquired drive command signals (P1, P2) to turn the semiconductor switching elements 136 on or off.

[0023] Next, a description will be given of the configuration and operation of an example of a semiconductor device 30 used in the free wheel diode 137 of the upper arm of the U-phase in the power conversion device 130 shown in Fig. 1. The free wheel diodes 137 of the lower arm of the U-phase and the upper and lower arms of the V and W-phases can also use a similar semiconductor device 30, and have the same configuration and operation.

[0024] Fig. 2 is a plan view of the semiconductor device of Example 1. Fig. 3 is a cross-sectional view of the semiconductor device of Example 1. Fig. 3 is a cross-sectional view taken along line A-B in Fig. 2. Some of the components shown in Fig. 3 are omitted in Fig. 2.

[0025] In this embodiment, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type. However, this is not limiting, and the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the anode and cathode are reversed, and the carriers of holes and electrons are reversed.

[0026] The semiconductor device 30 of this embodiment has an active region 31 having a diode 33 and a termination region 32 surrounding the active region 31 .

[0027] 2 shows a plan view of one main surface side (the side on which the anode is formed) of the semiconductor substrate. A cathode is formed on the other main surface side of the semiconductor substrate. A termination region 32 is provided to ensure the breakdown voltage of the diode 33 when a high voltage is applied to the cathode relative to the anode. An active region 31 surrounded by the termination region 32 is a current conducting region.

[0028] As shown in FIG. 3 , the diode 33 in the active region 31 of the semiconductor device 30 of this embodiment has a first electrode 11 (cathode electrode), a second electrode 12 (anode electrode), a first semiconductor layer 1 (cathode layer) of a first conductivity type electrically connected to the first electrode 11, a drift layer 5 of the first conductivity type having a lower impurity concentration than the first semiconductor layer 1, and a second semiconductor layer 2 (anode layer) of a second conductivity type in contact with the drift layer 5 and electrically connected to the second electrode 12.

[0029] The drift layer 5 is formed of, for example, a low-concentration n-type semiconductor substrate. A second semiconductor layer 2, which serves as an anode layer, is formed on one main surface side of the drift layer 5. A second electrode 12, which serves as an anode electrode, is in contact with at least a portion of the second semiconductor layer 2. A first semiconductor layer 1, which serves as a cathode layer, is formed on the other main surface side of the drift layer 5. The first semiconductor layer 1 is, for example, an n+ type high-concentration region. A first electrode 11, which serves as a cathode electrode, is in contact with the first semiconductor layer 1.

[0030] The active region 31 of the semiconductor device 30 of this embodiment has, between the diode 33 and the termination region 32, a third semiconductor layer 3 of the second conductivity type that is in contact with the drift layer 5 and is arranged closer to the second semiconductor layer 2 than the drift layer 5, and a fourth semiconductor layer 4 that is arranged between the second semiconductor layer 2 and the third semiconductor layer 3.

[0031] The third semiconductor layer 3 and the fourth semiconductor layer 4 are not directly connected to the second electrode 12. Therefore, it is desirable that the active region 31 of the semiconductor device 30 has a first insulating film 13 that covers the third semiconductor layer 3 and the fourth semiconductor layer 4. The first insulating film 13 is, for example, an oxide film. The first insulating film 13 also covers a portion of the second semiconductor layer 2 by the distance Δ in FIG. 3 , and the second semiconductor layer 2 and the second electrode 12 are connected at the opening of the first insulating film 13.

[0032] The third semiconductor layer 3 has a higher impurity concentration than the second semiconductor layer 2. The third semiconductor layer 3 is, for example, a p+ type high concentration region. The third semiconductor layer 3 is preferably formed at the end of the active region 31.

[0033] The fourth semiconductor layer 4 is of the second conductivity type or the first conductivity type, and has an impurity concentration set lower than that of the second semiconductor layer 2. The fourth semiconductor layer 4 is, for example, a p-type or n-type low concentration region. Note that when the fourth semiconductor layer 4 is of the first conductivity type, for example, the second semiconductor layer 2 and the third semiconductor layer 3 may be formed apart from each other on the surface of the drift layer 5, thereby leaving a part of the drift layer 5 between the second semiconductor layer 2 and the third semiconductor layer 3, and a part of the drift layer 5 may also serve as the fourth semiconductor layer 4.

[0034] Fig. 4 is a diagram showing the relationship between impurity concentrations along CD in Fig. 3. In Fig. 4, the horizontal axis represents horizontal distance x, and the vertical axis represents impurity concentration IC.

[0035] The impurity concentration of the fourth semiconductor layer 4 is designed to be lower than the impurity concentration of the second semiconductor layer 2. The impurity concentration of the second semiconductor layer 2 is, for example, 1×10 １４ / cm ３ ~1 x 10 １６ / cm ３ The impurity concentration of the fourth semiconductor layer 4 is, for example, 1×10１２ / cm ３ ~1 x 10 １４ / cm ３ The impurity concentration of the third semiconductor layer 3 is designed to be higher than the impurity concentration of the second semiconductor layer 2. The impurity concentration of the third semiconductor layer 3 is, for example, 1×10 １６ / cm ３ ~1 x 10 １８ / cm ３ is.

[0036] The ratio of the impurity concentration of the fourth semiconductor layer 4 to the impurity concentration of the second semiconductor layer 2 is 10 －１ ~10 －２ The impurity concentration of the third semiconductor layer 3 is preferably 10 times that of the second semiconductor layer 2. １ ~10 ２ Double is preferable.

[0037] The effects of the third semiconductor layer 3 and the fourth semiconductor layer 4 will be described in detail later in the description of the operation.

[0038] As shown in FIG. 3 , the termination region 32 of the semiconductor device 30 of this embodiment includes, for example, a drift layer 5, a first electrode 11, a first semiconductor layer 1, a second conductivity type breakdown voltage holding layer 21, a first conductivity type channel stopper 22, a second insulating film 23, and a termination portion field plate 24.

[0039] In termination region 32, a plurality of breakdown voltage holding layers 21 are formed so as to surround active region 31. Breakdown voltage holding layer 21 is, for example, a p+ type guard ring.

[0040] In addition to breakdown voltage holding layer 21, a structure for ensuring the breakdown voltage of diode 33 is formed, which includes a termination field plate 24 electrically connected to breakdown voltage holding layer 21 and adjusting the electric field distribution, and a channel stopper 22 provided at the outermost periphery of termination region 32 and terminating the electric field. Channel stopper 22 is, for example, n+ type. A termination field plate 24 electrically connected to channel stopper 22 is also provided. A second insulating film 23 is formed between termination field plate 24 and breakdown voltage holding layer 21, or between termination field plate 24 and channel stopper 22. Second insulating film 23 is, for example, an oxide film. An opening in second insulating film 23 provides electrical connection between termination field plate 24 and breakdown voltage holding layer 21, or between termination field plate 24 and channel stopper 22.

[0041] In FIG. 3, the plurality of breakdown voltage holding layers 21 are spaced apart from one another, but as long as the breakdown voltage of the diode 33 can be ensured, the breakdown voltage holding layers 21 do not necessarily have to all be spaced apart from one another, and some may be adjacent to one another.

[0042] Next, the operation of the semiconductor device 30 of this embodiment will be described separately for forward conduction and reverse recovery.

[0043] FIG. 5 is a schematic diagram showing the flow of holes during forward conduction in the semiconductor device of Example 1.

[0044] 5 , as shown by (+) on the anode side and (-) on the cathode side, the anode side has a higher potential than the cathode side, and during forward conduction when a forward voltage is applied between the anode and cathode, a large number of carriers are accumulated in drift layer 5. Carriers (holes) injected from the anode side are not only injected from second electrode 12 via second semiconductor layer 2 into drift layer 5 of active region 31 as indicated by arrow E, but also diffuse and are injected into drift layer 5 of termination region 32 via second electrode 12 via second semiconductor layer 2, fourth semiconductor layer 4, and third semiconductor layer 3 as indicated by arrow F, where they are accumulated.

[0045] In this embodiment, because the third semiconductor layer 3 and the fourth semiconductor layer 4 are not directly connected to the second electrode 12, carriers (holes) are injected into the drift layer 5 of the termination region 32 via the second semiconductor layer 2, the fourth semiconductor layer 4, and the third semiconductor layer 3. The fourth semiconductor layer 4 has a lower impurity concentration than the second semiconductor layer 2, and therefore functions as a high-resistance layer with a high sheet resistance (R). As a result, the hole current injected into the termination region 32 passes through the fourth semiconductor layer 4, which has a high sheet resistance (R), as indicated by arrow F. This allows the amount of holes injected into the termination region 32 to be suppressed even if the distance L from the edge of the region where the second electrode 12 and the second semiconductor layer 2 directly contact each other to the termination region 32 is short. The third semiconductor layer 3 has a higher impurity concentration than the second semiconductor layer 2, resulting in a low resistance. However, if the sheet resistance (R) of the fourth semiconductor layer 4 is sufficiently large, the effect on the required distance L is small.

[0046] Therefore, compared to when the second semiconductor layer 2, the third semiconductor layer 3, and the fourth semiconductor layer 4 all have the same impurity concentration, even if the distance L is short, the amount of carriers (holes) accumulated in the drift layer 5 of the termination region 32 can be reduced, thereby suppressing an increase in the chip area of ​​the semiconductor device 30.

[0047] FIG. 6 is a schematic diagram showing the flow of holes during reverse recovery in the semiconductor device of Example 1.

[0048] As shown in Figure 6, with the anode side (-) and the cathode side (+), the anode side has a lower potential than the cathode side, and during the off state (reverse recovery) when a high voltage is applied in the reverse direction between the anode and cathode, carriers accumulated in the drift layer 5 are discharged. Because the cathode has a higher potential than the anode, holes accumulated in the drift layer 5 flow toward the second electrode 12 and are discharged, as indicated by arrow G. At this time, not only holes accumulated in the drift layer 5 in the active region 31 but also holes accumulated in the drift layer 5 in the termination region 32, as indicated by arrow H, flow into the second semiconductor layer 2. For this reason, current and electric field concentrate at the termination portion of the second semiconductor layer 2, causing a dynamic avalanche, which may increase the temperature and destroy the diode 33.

[0049] In this embodiment, as described above, the amount of carriers (holes) injected into and accumulated in the drift layer 5 of the termination region 32 during forward conduction is reduced. This reduces current and electric field concentration during hole discharge during reverse recovery. Furthermore, because the impurity concentration of the third semiconductor layer 3 is set higher than that of the second semiconductor layer 2, the third semiconductor layer 3 functions as a low-resistance layer, and holes are more likely to collect in the third semiconductor layer 3 than when the impurity concentration of the third semiconductor layer 3 is the same as that of the second semiconductor layer 2. As a result, during reverse recovery, most of the holes accumulated in the drift layer 5 of the termination region 32 pass through the third semiconductor layer 3, the fourth semiconductor layer 4, and the second semiconductor layer 2, as indicated by arrow H, and then flow into the second electrode 12. Since the holes pass through the fourth semiconductor layer 4, which has a high sheet resistance (R), the current does not flow all at once. Instead, the current is dispersed over time, reducing the current density. This reduces current concentration at the termination portion of the second semiconductor layer 2 during reverse recovery. As a result, the electric field at the end portion of the second semiconductor layer 2 is suppressed, making it difficult for dynamic avalanche to occur, and even if the distance L is short, the blocking capability of the diode 33 is increased, thereby achieving high breakdown capability.

[0050] Thus, according to this embodiment, it is possible to suppress current concentration at the end of the active region 31 while suppressing an increase in chip area, and it is possible to realize a semiconductor device 30 with high interruption resistance and a power conversion device 130 using the same.

[0051] Modification of First Embodiment FIG. 7 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment.

[0052] In this modification, the fourth semiconductor layer 4 is of the second conductivity type, and has a configuration in which the depth of the bottom is shallower than the depths of the bottoms of the second semiconductor layer 2 and the fourth semiconductor layer 4. Such a fourth semiconductor layer 4 can be formed, for example, by forming the second semiconductor layer 2 and the third semiconductor layer 3 and then connecting them by lateral diffusion of impurities.

[0053] In this modification, the impurity concentration of the fourth semiconductor layer 4 can be made lower (the sheet resistance can be made higher) compared to Example 1. This is because the fourth semiconductor layer 4 is formed only by lateral diffusion of impurities from the second semiconductor layer 2 and the third semiconductor layer 3, rather than by introducing additional impurities using a method such as ion implantation, and therefore the impurity concentration of the fourth semiconductor layer 4 is relatively lower and the sheet resistance is higher compared to the case of ion implantation.

[0054] According to this modification, the sheet resistance of the fourth semiconductor layer 4 can be made even higher than in the first embodiment, so that current concentration can be more effectively suppressed and the interruption resistance of the semiconductor device 30 can be increased. Alternatively, if the interruption resistance is the same, the distance L can be further shortened and the chip area can be reduced.

[0055] FIG. 8 is a cross-sectional view of a semiconductor device according to a second embodiment.

[0056] Example 2 is a modified example of Example 1, in which the semiconductor device 30 has a first insulating film 13 that covers at least the fourth semiconductor layer 4, and a portion of the second electrode 12 is formed on the first insulating film 13 and covers at least the fourth semiconductor layer 4 via the first insulating film 13.

[0057] According to this embodiment, the second electrode 12 extends so as to cover at least the fourth semiconductor layer 4, and thus the extending portion (the portion having the distance L1 in FIG. 8 ) is formed on the fourth semiconductor layer 4 via the first insulating film 13 as a field plate connected to the second electrode 12. Therefore, during forward conduction in which the potential of the anode is higher than that of the cathode, the depletion layer is more likely to extend on the surface of the fourth semiconductor layer 4, and the sheet resistance of the fourth semiconductor layer 4 increases further than in Example 1. As a result, the amount of holes injected into the termination region 32 can be suppressed more than in Example 1. Therefore, even if the distance L is short, the amount of carriers (holes) accumulated in the drift layer 5 of the termination region 32 can be reduced.

[0058] Furthermore, during reverse recovery, when the potential of the cathode becomes higher than that of the anode, the field plate effect of the protruding portion widens the spacing between the equipotential lines in the fourth semiconductor layer 4. As a result, the potential difference (ΔV in FIG. 8 ) on the current path from the fourth semiconductor layer 4 to the second semiconductor layer 2 is reduced compared to Example 1, making it possible to effectively suppress current concentration. Therefore, the electric field in this region is suppressed, making it less likely for dynamic avalanche to occur, thereby increasing the interruption capability of the semiconductor device 30.

[0059] (Modification of Second Embodiment) FIG. 9 is a cross-sectional view of a semiconductor device according to a modification of the second embodiment.

[0060] The semiconductor device 30 of this modified example has a direct connection region in which the second electrode 12 and the second semiconductor layer 2 are in direct contact at least in part, and it is desirable that the planar distance (Δ in FIG. 8) between the end of the direct connection region (I in FIG. 8) and the boundary (J in FIG. 8) between the second semiconductor layer 2 and the third semiconductor layer 3 is 5 μm or less.

[0061] 9 shows the case where Δ=0 and I and J are the same. However, it is acceptable to ensure that the depletion layer on the surface of the fourth semiconductor layer 4 does not overlap the second semiconductor layer 2 (for example, up to about Δ=5 μm). Therefore, it is desirable that Δ≦5 μm.

[0062] In Example 2, during reverse recovery, when holes accumulated in drift layer 5 in termination region 32 flow toward second electrode 12 as indicated by arrow H in Figure 9, the potential of fourth semiconductor layer 4 increases by the product of the sum of the sheet resistances of second semiconductor layer 2 and fourth semiconductor layer 4 and the current flowing laterally through second semiconductor layer 2 and fourth semiconductor layer 4 during reverse recovery. As a result, the maximum electric field strength applied to first insulating film 13 between fourth semiconductor layer 4 and second electrode 12 increases, which may shorten the life of the insulating film.

[0063] In this modified example, by setting Δ≦5 μm, the contribution of the second semiconductor layer 2 to the sheet resistance is reduced, so that the potential of the fourth semiconductor layer 4 decreases and the maximum electric field strength applied to the first insulating film 13 is reduced, thereby working to ensure the life of the insulating film.

[0064] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment.

[0065] Example 3 is a modified example of Example 2, and is an example in which the semiconductor device 30 has a first insulating film 13 that covers at least the fourth semiconductor layer 4 and a field plate 14 formed inside the first insulating film 13, and the field plate 14 is electrically connected to the second electrode 12 and covers at least the fourth semiconductor layer 4 via the first insulating film 13.

[0066] According to this embodiment, the field plate 14 electrically connected to the second electrode 12 reduces the distance between the second electrode 12 and the fourth semiconductor layer 4 compared to that in the second embodiment. During forward conduction, in which the potential of the anode is higher than that of the cathode, the depletion layer at the surface of the fourth semiconductor layer 4 is more likely to extend than in the second embodiment, further increasing the sheet resistance of the fourth semiconductor layer 4. As a result, the amount of holes injected into the termination region 32 can be more effectively suppressed. Therefore, even if the distance L is short, the amount of carriers (holes) accumulated in the drift layer 5 of the termination region 32 can be reduced.

[0067] Furthermore, due to the field plate 14 electrically connected to the second electrode 12, the distance between the second electrode 12 and the fourth semiconductor layer 4 is shorter than in Example 2. During reverse recovery, when the potential of the cathode is higher than that of the anode, the field plate effect of the field plate 14 is further enhanced, further widening the spacing between the equipotential lines in the fourth semiconductor layer 4. As a result, the potential difference (ΔV in FIG. 10 ) on the current path from the fourth semiconductor layer 4 to the second semiconductor layer 2 is further reduced, making it possible to more effectively suppress current concentration. Therefore, the electric field in this region is suppressed, making it less likely that a dynamic avalanche will occur, thereby increasing the interruption capability of the semiconductor device 30.

[0068] FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth embodiment.

[0069] Example 4 is a modification of Example 3, and is an example in which a semiconductor device 30 has a first insulating film 13 that covers at least the fourth semiconductor layer 4, a field plate 14 formed inside the first insulating film 13, and a bias application electrode 15 for applying a biased voltage to the second electrode 12, and the field plate 14 is electrically connected to the bias application electrode 15 and covers at least the fourth semiconductor layer 4 via the first insulating film 13.

[0070] According to this example, when the bias application electrode 15 is positively biased with respect to the second electrode 12, the positively biased field plate 14 makes it easier for the depletion layer to extend at the surface of the fourth semiconductor layer 4 than in Example 3, further increasing the sheet resistance of the fourth semiconductor layer 4. As a result, the amount of holes injected into the termination region 32 can be more effectively suppressed. Therefore, even if the distance L is short, the amount of carriers (holes) accumulated in the drift layer 5 of the termination region 32 can be reduced.

[0071] Furthermore, when the bias application electrode 15 is positively biased with respect to the second electrode 12, the positively biased field plate 14 makes it easier for the depletion layer to extend on the surface of the fourth semiconductor layer 4 than in Example 3, and even during reverse recovery when the potential of the cathode becomes higher than that of the anode, the sheet resistance on the path of the hole current from the fourth semiconductor layer 4 to the second semiconductor layer 2 increases, making it possible to effectively suppress current concentration. Therefore, the electric field in that region is suppressed and dynamic avalanche is less likely to occur, thereby increasing the interruption capability of the semiconductor device 30.

[0072] (Modification of Fourth Embodiment) In a modification of the fourth embodiment, a MOS controlled diode 41 is used instead of the diode 33 in the fourth embodiment.

[0073] FIG. 12 is a cross-sectional view illustrating the structure of a MOS control diode used in a semiconductor device according to a modification of the fourth embodiment.

[0074] In the semiconductor device 30 of this modified example, the first conductivity type is n-type and the second conductivity type is p-type. The diode 33 has a first electrode 11, a second electrode 12, a first semiconductor layer 1, a second semiconductor layer 2, and a drift layer 5, similar to the fourth embodiment, and further has a gate electrode 42 to which a biased voltage is applied relative to the second electrode 12, and a gate insulating film 43 provided between the gate electrode 42 and the second semiconductor layer 2, and the bias application electrode 15 and the gate electrode 42 are electrically connected.

[0075] 12, a low concentration p-type is used as the second semiconductor layer 2, but this is not limiting. Even when a low concentration p-type is used as the second semiconductor layer 2, the impurity concentration of the third semiconductor layer 3 is made higher than that of the second semiconductor layer 2, and the impurity concentration of the fourth semiconductor layer 4 is made lower than that of the second semiconductor layer 2, as in the other examples.

[0076] 12, the gate electrode 42 is a so-called side gate type gate electrode 42 formed on the side wall of the wide trench 47, but this is not limiting. For example, the gate electrode 42 may be formed inside a normal trench that is not wide. In the case of a normal trench, the interlayer insulating film 48 provided inside the wide trench 47 does not need to be provided inside the normal trench.

[0077] In addition, in FIG. 12, the second electrode 12 and the second semiconductor layer 2 are electrically connected via the P+ layer 45, or via the P+ layer 45 and the P layer 44, or via the n+ layer 46 and the P layer 44, but this is not limited to this.

[0078] FIG. 13 is a timing chart illustrating a method for controlling a semiconductor device and a power conversion device according to a modification of the fourth embodiment.

[0079] The power conversion device 130 of this modification has a drive device (not shown) that applies drive signals (DG1, DG2) to the gate electrode 42 and bias application electrode 15 of the semiconductor device 30 of this modification that is used as the freewheeling diode 137. Similarly, in the fourth embodiment, the power conversion device 130 also has a drive device (not shown) that applies a bias voltage to the bias application electrode 15 of the semiconductor device 30 of the fourth embodiment that is used as the freewheeling diode 137. These drive devices are controlled by a drive command signal (not shown) from the command logic unit 132.

[0080] 13, at time t1, when drive command signal P2 from command logic unit 132 switches from H level to L level, gate driver 139 switches gate signal G2 applied to the gate of lower-arm semiconductor switching element 136 from +15 V to −15 V, turning off lower-arm semiconductor switching element 136. This initiates forward conduction period T1 during which upper-arm freewheel diode 137 is forward conductive. At this time, drive signal DG1 applied to gate electrode 42 of upper-arm freewheel diode 137 and bias application electrode 15 is a negative bias of −15 V.

[0081] At time t2, which is after dead time DT from time t1, drive command signal P1 from command logic unit 132 switches from L level to H level, and gate driver 139 switches gate signal G1 applied to the gate of upper-arm semiconductor switching element 136 from −15 V to +15 V, turning on upper-arm semiconductor switching element 136. This starts reverse recovery period td_rr2 of lower-arm freewheel diode 137.

[0082] At time t3, the reverse recovery period td_rr2 of the freewheeling diode 137 of the lower arm ends.

[0083] Time t4 is a predetermined period before time t6. At time t4, drive signal DG1 is switched from a negative bias of −15 V to a positive bias of +15 V. This turns on the MOS gate of MOS control diode 41, and a charge extraction period td_rr1 begins, during which charge is extracted from MOS control diode 41.

[0084] At time t5, the drive command signal P1 switches from H level to L level, and the gate signal G1 switches from +15 V to −15 V. This turns off the upper arm semiconductor switching element 136.

[0085] At time t6, which is after dead time DT from time t5, drive command signal P2 switches from L level to H level, and gate signal G2 switches from −15 V to +15 V. This turns on lower-arm semiconductor switching element 136. As a result, upper-arm freewheel diode 137 transitions to reverse recovery, ending forward conduction period T1 and charge extraction period td_rr1 of upper-arm freewheel diode 137 and starting reverse recovery period td_rr2 of upper-arm freewheel diode 137.

[0086] At time t7, the reverse recovery period td_rr2 of the upper arm freewheel diode 137 ends. At this time, the drive signal DG1 is switched from a positive bias of −15V to a negative bias of −15V.

[0087] By the operation of this modified example, the semiconductor switching element 136 of the lower arm is turned off at time t1, and the current flowing through the load, the electric motor 120, is commutated to the free wheel diode 137 of the upper arm. When the free wheel diode 137 of the upper arm is forward conductive, the drive signal DG1 applied to the gate electrode 42 of the free wheel diode 137 of the upper arm and the bias application electrode 15 is negatively biased (for example, the potential of the gate electrode 42 relative to the potential of the second electrode 12 is −15 V), so that the MOS gate of the MOS control diode 41 is turned off and the diode operates as a normal diode.

[0088] Then, at time t4, which is a predetermined period (charge extraction period td_rr1) before the timing at which the lower arm semiconductor switching element 136 turns on at time t6 and the upper arm freewheel diode 137 transitions to reverse recovery, the gate electrode 42 of the upper arm freewheel diode 137 is positively biased (for example, the potential of the gate electrode relative to the potential of the second electrode 12 is +15 V), which turns on the MOS gate of the MOS control diode 41 and creates a channel, so that carriers are extracted to the anode side and the carriers accumulated in the active region 31 are extracted.

[0089] Thereafter, the gate electrode 42 is maintained at a positive bias until reverse recovery of the upper arm freewheel diode 137 is completed at time t7 (reverse recovery period td_rr2), and then returned to a negative bias. Therefore, the positive bias application period T2 during which the gate electrode 42 is positively biased may be the combined period of the charge extraction period td_rr1 and the reverse recovery period td_rr2.

[0090] To summarize the above operations, in this modification, a negative bias voltage is applied to the gate electrode 42 and the bias application electrode 15 when the diode 33 (MOS control diode 41 in this modification) is in forward conduction, and a positive bias voltage is applied to the gate electrode 42 and the bias application electrode 15 during a predetermined period before the diode 33 transitions to reverse recovery (charge extraction period td_rr1) and during a period from when the diode 33 transitions to reverse recovery until the transition is completed (reverse recovery period td_rr2).

[0091] According to this modification, during the charge extraction period td_rr1, the field plate 14, which is positively biased with respect to the second electrode 12, makes it easier for the depletion layer to extend on the surface of the fourth semiconductor layer 4, as in the fourth embodiment, and further increases the sheet resistance of the fourth semiconductor layer 4. As a result, the amount of holes injected into the termination region 32 can be more effectively suppressed.

[0092] Furthermore, during the charge extraction period td_rr1, the MOS gate of the MOS control diode 41 is turned on, thereby extracting the carriers accumulated in the active region 31, thereby reducing the amount of accumulated holes diffusing into the termination region 32 more than in the fourth embodiment.

[0093] Therefore, even if the distance L is short, the amount of carriers (holes) accumulated in the drift layer 5 in the termination region 32 can be reduced.

[0094] Furthermore, during the reverse recovery period td_rr2, the field plate 14, which is positively biased with respect to the second electrode 12, makes it easier for the depletion layer to extend on the surface of the fourth semiconductor layer 4, as in Example 4, and also during reverse recovery when the potential of the cathode becomes higher than that of the anode, the sheet resistance on the path of the hole current from the fourth semiconductor layer 4 to the second semiconductor layer 2 increases.

[0095] Furthermore, due to the effect of charge extraction caused by the MOS gate of MOS control diode 41 being turned on during charge extraction period td_rr1, the amount of accumulated holes diffused into termination region 32 is sufficiently reduced compared to Example 4 immediately before reverse recovery.

[0096] Therefore, current concentration can be effectively suppressed. Furthermore, the electric field in the region is suppressed, making it difficult for dynamic avalanche to occur, and as a result, the interruption capability of the semiconductor device 30 can be increased.

[0097] Furthermore, since reverse recovery occurs in a state where carriers accumulated in the active region 31 have been sufficiently extracted, the reverse recovery charge is reduced, and the recovery loss of the diode 33 of the semiconductor device 30 is reduced.

[0098] Furthermore, the voltage applied to the gate electrode 42 of the MOS control diode 41 can be used as the voltage applied to the bias application electrode 15 .

[0099] The fifth embodiment is a modification of the power conversion devices of the first to fourth embodiments.

[0100] The semiconductor switching element 136 used in the power conversion device 130 is not limited to an IGBT. The semiconductor material may also be changed to Si, SiC, GaN, gallium oxide, etc. Furthermore, the device can be used in power conversion devices in general, not just for hybrid vehicles, electric vehicles, and railroad applications.

[0101] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied.

[0102] The impurity concentration is also an example, and can be changed as appropriate within a range that allows the intended operation of the embodiment to be realized.

[0103] 1: First semiconductor layer (cathode layer) 2: Second semiconductor layer (anode layer) 3: Third semiconductor layer 4: Fourth semiconductor layer 5: Drift layer 11: First electrode (cathode electrode) 12: Second electrode (anode electrode) 13: First insulating film 14: Field plate 15: Bias application electrode 21: Withstand voltage holding layer 22: Channel stopper 23: Second insulating film 24: Termination section field plate 30: Semiconductor device 31: Active region 32: Termination region 33: Diode 41: MOS control diode 42: Gate electrode 43: Gate insulating film 44: P layer 45: P+ layer 46: n+ layer 47: Trench 48: Interlayer insulating film 100: Motor control system 110: DC power supply 120: Motor 130: Power conversion device 131: Smoothing capacitor 132: Command logic unit 133: Positive electrode connecting wire 134: Negative electrode connecting wire 135: Inverter unit 136: Semiconductor switching element 137: Freewheeling diode 138: Connection point 139: Gate driving device x: Horizontal distance IC: Impurity concentration DT: Dead time td_rr1: Charge extraction period td_rr2: Reverse recovery period

Claims

1. A semiconductor device having an active region with a diode and a termination region surrounding the active region, wherein the diode includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type electrically connected to the first electrode, a drift layer of the first conductivity type having an impurity concentration lower than that of the first semiconductor layer, and a second semiconductor layer of a second conductivity type in contact with the drift layer and electrically connected to the second electrode; the active region has, between the diode and the termination region, a third semiconductor layer of the second conductivity type in contact with the drift layer and disposed on the side of the second semiconductor layer with respect to the drift layer, and a fourth semiconductor layer disposed between the second semiconductor layer and the third semiconductor layer; the third semiconductor layer and the fourth semiconductor layer are not directly connected to the second electrode; the third semiconductor layer has an impurity concentration higher than that of the second semiconductor layer; and the fourth semiconductor layer has a second conductivity type or a first conductivity type and an impurity concentration lower than that of the second semiconductor layer.

2. The semiconductor device according to claim 1, wherein the fourth semiconductor layer has a second conductivity type.

3. The semiconductor device according to claim 1, wherein the fourth semiconductor layer has a second conductivity type and a bottom depth shallower than the bottom depths of the second semiconductor layer and the fourth semiconductor layer.

4. The semiconductor device according to claim 1, having a first insulating film covering at least the fourth semiconductor layer, wherein a part of the second electrode is formed on the first insulating film and covers at least the fourth semiconductor layer via the first insulating film.

5. The semiconductor device according to claim 1, having a direct connection region where the second electrode and the second semiconductor layer are at least partially in direct contact, and a planar distance between an end of the direct connection region and a boundary between the second semiconductor layer and the third semiconductor layer is 5 μm or less.

6. The semiconductor device according to claim 1, having a first insulating film covering at least the fourth semiconductor layer and a field plate formed inside the first insulating film, wherein the field plate is electrically connected to the second electrode and covers at least the fourth semiconductor layer via the first insulating film.

7. In claim 1, there is a first insulating film covering at least the fourth semiconductor layer, a field plate formed inside the first insulating film, and a bias application electrode for applying a voltage biased with respect to the second electrode. The field plate is electrically connected to the bias application electrode and covers at least the fourth semiconductor layer via the first insulating film. A semiconductor device characterized by this.

8. In claim 7, the first conductivity type is n-type, the second conductivity type is p-type, the diode has a gate electrode to which a voltage biased with respect to the second electrode is applied, and a gate insulating film provided between the gate electrode and the second semiconductor layer. A semiconductor device characterized in that the bias application electrode and the gate electrode are electrically connected.

9. In claim 8, when the diode is forward-conducting, a negative bias voltage is applied to the gate electrode and the bias application electrode, and a positive bias voltage is applied during a predetermined period before the diode transitions to reverse recovery and during the period from when the diode transitions to reverse recovery until completion. A semiconductor device characterized by this.

10. In claim 1, the impurity concentration of the second semiconductor layer is 1×10 １４ / cm ３ to 1×10 １６ / cm ３ ; the impurity concentration of the third semiconductor layer is 1×10 １６ / cm ３ to 1×10 １８ / cm ３ ; and the impurity concentration of the fourth semiconductor layer is 1×10 １２ / cm ３ to 1×10 １４ / cm ３ A semiconductor device characterized by this.

11. In claim 1, the impurity concentration of the third semiconductor layer is 10 １ to 10 ２ times that of the second semiconductor layer, and the impurity concentration of the fourth semiconductor layer is 10 －１ to 10 －２ times that of the second semiconductor layer. A semiconductor device characterized by this.

12. In claim 1, the first conductivity type is n-type and the second conductivity type is p-type. A semiconductor device characterized by this.

13. A power conversion device that converts DC power into AC power, characterized by having a freewheeling diode using the semiconductor device according to any one of claims 1 to 12.

Images