Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device A1 comprises: a support 1; a first semiconductor element 5A that is supported by the support 1 and positioned on a first side z1 of the support 1 with respect to a first direction z; a first metal layer 3A that is interposed between the support 1 and the first semiconductor element 5A; and a first bonding layer 4A that is interposed between the support 1 and the first metal layer 3A. The first bonding layer 4A has a recess 45 that is recessed on a second side z2 along the first direction z. This configuration enables more appropriate bonding to be achieved.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes a support substrate and a semiconductor element. The semiconductor element is bonded by solid-state diffusion bonding via an intermediate metal layer.

[0003] JP 2022-63488 A

[0004] [Summary] If the bonding of a semiconductor element is insufficient, the semiconductor device may not be able to fully function.

[0005] The present disclosure has been made in light of the above circumstances, and an object of the present disclosure is to provide a semiconductor device that allows for more appropriate bonding and a method for manufacturing the semiconductor device.

[0006] A semiconductor device provided by a first aspect of the present disclosure comprises a support, a first semiconductor element located on a first side of the support in a first direction and supported by the support, a first metal layer interposed between the support and the first semiconductor element, and a first bonding layer interposed between the support and the first metal layer, wherein the first bonding layer has a recess recessed toward a second side in the first direction.

[0007] A semiconductor device provided by a second aspect of the present disclosure comprises a support, a first semiconductor element located on a first side of the support in a first direction and supported by the support, a heat sink located on a second side of the support in the first direction, and a fifth bonding layer interposed between the support and the heat sink, wherein the fifth bonding layer has a recess recessed toward the second side in the first direction.

[0008] A method for manufacturing a semiconductor device provided by a third aspect of the present disclosure includes the steps of placing a first bonding layer on a support, fixing the first bonding layer to the support, placing a first metal layer on the first bonding layer, placing a first semiconductor element on the first metal layer, and bonding the support, the first bonding layer, and the first metal layer by solid-state diffusion bonding.

[0009] A fourth aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising the steps of placing a fifth bonding layer on a heat sink, fixing the fifth bonding layer to the heat sink, placing a support on the fifth bonding layer, placing a first semiconductor element in a position overlapping the support when viewed in a first direction, and bonding the heat sink, the fifth bonding layer, and the support by solid-state diffusion bonding.

[0010] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0011] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 is a partially enlarged cross-sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a partially enlarged plan view showing a recess in the semiconductor device according to the first embodiment of the present disclosure. FIG. 6 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 7 is a partially enlarged cross-sectional view taken along line VII-VII in FIG. 6. FIG. 8 is a system configuration diagram showing a vehicle equipped with the semiconductor device according to the first embodiment of the present disclosure. FIG. 9 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 10 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 11 is a partially enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 12 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 13 is a partial plan view showing another example of a recess in the semiconductor device according to the first embodiment of the present disclosure. FIG. 14 is a partial plan view showing yet another example of a recess in the semiconductor device according to the first embodiment of the present disclosure. FIG. 15 is a partial plan view showing yet another example of a recess in the semiconductor device according to the first embodiment of the present disclosure. FIG. 16 is a partial plan view showing yet another example of a recess in the semiconductor device according to the first embodiment of the present disclosure. FIG. 17 is a partial plan view showing yet another example of a recess in the semiconductor device according to the first embodiment of the present disclosure. FIG. 18 is a partial plan view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 19 is a partial plan view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 20 is a partial plan view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 21 is a partial plan view showing a fourth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 22 is a partial plan view showing a fifth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 23 is a cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 24 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 25 is a cross-sectional view showing a method for manufacturing the semiconductor device according to the second embodiment of the present disclosure. FIG. 26 is a cross-sectional view showing a method for manufacturing the semiconductor device according to the second embodiment of the present disclosure.Fig. 27 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment of the present disclosure. Fig. 28 is a cross-sectional view showing a first modified example of the semiconductor device according to the second embodiment of the present disclosure. Fig. 29 is a partially enlarged cross-sectional view showing the first modified example of the semiconductor device according to the second embodiment of the present disclosure. Fig. 30 is a cross-sectional view showing a second modified example of the semiconductor device according to the second embodiment of the present disclosure. Fig. 31 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second modified example of the second embodiment of the present disclosure. Fig. 32 is a cross-sectional view showing a third modified example of the semiconductor device according to the second embodiment of the present disclosure.

[0012] DETAILED DESCRIPTION Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0013] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0014] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0015] 1 to 7 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a support 1, a first metal layer 3A, a first bonding layer 4A, and one or more first semiconductor elements 5A. In this embodiment, the semiconductor device A1 may further include one or more second bonding layers 6A, one or more second semiconductor elements 5B, one or more fourth bonding layers 6B, a fourth metal layer 3B, a positive input terminal 7A, an output terminal 7B, a negative input terminal 7C, a plurality of control terminals 7D, a plurality of control terminals 7E, a plurality of first wires 8A, a plurality of second wires 8B, a plurality of third wires 8C, a plurality of fourth wires 8D, and a sealing resin 9.

[0016] In these figures, one side of the first direction z is referred to as the first side z1, and the other side is referred to as the second side z2. Furthermore, a direction perpendicular to the first direction z is defined as the second direction x. One side of the second direction x is referred to as the first side x1, and the other side opposite the first side x1 is referred to as the second side x2. Furthermore, a direction perpendicular to the first direction z and the second direction x is defined as the third direction y. One side of the third direction y is referred to as the first side y1, and the other side is referred to as the second side y2.

[0017] The specific use of the semiconductor device A1 is not limited in any way. In the semiconductor device A1, a plurality of first semiconductor elements 5A form an upper arm circuit, and a plurality of second semiconductor elements 5B form a lower arm circuit, thereby forming a half-bridge circuit. The semiconductor device A1 forms, for example, an inverter that converts DC power to AC power and supplies power to a drive source such as a motor. Although the semiconductor device A1 of this embodiment will be described using an example in which it has one half-bridge circuit, it may also be configured to have, for example, three half-bridge circuits, thereby supplying power to a so-called three-phase AC motor.

[0018] Each of the multiple first semiconductor elements 5A and the multiple second semiconductor elements 5B may be configured using a semiconductor material primarily containing SiC (silicon carbide). The semiconductor material is not limited to SiC and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like. In this embodiment, the first semiconductor element 5A and the second semiconductor element 5B may be MOSFETs (metal-oxide-semiconductor field effect transistors). The first semiconductor element 5A and the second semiconductor element 5B may be field-effect transistors including MISFETs (metal-insulator-semiconductor FETs), bipolar transistors such as IGBTs (insulated gate bipolar transistors), IC chips such as LSIs, diodes, capacitors, or the like.

[0019] 6 and 7 , the first semiconductor element 5A of this embodiment may have an element body 50, a drain electrode 51, a source electrode 52, a gate electrode 53, and a source sense electrode 54. The element body 50 may be made of the semiconductor material described above. The drain electrode 51 is disposed on a second side z2 of the element body 50 in the first direction z. The source electrode 52, the gate electrode 53, and the source sense electrode 54 are disposed on a first side z1 of the element body 50 in the first direction z. The second semiconductor element 5B may have an element body 50, a drain electrode 51, a source electrode 52, a gate electrode 53, and a source sense electrode 54, similar to the first semiconductor element 5A.

[0020] As shown in FIGS. 2 and 3, the support 1 can have an insulating layer 10, a back metal layer 11, a second metal layer 2A, and a fifth metal layer 2B.

[0021] The insulating layer 10 may be an insulating plate-like member containing, for example, ceramic. The back surface metal layer 11 is laminated on a second side z2 in the first direction z of the insulating layer 10. The back surface metal layer 11 may contain a metal such as Cu (copper). The second metal layer 2A is laminated on a first side z1 in the first direction z of the insulating layer 10 on a first side x1 in the second direction x. The fifth metal layer 2B is laminated on a first side z1 in the first direction z of the insulating layer 10 on a second side x2 in the second direction x. The second metal layer 2A and the fifth metal layer 2B are separated from each other. The insulating layer 10, the back surface metal layer 11, the second metal layer 2A, and the fifth metal layer 2B may form, for example, a DBC (Direct Bonded Copper) substrate or an AMB (Active Metal Brazing) substrate.

[0022] As shown in FIG. 4 , the second metal layer 2A may include a substrate layer 20 and a surface metal layer 21. The substrate layer 20 may include, for example, Cu (copper). The surface metal layer 21 is located on a first side z1 in the first direction z with respect to the substrate layer 20. The thickness of the surface metal layer 21 in the first direction z is thinner than the thickness of the substrate layer 20 in the first direction z. The surface metal layer 21 may include, for example, Ag (silver). Like the second metal layer 2A, the fifth metal layer 2B may include a substrate layer 20 and a surface metal layer 21. The thickness of the substrate layer 20 is not particularly limited and may be, for example, 0.1 mm or more and 5 mm or less. The thickness of the surface metal layer 21 is not particularly limited and may be, for example, 0.1 μm or more and 30 μm or less.

[0023] The first metal layer 3A is bonded to the second metal layer 2A via a first bonding layer 4A. The first metal layer 3A may include a base layer 30 and a surface metal layer 31. The base layer 30 may include a metal such as Cu (copper). The surface metal layer 31 is located on a second side z2 in the first direction z relative to the base layer 30. The thickness of the surface metal layer 31 in the first direction z is thinner than the thickness of the base layer 30 in the first direction z. The surface metal layer 31 may include Ag (silver). The thickness of the base layer 30 is not limited and may be, for example, 0.5 mm or more and 20 mm or less. The thickness of the surface metal layer 31 is not limited and may be, for example, 0.1 μm or more and 30 μm or less. In this example, the thicknesses of the first metal layer 3A and the fourth metal layer 3B are thicker than the thicknesses of the second metal layer 2A and the fifth metal layer 2B.

[0024] The first bonding layer 4A is for bonding the second metal layer 2A and the first metal layer 3A by solid-state diffusion bonding. The specific configuration of the first bonding layer 4A is not limited in any way. As shown in FIG. 4 , in the illustrated example, the first bonding layer 4A can include a base layer 40, a surface metal layer 41, and a surface metal layer 42.

[0025] The substrate layer 40 may contain a material softer than the material of the substrate layer 30, such as Al (aluminum). The surface metal layer 41 is located on a first side z1 in the first direction z of the substrate layer 40. The thickness of the surface metal layer 41 in the first direction z is thinner than the thickness of the substrate layer 40 in the first direction z. The surface metal layer 41 may contain, for example, Ag (silver). The surface metal layer 42 is located on a second side z2 in the first direction z of the substrate layer 40. The thickness of the surface metal layer 42 in the first direction z is thinner than the thickness of the substrate layer 40 in the first direction z. The surface metal layer 42 may contain, for example, Ag (silver). The thickness of the substrate layer 40 is not limited and may be, for example, 0.01 mm or more and 0.5 mm or less. The thickness of the surface metal layer 41 is not limited and may be, for example, 0.1 μm or more and 30 μm or less. The thickness of the surface metal layer 42 is not limited and may be, for example, 0.1 μm or more and 30 μm or less.

[0026] The surface metal layer 31 and the surface metal layer 41 are bonded by solid-state diffusion bonding. The surface metal layer 21 and the surface metal layer 42 are bonded by solid-state diffusion bonding.

[0027] The fourth metal layer 3B is bonded to the fifth metal layer 2B via a third bonding layer 4B. The fourth metal layer 3B may include, for example, a base layer 30 and a surface metal layer 31 similar to those of the first metal layer 3A.

[0028] The third bonding layer 4B is for bonding the fifth metal layer 2B and the fourth metal layer 3B by solid-state diffusion bonding. The specific configuration of the third bonding layer 4B is not limited in any way, and the third bonding layer 4B can include, for example, a base layer 40, a surface metal layer 41, and a surface metal layer 42 similar to those of the first bonding layer 4A.

[0029] As shown in FIGS. 2 to 5 , the first bonding layer 4A has one or more recesses 45. The recesses 45 are recessed from a first side z1 to a second side z2 in the first direction z. The recesses 45 may be pressure marks formed when the first bonding layer 4A is temporarily bonded to the second metal layer 2A in the manufacturing method of the semiconductor device A1 described later. In this example, the recesses 45 are formed at least in the surface metal layer 41. The recesses 45 may also be formed in the base layer 40. The depth of the recesses 45 is not limited and may be on the order of several μm or several tens of μm. The recesses 45 may form voids and may be filled with the surface metal layer 31. The shape of the recesses 45 as viewed in the first direction z is not limited and may be a circle as shown in FIG. 5 .

[0030] In this example, the first bonding layer 4A has two recesses 45. The two recesses 45 are located apart in the third direction y. The two recesses 45 may be located on a first side x1 in the second direction x with respect to the first semiconductor element 5A. The recesses 45 may be spaced apart from the first semiconductor element 5A when viewed in the first direction z. A distance D1 between the recesses 45 and the edge of the first bonding layer 4A may be shorter than a distance D2 between the recesses 45 and the first semiconductor element 5A.

[0031] The third bonding layer 4B may have one or more recesses 45. In this example, the third bonding layer 4B has two recesses 45. The two recesses 45 are located apart in the third direction y. The two recesses 45 may be located on the second side x2 in the second direction x with respect to the second semiconductor element 5B. The recesses 45 may be spaced apart from the second semiconductor element 5B when viewed in the first direction z.

[0032] The plurality of first semiconductor elements 5A may be conductively bonded to the first metal layer 3A via a plurality of second bonding layers 6A. In this embodiment, the drain electrodes 51 of the first semiconductor elements 5A may be conductively bonded to the first metal layer 3A via the second bonding layer 6A. The second bonding layer 6A may be used to conductively bond the first semiconductor elements 5A and the first metal layer 3A, for example, by solid-state diffusion bonding. The specific configuration of the second bonding layer 6A is not limited in any way. When solid-state diffusion bonding is used, the second bonding layer 6A may be configured such that metal layers containing, for example, Ag (silver) are formed on both sides of a base layer containing, for example, Al (aluminum). In this case, metal layers containing, for example, Ag (silver) may be formed on the surfaces of the first semiconductor elements 5A and the first metal layer 3A. This allows, for example, the drain electrodes 51 of the plurality of first semiconductor elements 5A to be conductively connected to the first metal layer 3A. There are no particular limitations on the shape of the second bonding layer 6A, and in the illustrated example, it may be rectangular.

[0033] The plurality of second semiconductor elements 5B may be conductively bonded to the fourth metal layer 3B via a plurality of fourth bonding layers 6B. In this embodiment, the drain electrodes 51 of the second semiconductor elements 5B may be conductively bonded to the fourth metal layer 3B via the fourth bonding layer 6B. The fourth bonding layer 6B may be used to conductively bond the second semiconductor elements 5B and the fourth metal layer 3B, for example, by solid-state diffusion bonding. The specific configuration of the fourth bonding layer 6B is not limited in any way. When solid-state diffusion bonding is used, the fourth bonding layer 6B may be configured such that metal layers containing, for example, Ag (silver) are formed on both sides of a base layer containing, for example, Al (aluminum). In this case, metal layers containing, for example, Ag (silver) may be formed on the surfaces of the second semiconductor elements 5B and the fourth metal layer 3B. This allows, for example, the drain electrodes 51 of the plurality of second semiconductor elements 5B to be conductively connected to the fourth metal layer 3B. The specific shape of the fourth bonding layer 6B is not limited in any way, and in the illustrated example, it may be rectangular. The fourth bonding layer 6B may have a configuration similar to or different from the second bonding layer 6A.

[0034] The positive input terminal 7A may be a terminal connected to the positive side of a DC power supply, and may be conductively joined to the first metal layer 3A.

[0035] The output terminal 7B may be a terminal connected to the load side of a motor, etc. The output terminal 7B may be conductively joined to the fourth metal layer 3B.

[0036] The negative input terminal 7C may be a terminal connected to the negative side of a DC power supply. The negative input terminal 7C may be electrically connected to, for example, the source electrodes 52 of the second semiconductor elements 5B via a plurality of second wires 8B. The second wires 8B may include a metal such as copper (Cu), aluminum (Al), or gold (Au).

[0037] For example, the source electrodes 52 of the multiple first semiconductor elements 5A can be electrically connected to the fourth metal layer 3B via multiple first wires 8A. The first wires 8A can include a metal such as copper (Cu), aluminum (Al), or gold (Au).

[0038] The multiple control terminals 7D may be terminals for controlling the multiple first semiconductor elements 5A. The multiple control terminals 7D may be electrically connected to, for example, the gate electrodes 53, source sense electrodes 54, etc. of the multiple first semiconductor elements 5A via multiple third wires 8C. The third wires 8C may include a metal such as copper (Cu), aluminum (Al), or gold (Au).

[0039] The multiple control terminals 7E may be terminals for controlling the multiple second semiconductor elements 5B. The multiple control terminals 7E may be electrically connected to, for example, the gate electrodes 53, source sense electrodes 54, etc. of the multiple second semiconductor elements 5B via the multiple fourth wires 8D. The fourth wires 8D may include a metal such as copper (Cu), aluminum (Al), or gold (Au).

[0040] The sealing resin 9 may cover a portion of the support 1, the first metal layer 3A, the fourth metal layer 3B, the first bonding layer 4A, the third bonding layer 4B, the plurality of first semiconductor elements 5A, the plurality of second semiconductor elements 5B, etc. The positive input terminal 7A, the output terminal 7B, the negative input terminal 7C, the plurality of control terminals 7D, and the plurality of control terminals 7E may each partially protrude from the sealing resin 9. For ease of understanding, the sealing resin 9 is omitted from FIGS. 2 and 7 .

[0041] Next, a vehicle C1 equipped with the semiconductor device A1 will be described with reference to Fig. 8. The vehicle C1 is, for example, an electric vehicle (EV).

[0042] As shown in Fig. 8, vehicle C1 includes an on-board charger 910, a storage battery 920, and a drive system 930. Power is supplied to the on-board charger 910 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 910 via a wired connection. The on-board charger 910 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 910 is stepped up by the converter and then supplied to the storage battery 920. The stepped-up voltage is, for example, 600 V.

[0043] The drive system 930 drives the vehicle C1. The drive system 930 has an inverter 931 and a drive source 932. The semiconductor device A1 constitutes part of the inverter 931. The power stored in the storage battery 920 is supplied to the inverter 931. The power supplied from the storage battery 920 to the inverter 931 is DC power. In addition, unlike the power system shown in FIG. 8 , a step-up DC-DC converter may be further provided between the storage battery 920 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931 including the semiconductor device A1 is electrically connected to the drive source 932.

[0044] The drive source 932 includes an AC motor and a transmission. When AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle C1. This drives the vehicle C1. To drive the vehicle C1, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. The semiconductor device A1 in the inverter 931 is required to output AC power whose frequency has been appropriately changed to correspond to the required rotation speed of the AC motor.

[0045] Next, a method for manufacturing the semiconductor device A1 will be described below with reference to FIGS.

[0046] As shown in FIG. 9 , a support 1 is prepared. Next, the first bonding layer 4A and the third bonding layer 4B are placed on the support 1. The first bonding layer 4A and the third bonding layer 4B may be placed, for example, by holding the first bonding layer 4A and the third bonding layer 4B with a tool T1 and moving the tool T1 as needed. The tool T1 may hold the first bonding layer 4A and the third bonding layer 4B by suction, for example. The first bonding layer 4A is placed on the second metal layer 2A, and the third bonding layer 4B is placed on the fifth metal layer 2B.

[0047] Next, as shown in FIGS. 10 and 11 , the first bonding layer 4A is fixed to the second metal layer 2A. The method for fixing the first bonding layer 4A is not limited, and ultrasonic bonding, welding, metal bonding, etc. may be used as appropriate. Welding includes, for example, laser welding, electric welding, etc. In the illustrated example, the first bonding layer 4A is fixed to the second metal layer 2A by ultrasonic bonding. For example, the first bonding layer 4A may be ultrasonically bonded to the second metal layer 2A by applying pressure to the first bonding layer 4A toward the second side z2 in the first direction z using a tool T2 connected to an ultrasonic generating source (not shown). The pressure mark formed at this time becomes the recess 45. The tip shape of the tool T2 is not limited, and the shape of the recess 45 as viewed in the first direction z can be determined depending on the tip shape of the tool T2. Furthermore, the method for fixing the third bonding layer 4B to the fifth metal layer 2B may be similar to the method for fixing the first bonding layer 4A to the second metal layer 2A, and in the illustrated example, ultrasonic bonding may be adopted.

[0048] The first bonding layer 4A and the second metal layer 2A may be fixed after the first bonding layer 4A is placed on the second metal layer 2A, or may be fixed simultaneously with the step of placing the first bonding layer 4A on the second metal layer 2A. When the steps are performed simultaneously, for example, a tool T1 for holding the first bonding layer 4A and a tool T2 for fixing may be used simultaneously.

[0049] Next, as shown in FIG. 12 , the first metal layer 3A is placed on the first bonding layer 4A. The fourth metal layer 3B may be placed on the third bonding layer 4B. After this, a predetermined temperature and pressure are applied to the second metal layer 2A and the first metal layer 3A with the first bonding layer 4A sandwiched therebetween, thereby performing solid-state diffusion bonding. This bonds the second metal layer 2A, the first bonding layer 4A, and the first metal layer 3A. That is, the surface metal layer 31 and the surface metal layer 41 are bonded by solid-state diffusion bonding. The surface metal layer 21 and the surface metal layer 42 are bonded by solid-state diffusion bonding. Solid-state diffusion bonding may be performed by applying a predetermined temperature and pressure to the fifth metal layer 2B and the fourth metal layer 3B with the third bonding layer 4B sandwiched therebetween. The fifth metal layer 2B, the third bonding layer 4B, and the fourth metal layer 3B may be bonded.

[0050] 12 , and before performing the above-described solid-state diffusion bonding, the second bonding layer 6A and the first semiconductor element 5A may be placed on the first metal layer 3A, and the fourth bonding layer 6B and the second semiconductor element 5B may be placed on the fourth metal layer 3B. In the above-described solid-state diffusion bonding, the first metal layer 3A and the first semiconductor element 5A may be bonded with the second bonding layer 6A sandwiched therebetween, and the fourth metal layer 3B and the second semiconductor element 5B may be bonded with the fourth bonding layer 6B sandwiched therebetween.

[0051] Next, the operation of the semiconductor device A1 will be described.

[0052] According to this embodiment, the first bonding layer 4A has a recess 45. The recess 45 is a pressure mark formed in the process of fixing the first bonding layer 4A to the support 1 shown in FIGS. 10 and 11 . Therefore, it is possible to reduce unintentional displacement of the first bonding layer 4A placed on the second metal layer 2A before solid-state diffusion bonding with the first bonding layer 4A sandwiched therebetween. Therefore, solid-state diffusion bonding with the first bonding layer 4A sandwiched therebetween can be more appropriately performed.

[0053] 2 , the recess 45 is spaced apart from the first semiconductor element 5A when viewed in the first direction z. This reduces the inhibition of heat dissipation by the recess 45 when heat from the first semiconductor element 5A is transferred to the support 1 via the second bonding layer 6A, the first metal layer 3A, and the first bonding layer 4A.

[0054] By making the distance D1 between the recess 45 and the edge of the first bonding layer 4A shorter than the distance D2 between the recess 45 and the first semiconductor element 5A, it is possible to more reliably reduce the recess 45 from interfering with heat dissipation.

[0055] In the fixing process shown in FIGS. 11 and 12, by using ultrasonic bonding, it is possible to form recesses 45 of a desired size and shape at desired locations in the first bonding layer 4A.

[0056] 13 to 32 show modified examples and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0057] 13 to 17 show modified examples of the recess 45 as viewed in the first direction z.

[0058] In the modified example shown in FIG. 13 , the recess 45 is rectangular when viewed in the first direction z. In the modified example shown in FIG. 14 , the recess 45 is elongated when viewed in the first direction z, and in the illustrated example, may be shaped such that the longitudinal direction is the third direction y. In the modified example shown in FIG. 15 , the recess 45 has a portion extending from the center to both sides in the second direction x and a portion extending from the center to both sides in the third direction y. In the modified example shown in FIG. 16 , the recess 45 has a portion extending in the second direction x and a portion extending from that portion to the second side y2 in the third direction y. In the modified example shown in FIG. 17 , two recesses 45 are arranged side by side in the third direction y.

[0059] As can be seen from these modified examples, the shape of the recess 45 as viewed in the first direction z is not limited in any way.

[0060] 18 shows a first modification of the semiconductor device A1. The semiconductor device A11 of this modification differs from the semiconductor device A1 in the number and arrangement of the recesses 45 in the first bonding layer 4A.

[0061] In the semiconductor device A11, the first bonding layer 4A has four recesses 45. The four recesses 45 are arranged at positions corresponding to the four corners of the first bonding layer 4A. The third bonding layer 4B also has four recesses 45. The four recesses 45 are arranged at positions corresponding to the four corners of the third bonding layer 4B.

[0062] According to this modification, it is possible to more reliably prevent the first bonding layer 4A and the third bonding layer 4B from being misaligned.

[0063] 19 shows a second modification of the semiconductor device A1. The semiconductor device A12 of this modification differs from the semiconductor devices A1 and A11 in the number and arrangement of the recesses 45 in the first bonding layer 4A.

[0064] In the semiconductor device A12, the first bonding layer 4A has one recess 45. The one recess 45 is arranged at one of the four corners of the first bonding layer 4A on the first side x1 in the second direction x and corresponding to the first side y1 in the third direction y. The third bonding layer 4B also has one recess 45. The one recess 45 is arranged at one of the four corners of the third bonding layer 4B on the second side x2 in the second direction x and corresponding to the first side y1 in the third direction y.

[0065] According to this modification, it is possible to more reliably prevent misalignment of the first bonding layer 4A and the third bonding layer 4B. There is no limitation on the number of recesses 45. Even when one recess 45 is provided in each of the first bonding layer 4A and the third bonding layer 4B, the effect of preventing misalignment of the first bonding layer 4A and the third bonding layer 4B can be expected.

[0066] 20 shows a third modification of the semiconductor device A1. The semiconductor device A13 of this modification differs from the semiconductor device A1 in the relative positional relationship between the recess 45 of the first bonding layer 4A and the first metal layer 3A.

[0067] In the semiconductor device A13, when viewed in the first direction z, the recess 45 of the first bonding layer 4A partially overlaps with the first metal layer 3A, and the other portion protrudes from the first metal layer 3A. Furthermore, when viewed in the first direction z, the recess 45 of the third bonding layer 4B partially overlaps with the fourth metal layer 3B, and the other portion protrudes from the fourth metal layer 3B.

[0068] According to this modification, heat dissipation from the first semiconductor element 5A and the second semiconductor element 5B can be realized in a more preferable state.

[0069] 21 shows a fourth modification of the semiconductor device A14. The semiconductor device A14 of this modification differs from the semiconductor device A1 in the relative positional relationship between the recess 45 of the first bonding layer 4A and the first metal layer 3A.

[0070] In the semiconductor device A14, all of the recesses 45 in the first bonding layer 4A are spaced apart from the first metal layer 3A when viewed in the first direction z. All of the recesses 45 in the third bonding layer 4B are spaced apart from the fourth metal layer 3B when viewed in the first direction z.

[0071] According to this modification, heat dissipation from the first semiconductor element 5A and the second semiconductor element 5B can be realized in a more preferable state.

[0072] 22 shows a fifth modification of the semiconductor device A1. The semiconductor device A15 of this modification differs from the semiconductor device A1 in the relative positional relationship between the recess 45 of the first bonding layer 4A and the first semiconductor element 5A.

[0073] In the semiconductor device A15, the recess 45 of the first bonding layer 4A overlaps with the first semiconductor element 5A when viewed in the first direction z. Also, the recess 45 of the third bonding layer 4B overlaps with the second semiconductor element 5B when viewed in the first direction z.

[0074] This modification can reduce misalignment between the first bonding layer 4A and the third bonding layer 4B. As can be understood from this modification, the positions of the recesses 45 in the first bonding layer 4A and the third bonding layer 4B are not limited in any way.

[0075] 23 and 24 show a semiconductor device according to a second embodiment of the present disclosure. The semiconductor device A2 of this embodiment includes a support 1, a heat sink Hs, a fifth bonding layer 4C, and one or more first semiconductor elements 5A. The semiconductor device A2 may include a first bonding layer 4A, a third bonding layer 4B, a first metal layer 3A, a fourth metal layer 3B, one or more second bonding layers 6A, one or more fourth bonding layers 6B, one or more first semiconductor elements 5A, one or more second semiconductor elements 5B, and a sealing resin 9. The semiconductor device A2 may include a plurality of first bonding layers 4A, a plurality of third bonding layers 4B, a plurality of first semiconductor elements 5A, and a plurality of second semiconductor elements 5B, in which case the arrangement may be as shown in FIG. 2 .

[0076] The heat sink Hs is intended to promote heat dissipation from the first semiconductor element 5A to the outside. The heat sink Hs may also promote heat dissipation from the second semiconductor element 5B to the outside. The specific configuration of the heat sink Hs is not limited in any way, and in the illustrated example, the heat sink Hs may have a configuration including multiple fins each extending toward the second side z2 in the first direction z. Alternatively, the heat sink Hs may have a flow path therein through which a cooling fluid flows.

[0077] As shown in FIG. 24 , the heat sink Hs may include a base material H0 and a surface metal layer H1. The base material H0 may include, for example, Al (aluminum) or Cu (copper). The surface metal layer H1 is located on a first side z1 in the first direction z with respect to the base material H0. The thickness of the surface metal layer H1 in the first direction z is thinner than the thickness of the base material H0 in the first direction z. The surface metal layer H1 may include, for example, Ag (silver). The thickness of the base material H0 is not limited and may be, for example, 1 mm or more and 100 mm or less. The thickness of the surface metal layer H1 is not limited and may be, for example, 0.1 μm or more and 30 μm or less.

[0078] The fifth bonding layer 4C is for bonding the heat sink Hs and the back surface metal layer 11 by solid-state diffusion bonding. The specific configuration of the fifth bonding layer 4C is not limited in any way. In the illustrated example, the fifth bonding layer 4C is similar to the first bonding layer 4A, and the first bonding layer 4A may include a base layer 40, a surface metal layer 41, and a surface metal layer 42.

[0079] The back surface metal layer 11 may include a base layer 110 and a surface metal layer 111. The base layer 110 may include, for example, Cu (copper). The surface metal layer 111 is located on a second side z2 in the first direction z with respect to the base layer 110. The thickness of the surface metal layer 111 in the first direction z is thinner than the thickness of the base layer 110 in the first direction z. The surface metal layer 111 may include, for example, Ag (silver). The thickness of the base layer 110 is not limited in any way and may be, for example, 0.1 mm or more and 5 mm or less. The thickness of the surface metal layer 111 is not limited in any way and may be, for example, 0.1 μm or more and 30 μm or less.

[0080] The base material H0 and the surface metal layer 42 of the fifth bonding layer 4C are bonded by solid-state diffusion bonding. The surface metal layer 111 and the surface metal layer 41 are bonded by solid-state diffusion bonding.

[0081] The fifth bonding layer 4C has a recess 45. The recess 45 is recessed from the first side z1 to the second side z2 in the first direction z. The fifth bonding layer 4C may have, for example, the same depth, size, and shape as the recess 45 of the first bonding layer 4A. In this example, the recess 45 of the fifth bonding layer 4C overlaps with the back surface metal layer 11 when viewed in the first direction z.

[0082] Next, a method for manufacturing the semiconductor device A2 will be described below with reference to FIGS.

[0083] First, as shown in FIG. 25 , a heat sink Hs is prepared. Next, a fifth bonding layer 4C is placed on the heat sink Hs. Next, as shown in FIG. 26 , the fifth bonding layer 4C is fixed to the heat sink Hs. There are no particular limitations on the method for fixing the fifth bonding layer 4C to the heat sink Hs, and ultrasonic bonding, welding, metal bonding, or the like may be used as appropriate. Welding includes, for example, laser welding, electric welding, and the like. In the illustrated example, the fifth bonding layer 4C is fixed to the heat sink Hs by ultrasonic bonding.

[0084] 27 , the support body 1 is placed on the fifth bonding layer 4C. The heat sink Hs and the support body 1 are bonded together by solid-state diffusion bonding, sandwiching the fifth bonding layer 4C therebetween. Prior to this solid-state diffusion bonding, the second metal layer 2A, the fifth metal layer 2B, the first bonding layer 4A, the third bonding layer 4B, the first metal layer 3A, the fourth metal layer 3B, the second bonding layer 6A, the fourth bonding layer 6B, the first semiconductor element 5A, and the second semiconductor element 5B may be placed and then subjected to solid-state diffusion bonding all at once. After this, for example, a mold (not shown) having a cavity to accommodate the support 1, the second metal layer 2A, the fifth metal layer 2B, the first metal layer 3A, the fourth metal layer 3B, the first bonding layer 4A, the third bonding layer 4B, the first semiconductor element 5A, the second semiconductor element 5B, the second bonding layer 6A and the fourth bonding layer 6B is abutted against the heat sink Hs, and a resin material is injected into the cavity to form the sealing resin 9.

[0085] According to this embodiment, it is possible to reduce misalignment of the fifth bonding layer 4C, and it is possible to more appropriately bond the heat sink Hs and the support body 1 with the fifth bonding layer 4C sandwiched therebetween.

[0086] 28 and 29 show a first modified example of the semiconductor device A2. In a semiconductor device A21 of this modified example, the recess 45 of the fifth bonding layer 4C does not overlap with the back surface metal layer 11 when viewed in the first direction z, and is located outside the back surface metal layer 11. As shown in FIG. 29 , the recess 45 of the fifth bonding layer 4C can be filled with a part of the sealing resin 9.

[0087] According to this modification, it is possible to reduce misalignment of the fifth bonding layer 4C, and it is possible to more appropriately bond the heat sink Hs and the support body 1 with the fifth bonding layer 4C sandwiched therebetween. Furthermore, as can be understood from this modification, the relative positional relationship between the recess 45 of the fifth bonding layer 4C and the back surface metal layer 11 (support body 1) is not limited in any way.

[0088] 30 shows a second modification of the semiconductor device A2. In the semiconductor device A22 of this modification, the timing of forming the sealing resin 9 differs from that of the semiconductor device A2 and the semiconductor device A21 described above.

[0089] FIG. 31 shows a step in the manufacturing method of the semiconductor device A22. In this figure, the fifth bonding layer 4C has already been fixed to the heat sink Hs. During this fixing step, one or more recesses 45 are formed in the fifth bonding layer 4C. Meanwhile, the structure including the support 1, the second metal layer 2A, the fifth metal layer 2B, the first metal layer 3A, the fourth metal layer 3B, the first bonding layer 4A, the third bonding layer 4B, the first semiconductor element 5A, the second semiconductor element 5B, the second bonding layer 6A, the fourth bonding layer 6B, and the sealing resin 9 may have a configuration similar to that of the semiconductor device A1 described above. By pressing the back surface metal layer 11 of this structure against the heat sink Hs at a predetermined temperature and pressure, the back surface metal layer 11 and the heat sink Hs are solid-state diffusion bonded via the fifth bonding layer 4C.

[0090] 30 , in the semiconductor device A22, a gap may occur between the sealing resin 9 and the heat sink Hs. In the example shown in the figure, the recess 45 of the fifth bonding layer 4C overlaps with the back surface metal layer 11 as viewed in the first direction z, but is not limited to this and may be configured to be located outside the back surface metal layer 11 as viewed in the first direction z.

[0091] According to this modification, it is possible to reduce misalignment of the fifth bonding layer 4C, and it is possible to more appropriately bond the heat sink Hs and the support body 1 with the fifth bonding layer 4C sandwiched therebetween. Furthermore, as can be understood from this modification, the order of solid-state diffusion bonding of the back surface metal layer 11 and the heat sink Hs using the fifth bonding layer 4C and the formation of the sealing resin 9 is not limited in any way.

[0092] 32 shows a third modification of the semiconductor device A2. The semiconductor device A23 of this modification does not need to include the first metal layer 3A, the fourth metal layer 3B, the first bonding layer 4A, and the third bonding layer 4B of the semiconductor device A2. The first semiconductor element 5A may be bonded to the second metal layer 2A via the second bonding layer 6A. The second semiconductor element 5B may be bonded to the fifth metal layer 2B via the fourth bonding layer 6B.

[0093] As can be understood from this modification, the semiconductor device according to the second embodiment of the present disclosure may be configured without the first metal layer 3A and the fourth metal layer 3B.

[0094] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiment. The specific configurations of the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure can be freely modified in various ways.

[0095] [Supplementary Note 1] A semiconductor device (A1) comprising: a support (1); a first semiconductor element (5A) located on a first side (z1) in a first direction (z) relative to the support (1) and supported by the support (1); a first metal layer (3A) interposed between the support (1) and the first semiconductor element (5A); and a first bonding layer (4A) interposed between the support (1) and the first metal layer (3A), wherein the first bonding layer (4A) has a recess (45) recessed toward a second side (z2) in the first direction (z). [Supplementary Note 2] The semiconductor device (A1) according to Supplementary Note 1, wherein the recess (45) is spaced apart from the first semiconductor element (5A) as viewed in the first direction (z). [Supplementary Note 3] The semiconductor device (A1) according to Supplementary Note 2, wherein the distance between the recess (45) and an edge of the first bonding layer (4A) is shorter than the distance between the recess (45) and the first semiconductor element (5A). [Supplementary Note 4] The semiconductor device (A1) according to Supplementary Note 2, wherein at least a portion of the recess (45) protrudes from the first metal layer (3A) when viewed in the first direction (z). [Supplementary Note 5] The semiconductor device (A1) according to Supplementary Note 2, wherein the entirety of the recess (45) protrudes from the first metal layer (3A) when viewed in the first direction (z). [Supplementary Note 6] The semiconductor device (A1) according to Supplementary Note 1, wherein the recess (45) overlaps the first semiconductor element (5A) when viewed in the first direction (z). [Supplementary Note 7] The semiconductor device (A1) according to any one of Supplements 1 to 6, wherein the first bonding layer (4A) has a plurality of the recesses (45). [Appendix 8] The semiconductor device (A1) according to any one of Appendices 1 to 7, wherein the support (1) includes an insulating layer (10), a second metal layer (2A) located on the first side (z1) in the first direction (z) with respect to the insulating layer (10), and a back surface metal layer (11) located on the second side (z2) in the first direction (z) with respect to the insulating layer (10). [Appendix 9] The semiconductor device (A1) according to Appendices 8, wherein the first bonding layer (4A) includes a base layer (40), a first surface metal layer (41) located on the first side (z1) of the base layer (40) in the first direction (z), and a second surface metal layer (42) located on the second side (z2) of the base layer (40) in the first direction (z), and the recess (45) is formed in at least the first surface metal layer (41).[Supplementary Note 10] The semiconductor device (A1) according to Supplementary Note 9, wherein the second metal layer (2A) includes a base layer (20) and a surface metal layer (21) located on the first side (z1) in the first direction (z) relative to the base layer (20). [Supplementary Note 11] The semiconductor device (A1) according to Supplementary Note 10, wherein the first metal layer (3A) includes a base layer (30) and a surface metal layer (31) located on the second side (z2) in the first direction (z) of the base layer (30). [Supplementary Note 12] The semiconductor device (A1) according to any one of Supplementary Notes 9 to 11, wherein the first bonding layer (4A) is larger than the second metal layer (2A) and the first metal layer (3A) when viewed in the first direction (z). [Appendix 13] A semiconductor device (A2) comprising: a support (1); a first semiconductor element (5A) located on a first side (z1) in a first direction (z) relative to the support (1) and supported by the support (1); a heat sink (Hs) located on a second side (z2) in the first direction (z) relative to the support (1); and a fifth bonding layer (4C) interposed between the support (1) and the heat sink (Hs), wherein the fifth bonding layer (4C) has a recess (45) recessed toward the second side (z2) in the first direction (z). [Appendix 14] A method for manufacturing a semiconductor device (A1), comprising the steps of: placing a first bonding layer (4A) on a support (1); fixing the first bonding layer (4A) to the support (1); placing a first metal layer (3A) on the first bonding layer (4A); placing a first semiconductor element (5A) on the first metal layer (3A); and bonding the support (1), the first bonding layer (4A), and the first metal layer (3A) by solid-state diffusion bonding. [Appendix 15] A method for manufacturing a semiconductor device (A2), comprising the steps of: placing a fifth bonding layer (4C) on a heat sink (Hs); fixing the fifth bonding layer (4C) to the heat sink (Hs); placing a support (1) on the fifth bonding layer (4C); and bonding the heat sink (Hs), the fifth bonding layer (4C), and the support (1) by solid-state diffusion bonding.

Claims

1. A semiconductor device comprising a support, a first semiconductor element located on a first side in a first direction with respect to the support and supported by the support, a first metal layer interposed between the support and the first semiconductor element, and a first bonding layer interposed between the support and the first metal layer, wherein the first bonding layer has a recess recessed on a second side in the first direction.

2. The semiconductor device according to claim 1, wherein the recess is away from the first semiconductor element when viewed in the first direction.

3. The semiconductor device according to claim 2, wherein the distance between the recess and the edge of the first bonding layer is shorter than the distance between the recess and the first semiconductor element.

4. The semiconductor device according to claim 2, wherein at least a part of the recess protrudes from the first metal layer when viewed in the first direction.

5. The semiconductor device according to claim 2, wherein all of the recess protrudes from the first metal layer when viewed in the first direction.

6. The semiconductor device according to claim 1, wherein the recess overlaps the first semiconductor element when viewed in the first direction.

7. The semiconductor device according to any one of claims 1 to 6, wherein the first bonding layer has a plurality of the recesses.

8. The semiconductor device according to claim 1, wherein the support includes an insulating layer, a second metal layer located on the first side in the first direction with respect to the insulating layer, and a back metal layer located on the second side in the first direction with respect to the insulating layer.

9. The semiconductor device according to claim 8, wherein the first bonding layer includes a base material layer, a first surface metal layer located on the first side in the first direction of the base material layer, and a second surface metal layer located on the second side in the first direction of the base material layer, and the recess is formed at least in the first surface metal layer.

10. The semiconductor device according to claim 9, wherein the second metal layer includes a base material layer and a surface metal layer located on the first side in the first direction with respect to the base material layer.

11. The semiconductor device according to claim 10, wherein the first metal layer includes a base material layer and a surface metal layer located on the second side in the first direction of the base material layer.

12. The semiconductor device according to claim 9, wherein the first bonding layer is larger than the second metal layer and the first metal layer when viewed in the first direction.

13. A semiconductor device comprising a support, a first semiconductor element located on a first side of the support in a first direction and supported by the support, a heat sink located on a second side of the support in the first direction, and a fifth bonding layer interposed between the support and the heat sink, wherein the fifth bonding layer has a recess recessed on the second side in the first direction.

14. A method of manufacturing a semiconductor device, comprising the steps of placing a first bonding layer on a support, fixing the first bonding layer to the support, placing a first metal layer on the first bonding layer, placing a first semiconductor element on the first metal layer, and bonding the support, the first bonding layer, and the first metal layer by solid-phase diffusion bonding.

15. A method of manufacturing a semiconductor device, comprising the steps of placing a fifth bonding layer on a heat sink, fixing the fifth bonding layer to the heat sink, placing a support on the fifth bonding layer, and bonding the heat sink, the fifth bonding layer, and the support by solid-phase diffusion bonding.

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