Semiconductor device and power conversion device using same

Abstract

Provided is a semiconductor device in which a plurality of power semiconductor elements are connected in parallel. The semiconductor device reduces variation in the inductance generated between the power semiconductor elements to achieve both low switching loss due to high-speed switching and improvement of power cycle resistance by uniformization of the switching loss of the power semiconductor elements.　A semiconductor device according to the present invention includes at least one half-bridge circuit in which a first switch and a second switch that use a power semiconductor element are connected in series. The semiconductor device is characterized by comprising an insulated substrate, a first conductor layer pattern, a second conductor layer pattern, and a third conductor layer pattern that are provided on one surface of the insulated substrate and are electrically insulated from each other, a plurality of power semiconductor elements that are provided on the first conductor layer pattern and are connected to each other in parallel, a lead frame that connects each of the plurality of power semiconductor elements and the second conductor layer pattern, individual gate wirings that connect respective gate electrodes of the plurality of power semiconductor elements and the third conductor layer pattern, and a principal terminal that connects to the second conductor layer pattern, the lead frame having first connection surface parts that respectively connect to electrode surfaces of the plurality of power semiconductor elements, a lead frame branching part that has a plurality of branches, and a second connection surface part that is provided at an end part of the lead frame branching part and connects to the second conductor layer pattern, and the gate electrodes and the individual gate wirings being sandwiched between two branches of the lead frame branching part as seen in a top view of the insulated substrate.

Description

Semiconductor device and power conversion device using the same

[0001] The present invention relates to the configuration of a semiconductor device, and more particularly to a technique that is effective when applied to a power semiconductor module configured by connecting a plurality of power semiconductor elements in parallel.

[0002] Power semiconductor modules, which incorporate multiple semiconductor elements such as power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) and freewheel diodes, are used for power control and motor control in industrial equipment, electric railway vehicles, automobiles, home appliances, and other applications.

[0003] In recent years, GaN (gallium nitride) and SiC (silicon carbide) have been used as materials for power semiconductor elements, and are beginning to take advantage of their superior advantages over semiconductor elements that use Si (silicon), such as faster switching speeds and higher operating temperatures. Currently, GaN and SiC elements are small in size, so in order to configure a power semiconductor module that satisfies a specified current capacity, it is necessary to connect multiple power semiconductor elements in parallel and mount them on an insulating substrate within the module.

[0004] In applications such as automotive inverters, where power loss in the inverter affects the driving range of electric vehicles and fuel cell vehicles, it is necessary to minimize power loss generated in power semiconductor modules. To achieve this, it is important for power semiconductor modules to minimize both resistive loss during conduction and transient switching loss during switching. To reduce switching loss, switching must be performed in a short time, i.e., high-speed switching.

[0005] Furthermore, high reliability is required for power semiconductor modules used in inverters. The power cycle durability, which indicates the reliability of a power semiconductor module, is determined by the deterioration of the solder used to join the electrodes of the power semiconductor elements built into the module to the wiring material. In order to suppress solder deterioration and improve power cycle durability, it is necessary to reduce the thermal stress applied to the solder and to make the thermal stress uniform for each power semiconductor element.

[0006] If thermal stress is uneven between power semiconductor elements, one power semiconductor element will deteriorate first, causing a problem of early loss of reliability. Because this thermal stress is proportional to the power loss generated in the power semiconductor element, in order to improve the reliability of the power module, it is necessary to equalize the power loss generated between the power semiconductor elements.

[0007] For the above reasons, in automotive inverters and the like that utilize power semiconductor elements such as GaN and SiC, it is necessary to minimize both the resistive loss during conduction of the built-in power semiconductor module and the transient switching loss during switching in order to extend the driving range of the vehicle.In addition, in order to improve the reliability of the power semiconductor module and extend the life of the inverter, it is necessary to make the power loss of each of the multiple power semiconductor elements used in the power semiconductor module as uniform as possible.In particular, with regard to power loss, it is more important to reduce the variation in dynamic switching loss among the multiple power semiconductor elements than so-called static resistive loss.

[0008] As a background art in this technical field, for example, there is a technique such as that disclosed in Patent Document 1. Patent Document 1 discloses a semiconductor module capable of reducing variations in inductance between the gate and source.

[0009] In Patent Document 1, the objective of achieving even faster switching speeds is to reduce the inductance and suppress variations in the main current path of the power semiconductor module, and the need to further suppress variations in the inductance of the gate-source wiring between power semiconductor elements as much as possible is raised as a problem.

[0010] Furthermore, Patent Document 2 discloses a power semiconductor module that is configured by connecting multiple power semiconductor elements arranged on the same substrate in parallel, and that can reduce the chip arrangement area on the substrate while reducing wiring inductance within the module.

[0011] Patent Document 2 describes a technical problem in the internal structure of a power semiconductor module: when semiconductor chips are wired in parallel, the area of ​​the substrate on which the semiconductor chips are mounted increases in order to ensure an insulating distance. In particular, when using GaN or SiC semiconductor chips, the chip area is small, requiring many parallel wires. This increases the area allocated to ensuring spacing between wiring patterns, resulting in a larger substrate area. Furthermore, the document also clarifies the problem that the gate wiring is routed with low magnetic coupling to other wiring such as source and drain wiring, as well as to the lead frame and spacer in its path. This increases the inductance value generated in the gate wiring, which can easily cause unstable operation of the gate waveform when controlling the switching of the power semiconductor element.

[0012] JP 2021-141219 A JP 2022-34300 A

[0013] However, there are two problems to be solved in order to equalize the switching losses among the power semiconductor elements arranged in parallel in a power semiconductor module.

[0014] The following is an example of using MOSFETs as the type of power semiconductor element. Power semiconductor elements are electrically connected to conductor layer patterns, but one of the issues is that for each power semiconductor element, the impedance (especially resistance and inductance) varies from the main terminals and control terminals of the power semiconductor module to the gate electrodes, drain electrodes, and source electrodes of multiple chips.

[0015] In particular, variations in inductance values ​​have a significant impact on the paths from each terminal to the drain electrode and from each terminal to the source electrode, where rapid current changes occur due to high-speed switching, resulting in uneven values ​​of current flowing through each power semiconductor element.

[0016] Another issue is that the magnetic field induced by the sudden current changes generated by high-speed switching superimposes unnecessary noise voltage on the gate voltage that controls the operation of the power semiconductor element, and the unevenness of this noise voltage causes the switching current itself to vary between chips. This effect has become more apparent as the operating speed of switching elements has increased from Si-IGBT to SiC or GaN.

[0017] In other words, to reduce the variation in switching loss among multiple power semiconductor elements, it is necessary to minimize the deviation in impedance among the power semiconductor elements and to uniformize it among the chips while minimizing the influence of the magnetic field generated near the path through which the switching current flows.

[0018] In the above-mentioned Patent Document 1, in order to achieve high-speed switching, the following issues are raised: (1) reducing the inductance of the main current path and suppressing variations therein, and (2) suppressing variations in the inductance of the gate-source wiring between power semiconductor elements as much as possible, and measures to achieve these issues are described.

[0019] However, although the issue of variations in inductance of the gate-source wiring is mentioned, there is no mention of increasing the switching speed, i.e., the generation of a magnetic field caused by a sudden change in the main current, or the effect of this magnetic field on the gate-source wiring, and no countermeasures are made clear, so issues remain.

[0020] Furthermore, the above-mentioned Patent Document 2 points out as an issue that when semiconductor chips are wired in parallel, the area of ​​the substrate on which the semiconductor chips are mounted increases in order to ensure an insulating distance, and as a countermeasure to this, it describes a measure to use gate spacers to make the gate electrodes between multiple semiconductor chips that are wired in parallel into shared wiring, thereby reducing the planar area required for gate wiring.

[0021] However, although measures to reduce the area of ​​the substrate occupied by multiple semiconductor chips wired in parallel are mentioned, there is no mention of the variation in inductance that occurs between the conductor layer patterns that connect the electrodes of closely spaced semiconductor chips or how to reduce this variation, and no measures to address this issue are made clear, leaving issues unresolved.

[0022] Therefore, an object of the present invention is to provide a semiconductor device configured by connecting a plurality of power semiconductor elements in parallel, which reduces the variation in inductance that occurs between the power semiconductor elements, and is capable of achieving both low switching loss through high-speed switching and improved power cycle resistance by equalizing the switching loss of each power semiconductor element, and a power conversion device using the same.

[0023] In order to solve the above problem, the present invention provides a semiconductor device including one or more half-bridge circuits configured by connecting in series a first switch and a second switch using power semiconductor elements, the semiconductor device comprising: an insulating substrate; a first conductor layer pattern, a second conductor layer pattern, and a third conductor layer pattern that are arranged on one surface of the insulating substrate and are electrically insulated from each other; a plurality of power semiconductor elements that are arranged on the first conductor layer pattern and connected in parallel to each other; a lead frame that connects each of the plurality of power semiconductor elements to the second conductor layer pattern; individual gate wiring that connects a gate electrode of each of the plurality of power semiconductor elements to the third conductor layer pattern; and a main terminal that connects to the second conductor layer pattern, wherein the lead frame has first connection surface portions that are respectively connected to electrode surfaces of the plurality of power semiconductor elements, lead frame branch portions that are branched into a plurality of parts, and second connection surface portions that are provided at ends of the lead frame branch portions and are connected to the second conductor layer pattern, and the gate electrodes and the individual gate wiring are sandwiched between two of the lead frame branch portions when viewed from above with respect to the insulating substrate.

[0024] The present invention also provides a power conversion device comprising a main circuit having one or more pairs of high-voltage side and low-voltage side switch circuits, and a drive circuit that drives the high-voltage side and low-voltage side switch circuits, wherein the high-voltage side and low-voltage side switch circuits include the above-mentioned semiconductor device.

[0025] According to the present invention, in a semiconductor device configured by connecting a plurality of power semiconductor elements in parallel, it is possible to realize a semiconductor device that reduces the variation in inductance that occurs between the power semiconductor elements, and that can achieve both low switching loss through high-speed switching and improved power cycle resistance by equalizing the switching loss of each power semiconductor element, and a power conversion device using the semiconductor device.

[0026] This can contribute to improving the efficiency and reliability of the semiconductor device and the power conversion device using the same.

[0027] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments.

[0028] 5 is a plan view (top view) showing a schematic configuration of a power semiconductor module according to a first embodiment of the present invention. It is a cross-sectional view taken along the line AA' in FIG. 1 . It is a perspective view showing components arranged on the insulating substrate 10 of FIG. 1 . It is a diagram showing the connection surface of the lead frame 45 of FIG. 1 with the power semiconductor elements and the conductor layer pattern. It is a plan view (top view) showing a portion of a power semiconductor module of a comparative example. It is a diagram schematically showing the direction of current flow and the distribution of magnetic flux density when the parallel-connected power semiconductor elements in the structure of FIG. 5 are switched. It is a diagram schematically showing the direction of current flow and the distribution of magnetic flux density when the parallel-connected power semiconductor elements in the structure of FIG. 5 are switched. It is a diagram schematically showing the direction of current flow and the distribution of magnetic flux density when the parallel-connected power semiconductor elements in the structure of FIG. 5 are switched. It is an equivalent circuit diagram with simplified power semiconductor elements and a wiring structure, which schematically shows the generation of noise voltage generated in the gate voltage. It is a diagram schematically showing the direction of current flow and the distribution of magnetic flux density when the parallel-connected power semiconductor elements in the structure of FIG. 1 are switched. 5 is a diagram schematically showing the direction of current flow and the distribution of magnetic flux density when power semiconductor elements connected in parallel in the structure of FIG. 1 are switched. FIG. 5 is a diagram schematically showing the direction of current flow and the distribution of magnetic flux density when power semiconductor elements connected in parallel in the structure of FIG. 1 are switched. FIG. 5 is a diagram showing the transient waveform of current when switching in the structure of FIG. 5. FIG. 5 is a diagram showing the power consumption of power semiconductor elements when switching in the structure of FIG. 5. FIG. 5 is a diagram showing variations in magnetic flux density and gate voltage when switching between power semiconductor elements in a comparative example. FIG. 5 is a diagram showing variations in magnetic flux density and gate voltage when switching between power semiconductor elements in a power semiconductor module according to Example 1 of the present invention. FIG. 5 is a diagram showing the transient waveform of current when switching in the structure of FIG. 1. FIG. 5 is a diagram showing the power consumption of power semiconductor elements when switching in the structure of FIG. 1. FIG. 5 is a perspective view showing a schematic configuration of a power semiconductor module according to Example 2 of the present invention. FIG. 5 is a perspective view showing a schematic configuration of a power semiconductor module according to Example 3 of the present invention. FIG. 5 is a block diagram showing the circuit configuration of a power conversion device according to Example 4 of the present invention.

[0029] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In each drawing, the same components or components having similar functions are designated by the same reference numerals, and detailed description of overlapping parts will be omitted.

[0030] 1 to 12B, a power semiconductor module according to a first embodiment of the present invention will be described. This embodiment is an example of application to a power semiconductor module configured by connecting multiple power semiconductor elements in parallel to form half-bridge circuits arranged on the same substrate.

[0031] [Schematic Configuration] Fig. 1 is a diagram showing a schematic configuration of a power semiconductor module 100 of this embodiment, and is a plan view (top view) seen from above the power semiconductor module 100. Fig. 2 is a cross-sectional view taken along the line AA' in Fig. 1.

[0032] It should be noted that, for convenience, the layout of components on lower layers that are not visible due to the presence of components on upper layers is shown in a transparent manner in the plan view of Fig. 1. The perspective structure of the power semiconductor module 100 of Fig. 1 will be described later with reference to Fig. 3.

[0033] 1, power semiconductor module 100 has a half-bridge circuit, i.e., a 2-in-1 circuit, configured on a single insulating substrate 10, and includes main terminals consisting of a high-voltage side main terminal (high potential side main terminal) 1, an intermediate voltage terminal (intermediate potential terminal) 2, and a low-voltage side main terminal (low potential side main terminal) 3. In addition, for operational control of power semiconductor module 100, it includes auxiliary terminals (control terminals) 4 to 6 of the high-voltage side switch circuit and auxiliary terminals (control terminals) 7 to 9 of the low-voltage side switch circuit.

[0034] The high-voltage side potential refers to the voltage value applied to the high-voltage side main terminal 1, and the low-voltage side potential refers to the voltage value applied to the low-voltage side main terminal 3. The intermediate voltage refers to the intermediate voltage value between the voltages applied to the high-voltage side main terminal 1 and the low-voltage side main terminal 3, and this potential fluctuates due to switching operations.

[0035] [Connection of Main Terminals] Connection of main terminals will be described with reference to FIG.

[0036] 1 , a high-voltage main terminal 1 that applies a high-voltage potential is electrically connected to a conductor layer pattern 11 disposed on an insulating substrate 10. An intermediate voltage terminal 2 that applies an intermediate voltage and whose potential varies by switching is electrically connected to a conductor layer pattern 13 on the insulating substrate 10. A low-voltage main terminal 3 that applies a low-voltage potential is electrically connected to a conductor layer pattern 15.

[0037] The conductor layer pattern 13 connecting the intermediate voltage terminal 2 is electrically connected to the conductor layer pattern 12 by the lead frames 25 and 26 .

[0038] The method of connecting the high-voltage side main terminal 1, the intermediate voltage terminal 2, and the low-voltage side main terminal 3 to the conductor patterns to which they are electrically connected can be by means of soldering, metal bonding, or the like, and is not particularly limited to this method.

[0039] 1, an example is shown in which the high-voltage side switch of the half-bridge circuit (power semiconductor module 100) is configured with four chips, power semiconductor elements 21 to 24, connected in parallel. On the other hand, the low-voltage side switch is configured with four chips, power semiconductor elements 41 to 44, connected in parallel. Hereinafter, the power semiconductor elements 21 to 24 and power semiconductor elements 41 to 44 will be described as MOSFET transistors.

[0040] When the semiconductor substrates used to construct the elements are expensive, such as in SiC-MOSFETs, the element dimensions are often small to improve element yield. For example, a typical element size is 5 mm square. To achieve this, multiple element chips are connected in parallel to realize one switch function of a half-bridge circuit and accommodate a wide range of current values ​​flowing through the switch. While Figure 1 shows an example of four parallel connections, the number of parallel element chips is not limited.

[0041] The conductor layer pattern 11 electrically connected to the high-voltage side main terminal 1 branches to the left and right in the short direction of the insulating substrate 10, and is electrically and thermally connected by soldering or sintering bonding to the drain electrodes provided on the power semiconductor elements 21 and 22 on the left side and to the drain electrodes provided on the power semiconductor elements 23 and 24 on the right side.

[0042] The source electrodes of the power semiconductor elements 21 and 22 are connected to the conductor layer patterns 13 and 12, to which an intermediate voltage is applied, via a conductive lead frame 25. The conductive lead frame will hereinafter be simply referred to as the "lead frame."

[0043] Similarly, the source electrodes of the power semiconductor elements 23 and 24 are connected to the conductor layer patterns 13 and 12 via the lead frame 26. The lead frames 25 and 26 connect the source electrodes of the power semiconductor elements 21 to 24 and the conductor layer patterns 13 and 12 in a bridge-like configuration.

[0044] To control the operation of the power semiconductor elements 21-24, the gate electrodes (reference numerals 21G-24G in FIG. 3 , described later) of each power semiconductor element 21-24 are connected to the conductor layer pattern 14 via individual gate wiring 31-34. The individual gate wiring may be configured using, for example, a bonding wire. The conductor layer pattern 14, which is the gate control wiring of the high-voltage side switch circuit, is electrically connected to the gate potential control terminal pin 5 (G1 terminal; control terminal). The reference potential of the gate potential control terminal pin 5 is the source sense potential control terminal pin 6 (SS1 terminal; control terminal). The source sense potential control terminal pin 6 is connected to the conductor layer pattern 13, which connects the source electrodes of the power semiconductor elements 21-24 via lead frames 25 and 26. Furthermore, the drain sense potential control terminal pin 4 (DS1 terminal; control terminal) is connected to the conductor layer pattern 11 in an area that does not overlap with the lead frames 25 and 26 or the power semiconductor elements 21-24 in a planar view. The above configuration realizes the high-voltage side switch function of the half-bridge circuit.

[0045] The conductor layer pattern 12 is connected to the drain electrodes of the power semiconductor elements 41 to 44, which perform the switching function on the low voltage side. The four power semiconductor elements 41 to 44 are arranged at equal intervals in the short direction of the insulating substrate 10. The lead frame 45, with its bridge-like shape, connects the source electrodes of the power semiconductor elements 41 to 44 to the conductor layer pattern 15.

[0046] The gate electrodes (reference numerals 41G to 44G in FIG. 3 , which will be described later) of the power semiconductor elements 41 to 44 are connected to a conductor layer pattern 16, which is the gate wiring for the low-voltage side switch circuit, via individual gate wirings 51 to 54, and the potential (voltage) thereof is controlled by a low-voltage gate voltage control terminal pin 8 (G2 terminal; control terminal). The operating reference potential of the G2 terminal is a conductor layer pattern 17, which is connected to a source sense voltage control terminal pin 9 (SS2 terminal; control terminal). The conductor layer pattern 17 is connected to an arm structure for source potential sense wiring provided on the lead frame 45 and a connection portion (reference numeral 45S in FIG. 3 , which will be described later).

[0047] The lead frame 45 has a concave-convex shape that connects to the source electrodes of the power semiconductor elements 41 to 44, as well as a plurality of connection portions (described later with reference to the perspective view of FIG. 3) with the conductor layer patterns 15 and 17, etc. In addition to the connection portions that serve both as electrical connections and as one end of the bridge shape, it also has a connection portion that specializes as a support portion for realizing the bridge shape. The above configuration realizes the switch function on the low-voltage side of the half-bridge circuit.

[0048] In this way, the switching functions of the high voltage side and low voltage side of the half-bridge circuit are realized, and the half-bridge circuit is constituted by a plurality of conductor layer patterns, a plurality of lead frames, and a group of main terminals arranged on a single insulating substrate 10.

[0049] [Cross-Sectional Structure] The cross-sectional structure of the power semiconductor module 100 will be described with reference to FIG.

[0050] The power semiconductor module 100 of this embodiment uses one insulating substrate 10 and adopts a one-sided cooling structure in which a heat dissipation path is provided on one side via a base plate 99 .

[0051] 2, gaps where no components are shown are filled with insulating resin. In the following description, a description of gaps will be omitted unless otherwise necessary.

[0052] The insulating substrate 10 disposed below the power semiconductor module 100 has conductor layer patterns 11 to 20 (see FIGS. 1 and 3) on the upper surface of the insulating substrate 10 and a conductor layer pattern 98 (see FIG. 2) on the lower surface. The conductor layer pattern 98 is electrically and thermally connected to a base plate 99 via a solder layer 97.

[0053] Among the multiple power semiconductor elements 21-24 and 41-44, the power semiconductor elements 24 and 44 shown in the cross-sectional view of FIG. 2 have their drain electrodes aligned along the direction of the base plate 99 and their source and gate electrodes aligned along the direction of the lead frames 26 and 45. When a current flows in the forward direction, it flows from the drain electrode to the source electrode in the vertical direction. When a current flows in the reverse direction, it flows from the source electrode to the drain electrode. In FIG. 2, the drain-side electrode structure of the power semiconductor element, taking the power semiconductor element 44 as an example, is illustrated with a solder layer 44DS for electrical and thermal connection between the drain electrode 44D and the conductor layer pattern 12. The source electrode 44S is connected to the lead frame 45 by a solder layer 44SS, and the gate electrode 44G is connected to the individual gate wiring 53 by wire bonding. The on / off of the current is controlled by the voltage applied to the gate electrode 44G, with the potential of the source electrode 44S as the reference.

[0054] The cross-sectional view of the half-bridge circuit (power semiconductor module 100) shown in Fig. 2 is a structure showing both a high-voltage side switch circuit and a low-voltage side switch circuit, in which a power semiconductor element 24 is connected above the conductor layer pattern 11 (the side where the lead frame is arranged with respect to the insulating substrate 10) via a solder layer 24DS. A power semiconductor element 44 is connected above the conductor layer pattern 12 via a solder layer 44DS.

[0055] A source electrode 24S of the power semiconductor element 24 is connected to the lead frame 26 using a solder layer 24SS, and a source electrode 44S of the power semiconductor element 44 is connected to the lead frame 45 using a solder layer 44SS. The lead frame 26 has the power semiconductor element 24 in the center and bonding portions with the conductor layer patterns on both sides, and is connected via solder layers 26AS and 26BS, which are bonding materials.

[0056] 1 and the cross-sectional view of Fig. 2, the lead frames 26 and 45 have a so-called "double-supported" structure in which the power semiconductor element is disposed and connected in a central region, the lead frame shape extends on both sides to sandwich the power semiconductor element, and the ends of the lead frames are connected to the conductor layer pattern. This structure, in which the lead frame shape extends on both sides to sandwich the power semiconductor element, ensures the thickness of the solder layers 24SS and 44SS (Fig. 2) during solder reflow, prevents tilting of the lead frame that may occur during solder reflow, and makes the flat portion of the lead frame as parallel as possible to the plane of the insulating substrate 10.

[0057] Furthermore, when viewed from above with respect to the insulating substrate 10, the individual gate wirings 31 to 34, the conductor layer pattern 11, and a portion of the conductor layer pattern 14 are arranged within the area surrounded by the branching portions of the two lead frames 25, 26 and the conductor layer pattern 13, and there is also an area where the conductor layer pattern 11, the conductor layer pattern 13, and the conductor layer pattern 14 are not present and the insulating substrate 10 is arranged.

[0058] [Perspective Structure] Fig. 3 is a perspective view of components arranged on the insulating substrate 10 shown in Fig. 1. The perspective view of Fig. 3 clearly shows the relationship between the shape of the lead frame and the arrangement of the gate wiring path of the power semiconductor element.

[0059] [Shape of Lead Frame] Lead frame 25 used in the circuit configuration of the high-voltage side switch circuit is connected to the source electrode of power semiconductor element 21 at connection portion 25P1 via a connection conductor such as solder. Connection portion 25P1 has a shape that is obtained when lead frame 25 is half-pressed in the thickness direction. For example, the planar dimensions of the connection portion are 2 mm × 3 mm, the lead frame thickness is 1.5 mm, and the half-pressing has an upper limit of about half the thickness, which are feasible values.

[0060] The surface that connects to the source electrode 21S of the power semiconductor element 21 via the solder layer 21SS (not shown) is the lower flat surface of the connection portion 25P1 shown in Fig. 3. The connection portion 25P2 is the connection surface with the power semiconductor element 22, and the connection portion 25A is the connection surface with the conductor layer pattern 12. The connection portion 25B is the connection surface with the conductor layer pattern 13. The connection portions 25P1 and 25P2 are formed in a stepped shape by a half-pressing process or the like, and form the connection surfaces to the source electrode of the power semiconductor element.

[0061] The connection portions of the lead frame connecting to the conductor layer patterns 12 and 13 are arm-shaped with obtuse-angle bends formed by bending. When forming multiple protrusions on a single lead frame, a half-pressed shape, which can achieve a sharp shape when the distance between the power semiconductor elements and the connection surfaces needs to be short, and a bending process, which achieves an obtuse-angle bend, are used when the distance between the connection surfaces can be long. Using different connection surface shapes and manufacturing processes depending on the distance between the connection surfaces is a way to achieve a compact lead frame using thick conductor materials, such as 1 mm or 1.5 mm. Lead frame 26 has the same structure as lead frame 25. Consideration was given to evenly dividing the switching current flowing through the power semiconductor elements 21-24 with the axis of symmetry near the longitudinal center of insulating substrate 10.

[0062] Lead frame 45 is used in the circuit configuration of the low-voltage side switch circuit. Connection surface 45P1, which is formed with a concave and convex shape using the same manufacturing method as lead frames 25 and 26, is used for connection to power semiconductor element 41, connection surface 45P2, connection surface 45P3, connection surface 45P4, and connection surface 45P5 are used for connection to the source electrode of power semiconductor element 44.

[0063] The connection surface 45A with the conductor layer pattern 15 includes two surfaces 45A1 corresponding to the connection surfaces 45P1 and 45P2 with the power semiconductor elements, and a surface 45A2 corresponding to the connection surfaces 45P3 and 45P4 with the power semiconductor elements.

[0064] Here, the "branch portion" of the lead frame 45 is defined. A part of the lead frame in the longitudinal direction of the connection surface portion 45P1, in the direction in which the connection surface portion 45A1 is arranged, is defined as the lead frame branch portion. In other words, the lead frame branch portion is a portion arranged on both sides of a gap provided in the lead frame 45 so as not to interfere with the individual gate wirings 51 and 52 of the power semiconductor elements 41 and 42. The current flowing through the power semiconductor elements 41 to 44 passes through the connection surface portions 45P1 to 45P4, then flows through the "branch portion" toward the conductor layer pattern 13.

[0065] Hole 45H in the lead frame is a resin filling hole that prevents the resin from flowing around lead frame 45 and leaving undesired unfilled portions when insulating resin is filled into power semiconductor module 100. At the same time, hole 45H also serves as a current separation structure that guides the current flowing through lead frame 45 from connection surface 45P2 to connection surface 45A1, and the current flowing through lead frame 45 from connection surface 45P3 to connection surface 45A2.

[0066] 4 shows the structure of the connection surface side of lead frame 45 with the power semiconductor element. 45P1LP, which is the lower flat surface of connection surface 45P1, is the surface that connects to the source electrode of power semiconductor element 41 via solder layer 41SS. Similarly, 45P2LP, which is the lower flat surface of connection surface 45P2, connects to the source electrode of power semiconductor element 42 via solder layer 42SS. 45P3LP, which is the lower flat surface of connection surface 45P3, connects to the source electrode of power semiconductor element 43 via solder layer 43SS. 45P4LP, which is the lower flat surface of connection surface 45P4, connects to the source electrode of power semiconductor element 44 via solder layer 44SS.

[0067] The layout and shape of connection surface portions 45A1 and 45A2, which are connection surfaces of the lead frame connected to the conductor layer pattern via a solder layer and which are one support structure of the "double-supported structure," and connection surface portion 45B, which is the other support structure of the "double-supported structure," are also clearly shown. 45B is connected to conductor layer pattern 18 by a bonding material such as a solder layer, as shown in Figure 3. However, conductor layer pattern 18 is an independent pattern that is not connected to other elements or conductor layer patterns, and no current flows through connection surface portion 45B.

[0068] The following points are clear from the arrangement of the lead frame 45, the power semiconductor elements 41 to 44, and the individual gate wirings 51 to 54 described with reference to FIGS.

[0069] (1) For example, gate electrodes of two power semiconductor elements and individual gate wirings connected thereto are arranged in a gap between the two branched portions of the lead frame. The gap is a space formed inside the lead frame 45 when viewed from above with respect to the plane of the insulating substrate 10, and refers to a space provided to prevent interference between the individual gate wirings and the lead frame.

[0070] For example, the gate electrodes 41G and 42G of the power semiconductor elements 41 and 42 and the individual gate wirings 51 and 52 are sandwiched between two lead frame branch portions when viewed from above with respect to the plane of the insulating substrate 10.

[0071] (2) Current flowing from the source electrodes of the power semiconductor elements 41-44 flows via the connection surfaces 45P1-45P4 to the connection surfaces 45A1-45A2 connected to the conductor layer pattern 15. The connection surface 45A1 is positioned between the connection surfaces 45P1 and 45P2 in a direction perpendicular to the arrangement of the power semiconductor elements 41 and 42 and parallel to the planar direction of the insulating substrate 10. This is because the electrical path length from the connection surface 45P1 to the connection surface 45A1 is equal to the electrical path length from the connection surface 45P2 to the connection surface 45A1. The same applies to the connection surfaces 45P3, 45P4, and 45A2. Consideration has been given to ensure that the switching current flowing through the power semiconductor elements 41 to 42 is evenly divided with the center of the insulating substrate 10 in the longitudinal direction as the axis of symmetry, and similarly, consideration has been given to ensure that the switching current flowing through the power semiconductor elements 43 to 44 is evenly divided.

[0072] (3) The connection portion (2A in FIG. 1) between intermediate voltage terminal 2 and conductor layer pattern 13 is arranged in a direction connecting the connection positions (25P1, 25P2, 26P1, 26P2) between lead frames 25 and 26 constituting the high-voltage side switch circuit and the power semiconductor element, and the connection positions (25A2, 26A2) between lead frames 25 and 26 and conductor layer pattern 13. In other words, intermediate voltage terminal 2 is arranged in the longitudinal direction (current flow) of the branched portions of lead frames 25 and 26.

[0073] Furthermore, the connection portion (reference numeral 3A in FIG. 1) between low-voltage side main terminal 3 and conductor layer pattern 15 is arranged in a direction connecting connection positions (45P1 to 45P4) between lead frame 45 constituting the low-voltage side switch circuit and the power semiconductor element, and connection positions (45A1, 45A2) between lead frame 45 and conductor layer pattern 15. This arrangement is intended to prevent unnecessary induction magnetic fields from being generated in individual gate wiring 31 to 34, 51 to 54 of each power semiconductor element when current flows through the branching portions of each lead frame via conductor layer patterns 13 and 15 to intermediate voltage terminal 2 and low-voltage side main terminal 3.

[0074] With the structure clarified above, in the case of a low-voltage side switch circuit as an example, it is possible to reduce the noise voltage superimposed on the gate voltage that determines the switching operation of the power semiconductor elements 41 to 44 due to the influence of the magnetic field generated by the current flowing through the lead frame 45. This effect will be described below in comparison with the <Comparative Example>.

[0075] In the power semiconductor module 100 of this embodiment, the source electrodes of the power semiconductor elements are electrically and thermally connected to the conductor layer patterns using lead frames 25, 26, and 45. Heat generated by the power semiconductor elements is primarily dissipated from the drain electrode toward the base plate 99 (FIG. 2), which functions as a heat sink. However, if the lead frames are made of a material with good thermal conductivity, such as copper, they act as a second heat dissipation path, effectively lowering the temperature of the power semiconductor elements. When viewed as a heat conduction path, the lead frames have the effect of distributing heat near the power semiconductor elements to the conductor layer patterns on the insulating substrate 10, which are separated from the power semiconductor elements. This increases the area of ​​the heat conduction path, and therefore clearly functions as a heat dissipation path.

[0076] [Effects] The effects obtained by this embodiment will be described below. Before describing the effects of this embodiment, a comparative example will first be described.

[0077] <Structure of Comparative Example> A comparative example will be described with reference to FIGS. 5 to 7. FIG.

[0078] 5 is a plan view of a power semiconductor module 110 of the comparative example, viewed from above, showing a low-voltage side switch circuit.

[0079] The comparative example shown in Fig. 5 uses a lead frame 46. The same components as those in Fig. 1, such as the insulating substrate (insulating layer), power semiconductor element, and conductor layer pattern, have the same functions as those in Fig. 1, and therefore descriptions thereof will be omitted.

[0080] 1, a power semiconductor module 110 of the comparative example shown in Fig. 5 configures a half-bridge circuit using a plurality of conductive layers and power semiconductor elements on a single insulating substrate 10. The number of power semiconductor elements is also the same as in Fig. 1, and this is an example in which four power semiconductor elements are used in the low-voltage side switch circuit for comparison.

[0081] The power semiconductor module 110 of the comparative example differs from the power semiconductor module 100 of FIG. 1 in the arrangement of the gate electrodes of the power semiconductor elements and their individual gate wiring, and in the shape of the lead frame 46 .

[0082] The lead frame 46 has bonding surface portions 46P1 to 46P4 and is connected to the source electrodes of the power semiconductor elements 41 to 44.

[0083] The bonding surfaces 46P1 and 46P2 are electrically bonded to the source electrodes of the power semiconductor elements 41 and 42, and connect the current flow to the conductor layer pattern 11 via the bonding surface 46A1. What differs from the lead frame 45 shown in Fig. 1 is the arrangement relationship between the current flowing parts of the lead frame and the gate electrodes and individual gate wirings of the power semiconductor elements.

[0084] In the power semiconductor module 110, when viewed from above relative to the plane of the insulating substrate 10, the gate electrode 41G and the individual gate wiring 51′ are arranged independently on the left side of the branch portion of the lead frame 46 (the portion from the bonding surface portions 46P1 and 46P2 to the bonding surface portion 46A1), and are connected to the conductor layer pattern 16 that serves as the gate wiring.

[0085] On the other hand, the gate electrode 42G and the individual gate wiring 52', and the gate electrode 43G and the individual gate wiring 53' are arranged between the portion from bonding surfaces 46P1 and 46P2 to bonding surface 46A1, which is a branch portion of the lead frame 46, and the portion from bonding surfaces 46P3 and 46P4 to bonding surface 46A2. Furthermore, the gate electrode 44G and the individual gate wiring 54' are arranged on the right side of the branch portion of the lead frame from bonding surfaces 46P3 and 46P4 to bonding surface 46A2.

[0086] That is, the wiring related to the gates of the four power semiconductor elements 41 to 44 arranged in parallel is arranged in a different manner with respect to the branching portion of the lead frame 46. The details will be described in detail with reference to Figures 6A to 6C.

[0087] <Comparative Example: Explanation of Magnetic Field Distribution> Figure 6A is a diagram that shows a schematic diagram of the change in magnetic field distribution due to a change in main current for the power semiconductor elements 41 to 44 that constitute the low-voltage side switch circuit of the <Comparative Example> shown in Figure 5. Here, the magnetic field H is used as a "term that indicates the properties of space," and the magnetic flux density B is used as an index that indicates the strength of a local magnetic field within the magnetic field, that is, the distribution of the magnetic field. The magnetic flux density indicates the strength of the magnetic flux per unit area, and its unit is [Wb / m ２ ].

[0088] Fig. 6B is a diagram showing a cross-sectional image taken along line A-A' in Fig. 6A. Fig. 6C is a diagram showing a schematic diagram of the relationship between the noise voltage generated in the individual gate wiring of each power semiconductor element and the magnetic flux density. It should be noted that Figs. 6A and 6B are diagrams showing only the elements necessary for the explanation of the effects, for the sake of convenience.

[0089] 6A is a schematic diagram showing the transient flow of switching currents from the power semiconductor elements 41 to 44 in the lead frame 46 of the comparative example. For example, when the switching current ΔI1 of the power semiconductor element 41 flows transiently, an induced magnetic field is generated. The induced magnetic field is generated according to the right-hand rule with respect to the direction of the current ΔI1, so that in the vicinity of the individual gate wiring 51′, the magnetic field is oriented from the front to the back of the page. In FIG. 6B, this local magnetic field distribution is represented as magnetic flux density B1. The magnetic field is depicted as an arrow, with a symbol of a cross within a circle, representing the feathers of an arrow.

[0090] On the other hand, when the switching current ΔI4 of the power semiconductor element 44 flows transiently and a current ΔI5 also flows in the conductor layer pattern, the induced magnetic field is generated according to the right-hand screw rule in the direction of the currents ΔI4 and ΔI5, and therefore the direction of the magnetic field in the vicinity of the individual gate wiring 54' is from the back to the front of the page. This case is represented by a symbol of a small circle inside a circle, as indicated by an arrowhead.

[0091] That is, magnetic flux density B1 near the individual gate wiring of power semiconductor element 41 is generated from the front to the back of the paper by current ΔI1. Magnetic flux density near the individual gate wiring of power semiconductor element 44 is generated from the back to the front of the paper by currents ΔI4 and ΔI5.

[0092] The magnetic flux density near the individual gate wiring 52' of the power semiconductor element 42 is affected by the induced magnetic fields from the currents ΔI2 and ΔI3 flowing through the two adjacent lead frames 46, and therefore becomes a magnetic flux density that is a composite of the magnetic flux density B21 directed from the back to the front of the paper and the magnetic flux density B32 directed from the front to the back of the paper.

[0093] The magnetic flux density in the vicinity of individual gate wiring 53' of power semiconductor element 43 is also affected by the induced magnetic fields from currents ΔI2 and ΔI3, just like in the vicinity of individual gate wiring 52', and becomes a magnetic flux density that is a composite of magnetic flux density B22 directed from the back to the front of the paper and magnetic flux density B31 directed from the front to the back of the paper.

[0094] The magnitude and direction of the magnetic flux density, which has vector properties, will be explained using the schematic cross-sectional view shown in Figure 6B. Figure 6B is a cross-sectional structure diagram taken along the line A-A' in Figure 6A, viewed from the conductor layer pattern 15 toward the conductor layer pattern 12. The source and drain electrodes of the power semiconductor element are not shown.

[0095] The drain electrode of each power semiconductor element is electrically and thermally connected to the conductor layer pattern 12 via bonding materials (41DS to 44DS).

[0096] The gate electrodes of the power semiconductor elements are electrically connected to the conductor layer pattern 16, which is the gate wiring, via individual gate wirings (51' to 54').

[0097] The lead frame 46 has a protrusion facing the arrangement direction of the power semiconductor elements, and is electrically and thermally connected to the source electrodes of the power semiconductor elements 41 to 44 via bonding materials (41SS to 44SS).

[0098] The distribution of magnetic flux density will be described using individual gate wiring 52' and individual gate wiring 53' as examples. A magnetic flux density in the direction of B21 shown in the figure (dotted arrow) is generated near individual gate wiring 52' of power semiconductor element 42 due to a change in switching current ΔI2. Similarly, a magnetic flux density in the direction of B22 is generated near individual gate wiring 53' due to ΔI2. ΔI2, which generates the current change, is located at the edge of lead frame 46A, and there is a magnitude relationship between it being close to individual gate wiring 52' and far from individual gate wiring 53'. Therefore, the magnitude relationship between B21 and B22 can be summarized as |B21| > |B22|. B21 and B22 are oriented in the same direction.

[0099] In addition, the influence of the magnetic field generated by the change ΔI3 in the switching current is also superimposed near the individual gate wiring 52'. A magnetic flux density in the direction of B31 shown in the figure (dotted arrow) is generated near the individual gate wiring 53' of the power semiconductor element 43 due to the change ΔI3 in the switching current flowing through the lead frame 46B. A magnetic flux density in the direction of B32 is also generated near the individual gate wiring 52' due to ΔI3. Because ΔI3, which generates the current change, is located at the edge of the lead frame 46B, there is a magnitude relationship between the distances, that is, close to the individual gate wiring 53' and far from the individual gate wiring 52'. Therefore, the magnitude relationship between B31 and B32 is expressed as |B31| > |B32|.

[0100] Focusing on the vicinity of the individual gate wiring 52', it can be seen that magnetic flux densities B21 and B32 are generated simultaneously and are directed in opposite directions. Therefore, due to the cancellation of the magnetic fields, the magnitude of the effective magnetic flux density in the vicinity of the individual gate wiring 52' is |B21 - B32|. When the current changes ΔI2 and ΔI3 are equal in magnitude, the magnitude relationship of the magnetic flux densities caused by the current changes is proportional to the distance from the location where the current change occurs, and therefore the relationship is |B21| > |B32|. Therefore, as a result of adding up the superimposed magnetic fields, the direction of the magnetic flux density becomes the direction of B21.

[0101] Similarly, when focusing on the vicinity of the individual gate wiring 53′, the magnitude of the effective magnetic flux density is |B31−B22|. The magnitude relationship of the magnetic flux densities caused by current changes is |B31|>|B22|, and therefore, as a result of adding up the superimposed magnetic fields, the direction of the magnetic flux density becomes the direction of B31.

[0102] In the vicinity of the individual gate wiring 51', the current changes ΔI1 and ΔI2 in the lead frame 46A are factors in generating a magnetic field, but because there is a distance from the location where ΔI2 is generated, the magnetic field generated by the closest ΔI1 becomes the main factor. Therefore, a magnetic flux density B1 proportional to the magnitude of ΔI1 is generated.

[0103] In the vicinity of the individual gate wiring 54', due to the operation of a power semiconductor module equipped with both high-voltage and low-voltage switch circuits, the current change ΔI4 in the lead frame 46B and the current change ΔI5 flowing through the conductor layer pattern 11 are opposite in direction. Therefore, in the vicinity of the individual gate wiring 54' sandwiched between the locations where ΔI4 and ΔI5 are generated, the magnetic flux density B4 proportional to the magnitude of ΔI4 and the magnetic flux density B5 proportional to the magnitude of ΔI5 are oriented in the same direction. Therefore, in the vicinity of the individual gate wiring 54', the two magnetic flux densities are superimposed in the same direction.

[0104] The effective magnetic flux density (magnetic flux density when superimposed magnetic fields are added together) near the individual gate wiring can be summarized as follows: For convenience, the direction of magnetic flux density B1 shown in FIG.

[0105] The magnetic flux density B51' near individual gate wiring 51' is: B51' ≒ B1 < 0 ... formula (1) The magnetic flux density B52' near individual gate wiring 52' is: B52' ≒ B21 - B32 > 0 ... formula (2) The magnetic flux density B53' near individual gate wiring 53' is: B53' ≒ B31 - B22 < 0 ... formula (3) The magnetic flux density B54' near individual gate wiring 54' is: B54' ≒ B4 + B5 > 0 ... formula (4) Here, it can be seen that the strength of the change in the magnetic field near individual gate wiring 52' and individual gate wiring 53', which are located between switching currents ΔI2 and ΔI3, have different signs, but are the difference between magnetic flux densities in opposite directions, so the absolute values ​​of these values ​​are small, and the absolute values ​​of B51' and B54' which do not include magnetic flux densities in the opposite directions are large.

[0106] From the above, it is clear that in the configuration of the <Comparative Example>, with respect to the power semiconductor elements 41 to 44, the magnetic flux density in the vicinity of the individual gate wirings 51' to 54' varies greatly, resulting in the relationship described in the following equation.

[0107] |B52'| ≒ |B53'| < |B51'| < |B54'| ... Equation (5) B51' < B53' < B52' < B54' ... Equation (6) <Equivalent Circuit Description of Comparative Example and Equation for the Relationship Between Gate Voltages> Figure 6C shows an equivalent circuit using power MOSFET circuit diagram symbols (#41 to #44) that represents the effect of the magnetic field distribution due to the switching current described above using Figures 6A and 6B.

[0108] The current changes ΔI1 to ΔI4 flow from the source of each power MOSFET and through source current path inductances Ls41 to Ls44 into wiring corresponding to conductor layer pattern 15 shown in Fig. 6A. The gate of each power MOSFET is connected to wiring corresponding to conductor layer pattern 16 shown in Fig. 6A, which serves as gate wiring, through individual gate inductances (Lg51' to Lg54') corresponding to each individual gate wiring.

[0109] Symbols for the magnetic flux densities generated by the current changes ΔI1 to ΔI4 are shown near the individual gate inductances, and the mathematical expressions for the magnetic flux densities are shown at the bottom of the figure.

[0110] Referring to FIG. 7, the noise voltage Vnoise superimposed on the gate voltage of each power semiconductor element in response to the magnetic flux density in the vicinity of the individual gate wiring will be described.

[0111] FIG. 7 is a basic diagram illustrating the operating principle of a single power semiconductor element, from a change in its switching current to the superposition of a noise voltage on the gate voltage.

[0112] Although not shown in detail, a closed circuit 60 driven by a gate voltage is established between the gate (nG) and source (nS) of the power semiconductor element 40, and a drain-source closed circuit 70 including a part of the power semiconductor module is established between the drain (nD) and source (nS). Also, the individual gate wiring in the module structure diagram already explained is equivalently represented by an individual gate inductance Lg.

[0113] The operating principle will be explained starting from the occurrence of a change ΔIs in the switching current in the source (STEP 1).

[0114] In STEP 1, when a change in main current (switching current) ΔIs occurs, an induced magnetic field is induced.

[0115] In STEP 2, a magnetic flux density B is generated in response to the induced magnetic field generated in the vicinity of the individual gate inductance Lg.

[0116] In STEP 3, because the individual gate inductance Lg is part of a closed circuit including the gate drive circuit, an induced current ΔImi is induced. Here, the absolute value of ΔImi is proportional to the magnitude of the magnetic flux density B, so it is clear that the magnitude of the current flowing to the individual gate inductance Lg changes depending on the magnitude of the magnetic flux density B.

[0117] In STEP 4, an induced current ΔImi flows into the individual gate inductance Lg, and an induced electromotive force, that is, a noise voltage Vnoise, is generated in the individual gate inductance Lg, and the magnitude thereof follows equation (7).

[0118] Vnoise=Lg×d(Iim) / dt (7) where Lg is the inductance value of the individual gate wiring.

[0119] Since the magnitude of the induced current Iim is proportional to the magnitude of the magnetic flux density B, the transient rate of change d(Iim) / dt of the induced current is also proportional to B. Therefore, it is clear from equation (7) that a noise voltage Vnoise is generated in the gate voltage of the power semiconductor element depending on the magnitude of the magnetic flux density B.

[0120] The voltage sharing of the closed circuit that drives the gate, including Vnoise, is summarized below.

[0121] The gate-source voltage VgsChip to each power semiconductor element is determined by the gate drive voltage VgsDrv, the voltage V_Ls generated across the inductance Ls of the source current path, and the noise voltage Vnoise.

[0122] VgsChip=VgsDrv-V_Ls-Vnoise (8) V_Ls=Ls×d(Is) / dt (9) where d(Is) / dt in equation (9) is the time rate of change of the switching current. The value of V_Ls is determined by ΔIs and Ls, but is uncorrelated with the magnetic flux density B generated near the individual gate wiring.

[0123] Therefore, if VgsDrv is a constant value and the values ​​of Ls and d(Is) / dt are uniform for each power semiconductor element, it is clear that the gate-source voltage VgsChip applied to the power semiconductor element shown in equation (8) varies depending on Vnoise. In other words, if the values ​​are uniform for each power semiconductor element, the direction and magnitude of the gate induced current ΔImi determine Vnoise, and as a result, VgsChip fluctuates.

[0124] From the above, it can be seen that if there is variation in the magnitude and direction of the magnetic flux density B corresponding to the change ΔIs in the switching current, differences will occur in the gate-source voltage of each power semiconductor element, resulting in adverse effects such as large differences in the current and voltage waveforms during the switching period between elements.

[0125] In the case of the comparative example described with reference to FIGS. 6A to 6C, the magnitude relationship of Vnoise that varies the gate-source voltage VgsChip of each power semiconductor element is calculated as follows:

[0126] Referring to the magnitude relationship of the magnetic flux density B shown in equation (6), the relationship of the absolute values ​​is as follows:

[0127] |Vnoise42| ≈ |Vnoise43| < |Vnoise41| < |Vnoise44| ... Equation (10) The magnitude relationship, including positive and negative signs, is Vnoise41 < Vnoise43 < 0, 0 < Vnoise42 < Vnoise44| ... Equation (11) If we assume that the voltage V_Ls generated in the inductance Ls of the source current path is uniform for each power semiconductor element, the magnitude relationship of VgsChip is as follows from equations (8) and (11), and it is clear that there are differences between each power semiconductor element.

[0128] VgsChip44<VgsChip42<VgsChip43<VgsChip41 Equation (12) <Switching Waveform: Comparative Example> The phenomenon of noise superposition on the gate voltage accompanying changes in the main current shown in Figures 6A to 6C and 7 can be verified by using a circuit network obtained by performing electromagnetic field analysis on the structure of a power semiconductor module. The circuit network here refers to a circuit network that includes self-inductance components and capacitance components generated in wiring, and mutual inductance components that indicate magnetic coupling generated between wiring and between the lead frame and wiring.

[0129] By extracting magnetic coupling from the module structure and creating an equivalent circuit in the form of self-inductance and mutual inductance in the circuit network, it is possible to calculate the effects of the induced magnetic field and the resulting induced current described above.By combining this circuit network with a transistor model of the power semiconductor element and performing a transient analysis, it is possible to analytically calculate the noise voltage superimposition on the gate voltage.

[0130] First, the switching waveforms in the low potential side switch circuit of the <Comparative Example> shown in FIG. 5 were calculated by circuit analysis, and the obtained results are shown in FIGS. 9A and 9B.

[0131] 9A shows an example of calculated waveforms of currents Is_43 and Is_44 (corresponding to ΔI3 and ΔI4 in FIG. 6) flowing through power semiconductor elements 43 and 44 when the power semiconductor elements are turned on. In other words, in terms of FIG. 6C, it shows the magnitude of the influence of the strength of magnetic field changes B53' and B54' in terms of switching current waveforms. In other words, it shows how noise voltages Vnoise43 and Vnoise44 superimposed on the gate voltages of the power semiconductor elements affect the switching waveforms.

[0132] During the rising period of the switching current, a difference occurs between the current values ​​of Is_43 and Is_44, causing them to separate. This is an example that supports the phenomenon of a deviation in the switching current values, occurring when a magnetic field changes as the switching current transiently changes (in this case, the current increases due to turn-on), as shown in Figures 6A to 6C and 7, and noise voltages of different values ​​are superimposed on the gate voltages of power semiconductor elements 43 and 44. As the switching current increases, the switching current values ​​of each power semiconductor element differ, and the peak current values ​​of the turn-on current also differ.

[0133] This clearly indicates that differences occur in the switching loss at turn-on. Similarly, differences occur in the switching loss for each power semiconductor element at turn-off.

[0134] Figure 9B shows the transient waveform of the instantaneous power obtained by multiplying the switching current by the drain-source voltage of the power semiconductor element. As inferred from the difference in the transient waveform of the switching current, the instantaneous power differs during the rise period at turn-on. Therefore, it can be seen that the arrangement of the power semiconductor element and lead frame in the <Comparative Example> in Figure 5 results in a difference in the switching loss of the power semiconductor element.

[0135] For example, when the switching loss is calculated assuming a power supply voltage of 800 V and a switching current of 400 A, the turn-on switching loss of power semiconductor element 43 can be roughly calculated as 9.1 mJ per switching. On the other hand, the current during switching of power semiconductor element 44 is small, so the loss is 8.4 mJ. It is clear that a difference of approximately 8% occurs between these two power semiconductor elements.

[0136] <<Explanation of Magnetic Field Distribution in This Example>> FIGS. 8A to 8C are diagrams showing the effects of this example of the present invention in comparison with a <Comparative Example>>.

[0137] Fig. 8A is a diagram schematically showing the influence of a magnetic field due to a main current on power semiconductor elements 41 to 44 constituting the low-voltage side switch circuit of Example 1 shown in Fig. 1 to Fig. 3. Fig. 8B shows a cross-sectional image (line A-A') of the schematic diagram of Fig. 8A, and Fig. 8C is a diagram simply showing, using an equivalent circuit, the noise voltage generated in the inductance of the individual gate wiring of each power semiconductor.

[0138] 8A is a diagram illustrating the distribution of magnetic fields when switching currents from the power semiconductor elements 41 to 44 flow transiently through the lead frame 45 of this embodiment. It should be noted that the lead frame 45 is shown divided into two components, 45A and 45B, for ease of comparison with FIGS. 6A to 6C and for convenience of explaining the operating principle. The following explanation is also applicable to lead frames that are shaped to connect to four power semiconductor elements, such as the lead frame 45 shown in FIG. 1.

[0139] The power semiconductor elements 41 to 44 have drain electrodes (not shown) connected to the conductor layer pattern 12, gate electrodes connected via individual gate wirings 51 to 54 to the conductor layer pattern 16 that functions as a gate wiring pattern, and source electrodes connected to the lead frame (45A, 45B) via a bonding material such as solder.

[0140] The main current flowing through lead frames 45A and 45B flows through the lead frame branches in the directions indicated by the arrows of current changes ΔI1 to ΔI4. As shown in Fig. 8A, when viewed from above, insulating substrate 10 is characterized by the structure in which two lead frame branches sandwich individual gate wirings 51 to 54. In the case of Fig. 8A, the two lead frame branches sandwich individual gate wirings corresponding to two power semiconductor elements.

[0141] An induced magnetic field is generated when a current change (ΔI1 to ΔI4) occurs in the main current flowing from the source electrodes of the power semiconductor elements 41 to 44. Focusing on the vicinity of the individual gate wirings 51 to 54, it can be seen that the area is affected by the induced magnetic fields caused by multiple current changes.

[0142] For example, a magnetic field caused by a current change ΔI1 is generated in the direction from the back to the front of the paper near the individual gate wiring 51. A magnetic field caused by a current change ΔI2 is generated in the direction from the front to the back of the paper.

[0143] Current changes ΔI1 and ΔI2 in the current flowing through the branch portion of lead frame 45A flow through conductor layer pattern 15 via connection portion 45A1 between the lead frame and conductor layer pattern 15. Current changes ΔI3 and ΔI4 in the current flowing through the branch portion of lead frame 45B flow through conductor layer pattern 15 via connection portion 45A2 between the lead frame and conductor layer pattern 15. At connection portion 3A between low-voltage side main terminal 3 and conductor layer pattern 15, the sum of the above current changes, ΔI1+ΔI2+ΔI3+ΔI4, flows into low-voltage side main terminal 3.

[0144] In this way, the connection portions (45A1, 45A2) between the lead frames 45A, 45B and the conductor layer pattern 15, and the connection portion 3A between the low-voltage side main terminal 3 and the conductor layer pattern 15 are arranged along the direction in which the current flows through the branch portion of the lead frame. In other words, the current flowing through the lead frame is arranged so that it moves uniformly away from the individual gate wirings 51 to 54. This is a measure to manage the induced magnetic field generated near the individual gate wiring and to prevent the generation of a new induced magnetic field that will become a noise voltage in the gate wiring.

[0145] In order to explain the direction and magnitude relationship of the local magnetic flux density, a cross-sectional image (cross-section of line A-A' in FIG. 8A) is shown in FIG. 8B. FIG. 8B shows a cross-sectional structure viewed from the cross-section of line A-A' in the direction of arrangement of conductor layer patterns 16 and 12. The electrode patterns of the source electrode, drain electrode, and gate electrode of the power semiconductor element are not shown.

[0146] The drain electrode of each power semiconductor element is electrically and thermally connected to the conductor layer pattern 12 via bonding materials (41DS to 44DS). The gate electrode of each power semiconductor element is electrically connected to the conductor layer pattern 16, which is the gate wiring, via individual gate wirings 51 to 54. The lead frames 45A and 45B have convex portions facing the arrangement direction of the power semiconductor elements, and are electrically and thermally connected to the source electrodes of the power semiconductor elements 41 to 44 via bonding materials (41SS to 44SS).

[0147] The induced magnetic field generated near the individual gate wirings 51 to 54 of the power semiconductor elements 41 to 44 will be summarized.

[0148] Near the individual gate wiring 51, the magnetic flux density B11 due to the current change ΔI1 and the magnetic flux density B22 due to the current change ΔI2 are dominant. Although magnetic flux densities are generated by other current changes, the dominant factors will be described by comparing the magnitude of the absolute values ​​of the magnetic flux densities. The magnetic flux densities B11 and B22 have opposite directions, and the magnitude relationship of their absolute values ​​is proportional to the distance from the edge of the lead frame branch where the current change occurs, so |B11| > |B22|.

[0149] The magnetic flux density B21 due to the current change ΔI2 and the magnetic flux density B12 due to the current change ΔI1 are dominant near the individual gate wiring 52. The magnetic flux densities B21 and B12 have opposite directions, and the magnitude relationship between their absolute values ​​is |B21|>|B12|, based on the same reasoning as above.

[0150] The same concept as described above for the vicinity of individual gate wirings 51 and 52 can also be applied to the vicinity of individual gate wirings 53 and 54. Magnetic flux density B31 and magnetic flux density B42 are in opposite directions, and the magnitude relationship between their absolute values ​​is |B31|>|B42|. Furthermore, magnetic flux density B41 and magnetic flux density B32 are in opposite directions, and the magnitude relationship between their absolute values ​​is |B41|>|B32|.

[0151] An induced magnetic field is generated by the current change ΔI5 in the conductor layer pattern 11, and its magnetic flux density is shown as B5, but since there is a distance from the individual gate wiring of the power semiconductor element, its influence is ignored.

[0152] 8B, the effective magnetic flux density (magnetic flux density when superimposed magnetic fields are added together) near the individual gate wiring can be summarized as follows: For convenience, the direction of magnetic flux density B21 shown in FIG. 8B, that is, the direction from the source electrode to the drain electrode of the power semiconductor element, is determined to be the negative direction.

[0153] The magnetic flux density B51 near the individual gate wiring 51 is: B51≈B11-B22>0 Formula (13) The magnetic flux density B52 near the individual gate wiring 52 is: B52≈B21-B12<0 Formula (14) The magnetic flux density B53 near the individual gate wiring 53 is: B53≈B31-B42>0 Formula (15) The magnetic flux density B54 near the individual gate wiring 54 is: B54≈B41-B32<0 Formula (16) |B51|≈|B52|≈|B53|≈|B54| Formula (17) B51>0, B52<0, B53>0, B54<0 Formula (18) As described in equations (13) to (16), the magnetic flux densities B51 to B54 are all composites of magnetic flux densities in opposite directions, and although their directions are divided into positive and negative, the variation in absolute values ​​can be kept small compared to the structure of FIG. 6B.

[0154] Assuming that the current changes ΔI1 to ΔI4 are equal in both the comparative example of FIG. 6B and the present embodiment of FIG. 8B, the variation in magnetic flux density near the individual gate wiring differs between the comparative example and the present embodiment due to the difference in the positional relationship between the lead frame and the individual gate wiring.

[0155] <<Equivalent Circuit Description and Gate Voltage Magnitude Relationship of the Present Example>> FIG. 8C shows the effect of the magnetic field distribution due to the switching current described above with reference to FIGS. 8A and 8B, expressed in an equivalent circuit using power MOSFET circuit diagram symbols (#41 to #44).

[0156] The current changes ΔI1 to ΔI4 flow into the wiring corresponding to the conductor layer pattern 15 shown in Fig. 8A via the inductances Ls41 to Ls44 of the source current path. The gate of each power MOSFET is connected to the wiring corresponding to the conductor layer pattern 16 shown in Fig. 8A, which serves as the gate wiring, via the individual gate inductances Lg51 to Lg54 corresponding to each individual gate wiring. Symbols for the magnetic flux densities generated by the current changes ΔI1 to ΔI4 are shown near the individual gate inductances, and mathematical expressions for the magnetic flux densities are shown at the bottom of the figure.

[0157] In the case of the present embodiment described with reference to FIGS. 8A to 8C, the magnitude relationship of Vnoise that varies the gate-source voltage VgsChip of each power semiconductor element is calculated as follows:

[0158] Referring to the magnitude relationships of the magnetic flux densities B51 to B54 described in equations (13) to (18), the relationships of the absolute values ​​are as follows:

[0159] |Vnoise41| ≒ |Vnoise42| ≒ |Vnoise43| ≒ |Vnoise44| ...Equation (19) The magnitude relationship, including positive and negative signs, is: Vnoise42 ≒ Vnoise44 < 0, 0 < Vnoise41 ≒ Vnoise43 ...Equation (20) Assuming that the voltage V_Ls generated across the inductance Ls of the source current path is uniform for each power semiconductor element, the magnitude relationship of VgsChip is as follows from equations (8) and (20).

[0160] VgsChip41≒VgsChip43<VgsChip42≒VgsChip44 Equation (21) <Comparison between Comparative Example and This Example: FIGS. 10 and 11> Figure 10 illustrates and organizes the magnetic flux densities B51' to B54' near the individual gate wirings of the Comparative Example, with reference to Equations (5) and (6). The magnitude relationships of the gate voltages VgsChip41 to VgsChip44 of each power semiconductor element, which are determined in accordance with the magnetic flux densities B51' to B54', are also illustrated.

[0161] Figure 10 shows that magnetic flux densities B52' and B53' are almost equal in absolute value, but have different directions. Magnetic flux density B51' represents only a single induced magnetic field due to current change ΔI1, and is a negative magnetic flux density. Its absolute value is greater than B52' and B53'. This is because B52' and B53' are themselves generated by the difference between two magnetic flux densities with different directions. B54' is composed of the sum of magnetic flux densities in the same direction due to current changes ΔI4 and ΔI5. The magnetic flux density is oriented in the positive direction, and its absolute value is greater than B51'.

[0162] For convenience, the difference in magnetic flux density between B51' and B54' is defined as ΔB1, and the difference in magnetic flux density between B53' and B54' is defined as ΔB2. The gate voltages VgsChip41-44 of each power semiconductor element reflect the influence of gate noise voltages proportional to the magnetic flux densities B51'-B54', so VgsChip44 is the smallest and VgsChip41 is the largest. Current deviations occur between the power semiconductor elements during switching depending on the magnitude of the gate voltage VgsChip. For example, since VgsChip43 > VgsChip44, the current waveform at turn-on shown in FIG. 9A is such that Is_43 flowing through power semiconductor element 43 is larger than Is_44 flowing through power semiconductor element 44.

[0163] FIG. 11 graphically summarizes the magnetic flux density near the individual gate wiring of this embodiment, with reference to equations (13) to (18). It also shows an image of the magnitude of the gate voltage VgsChip. From equation (17), it can be seen that the absolute values ​​of magnetic flux densities B51 to B54 are approximately equal, but B51 and B53 are positive, and B52 and B54 are negative. Because the magnetic flux density near the individual gate wiring of the four power semiconductor elements 41 to 44 varies in both positive and negative directions, an absolute value of ΔB3 occurs. However, it is clear that this variation can be suppressed to a smaller value than in the comparative example shown in FIG. 10. Comparing the magnetic flux density differences ΔB1 and ΔB2 shown in FIG. 10, it can be said that ΔB3<ΔB1 and ΔB3<ΔB2.

[0164] The magnitude relationship of the gate voltage VgsChip in FIG. 11 is two levels, reflecting equation (21), and the difference voltage ΔVgs3 is smaller than the gate voltage differences ΔVgs1 and ΔVgs2 shown in FIG. 10, and it can be said that ΔVgs3<ΔVgs1 and ΔVgs3<ΔVgs2.

[0165] In this embodiment, the effect of suppressing the range of variation in the gate noise voltage between the power semiconductor elements and the range of variation in the gate voltage VgsChip is due to the structure shown in FIG. 8A in which "when the insulating substrate is viewed from above, two lead frame branch portions sandwich the individual gate wirings 51 to 54."

[0166] <Switching Waveforms: In the Case of the Present Example> Fig. 12A shows an example of calculation of the waveforms of currents Is_43 and Is_44 that flow through power semiconductor elements 43 and 44 when the power semiconductor elements are turned on in this example. The calculation conditions are the same as in Fig. 9A, but the arrangement of the power semiconductor elements and lead frames in the low-voltage side switch circuit is the structure of this example.

[0167] Comparing with FIG. 9A, it can be seen that the waveform shapes of current Is_43 and current Is_44 are similar at the rising edge of the switching current, and the difference between the currents is small.

[0168] Figure 12B shows the transient waveform of the instantaneous power obtained by multiplying the switching current by the drain-source voltage of the power semiconductor element. As with the transient waveform of the switching current, the difference in the instantaneous power during the rise period at turn-on is also clearly smaller than in Figure 9B. Therefore, it is clear that by applying this embodiment, the difference in switching loss between the power semiconductor elements arranged in parallel can be reduced.

[0169] As in the comparative example, in an example where the switching loss is calculated with a power supply voltage of 800 V and a switching current of 400 A, the switching loss at turn-on of power semiconductor element 44 can be roughly estimated to be 9.1 mJ per switching, and the loss at turn-on of power semiconductor element 43 is also 8.8 mJ. The difference in switching loss at turn-on between these two power semiconductor elements is approximately 3%.

[0170] Since the difference in switching loss at turn-on in the comparative example (difference between power semiconductor elements 43 and 44) ​​was 8%, it became clear that this example can reduce the difference in switching loss between power semiconductor elements from 8% to 3%, or about 40%.

[0171] By applying the structure of this embodiment, it is possible to reduce "variation in switching loss between power semiconductor elements arranged in parallel," which is a major factor in the power cycle resistance of power semiconductor elements used in automobile inverters, etc.

[0172] Second Embodiment A power semiconductor module according to a second embodiment of the present invention will be described with reference to FIG.

[0173] In the present embodiment shown in FIG. 13, the lead frames 25 and 26 of the high-voltage side switch circuit are changed to lead frames 27 and 28, and the lead frame 45 of the low-voltage side switch circuit is changed to lead frame 47, in comparison with the power semiconductor module 100 of the first embodiment (FIG. 1).

[0174] In the lead frames of the high-voltage side and low-voltage side switch circuits used in this embodiment, the connection portions to the conductor layer patterns 13 and 15 are separated.

[0175] As shown, the connection portions of the lead frames 27 and 28 are separated into 27B-1 and 27B-2, and 28B-1 and 28B-2, respectively. The connection portions of the lead frame 47 are separated into 47A1-1, 47A1-2, 47A2-1, and 47A2-2.

[0176] The effects of this embodiment include those described in the first embodiment, and also include the effects described in the first embodiment. By separating the connection between the lead frame and the conductor layer pattern into multiple parts and reducing the total cross-sectional area of ​​the connection, the stress that the lead frame exerts on the conductor layer pattern and the insulating substrate 10 can be reduced while maintaining electrical characteristics equivalent to those of the first embodiment. In other words, the rigidity of the lead frame can be reduced. By adopting this structure, the reliability of the power semiconductor module can be improved.

[0177] The insulating substrates and conductor layer patterns mounted on power semiconductor modules periodically warp due to heat generated by the power semiconductor elements. To improve reliability, it is desirable for the rigidity of the components to be approximately the same. Therefore, as a measure to adjust the rigidity of the lead frame, the shape of the connection part (the width of the connection part of the lead frame) is designed as described above.

[0178] Third Embodiment A power semiconductor module according to a third embodiment of the present invention will be described with reference to FIG.

[0179] The present embodiment shown in FIG. 14 is configured such that, compared to the power semiconductor module 100 of Example 1 (FIG. 1), the lead frame 45 of the low-voltage side switch circuit is separated into two lead frames: a lead frame 45-1 that electrically connects the source electrodes of the power semiconductor elements, and a lead frame 45-2 that electrically connects the source electrodes of the power semiconductor elements and the conductor layer pattern 15.

[0180] If a current imbalance occurs when each power semiconductor element outputs a switching current from its source electrode, the lead frame 45-1 becomes a flow path for the unbalanced current. In Fig. 14, four power semiconductor elements are electrically connected to each other, but it is not necessary to connect all of the power semiconductor elements, and it is sufficient to selectively connect the power semiconductor elements as needed.

[0181] Therefore, the effects of this embodiment include the effects described in the first embodiment as well as the effect of selectively realizing electrical connection of source electrodes between power semiconductor elements, while electrically connecting the source electrodes of functionally essential power semiconductor elements to the conductor layer pattern 15.

[0182] By adopting this lead frame structure, it is possible to reduce variations in switching elements between power semiconductor elements connected in parallel in a power semiconductor module.

[0183] Fourth Embodiment A power conversion device according to a fourth embodiment of the present invention will be described with reference to FIG.

[0184] FIG. 15 is a block diagram showing the circuit configuration of a power conversion device 260 of this embodiment.

[0185] FIG. 15 shows an example of a three-phase AC motor that drives the axles of an electric vehicle, which is composed of a battery (or power supply circuit) 250, a power conversion device 260, and an electric motor 270 that serves as a load.

[0186] The power conversion device 260 of this embodiment includes a 6-in-1 power module configured with a three-phase circuit in which the power semiconductor module 100 (FIG. 1) is used as one phase, a capacitor 240, and a control circuit 230. The power semiconductor module 100 in FIG. 15 is a half-bridge circuit.

[0187] The power conversion device 260 includes gate drive circuits 210 (210a, 210b, 210c) equal in number to the number of AC phases. The power conversion device 260 holds a main voltage (Vcc) using a capacitor 240, and gate drive signals for the power semiconductor elements in each power semiconductor module 100 or 101 generated by a control circuit 230 are input to each power semiconductor module 100, 101 via the gate drive circuits 210a, 210b, 210c.

[0188] The leg circuits 220a, 220b, and 220c respectively constitute a first-phase inverter leg, a second-phase inverter leg, and a third-phase inverter leg. The output of each inverter leg is connected to the electric motor 270.

[0189] In this embodiment, the leg circuits 220a, 220b, and 220c have the same circuit configuration, so the circuit configuration will be described using the leg circuit 220a as an example.

[0190] The leg circuit 220a includes a pair of upper and lower switch circuits configured by the power semiconductor module 100 or 101, and a gate drive circuit 210a that controls the on / off of the power semiconductor module.

[0191] According to this embodiment, the power semiconductor modules 100, 101 mounted on the power conversion device 260 are the power semiconductor modules described in any one of the first to third embodiments, and by reducing the variation in switching loss of the power semiconductor elements arranged in parallel and built into the module, it is possible to improve the power cycle resistance that determines the lifespan of the power semiconductor module.

[0192] Therefore, the power conversion device 260 configured using the power semiconductor modules 100, 101 and the motor drive system for an electric vehicle configured including the power conversion device 260 can perform high-speed switching and obtain high reliability.

[0193] The present invention is not limited to the above-described embodiments, but includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0194] For example, the dimensions and insulation distances of the components constituting the power semiconductor module 100 may be arbitrary depending on the application.

[0195] Furthermore, the chip arrangement of the power semiconductor elements that make up the power semiconductor module 100 is not limited to the form shown in the drawings.

[0196] Furthermore, in the embodiment in which the upper and lower switch circuits are mounted on the same power semiconductor module 100, the explanation has been given focusing on one of the switch circuits, but the other switch circuit also has the same effect, and there is no reduction in the effect due to the 2-in-1 configuration.

[0197] 1, for example, the lead frames connecting the power semiconductor elements are such that in the high-voltage side switch circuit, two lead frames, 25 and 26, connect four power semiconductor elements, and in the low-voltage side switch circuit, one lead frame 45 connects four power semiconductor elements. The number of lead frames and the combination of connected power semiconductor elements are not limited as long as they are within a range that achieves the effects shown in the above embodiments.

[0198] The power semiconductor module 100 may be a unipolar device such as a JFET (Junction Field Effect Transistor) or a bipolar device such as an IGBT, in addition to a MOFET. Depending on the device, the main terminal and the sense terminal are called the "collector" and the "emitter" instead of the above-mentioned "drain" and "source."

[0199] Furthermore, it is clear that the effects described in this specification can be obtained regardless of the form in which the power semiconductor module is configured, whether the 2-in-1 configuration using the power semiconductor module 100 shown in the embodiment is used as a module unit, or whether three 2-in-1 configurations are combined for three phases to form a 6-in-1 module.

[0200] Furthermore, a power conversion device to which the power semiconductor module 100 is applied can be used in motor drive systems for various types of moving objects, including railway vehicles and electric vehicles, as well as industrial systems, PCSs (Power Conditioning Systems) in solar power generation systems and wind power generation systems, smart grids (power distribution systems), and the like.

[0201] DESCRIPTION OF SYMBOLS 1...High-voltage side main terminal 2...Intermediate voltage terminal 2A...Connection portion between intermediate voltage terminal 2 and conductor layer pattern 13 3...Low-voltage side main terminal 3A...Connection portion between low-voltage side main terminal 3 and conductor layer pattern 15 4-9...Control terminal pin (auxiliary terminal) 10...Insulating substrate (insulating layer) 11-20, 98...Conductive layer patterns 21-24, 40-44...Power semiconductor elements 21G-24G, 41G-44G...Gate electrodes 21S, 24S, 44S...Source electrodes 21SS, 24DS, 24SS, 26AS, 26BS, 41SS, 42SS, 43SS, 44DS, 44SS, 97...Solder layer 25, 26, 27, 27B-1, 27B-2, 28, 28B-1, 28B-2, 45, 45A, 45B, 45-1, 45-2, 46, 46A, 46B, 47, 47A1-1, 47A1-2, 47A2-1, 47A2-2... Lead frames 25A, 25A2, 25B, 26A, 26A2, 26B, 45A, 45A1, 45A2, 45B... Connection surface portions (connection portions) for connection with conductor layer patterns of lead frames 25P1 to 25P2, 26P1 to 26P2, 45P1 to 45P4, 45P1LP to 45P4LP... Connection surface portions (connection portions) for connection with electrodes of power semiconductor elements of lead frames 31 to 34, 51 to 54, 51' to 54'... Individual gate wiring 41DS to 44DS, 41SS to 44SS... Bonding material 41G to 44G... Gate electrode 44D... Drain electrode 45H... Hole portion of lead frame 46A1, 46A2... Bonding surface portion with conductor layer pattern of lead frame 46P1 to 46P4... Bonding surface portion of lead frame with electrode of power semiconductor element 60, 70... Closed circuit 99... Base plate 100, 101... Power semiconductor module (half bridge circuit) 110... Power semiconductor module of comparative example 210, 210a, 210b, 210c... Gate drive circuit 220, 220a, 220b, 220c... Leg circuit 230... Control circuit 240... Capacitor 250... Battery (or power supply circuit) 260... Power conversion device 270... Motor Lg51 to Lg54, Lg51' to Lg54'...individual gate inductances Ls41 to Ls44...inductances.

Claims

1. A semiconductor device including one or more half-bridge circuits configured by connecting a first switch and a second switch using power semiconductor devices in series, the semiconductor device comprising: an insulating substrate; a first conductor layer pattern, a second conductor layer pattern, and a third conductor layer pattern disposed on one surface of the insulating substrate and electrically insulated from each other; a plurality of power semiconductor devices disposed on the first conductor layer pattern and connected in parallel to each other; a lead frame connecting each of the plurality of power semiconductor devices and the second conductor layer pattern; an individual gate wiring connecting a gate electrode of each of the plurality of power semiconductor devices and the third conductor layer pattern; and a main terminal connected to the second conductor layer pattern, wherein the lead frame has a first connection portion connected to an electrode surface of each of the plurality of power semiconductor devices, a lead frame branch portion branched into a plurality of parts, and a second connection portion provided at an end of the lead frame branch portion and connected to the second conductor layer pattern, and in a top view with respect to the insulating substrate, the gate electrode and the individual gate wiring are sandwiched between two of the lead frame branch portions.

2. The semiconductor device according to claim 1, wherein the main terminal is disposed in a longitudinal direction of the lead frame branch portion.

3. The semiconductor device according to claim 1, wherein the lead frame has a plurality of the first connection portions and is electrically connected to the plurality of power semiconductor devices.

4. The semiconductor device according to claim 1, wherein in a top view with respect to the insulating substrate, a part of the individual gate wiring, the first conductor layer pattern, and the third conductor layer pattern is disposed inside a region surrounded by two of the lead frame branch portions and the second conductor layer pattern, and a region where the insulating substrate is disposed without the first conductor layer pattern, the second conductor layer pattern, and the third conductor layer pattern is provided.

5. The semiconductor device according to claim 1, wherein in a top view with respect to the insulating substrate, the two lead frame branch portions are integrated at their ends to form one of the second connection surface portions, and the one second connection surface portion is disposed between the extension lines in the longitudinal direction of the two lead frame branch portions.

6. The semiconductor device according to claim 1, wherein the individual gate wiring is a bonding wire.

7. The semiconductor device according to claim 1, wherein in a top view with respect to the insulating substrate, the two lead frame branch portions each have the second connection surface portion individually, and are connected to the second conductor layer pattern by the second connection surface portion.

8. The semiconductor device according to claim 1, wherein the lead frame is configured by being divided into a plurality of lead frames, and the first connection surface portion and the second connection surface portion are formed on different lead frames.

9. A power conversion device including a main circuit having one or more pairs of high-voltage side and low-voltage side switch circuits, and a drive circuit for driving the high-voltage side and low-voltage side switch circuits, wherein the high-voltage side and low-voltage side switch circuits have the semiconductor device according to any one of claims 1 to 8.

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