Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises: a support; a first semiconductor element; a first control terminal; and a sealing resin. The first semiconductor element is supported on the support. The first control terminal is electrically connected to the first semiconductor element. The sealing resin covers the first semiconductor element. The first control terminal includes a holder and a metal pin supported by the holder and protruding from the sealing resin. The holder is directly bonded to the support. As an example, the holder has a cylindrical part, and the metal pin is inserted into the cylindrical part.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Conventionally, semiconductor devices including power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have been known. Such semiconductor devices are installed in a wide variety of electronic devices, from industrial equipment to home appliances, information terminals, and automotive equipment. Patent Document 1 (Patent Document 1) discloses a conventional semiconductor device (power module). The semiconductor device described in Patent Document 1 includes a semiconductor element, a main substrate, and a substrate. The main substrate has a metal layer. The semiconductor element is conductively joined to the metal layer. The sub-substrate is supported by the main substrate. The semiconductor element is provided with a gate terminal.

[0003] Japanese Patent Application Laid-Open No. 2021-190505

[0004] [Summary] If the attachment of the gate terminal is unstable, it may cause problems in the operation of the semiconductor device.

[0005] An object of the present disclosure is to provide an improved semiconductor device. Another object of the present disclosure is to provide a method for manufacturing such a semiconductor device. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device capable of appropriately fixing a control terminal and a method for manufacturing such a semiconductor device.

[0006] A semiconductor device according to a first aspect of the present disclosure includes a support, a first semiconductor element supported by the support, a first control terminal electrically connected to the first semiconductor element, and a sealing resin covering the first semiconductor element. The first control terminal includes a holder and a metal pin supported by the holder and protruding from the sealing resin. The holder is directly bonded to the support.

[0007] A method for manufacturing a semiconductor device provided by a second aspect of the present disclosure includes the steps of directly joining a holder to a support, mounting a first semiconductor element on the support, forming a sealing resin that covers the first semiconductor element, and supporting a first control terminal on the holder.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a partial perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a partial perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 4 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 5 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 6 is a partial side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 7 is a partial enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 8 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 9 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 10 is a side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 11 is a bottom view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5. FIG. 13 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 14 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 5. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 5 . FIG. 17 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 18 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 19 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 20 is a partially enlarged cross-sectional view taken along line XX-XX in FIG. 19 . FIG. 21 is a configuration diagram showing a vehicle according to the first embodiment of the present disclosure. FIG. 22 is a partially enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 23 is a partially enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 24 is a partially enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 25 is a partially enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 26 is a partially enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 27 is a partially enlarged plan view showing another example of a holder for a semiconductor device according to the first embodiment of the present disclosure. FIG. 28 is a partially enlarged plan view showing yet another example of a holder for a semiconductor device according to the first embodiment of the present disclosure.FIG. 29 is a partial enlarged plan view showing yet another example of a holder for a semiconductor device according to the first embodiment of the present disclosure. FIG. 30 is a partial enlarged plan view showing yet another example of a holder for a semiconductor device according to the first embodiment of the present disclosure. FIG. 31 is a partial enlarged plan view showing yet another example of a holder for a semiconductor device according to the first embodiment of the present disclosure. FIG. 32 is a partial enlarged plan view showing yet another example of a holder for a semiconductor device according to the first embodiment of the present disclosure. FIG. 33 is a partial enlarged cross-sectional view showing a first modified example of a semiconductor device according to the first embodiment of the present disclosure. FIG. 34 is a partial enlarged cross-sectional view showing a second modified example of a semiconductor device according to the first embodiment of the present disclosure. FIG. 35 is a partial enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 36 is a partial enlarged cross-sectional view showing a manufacturing method of a semiconductor device according to the second embodiment of the present disclosure. FIG. 37 is a partial enlarged cross-sectional view showing a first modified example of a semiconductor device according to the second embodiment of the present disclosure. FIG. 38 is a partial enlarged cross-sectional view showing a second modified example of a semiconductor device according to the second embodiment of the present disclosure. FIG. 39 is a partial perspective view showing a semiconductor device according to a third embodiment of the present disclosure. FIG. 40 is a partial plan view showing a semiconductor device according to the third embodiment of the present disclosure. Fig. 41 is a partially enlarged cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure, Fig. 42 is a partially enlarged cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure, and Fig. 43 is a partially enlarged cross-sectional view showing a first modified example of the semiconductor device according to the fourth embodiment of the present disclosure.

[0010] DETAILED DESCRIPTION Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0011] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0012] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." In the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0013] 1 to 21 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a plurality of first semiconductor elements 10A, a plurality of second semiconductor elements 10B, a support 1, a first terminal 41, a second terminal 42, a plurality of third terminals 43, a fourth terminal 44, a plurality of control terminals 45, a first conductive member 5, a second conductive member 6, and a sealing resin 8.

[0014] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a partial perspective view showing the semiconductor device A1. FIG. 3 is a partial perspective view showing the semiconductor device A1. FIG. 4 is a plan view showing the semiconductor device A1. FIG. 5 is a partial plan view showing the semiconductor device A1. FIG. 6 is a partial side view showing the semiconductor device A1. FIG. 7 is a partial enlarged plan view showing the semiconductor device A1. FIG. 8 is a partial plan view showing the semiconductor device A1. FIG. 9 is a partial plan view showing the semiconductor device A1. FIG. 10 is a side view showing the semiconductor device A1. FIG. 11 is a bottom view showing the semiconductor device A1. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5. FIG. 13 is a partial enlarged cross-sectional view showing the semiconductor device A1. FIG. 14 is a partial enlarged cross-sectional view showing the semiconductor device A1. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 5. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 5. FIG. 17 is a partial enlarged plan view showing the semiconductor device A1. FIG. 18 is a partial enlarged plan view showing the semiconductor device A1. Fig. 19 is a partially enlarged plan view showing the semiconductor device A1. Fig. 20 is a partially enlarged cross-sectional view taken along line XX-XX in Fig. 19. Fig. 21 is a configuration diagram showing a vehicle according to the first embodiment of the present disclosure. For ease of understanding, the sealing resin 8 is omitted from Figs. 2, 3, 5 to 9, and 17 to 19.

[0015] In these figures, the thickness direction z corresponds to, for example, the up-and-down direction in Figure 1. The first direction x is a direction perpendicular to the thickness direction z. The second direction y is a direction perpendicular to the thickness direction z and the first direction x.

[0016] First semiconductor element 10A, second semiconductor element 10B: The first semiconductor elements 10A and the second semiconductor elements 10B are electronic components that are the core of the semiconductor device A1. The first semiconductor elements 10A and the second semiconductor elements 10B are made of a semiconductor material primarily composed of, for example, silicon carbide (SiC). This semiconductor material is not limited to silicon carbide (SiC) and may be silicon (Si), gallium nitride (GaN), or diamond (C). Each of the first semiconductor elements 10A and the second semiconductor elements 10B is a power semiconductor chip with switching functionality, such as a metal oxide semiconductor field effect transistor (MOSFET). While this embodiment illustrates a case in which the first semiconductor elements 10A and the second semiconductor elements 10B are MOSFETs, other transistors, such as insulated gate bipolar transistors (IGBTs), may also be used. The first semiconductor elements 10A and the second semiconductor elements 10B may have different configurations or may have the same configuration. In the following description, the first semiconductor elements 10A and the second semiconductor elements 10B are all the same element. Each of the first semiconductor elements 10A and the second semiconductor elements 10B is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0017] 13 and 14 , the first semiconductor element 10A and the second semiconductor element 10B each have an element main surface 101 and an element back surface 102. In each of the first semiconductor elements 10A and the second semiconductor elements 10B, the element main surface 101 and the element back surface 102 are spaced apart in the thickness direction z. The element main surface 101 faces the z1 side in the thickness direction z, and the element back surface 102 faces the z2 side in the thickness direction z.

[0018] The number of first semiconductor elements 10A and the number of second semiconductor elements 10B are changed as appropriate depending on the required performance, such as the current capacity handled by the semiconductor device A1. In this embodiment, as shown in Figures 8 and 9, four first semiconductor elements 10A and four second semiconductor elements 10B are arranged. The number of first semiconductor elements 10A and four second semiconductor elements 10B may be two or three, or five or more. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be equal to or different from each other.

[0019] The semiconductor device A1 is configured, for example, as a half-bridge switching circuit. In this case, a plurality of first semiconductor elements 10A form an upper arm circuit of the semiconductor device A1, and a plurality of second semiconductor elements 10B form a lower arm circuit. In the upper arm circuit, the plurality of first semiconductor elements 10A are connected in parallel with each other, and in the lower arm circuit, the plurality of second semiconductor elements 10B are connected in parallel with each other. The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are connected in series to form a bridge layer.

[0020] As shown in Figures 8, 9, and 16, each of the multiple first semiconductor elements 10A is mounted on a first conductive portion 32A of the main substrate 3, which will be described later. In the example shown in Figures 8 and 9, the multiple first semiconductor elements 10A are lined up, for example, in the second direction y and spaced apart from one another. Each first semiconductor element 10A is conductively bonded to the first conductive portion 32A via a first conductive bonding material 19A. The element back surface 102 faces the first conductive portion 32A.

[0021] As shown in Figures 8, 9, and 15, each of the multiple second semiconductor elements 10B is mounted on a second conductive portion 32B of the main substrate 3 (described later). In the example shown in Figures 8 and 9, the multiple second semiconductor elements 10B are aligned, for example, in the second direction y and spaced apart from one another. Each second semiconductor element 10B is conductively bonded to the second conductive portion 32B via a second conductive bonding material 19B. The element back surface 102 faces the second conductive portion 32B. As can be seen from Figure 9, the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap when viewed in the first direction x, but they do not necessarily have to overlap.

[0022] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B each have a first principal surface electrode 11, a second principal surface electrode 12, a third principal surface electrode 13, and a back surface electrode 15. The configurations of the first principal surface electrode 11, the second principal surface electrode 12, the third principal surface electrode 13, and the back surface electrode 15 described below are common to each of the first semiconductor elements 10A and each of the second semiconductor elements 10B. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are provided on the element main surface 101. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the element back surface 102.

[0023] The first principal surface electrode 11 is, for example, a gate electrode, to which a drive signal (for example, a gate voltage) for driving the first semiconductor element 10A (second semiconductor element 10B) is input. In the first semiconductor element 10A (second semiconductor element 10B), the second principal surface electrode 12 is, for example, a source electrode, through which a source current flows. The third principal surface electrode 13 is, for example, a source sense electrode, through which a source current flows. The back surface electrode 15 is, for example, a drain electrode, through which a drain current flows. The back surface electrode 15 covers the entire area (or substantially the entire area) of the element back surface 102. The back surface electrode 15 is, for example, formed by Ag (silver) plating.

[0024] When a drive signal (gate voltage) is input to the first principal surface electrode 11 (gate electrode), each first semiconductor element 10A (each second semiconductor element 10B) switches between a conductive state and a non-conductive state in response to the drive signal. In the conductive state, current flows from the back surface electrode 15 (drain electrode) to the second principal surface electrode 12 (source electrode), and in the non-conductive state, current does not flow. In other words, each first semiconductor element 10A (each second semiconductor element 10B) performs a switching operation. The semiconductor device A1 converts a DC voltage input between the single fourth terminal 44 and the two first and second terminals 41 and 42 into, for example, an AC voltage, and outputs the AC voltage from the third terminal 43, using the switching functions of the multiple first semiconductor elements 10A and multiple second semiconductor elements 10B.

[0025] Support 1: The support 1 supports the first semiconductor element 10A, the second semiconductor element 10B, and a plurality of control terminals 45. There are no limitations on the specific configuration of the support 1. In this embodiment, the support 1 includes the main substrate 3, a first sub-substrate 48A, and a second sub-substrate 48B.

[0026] Main substrate 3: The main substrate 3 supports a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. The specific configuration of the main substrate 3 is not limited, and may be, for example, a direct bonded copper (DBC) substrate or an active metal brazing (AMB) substrate. The main substrate 3 includes a main insulating layer 31, a first main metal layer 32, and a second main metal layer 33. The first main metal layer 32 includes a first conductive portion 32A and a second conductive portion 32B. The dimension of the main substrate 3 in the thickness direction z is not limited, and may be, for example, 0.4 mm or more and 3.0 mm or less. In the illustrated example, the first main metal layer 32 does not include a plating layer or the like and may be a single layer, or may be a multi-layer structure including a plating layer of Ni or the like.

[0027] The constituent material of the main insulating layer 31 includes, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include SiN (silicon nitride). The constituent material of the main insulating layer 31 is not limited to ceramics and may be an insulating resin sheet or the like. The main insulating layer 31 has, for example, a rectangular shape in a plan view. The dimension of the main insulating layer 31 in the thickness direction z is not limited in any way and is, for example, 0.05 mm to 1.0 mm.

[0028] As shown in FIGS. 8, 9, and 12, the first conductive portion 32A supports a plurality of first semiconductor elements 10A, and the second conductive portion 32B supports a plurality of second semiconductor elements 10B. The first conductive portion 32A and the second conductive portion 32B are formed on the upper surface (the surface facing the z1 side in the thickness direction z) of the main insulating layer 31. The constituent material of the first conductive portion 32A and the second conductive portion 32B includes, for example, Cu (copper). The constituent material may include, for example, Al (aluminum) other than Cu (copper). The first conductive portion 32A and the second conductive portion 32B are spaced apart in the first direction x. The first conductive portion 32A is located on the x1 side of the second conductive portion 32B in the first direction x. The first conductive portion 32A and the second conductive portion 32B each have, for example, a rectangular shape in a plan view. The first conductive portion 32A and the second conductive portion 32B, together with the first conductive member 5 and the second conductive member 6, constitute a path of the main circuit current switched by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B.

[0029] The first conductive portion 32A has a first main surface 301A. The first main surface 301A is a flat surface facing the z1 side in the thickness direction z. A plurality of first semiconductor elements 10A are bonded to the first main surface 301A of the first conductive portion 32A via first conductive bonding materials 19A. The second conductive portion 32B has a second main surface 301B. The second main surface 301B is a flat surface facing the z1 side in the thickness direction z. A plurality of second semiconductor elements 10B are bonded to the second main surface 301B of the second conductive portion 32B via second conductive bonding materials 19B. The constituent materials of the first conductive bonding material 19A and the second conductive bonding material 19B are not particularly limited and may be, for example, solder, a metal paste material containing a metal such as Ag (silver), or a sintered metal containing a metal such as Ag (silver). The dimensions of first conductive portion 32A and second conductive portion 32B in thickness direction z are not limited in any way and may be, for example, 0.1 mm or more and 1.5 mm or less.

[0030] The second main metal layer 33 is formed on the lower surface (surface facing the z2 side in the thickness direction z) of the main insulating layer 31. The constituent material of the second main metal layer 33 is, for example, the same as the constituent material of the first main metal layer 32. The second main metal layer 33 has a back surface 302. The back surface 302 is a flat surface facing the z2 side in the thickness direction z. In the example shown in FIG. 11 , the back surface 302 is exposed from the sealing resin 8, for example. A heat dissipation member (e.g., a heat sink) (not shown) can be attached to the back surface 302. The back surface 302 may not be exposed from the sealing resin 8 and may be covered by the sealing resin 8. The second main metal layer 33 overlaps both the first conductive portion 32A and the second conductive portion 32B in a plan view.

[0031] First terminal 41, second terminal 42, third terminal 43, fourth terminal 44: The specific configurations of the first terminal 41, second terminal 42, the plurality of third terminals 43, and fourth terminal 44 are not limited in any way, and in this embodiment, they are made of a plate-shaped metal plate. This metal plate contains, for example, Cu (copper) or a Cu (copper) alloy. In the examples shown in Figures 1 to 6, 8, 9, and 11, the semiconductor device A1 includes one each of the first terminal 41, second terminal 42, and fourth terminal 44, and two third terminals 43, but the number of each terminal is not limited in any way.

[0032] A DC voltage to be converted into power is input to the first terminal 41, the second terminal 42, and the fourth terminal 44. For example, the fourth terminal 44 is a positive electrode (P terminal), and the first terminal 41 and the second terminal 42 are each a negative electrode (N terminal). An AC voltage converted into power by the first semiconductor element 10A and the second semiconductor element 10B is output from the plurality of third terminals 43. The first terminal 41, the second terminal 42, the plurality of third terminals 43, and the fourth terminal 44 each include a portion covered with the sealing resin 8 and a portion exposed from the sealing resin 8.

[0033] As shown in FIG. 12 , the fourth terminal 44 is conductively bonded to the first conductive portion 32A. The conductive bonding method is not limited, and methods such as ultrasonic bonding, laser bonding, and welding, or methods using solder, metal paste, silver sintered body, etc., may be appropriately adopted. The fourth terminal 44 may be integrally formed with the first conductive portion 32A. As shown in FIGS. 8 and 9 , the fourth terminal 44 is located on the x1 side in the first direction x with respect to the multiple first semiconductor elements 10A and the first conductive portions 32A. The fourth terminal 44 is conductively connected to the first conductive portion 32A and, via the first conductive portion 32A, to the back surface electrode 15 (drain electrode) of each first semiconductor element 10A.

[0034] As shown in FIG. 5 , the first terminal 41 and the second terminal 42 are conductively joined to the second conductive member 6. The method of conductive joining is not limited, and methods such as ultrasonic bonding, laser bonding, welding, or methods using solder, metal paste, silver sintered body, etc. may be appropriately adopted. The first terminal 41 and the second terminal 42 may be integrally formed with the second conductive member 6. As shown in FIGS. 5 , 8 , etc., the first terminal 41 and the second terminal 42 are each located on the x1 side of the first direction x with respect to the multiple first semiconductor elements 10A and the first conductive portions 32A. The first terminal 41 and the second terminal 42 are each conductively connected to the second conductive member 6 and, via the second conductive member 6, to the second principal surface electrodes 12 (source electrodes) of each second semiconductor element 10B.

[0035] As shown in FIGS. 1 to 5 and 11 , the first terminal 41, the second terminal 42, and the fourth terminal 44 each protrude from the sealing resin 8 toward the x1 side in the first direction x in the semiconductor device A1. The first terminal 41, the second terminal 42, and the fourth terminal 44 are spaced apart from one another. The first terminal 41 and the second terminal 42 are located on opposite sides of the fourth terminal 44 in the second direction y. The first terminal 41 is located on the y1 side of the fourth terminal 44 in the second direction y, and the second terminal 42 is located on the y2 side of the fourth terminal 44 in the second direction y. The first terminal 41, the second terminal 42, and the fourth terminal 44 overlap one another when viewed in the second direction y.

[0036] As can be seen from FIGS. 8 , 9 , and 12 , the two third terminals 43 are each conductively bonded to the second conductive portion 32B. The conductive bonding method is not limited to any particular method, and methods such as ultrasonic bonding, laser bonding, and welding, or methods using solder, metal paste, silver sintered body, etc., may be appropriately employed. As shown in FIG. 8 and other figures, the two third terminals 43 are each located on the x2 side of the second semiconductor elements 10B and the second conductive portions 32B in the first direction x. Each third terminal 43 is conductively connected to the second conductive portion 32B and, via the second conductive portion 32B, to the back electrode 15 (drain electrode) of each second semiconductor element 10B. The number of third terminals 43 is not limited to two and may be, for example, one or three or more. For example, when there is one third terminal 43, it is preferably connected to the center portion of the second conductive portion 32B in the second direction y.

[0037] First sub-substrate 48A, second sub-substrate 48B: The first sub-substrate 48A and the second sub-substrate 48B support a plurality of control terminals 45. The first sub-substrate 48A and the second sub-substrate 48B are interposed between the first main surface 301A and the second main surface 301B and the plurality of control terminals 45 in the thickness direction z. The first sub-substrate 48A and the second sub-substrate 48B may have different configurations or may have the same configuration. The first sub-substrate 48A is disposed on the first conductive portion 32A. The second sub-substrate 48B is disposed on the second conductive portion 32B. In this embodiment, the first sub-substrate 48A and the second sub-substrate 48B have the same configuration and are rotated 180 degrees relative to each other when viewed in the thickness direction z.

[0038] The specific configuration of the first sub-substrate 48A and the second sub-substrate 48B is not limited in any way. Specific examples of the first sub-substrate 48A and the second sub-substrate 48B include an IMS (Insulated Metal Substrate) substrate, a glass epoxy resin substrate, a metal substrate, etc. In this embodiment, the first sub-substrate 48A and the second sub-substrate 48B are IMS substrates. As shown in FIG. 20 , the first sub-substrate 48A and the second sub-substrate 48B have a sub-insulation layer 481, a first sub-metal layer 482, and a second sub-metal layer 483 stacked on top of each other.

[0039] The sub-insulating layer 481 is made of, for example, ceramics. The sub-insulating layer 481 has, for example, a rectangular shape in plan view. The thickness of the sub-insulating layer 481 is not particularly limited and is, for example, 0.05 mm to 1.0 mm.

[0040] The first sub-metal layer 482 is formed on the upper surface (surface facing the z1 side in the thickness direction z) of the sub-insulating layer 481. The first sub-metal layer 482 includes, for example, Cu (copper) or a Cu (copper) alloy. The specific configuration of the first sub-metal layer 482 is not limited in any way. The thickness of the first sub-metal layer 482 is not limited in any way and is, for example, 0.035 mm or more and 2.0 mm or less.

[0041] 17 and 18, the first sub-metal layer 482 includes a plurality of regions 482A, 482B, 482C, 482D, 482E, and 482F. The plurality of regions 482A, 482B, 482C, 482D, 482E, and 482F are separated and insulated from one another.

[0042] The region 482A includes a connection portion 4821A and a terminal portion 4822A. In the first sub-substrate 48A, the connection portion 4821A is located on the x2 side in the first direction x, and the terminal portion 4822A is located on the x1 side in the first direction x. In the second sub-substrate 48B, the connection portion 4821A is located on the x1 side in the first direction x, and the terminal portion 4822A is located on the x2 side in the first direction x. The connection portion 4821A has a shape that extends elongatedly in the second direction y. The terminal portion 4822A is circular (or approximately circular) in shape.

[0043] A plurality of wires 71 are bonded to the connection portion 4821A. In this embodiment, the wires 71 are bonded to a surface metal layer 4829 of the connection portion 4821A. The constituent material of the wires 71 is not limited in any way and includes, for example, Al (aluminum) or an Al (aluminum) alloy. The region 482A is electrically connected to the first main surface electrodes 11 (gate electrodes) of the plurality of first semiconductor elements 10A (the plurality of second semiconductor elements 10B) via the plurality of wires 71.

[0044] The region 482B includes a connection portion 4821B and a terminal portion 4822B. In the first sub-substrate 48A, the connection portion 4821B is located on the x2 side in the first direction x, and the terminal portion 4822B is located on the x1 side in the first direction x. In the second sub-substrate 48B, the connection portion 4821B is located on the x1 side in the first direction x, and the terminal portion 4822B is located on the x2 side in the first direction x. In the first sub-substrate 48A, the region 482B is located on the x1 side in the first direction x of the connection portion 4821A. In the second sub-substrate 48B, the region 482B is located on the x2 side in the first direction x of the connection portion 4821A. The connection portion 4821B has a shape that extends elongated in the second direction y. The terminal portion 4822B has a semicircular shape (or an approximately semicircular shape). On the first sub-substrate 48A, the terminal portion 4822B is located on the y2 side of the terminal portion 4822A in the second direction y. On the second sub-substrate 48B, the terminal portion 4822B is located on the y1 side of the terminal portion 4822A in the second direction y.

[0045] A plurality of wires 72 are joined to the connection portion 4821B. In this embodiment, the wires 72 are joined to a surface metal layer 4829 of the connection portion 4821B. The constituent material of the wires 72 is not limited in any way and includes, for example, Al (aluminum) or an Al (aluminum) alloy. The region 482B is electrically connected to the third principal surface electrodes 13 (source sense electrodes) of the plurality of first semiconductor elements 10A (the plurality of second semiconductor elements 10B) via the plurality of wires 72.

[0046] The region 482C includes a connection portion 4821C and a terminal portion 4822C. In the first sub-substrate 48A, the connection portion 4821C is located on the y2 side in the second direction y, and the terminal portion 4822C is located on the y1 side in the second direction y. In the second sub-substrate 48B, the connection portion 4821C is located on the y1 side in the second direction y, and the terminal portion 4822C is located on the y2 side in the second direction y. The connection portion 4821C has a bent shape extending in the second direction y. The terminal portion 4822C has a circular shape (or a substantially circular shape). In the first sub-substrate 48A, the terminal portion 4822C is located on the x1 side in the first direction x of the connection portion 4821A, and on the y2 side in the second direction y of the terminal portion 4822B. On the second sub-substrate 48B, the connecting portion 4821A is located on the x2 side in the first direction x, and the terminal portion 4822C is located on the y1 side in the second direction y of the terminal portion 4822B.

[0047] The region 482D includes a connection portion 4821D and a terminal portion 4822D. In the first sub-substrate 48A, the connection portion 4821D is located on the y2 side in the second direction y, and the terminal portion 4822D is located on the y1 side in the second direction y. The connection portion 4821D is, for example, rectangular, and the terminal portion 4822D is, for example, circular (or approximately circular). In the first sub-substrate 48A, the connection portion 4821D is located on the x1 side in the first direction x of the connection portion 4821C. In the second sub-substrate 48B, the connection portion 4821D is located on the x2 side in the first direction x of the connection portion 4821C. In the first sub-substrate 48A, the terminal portion 4822D is located on the y2 side in the second direction y of the terminal portion 4822C. On the second sub-substrate 48B, the terminal portion 4822D is located on the y1 side in the second direction y of the terminal portion 4822C.

[0048] In the first sub-substrate 48A, the region 482E is located on the y2 side in the second direction y of the connecting portion 4821A, and on the x2 side in the first direction x of the connecting portion 4821C. In the second sub-substrate 48B, the region 482E is located on the y1 side in the second direction y of the connecting portion 4821A, and on the x1 side in the first direction x of the connecting portion 4821C. The region 482E has a shape that extends in the second direction y.

[0049] The multiple regions 482F are arranged alternately in the second direction y, with the terminal portion 4822A, the terminal portion 4822B, the terminal portion 4822C, and the terminal portion 4822D. The shape of the multiple regions 482F is not limited in any way and may be rectangular, circular, or the like, and is rectangular in the illustrated example.

[0050] 13, 14, 20, etc., the second sub-metal layer 483 is formed on the lower surface (the surface on the z2 side in the thickness direction z) of the sub-insulating layer 481. The constituent material of the second sub-metal layer 483 includes, for example, Cu (copper) or a Cu (copper) alloy. The thickness of the second sub-metal layer 483 is not particularly limited and is, for example, 0.035 mm to 3.0 mm.

[0051] The second sub-metal layer 483 of the first sub-substrate 48A is conductively bonded to the first conductive portion 32A. The second sub-metal layer 483 of the second sub-substrate 48B is conductively bonded to the second conductive portion 32B. The method for conductively bonding the second sub-metal layer 483 to the first conductive portion 32A or the second conductive portion 32B is not limited in any way. Examples of conductive bonding methods include a method using a conductive bonding material, a laser bonding method, an ultrasonic bonding method, and a solid-state bonding method. In this embodiment, the second sub-metal layers 483 of the first sub-substrate 48A and the second sub-substrate 48B are conductively bonded to the first conductive portion 32A and the second conductive portion 32B via a conductive bonding material 49, as shown in FIG. 20 . The conductive bonding material 49 is, for example, solder.

[0052] 20 , in the first sub-substrate 48A, a wire 73 is connected between the connection portion 4821D and the first conductive portion 32A. The material of the wire 73 is not limited in any way and includes, for example, Al (aluminum) or an Al (aluminum) alloy. This provides electrical continuity between the region 482D and the first conductive portion 32A.

[0053] 18 , on the second sub-board 48B, a thermistor 17 is connected to the connection portion 4821C and the connection portion 4821D. The thermistor 17 is used as a temperature detection sensor. In addition to the thermistor 17, for example, a temperature-sensitive diode or the like may be provided, or the thermistor 17 or the like may not be provided.

[0054] The wires 71, 72, and 73 are not connected to the first main metal layer 32. In other words, the first main metal layer 32 is separated from the plurality of wires 71, 72, and 73.

[0055] Control terminals 45: The multiple control terminals 45 are terminals for controlling each first semiconductor element 10A and each second semiconductor element 10B. The multiple control terminals 45 include multiple first control terminals 46A, 46B, 46E and multiple second control terminals 47A to 47D. The multiple first control terminals 46A, 46B, 46E are used to control each first semiconductor element 10A, etc. The multiple second control terminals 47A to 47D are used to control each second semiconductor element 10B, etc. The multiple first control terminals 46A, 46B, 46E and the multiple second control terminals 47A to 47D are supported by the support body 1 and directly bonded to the support body 1.

[0056] The multiple first control terminals 46A, 46B, 46E are arranged at intervals in the second direction y. The multiple first control terminals 46A, 46B, 46E are supported by the first conductive portion 32A via the first sub-substrate 48A, as shown in Figures 2, 3, 5, 6, 8, 17, etc. The multiple first control terminals 46A, 46B, 46E are located between the multiple first semiconductor elements 10A and the first terminal 41, the second terminal 42, and the fourth terminal 44 in the first direction x, as shown in Figure 5.

[0057] 17 , the first control terminal 46A is disposed on the terminal portion 4822A. The first control terminal 46A is a terminal (gate terminal) for inputting drive signals for the plurality of first semiconductor elements 10A. A drive signal for driving the plurality of first semiconductor elements 10A is input to the first control terminal 46A (for example, a gate voltage is applied).

[0058] The first control terminal 46B is disposed on the terminal portion 4822B. The first control terminal 46B is a terminal (source sense terminal) for detecting source signals of the multiple first semiconductor elements 10A. The first control terminal 46B detects a voltage (a voltage corresponding to a source current) applied to each second main surface electrode 12 (source electrode) of the multiple first semiconductor elements 10A.

[0059] The first control terminal 46E is disposed on the terminal portion 4822D. The first control terminal 46E is a terminal (drain sense terminal) for detecting drain signals of the multiple first semiconductor elements 10A. The first control terminal 46E detects the voltage (voltage corresponding to the drain current) applied to each back surface electrode 15 (drain electrode) of the multiple first semiconductor elements 10A.

[0060] The second control terminals 47A to 47D are arranged at intervals in the second direction y. The second control terminals 47A to 47D are supported by the second conductive portion 32B via the second sub-substrate 48B, as shown in Figures 2, 3, 5, 6, 8, 18, etc. The second control terminals 47A to 47D are located between the second semiconductor elements 10B and the third terminals 43 in the first direction x, as shown in Figure 5.

[0061] 18 , the second control terminal 47A is disposed on the terminal portion 4822A. The second control terminal 47A is a terminal (gate terminal) for inputting drive signals for the plurality of second semiconductor elements 10B. A drive signal for driving the plurality of second semiconductor elements 10B is input to the second control terminal 47A (for example, a gate voltage is applied).

[0062] The second control terminal 47B is disposed on the terminal portion 4822B. The second control terminal 47B is a terminal (source sense terminal) for detecting source signals of the plurality of second semiconductor elements 10B. The second control terminal 47B detects a voltage (a voltage corresponding to a source current) applied to each second main surface electrode 12 (source electrode) of the plurality of second semiconductor elements 10B.

[0063] The second control terminal 47C is disposed on the terminal portion 4822C. The second control terminal 47D is disposed on the terminal portion 4822D. The second control terminals 47C and 47D are terminals that are electrically connected to the thermistor 17.

[0064] As shown in FIGS. 12 and 17 to 20, each of the plurality of control terminals 45 (the plurality of first control terminals 46A, 46B, 46E and the plurality of second control terminals 47A to 47D) includes a holder 451 and a pin 452.

[0065] The holder 451 is made of a conductive material. As shown in Fig. 20, the holder 451 is directly bonded to the first sub-metal layer 482. There are no particular limitations on the method for directly bonding the holder 451 to the first sub-metal layer 482, and ultrasonic bonding, laser bonding, solid-state diffusion bonding, or the like may be used as appropriate. In this example, ultrasonic bonding is used.

[0066] As shown in FIGS. 19 and 20 , the holder 451 has a tubular portion 4510, a first flange 4511, and a second flange 4512. The tubular portion 4510 has a tubular shape with its axial direction aligned with the thickness direction z, and in the illustrated example, is cylindrical. The first flange 4511 is connected to the end of the tubular portion 4510 on the z2 side in the thickness direction z. The shape of the first flange 4511 is not limited, and in the illustrated example, it is ring-shaped. The second flange 4512 is connected to the end of the tubular portion 4510 on the z1 side in the thickness direction z. The shape of the second flange 4512 is not limited, and in the illustrated example, it is ring-shaped. In this example, the first flange 4511 protrudes from the second flange 4512 when viewed in the thickness direction z. That is, the outer diameter of the first flange 4511 is larger than the outer diameter of the second flange 4512.

[0067] As shown in FIGS. 19 and 20 , the first flange 4511 may have a thick portion 4518 and a thin portion 4519. The thick portion 4518 is connected to the cylindrical portion 4510. The thin portion 4519 includes a portion located on the opposite side of the thick portion 4518 from the cylindrical portion 4510. The thickness of the thick portion 4518 is thinner than the thickness of the thin portion 4519. In the illustrated example, both the thick portion 4518 and the thin portion 4519 are annular. When ultrasonic bonding is used as the bonding method for the holder 451, the first flange 4511 is likely to have a configuration including the thick portion 4518 and the thin portion 4519. The thin portion 4519 mainly contributes to the bonding between the holder 451 and the first sub-metal layer 482.

[0068] 20 , the holder 451 is in contact with the sealing resin 8. The cylindrical portion 4510 and the first flange 4511 are each entirely covered with the sealing resin 8. The surface of the second flange 4512 on the z2 side in the thickness direction z is in contact with the sealing resin 8, and the surface on the z1 side in the thickness direction z is exposed from the sealing resin 8.

[0069] The pin 452 is a rod-shaped member extending in the thickness direction z. The pin 452 is supported, for example, by being press-fitted into a cylindrical portion 4510 of the holder 451. The pin 452 is electrically connected to the first sub-metal layer 482 at least via the holder 451. As shown in FIGS. 1 and 12 , the pin 452 protrudes from the sealing resin 8 toward the z1 side in the thickness direction z. In the illustrated example, the pin 452 includes a thick-diameter portion 4521. The thick-diameter portion 4521 is provided near the end of the pin 452 on the z1 side in the thickness direction z. The thick-diameter portion 4521 has a larger dimension in a direction perpendicular to the thickness direction z than other portions of the holder 451. The thick-diameter portion 4521 may be press-fitted into a through-hole provided in a control board (not shown) external to the semiconductor device A1 when the pin 452 is connected to the control board.

[0070] First conductive member 5, second conductive member 6: The first conductive member 5 and the second conductive member 6, together with the first conductive portion 32A and the second conductive portion 32B, constitute a path for a main circuit current switched by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The first conductive member 5 and the second conductive member 6 are spaced apart from the first main surface 301A and the second main surface 301B on the z1 side in the thickness direction z and overlap the first main surface 301A and the second main surface 301B in a plan view. In this embodiment, the first conductive member 5 and the second conductive member 6 are each made of a metal plate material. The metal includes, for example, Cu (copper) or a Cu (copper) alloy. Specifically, the first conductive member 5 and the second conductive member 6 are made of an appropriately bent metal plate material.

[0071] The first conductive member 5 is connected to the second principal surface electrode 12 (source electrode) of each first semiconductor element 10A and the second conductive portion 32B, thereby electrically connecting the second principal surface electrode 12 of each first semiconductor element 10A and the second conductive portion 32B. The first conductive member 5 forms a path for a main circuit current switched by the multiple first semiconductor elements 10A. As shown in FIGS. 7 and 8 , the first conductive member 5 includes a main portion 51, multiple first bonding portions 52, and multiple second bonding portions 53.

[0072] The main portion 51 is located between the plurality of first semiconductor elements 10A and the second conductive portion 32B in the first direction x and is a strip-shaped portion extending in the second direction y in a plan view. The main portion 51 overlaps both the first conductive portion 32A and the second conductive portion 32B in a plan view and is spaced apart in the thickness direction z from the first main surface 301A and the second main surface 301B on the z1 side in the thickness direction z. As shown in FIG. 16 and other figures, the main portion 51 is located on the z2 side in the thickness direction z with respect to a third path portion 66 and a fourth path portion 67 of the second conductive member 6 described later and is closer to the first main surface 301A and the second main surface 301B than the third path portion 66 and the fourth path portion 67.

[0073] In this embodiment, the main portion 51 is disposed parallel to the first main surface 301A and the second main surface 301B.

[0074] As shown in FIG. 8 and other figures, the main portion 51 extends continuously in the second direction y to correspond to the region in which the multiple first semiconductor elements 10A are arranged. In this embodiment, as shown in FIGS. 7 , 8 , 12 , and other figures, multiple first openings 514 are formed in the main portion 51. Each of the multiple first openings 514 is, for example, a through hole penetrating in the thickness direction z (the plate thickness direction of the main portion 51). The multiple first openings 514 are arranged at intervals in the second direction y. The multiple first openings 514 are provided corresponding to each of the multiple first semiconductor elements 10A. In this embodiment, four first openings 514 are provided in the main portion 51, and these first openings 514 and the multiple (four) first semiconductor elements 10A are positioned at the same position in the second direction y.

[0075] 8, 12, etc., in the present embodiment, each first opening 514 overlaps with a gap between the first conductive portion 32A and the second conductive portion 32B in a plan view. The multiple first openings 514 are formed to facilitate the flow of the resin material between the upper side (the z1 side in the thickness direction z) and the lower side (the z2 side in the thickness direction z) near the main portion 51 (first conductive member 5) when injecting the flowable resin material to form the sealing resin 8.

[0076] As shown in FIG. 8 and other figures, the multiple first bonding portions 52 and the multiple second bonding portions 53 are connected to the main portion 51 and are arranged corresponding to the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B. Specifically, each first bonding portion 52 is located on the x1 side of the main portion 51 in the first direction x. Each second bonding portion 53 is located on the x2 side of the main portion 51 in the first direction x. As shown in FIG. 13 , the multiple first bonding portions 52 are individually bonded to the second principal surface electrodes 12 of the multiple first semiconductor elements 10A via conductive bonding materials 59. The multiple second bonding portions 53 and the second conductive portion 32B are bonded to each other via the conductive bonding material 59. The material of the conductive bonding material 59 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal. In this embodiment, the first bonding portion 52 has two portions spaced apart in the second direction y.

[0077] The second conductive member 6 electrically connects the second main surface electrode 12 (source electrode) of each second semiconductor element 10B to the first terminal 41 and the second terminal 42. The second conductive member 6 is formed integrally with the first terminal 41 and the second terminal 42. The second conductive member 6 constitutes a path for a main circuit current switched by the plurality of second semiconductor elements 10B. As shown in FIGS. 2 and 5 to 7 , the second conductive member 6 includes a plurality of third joint portions 61, a first path portion 64, a second path portion 65, a plurality of third path portions 66, and a fourth path portion 67.

[0078] The multiple third bonding portions 61 are portions that are individually bonded to the multiple second semiconductor elements 10B. Each third bonding portion 61 and the second main surface electrode 12 of each second semiconductor element 10B are bonded via a conductive bonding material 69. The material of the conductive bonding material 69 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal. In this embodiment, the third bonding portion 61 has two flat portions 611 and two first inclined portions 612.

[0079] The two flat portions 611 are aligned in the second direction y. The two flat portions 611 are spaced apart from each other in the second direction y. The shape of the flat portions 611 is not limited in any way, and in the illustrated example, they are rectangular. The two flat portions are joined to the second principal surface electrode 12 on both sides in the second direction y.

[0080] The two first inclined portions 612 are connected to the outside of the two flat portions 611 in the second direction y. That is, the first inclined portion 612 located on the y1 side in the second direction y is connected to the y1 side in the second direction y of the flat portion 611 located on the y1 side in the second direction y. The first inclined portion 612 located on the y2 side in the second direction y is connected to the y2 side in the second direction y of the flat portion 611 located on the y2 side in the second direction y. The first inclined portion 612 is inclined so that the farther it is from the flat portion 611 in the second direction y, the closer it is to the z1 side in the thickness direction z.

[0081] The first path portion 64 is interposed between the plurality of third joint portions 61 and the first terminal 41. In the illustrated example, the first path portion 64 is connected to the first terminal 41 via a first step portion 602. The first path portion 64 overlaps the first conductive portion 32A in a plan view. The first path portion 64 has a shape that extends as a whole in the first direction x.

[0082] The first path portion 64 includes a first band portion 641 and a first extending portion 643. The first band portion 641 is located on the x2 side in the first direction x with respect to the first terminal 41, and is substantially parallel to the first main surface 301A. The first band portion 641 has a shape that extends in the first direction x as a whole.

[0083] The first extending portion 643 extends from the side end of the first strip portion 641 on the y1 side in the second direction y to the z2 side in the thickness direction z. The first extending portion 643 is spaced apart from the first conductive portion 32A. In the example shown, the first extending portion 643 is shaped along the thickness direction z and has an elongated rectangular shape with the first direction x as the longitudinal direction. The first path portion 64 may not have the first extending portion 643.

[0084] The second path portion 65 is interposed between the plurality of third joint portions 61 and the second terminal 42. In the illustrated example, the second path portion 65 is connected to the second terminal 42 via the second step portion 603. The second path portion 65 overlaps the first conductive portion 32A in a plan view. The second path portion 65 has a shape that extends as a whole in the first direction x.

[0085] The second path portion 65 includes a second band portion 651 and a second extending portion 653. The second band portion 651 is located on the x2 side in the first direction x with respect to the second terminal 42 and is substantially parallel to the first main surface 301A. The second band portion 651 has a shape that extends in the first direction x as a whole.

[0086] The second extending portion 653 extends from the side end of the second strip portion 651 on the y2 side in the second direction y to the z2 side in the thickness direction z. The second extending portion 653 is spaced apart from the first conductive portion 32A. In the example shown, the second extending portion 653 is shaped along the thickness direction z and has an elongated rectangular shape with the first direction x as the longitudinal direction. The second path portion 65 may not have the second extending portion 653.

[0087] The multiple third path portions 66 are individually connected to the multiple third joint portions 61. Each third path portion 66 has a shape extending in the first direction x and is arranged at a distance from one another in the second direction y. There is no limitation on the number of multiple third path portions 66, and in the example shown, five third path portions 66 are arranged. Each third path portion 66 is arranged so as to be located between the multiple second semiconductor elements 10B in the second direction y or to be located outward of the multiple second semiconductor elements 10B in the second direction y.

[0088] In the present embodiment, one third joint 61 is disposed between two third path portions 66 adjacent to each other in the second direction y. In one third joint 61, the first inclined portion 612 located on the y1 side in the second direction y is connected to the third path portion 66 located on the y1 side in the second direction y, of the two third path portions 66 adjacent to each other in the second direction y. In one third joint 61, the first inclined portion 612 located on the y2 side in the second direction y is connected to the third path portion 66 located on the y2 side in the second direction y, of the two third path portions 66 adjacent to each other in the second direction y.

[0089] The fourth path portion 67 is connected to the ends of the plurality of third path portions 66 on the x1 side in the first direction x. The fourth path portion 67 has a shape that extends elongatedly in the second direction y. The fourth path portion 67 is connected to the ends of the first band portion 641 of the first path portion 64 and the second band portion 651 of the second path portion 65 on the x2 side in the first direction x. In the example shown, the first path portion 64 is connected to the end of the fourth path portion 67 on the y1 side in the second direction y. The second path portion 65 is connected to the end of the fourth path portion 67 on the y2 side in the second direction y.

[0090] Sealing resin 8: The sealing resin 8 covers the multiple first semiconductor elements 10A, the multiple second semiconductor elements 10B, the main substrate 3 (excluding the back surface 302), the first terminal 41, the second terminal 42, portions of the multiple third terminals 43, and portions of the fourth terminal 44, portions of the multiple control terminals 45, the first sub-substrate 48A and the second sub-substrate 48B, the first conductive member 5, the second conductive member 6, and the multiple wires 71 to 73. The sealing resin 8 is made of, for example, black epoxy resin. The sealing resin 8 is formed, for example, by molding. The size of the sealing resin 8 is not limited in any way, and may be, for example, approximately 35 mm to 60 mm in the first direction x, approximately 35 mm to 50 mm in the second direction y, and approximately 4 mm to 15 mm in the thickness direction z. These dimensions are the sizes of the largest portions along each direction. The sealing resin 8 has a resin main surface 81, a resin back surface 82, and a plurality of resin side surfaces 831 to 834.

[0091] As shown in Figures 10, 12, and 15, the resin main surface 81 and the resin back surface 82 are spaced apart in the thickness direction z. The resin main surface 81 faces the z1 side in the thickness direction z, and the resin back surface 82 faces the z2 side in the thickness direction z. A plurality of control terminals 45 (a plurality of first control terminals 46A, 46B, and 46E and a plurality of second control terminals 47A to 47D) protrude from the resin main surface 81. As shown in Figure 11, the resin back surface 82 has a frame shape that surrounds the back surface 302 (the lower surface of the second main metal layer 33) of the main substrate 3 in a plan view. The back surface 302 of the main substrate 3 is exposed from the resin back surface 82 and is, for example, flush with the resin back surface 82.

[0092] Each of the multiple resin side surfaces 831 to 834 is connected to both the resin main surface 81 and the resin back surface 82 and is sandwiched between them in the thickness direction z. As shown in FIG. 4 and other figures, the resin side surface 831 and the resin side surface 832 are spaced apart in the first direction x. The resin side surface 831 faces the x2 side of the first direction x, and the resin side surface 832 faces the x1 side of the first direction x. Two third terminals 43 protrude from the resin side surface 831, and the first terminal 41, the second terminal 42, and the fourth terminal 44 protrude from the resin side surface 832. As shown in FIG. 4 and other figures, the resin side surface 833 and the resin side surface 834 are spaced apart in the second direction y. The resin side surface 833 faces the y2 side of the second direction y, and the resin side surface 834 faces the y1 side of the second direction y.

[0093] As shown in FIG. 4 , a plurality of recesses 832a are formed in the resin side surface 832. Each recess 832a is a portion recessed in the first direction x in a plan view. The plurality of recesses 832a include those formed between the first terminal 41 and the fourth terminal 44 and those formed between the second terminal 42 and the fourth terminal 44 in a plan view. The plurality of recesses 832a are provided to increase the creepage distance along the resin side surface 832 between the first terminal 41 and the fourth terminal 44 and the creepage distance along the resin side surface 832 between the second terminal 42 and the fourth terminal 44.

[0094] Next, a vehicle B1 equipped with the semiconductor device A1 will be described with reference to Fig. 21. The vehicle B1 is, for example, an electric vehicle (EV).

[0095] As shown in Fig. 21 , vehicle B1 includes an on-board charger 91, a storage battery 92, and a drive system 93. Power is supplied to the on-board charger 91 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 91 via a wired connection. The on-board charger 91 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 91 is stepped up by the converter and then supplied to the storage battery 92. The stepped-up voltage is, for example, 600 V.

[0096] The drive system 93 drives the vehicle B1. The drive system 93 has an inverter 931 and a drive source 932. The semiconductor device A1 constitutes part of the inverter 931. Power stored in the storage battery 92 is supplied to the inverter 931. The power supplied from the storage battery 92 to the inverter 931 is DC power. In addition, unlike the power system shown in FIG. 20 , a step-up DC-DC converter may be further provided between the storage battery 92 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931 including the semiconductor device A1 is electrically connected to the drive source 932.

[0097] The drive source 932 includes an AC motor and a transmission. When AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle B1. This drives the vehicle B1. To drive the vehicle B1, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. The semiconductor device A1 in the inverter 931 is required to output AC power whose frequency has been appropriately changed to correspond to the required rotation speed of the AC motor.

[0098] Next, a method for manufacturing the semiconductor device A1 will be described below with reference to FIGS.

[0099] First, a support body 1 is prepared as shown in Fig. 22. In this embodiment, the support body 1 has a configuration in which a first sub-substrate 48A and a second sub-substrate 48B are joined to a main substrate 3 with a conductive bonding material 49.

[0100] Next, the plurality of control terminals 45 are joined. The first control terminal 46A will be described as an example of joining the plurality of control terminals 45, and a similar method may be used for the other control terminals 45. The holder 451 is placed on the first sub-metal layer 482 of the first sub-substrate 48A.

[0101] 23 , the tool TL is pressed against the first flange 4511 of the holder 451 from the z1 side in the thickness direction z. The tool TL is connected to, for example, an ultrasonic generator or the like and transmits ultrasonic waves. With the tool TL pressed against the holder 451 with a predetermined pressing force, ultrasonic waves are applied from the tool TL to the holder 451. As a result, a portion of the first flange 4511 is thinned by the pressing, becoming a thin-walled portion 4519. The thin-walled portion 4519 is ultrasonically bonded to the first sub-metal layer 482 and directly bonded to the first sub-metal layer 482. In the illustrated example, the tool TL is cylindrical and can accommodate the holder 451.

[0102] In addition to the process of joining the holder 451, before or after this process, the first semiconductor element 10A and the second semiconductor element 10B are mounted, wires 71, 72, and 73 are bonded, and the first terminal 41, the second terminal 42, the third terminal 43, the fourth terminal 44, the first conductive member 5, and the second conductive member 6 are attached as appropriate.

[0103] Next, the sealing resin 8 is formed as shown in Fig. 24. A mold Md is pressed against the holder 451, which is directly joined to the support body 1, from the z1 side in the thickness direction z. As a result, a cavity is formed by the support body 1, the holder 451, and the mold Md. A liquid resin material is filled into this cavity, and the resin material is hardened to form the sealing resin 8.

[0104] 25, the pin 452 is press-fitted into the cylindrical portion 4510 of the holder 451. Through the above steps, the semiconductor device A1 is obtained.

[0105] Next, the operation of the semiconductor device A1 will be described.

[0106] In this embodiment, the holder 451 is directly joined to the support body 1. This reduces the possibility of the holder 451 becoming misaligned when the solder melts during soldering. While there is concern that the mechanical joint strength and electrical conductivity of the holder 451 may be inadequate if the soldering is insufficient, this embodiment reduces such concerns. Therefore, the control terminal 45 can be more appropriately fixed.

[0107] 23 , when the holder 451 is directly joined to the support body 1, the pin 452 has not yet been attached. This makes it possible to avoid interference between the tool TL and the pin 452. In particular, since the pin 452 has a shape that protrudes in the thickness direction z, it is preferable that interference can be avoided.

[0108] The support 1 includes the first control terminals 46A and 46B, and the holders 451 for the multiple control terminals 45 are directly bonded to the first control terminals 46A and 46B. The first control terminals 46A and 46B are easier to pattern into finer conductive portions than the main substrate 3. This allows for improved electrical functionality and miniaturization.

[0109] As shown in Fig. 20 , the sealing resin 8 is in contact with the holder 451. This allows the holder 451 to be held by the sealing resin 8, and the control terminals 45 can be more firmly fixed. Because the holder 451 has the second flange 4512, as shown in Fig. 24 , it is easy to abut the mold Md against the pins 452 when forming the sealing resin 8. This allows the sealing resin 8 to be formed so as to be in contact with the cylindrical portion 4510 of the holder 451, and reduces the risk of the sealing resin 8 accidentally entering the interior of the cylindrical portion 4510.

[0110] 26 to 43 show modified examples and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. The configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0111] 26 shows another example of a manufacturing method for the semiconductor device A1. In this example, laser welding is used to bond the holder 451 to the support 1 (first sub-metal layer 482). In this case, the first flange 4511 may have a configuration in which the thin portion 4519 described above is not formed. This example also allows the control terminal 45 to be more appropriately fixed.

[0112] 27 to 32 show other examples of the holder 451. FIG.

[0113] 27, the first flange 4511 has a plurality of band-shaped portions extending radially from the cylindrical portion 4510. In this example, the first flange 4511 has four band-shaped portions, each forming an angle of approximately 90°.

[0114] 28, the first flange 4511 has two band-shaped portions that extend in opposite directions with the cylindrical portion 4510 in between.

[0115] 29, the first flange 4511 has three band-shaped portions, each of which forms an angle of approximately 60 degrees.

[0116] 30, the first flange 4511 has one band-shaped portion that extends from the cylindrical portion 4510 in the second direction y.

[0117] In the example shown in FIG. 31, two thick portions 4518 are provided on the inside and outside with a thin portion 4519 sandwiched therebetween.

[0118] 32, there are provided a plurality of thinned portions 4519. In the illustrated example, four thinned portions 4519 are arranged on a circle centered on the pin 452. The angles formed by each of the four thinned portions 4519 are approximately 90°.

[0119] As can be seen from the examples shown in FIGS. 27 to 32, the shape of the first flange 4511 is not limited in any way.

[0120] 33 shows a first modification of the semiconductor device A1. In the semiconductor device A11 of this modification, the thickness of the first sub-metal layer 482 is thicker than the thickness of the second sub-metal layer 483. This thickness is advantageous for increasing the bonding strength when the holder 451 is directly bonded to the first sub-metal layer 482 by ultrasonic bonding, laser bonding, or the like.

[0121] Second Modification of First Embodiment: Figure 34 shows a second modification of the semiconductor device A1. In a semiconductor device A12 of this embodiment, the first sub-substrate 48A further includes a spacer 489. The spacer 489 is disposed on the first sub-metal layer 482. The spacer 489 includes a metal such as Cu (copper). The spacer 489 is bonded to the first sub-metal layer 482 by, for example, solder bonding, ultrasonic bonding, or the like. The holder 451 is bonded to the spacer 489 by, for example, laser bonding.

[0122] According to this modified example, even if the thickness of the first sub-metal layer 482 is not sufficient when the holder 451 is joined to the first sub-metal layer 482 by laser joining, the spacer 489 can ensure the thickness of the metal portion required for laser joining.

[0123] 35 shows a semiconductor device according to a second embodiment of the present disclosure. In the semiconductor device A2 of this embodiment, a through hole 811 is formed in the sealing resin 8. The through hole 811 opens to the resin main surface 81 and reaches the support body 1. The holder 451 is housed in the through hole 811 and is spaced apart from the sealing resin 8. The through hole 811 may have, for example, a constant cross-sectional shape, a tapered shape, a stepped shape, or the like.

[0124] 36 shows a method for manufacturing the semiconductor device A2. In this example, after the sealing resin 8 is formed, the holder 451 is directly bonded to the support body 1 (first sub-metal layer 482).

[0125] This embodiment also makes it possible to more appropriately fix the control terminal 45. When forming the sealing resin 8, the temperature of the support body 1 rises. After the sealing resin 8 is formed, the first control terminal 46A is directly bonded to the support body 1, thereby improving the positional accuracy of the first control terminal 46A (control terminal 45) in the semiconductor device A2.

[0126] 36 , the tapered shape of the through hole 811 makes it easy to position the tool TL inside the through hole 811. When performing laser joining, this has the advantage that it is easy to irradiate the first flange 4511 with laser light from an oblique angle.

[0127] 37 shows a first modification of the semiconductor device A2. In the semiconductor device A21 of this modification, the holder 451 has a cylindrical portion 4510 and a first flange 4511, but does not have a second flange 4512.

[0128] In this embodiment, when the sealing resin 8 is formed, the holder 451 is not yet bonded to the support body 1. Therefore, it is not necessary to abut a part of the holder 451 against the mold Md. Therefore, the holder 451 may not have the second flange 4512.

[0129] Second Modification of Second Embodiment: Figure 38 shows a second modification of the semiconductor device A2. In this modification, the semiconductor device A22 has through-holes 811 filled with a filling resin 89. The filling resin 89 is formed, for example, by filling the through-holes 811 with a liquid resin material and then curing the resin material, with the configuration shown in Figure 35 as the target. The material of the filling resin 89 is not limited in any way and may be, for example, epoxy resin, silicone resin, or the like.

[0130] This modification also allows the control terminal 45 to be more appropriately fixed. The provision of the filling resin 89 more reliably achieves insulation of the semiconductor device A22 from the outside. The filling resin 89 more firmly supports the first control terminal 46A (control terminal 45).

[0131] 39 to 42 show a semiconductor device according to a third embodiment of the present disclosure. In the semiconductor device A3 of this embodiment, the support body 1 is formed by the main substrate 3, and does not include the first sub-substrate 48A or the second sub-substrate 48B. The holders 451 of the multiple control terminals 45 are directly bonded to the support body 1.

[0132] 40 , the first conductive part 32A has a first part 320A, a second part 321A, and a third part 322A. A plurality of first semiconductor elements 10A are mounted on the first part 320A. A holder 451 of the first control terminal 46E is directly joined to the first part 320A.

[0133] The second portion 321A is directly joined to the holder 451 of the first control terminal 46A, and is connected to a plurality of wires 71. The third portion 322A is directly joined to the holder 451 of the first control terminal 46B, and is connected to a plurality of wires 72.

[0134] The second conductive portion 32B has a first portion 320B, a second portion 321B, a third portion 322B, a fourth portion 323B, and a fifth portion 324B. A plurality of second semiconductor elements 10B are mounted on the first portion 320B.

[0135] The second portion 321B is directly joined to the holder 451 of the second control terminal 47A, and is connected to a plurality of wires 71. The third portion 322B is directly joined to the holder 451 of the second control terminal 47B, and is connected to a plurality of wires 72.

[0136] The fourth portion 323B is directly joined to the holder 451 of the second control terminal 47C, and is connected to the thermistor 17. The fifth portion 324B is directly joined to the holder 451 of the second control terminal 47D, and is connected to the thermistor 17.

[0137] 41 , the first flange 4511 of the holder 451 is directly bonded to the first conductive portion 32A (first main metal layer 32) of the main substrate 3. There are no particular limitations on the method for directly bonding the first flange 4511, and ultrasonic bonding, laser bonding, solid-state diffusion bonding, or the like may be used as appropriate. When ultrasonic bonding is used, the first flange 4511 may have a thick portion 4518 and a thin portion 4519.

[0138] This embodiment also makes it possible to more appropriately fix the control terminal 45. Since the support 1 is composed of only the main substrate 3, it is possible to reduce the number of parts and the dimension of the semiconductor device A3 in the thickness direction z.

[0139] 42 shows a semiconductor device according to a fourth embodiment of the present disclosure. In the semiconductor device A4 of this embodiment, the sealing resin 8 has a through hole 811. The through hole 811 reaches the first main metal layer 32 of the main substrate 3. A holder 451 is housed in the through hole 811. The holder 451 is spaced apart from the sealing resin 8.

[0140] This embodiment also allows the control terminal 45 to be fixed more appropriately.

[0141] 43 shows a first modification of the semiconductor device A4. In the semiconductor device A41 of this modification, the through holes 811 are filled with a filling resin 89. The filling resin 89 contacts the first main metal layer 32.

[0142] This modification also allows the control terminal 45 to be fixed more appropriately.

[0143] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiments. The specific configurations of the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure can be freely modified in various ways. The present disclosure includes the embodiments described in the following appendices.

[0144] Supplementary Note 1. A semiconductor device (A1) comprising: a support (1); a first semiconductor element (10A) supported by the support (1); a first control terminal (46A) electrically connected to the first semiconductor element (10A); and a sealing resin (8) covering the first semiconductor element (10A), wherein the first control terminal (46A) includes a holder (451) and a metal pin (452) supported by the holder (451) and protruding from the sealing resin (8), and the holder (451) is directly bonded to the support (1). Supplementary Note 2. The semiconductor device (A1) according to Supplementary Note 1, wherein the holder (451) has a cylindrical portion (4510), and the metal pin (452) is inserted into the cylindrical portion (4510). Supplementary Note 3. The semiconductor device (A1) according to Supplementary Note 2, wherein the holder (451) has a first flange (4511) located at one end of the cylindrical portion (4510), and the first flange (4511) is directly joined to the support (1). Supplementary Note 4. The semiconductor device (A1) according to Supplementary Note 3, wherein the first flange (4511) includes a thick portion (4518) connected to the cylindrical portion (4510) and a thin portion (4519) including a portion located on the opposite side of the cylindrical portion (4510) with respect to at least a portion of the thick portion (4518). Supplementary Note 5. The semiconductor device (A1) according to Supplementary Note 3 or 4, wherein the holder (451) has a second flange (4512) located at the other end of the cylindrical portion (4510). Supplementary Note 6. The semiconductor device (A1) according to Supplementary Note 5, wherein the first flange (4511) protrudes from the second flange (4512) when viewed in the direction of the central axis of the cylindrical portion (4510). Supplementary Note 7. The semiconductor device (A1) according to any one of Supplements 1 to 6, wherein the sealing resin (8) is in contact with the holder (451). Supplementary Note 8. The semiconductor device (A12) according to any one of Supplements 1 to 6, wherein the sealing resin (8) has a through hole (811), and the holder (451) is housed in the through hole (811). Supplementary Note 9. The semiconductor device (A1) according to any one of Supplements 1 to 8, wherein the support (1) includes a main substrate (3) and a first sub-substrate (48A) mounted on the main substrate (3), and the holder (451) is directly bonded to the first sub-substrate (48A).Appendix 10. The semiconductor device (A1) according to Appendix 9, wherein the first sub-substrate (48A) includes a sub-insulating layer (481), a first sub-metal layer (482), and a second sub-metal layer (483) located on the opposite side of the sub-insulating layer (481) from the first sub-metal layer (482), and the holder (451) is directly bonded to the first sub-metal layer (482). Appendix 11. The semiconductor device (A11) according to Appendix 10, wherein the first sub-metal layer (482) is thicker than the second sub-metal layer (483). Appendix 12. The semiconductor device (A1) according to Supplementary Note 10 or 11, wherein the main substrate (3) includes a main insulating layer (31), a first main metal layer (32), and a second main metal layer (33) located on the opposite side of the main insulating layer (31) from the first main metal layer (32), and the first sub-substrate (48A) is bonded to the first main metal layer (32).Supplementary Note 13. The semiconductor device (A2) according to any of Supplements 1 to 8, wherein the support (1) includes a main substrate (3), wherein the main substrate (3) includes a main insulating layer (31), a first main metal layer (32), and a second main metal layer (33) located on the opposite side of the main insulating layer (31) from the first main metal layer (32), and the holder (451) is directly bonded to the first main metal layer (32).Supplementary Note 14. A method for manufacturing a semiconductor device (A1), comprising the steps of: directly bonding a holder (451) to a support (1); mounting a first semiconductor element (10A) on the support (1); forming a sealing resin (8) that covers the first semiconductor element (10A); and having the holder (451) support a first control terminal (46A). Appendix 15. A method for manufacturing a semiconductor device (A1) according to Appendix 14, wherein, in the step of directly bonding the holder (451) to the support (1), the holder (451) is directly bonded to the support (1) by ultrasonic bonding. Appendix 16. A method for manufacturing a semiconductor device (A1) according to Appendix 14 or 15, wherein, in the step of forming the sealing resin (8), the sealing resin (8) is brought into contact with the holder (451).

[0145] A1, A11, A12, A2, A21, A22, A3, A4, A41: semiconductor device 1: support 3: main substrate 5: first conductive member 6: second conductive member 8: sealing resin 10A: first semiconductor element 10B: second semiconductor element 11: first principal surface electrode 12: second principal surface electrode 13: third principal surface electrode 15: back surface electrode 17: thermistor 19A: first conductive bonding material 19B: second conductive bonding material 31: main insulating layer 32: first main metal layer 32A: first conductive portion 32B: second conductive portion 33: second main metal layer 41: first terminal 42: second terminal 43: third terminal 44: fourth terminal 45: control terminal 46A, 46B, 46E, 47A: second control terminal 47B, 47C, 47D: Second control terminal 48A: First sub-board 48B: Second sub-board 49: Conductive bonding material 51: Main portion 52: First joint portion 53: Second joint portion 59: Conductive bonding material 61: Third joint portion 64: First path portion 65: Second path portion 66: Third path portion 67: Fourth path portion 69: Conductive bonding material 71, 72, 73: Wire 81: Resin main surface 82: Resin back surface 89: Filled resin 91: On-board charger 92: Storage battery 93: Drive system 101: Element main surface 102: Element back surface 301A: First main surface 301B: Second main surface 302: Back surface 320A: First part 320B: First part 321A: Second part 321B: Second part 322A: Third part 322B: Third part 323B: Fourth part 324B: Fifth part 451: Holder 452: Pin 481: Sub-insulation layer 482: First sub-metal layer 482A, 482B, 482C, 482D, 482E,482F: Region 483: Second sub-metal layer 489: Spacer 514: First opening 602: First step portion 603: Second step portion 611: Flat portion 612: First inclined portion 641: First strip-shaped portion 643: First extending portion 651: Second strip-shaped portion 653: Second extending portion 811: Through hole 831: Resin side surface 832: Resin side surface 832a: Recess 833: Resin side surface 834: Resin side surface 931: Inverter 932: Driving source 4510: Cylindrical portion 4511: First flange 4512: Second flange 4518: Thick portion 4519: Thin portion 4521: Large diameter portion 4821A, 4821B, 4821C, 4821D: Connection portion 4822A, 4822B, 4822C, 4822D: Terminal portion 4829: Surface metal layer B1: Vehicle Md: Mold TL: Tool x: First direction y: Second direction z: Thickness direction

Claims

1. A semiconductor device comprising a support, a first semiconductor element supported by the support, a first control terminal electrically connected to the first semiconductor element, and a sealing resin covering the first semiconductor element, wherein the first control terminal includes a holder and a metal pin supported by the holder and protruding from the sealing resin, and the holder is directly bonded to the support.

2. The semiconductor device according to claim 1, wherein the holder has a cylindrical portion, and the metal pin is inserted into the cylindrical portion.

3. The semiconductor device according to claim 2, wherein the holder has a first flange located at one end of the cylindrical portion, and the first flange is directly bonded to the support.

4. The semiconductor device according to claim 3, wherein the first flange includes a thick portion connected to the cylindrical portion and a thin portion located on the side opposite to the cylindrical portion with respect to at least a part of the thick portion.

5. The semiconductor device according to claim 3 or 4, wherein the holder has a second flange located at the other end of the cylindrical portion.

6. The semiconductor device according to claim 5, wherein the first flange protrudes from the second flange when viewed in the central axis direction of the cylindrical portion.

7. The semiconductor device according to any one of claims 1 to 6, wherein the sealing resin is in contact with the holder.

8. The semiconductor device according to any one of claims 1 to 6, wherein the sealing resin has a through hole, and the holder is accommodated in the through hole.

9. The semiconductor device according to any one of claims 1 to 8, wherein the support includes a main substrate and a first sub-substrate mounted on the main substrate, and the holder is directly bonded to the first sub-substrate.

10. The semiconductor device according to claim 9, wherein the first sub-substrate includes a sub-insulating layer, a first sub-metal layer, and a second sub-metal layer located on the side opposite to the first sub-metal layer with the sub-insulating layer interposed therebetween, and the holder is directly bonded to the first sub-metal layer.

11. The semiconductor device according to claim 10, wherein the first sub-metal layer is thicker than the second sub-metal layer.

12. The semiconductor device according to claim 10 or 11, wherein the main substrate includes a main insulating layer, a first main metal layer, and a second main metal layer located on the side opposite to the first main metal layer with the main insulating layer interposed therebetween, and the first sub-substrate is bonded to the first main metal layer.

13. The support includes a main substrate, the main substrate includes a main insulating layer, a first main metal layer, and a second main metal layer located on the side opposite to the first main metal layer with the main insulating layer therebetween, and the holder is directly bonded to the first main metal layer. The semiconductor device according to any one of claims 1 to 8.

14. A method for manufacturing a semiconductor device, comprising: a step of directly bonding a holder to a support; a step of mounting a first semiconductor element on the support; a step of forming a sealing resin covering the first semiconductor element; and a step of supporting a first control terminal on the holder.

15. In the step of directly bonding the holder to the support, the holder is directly bonded to the support by ultrasonic bonding. The method for manufacturing a semiconductor device according to claim 14.

16. In the step of forming the sealing resin, the sealing resin is brought into contact with the holder. The method for manufacturing a semiconductor device according to claim 14 or 15.

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