Multilayer wiring board, method for manufacturing multilayer wiring board, and multilayer wiring base board

Abstract

The purpose of the present invention is to provide technology that makes it possible to ensure reliability of a multilayer wiring board by avoiding damage to a core substrate even when the core substrate is thick, and technology that makes it possible to reduce the number of manufacturing steps and the manufacturing cost of the multilayer wiring board.　A multilayer wiring board (1) according to the present invention comprises: a core substrate (10) that has a first surface (10a), a second surface (10b) facing the first surface (10a), and a side surface (10c) connecting a peripheral edge portion of the first surface (10a) and a peripheral edge portion of the second surface (10b); a first wiring layer (21) that is formed on the first surface (10a); and a second wiring layer (22) that is formed on the second surface (10b), wherein, in a cross-sectional view taken along a direction perpendicular to the first surface (10a) and the second surface (10b), the side surface (10c) has a shape that bulges further toward the outer side of the core substrate (10) than a straight line connecting the intersection of the first surface (10a) and the side surface (10c) and the intersection of the second surface (10b) and the side surface (10c), the side surface (10c) being covered by an insulating resin portion (24).

Description

Multilayer wiring board, manufacturing method of multilayer wiring board, and multilayer wiring base material board

[0001] The present invention relates to a multilayer wiring board, a method for manufacturing a multilayer wiring board, and a multilayer wiring base material substrate.

[0002] As electronic devices become more sophisticated and smaller, there is an increasing demand for higher density multilayer wiring boards that constitute semiconductor devices. Traditionally, organic materials, such as glass epoxy resin, have been commonly used as materials for multilayer wiring boards. In recent years, advances in glass drilling technology have made it possible to form small through-holes of 100 μm or less at a pitch of 150 μm or less in a 300 μm-thick glass substrate. For this reason, glass has been attracting attention as a material for electronic circuit boards.

[0003] In the manufacturing process of multilayer wiring boards, grinding is performed to separate multilayer wiring boards with glass material as the core substrate. The grinding process generates extremely small cracks on the edge surfaces of the separated glass substrates, and the cracks propagate due to stress generated by the difference in linear expansion coefficient between the glass substrate and the wiring layer, resulting in μ-cracks, which are cracks that grow into the interior of the glass substrate. Since μ-cracks affect the reliability of multilayer wiring boards, countermeasures are being investigated.

[0004] For example, Patent Document 2 aims to provide a low-cost, reliable glass core device and its manufacturing method, which has sufficient mechanical strength by flattening and protecting the surface of the glass core on which TGVs are formed, and discloses the following content regarding the glass core device and its manufacturing method: "In the glass core device, wiring on the first surface 10a of the glass core 10 is electrically connected to wiring on the second surface 10b thereof by wiring embedded in TGVs 11 formed in the glass core 10. When the glass core device is singulated by dicing, an outer protective layer 62 covers the side surface of the glass core, continuing from the second surface 10b of the glass core 10."

[0005] Patent No. 7106875

[0006] In Patent Document 1, a protective resin forming an exterior protective layer is coated with an insulating resin in grooves formed in a glass core, and then dicing is performed to separate the glass core with the insulating resin fixed to the periphery, thereby manufacturing a glass core device with an outer protective layer formed. However, if the thickness of the glass core is increased, it becomes difficult to coat the insulating resin in the grooves of the glass core, making it difficult to sufficiently distribute the insulating resin over the entire sidewall of the glass core device. This point is not sufficiently considered in Patent Document 1.

[0007] Therefore, an object of the present invention is to provide a technology that can prevent damage to the core substrate even when the core substrate is thick, and ensure the reliability of the multilayer wiring board.

[0008] In order to solve the above-mentioned problems, a typical multilayer wiring board of the present invention is a multilayer wiring board having a core substrate having a first surface, a second surface opposite to the first surface, and a side surface connecting the peripheral edge of the first surface and the peripheral edge of the second surface, a first wiring layer which is a wiring layer formed on the first surface, and a second wiring layer which is a wiring layer formed on the second surface, wherein, in a cross-sectional view when cut along a direction perpendicular to the first surface and the second surface, the side surface has a shape that bulges outward from the core substrate more than a straight line connecting the intersection of the first surface and the side surface and the intersection of the second surface and the side surface, and the side surface is covered with an insulating resin portion.

[0009] According to the present invention, even if the core substrate is thick, damage to the core substrate can be avoided and the reliability of the multilayer wiring board can be ensured. Problems, configurations, and effects other than those described above will become clear from the description of the following embodiments.

[0010] FIG. 1 is a cross-sectional view showing a multilayer wiring substrate according to the first embodiment. FIG. 2 is an enlarged cross-sectional view showing the structure of a through electrode in the multilayer substrate wiring according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a glass substrate preparation step in the manufacturing method according to the first embodiment. FIG. 4 is a cross-sectional view illustrating a laser-modified portion formation step in the manufacturing method according to the first embodiment. FIG. 5 is a diagram illustrating a location where the laser-modified portion is formed in the manufacturing method according to the first embodiment. FIG. 6 is a cross-sectional view illustrating a first through-hole formation step by etching in the manufacturing method according to the first embodiment. FIG. 7 is a cross-sectional view illustrating a first wiring layer formation step in the manufacturing method according to the first embodiment. FIG. 8 is a cross-sectional view illustrating a laser-modified portion formation step in the manufacturing method according to the first embodiment. FIG. 9 is a cross-sectional view illustrating a first support bonding step in the manufacturing method according to the first embodiment. FIG. 10 is a cross-sectional view illustrating a second through-hole formation step by etching in the manufacturing method according to the first embodiment. FIG. 11 is a bottom view of a glass substrate when a second separation groove portion is formed. FIG. 12 is an enlarged schematic view of a portion of the second separation groove portion. FIG. 13 is a diagram schematically showing the side surfaces of the first separation trench and the second separation trench. FIG. 14 is a diagram schematically showing an enlarged view of the separation trench. FIG. 15 is a diagram schematically showing an enlarged view of a portion of the bottom view of the separation trench. FIG. 16 is a cross-sectional view illustrating a step of forming a second wiring layer in the manufacturing method according to the first embodiment. FIG. 17 is a cross-sectional view illustrating a step of peeling off a first support in the manufacturing method according to the first embodiment. FIG. 18 is a cross-sectional view illustrating a step of forming a build-up layer in the manufacturing method according to the first embodiment. FIG. 19 is a cross-sectional view illustrating a step of forming connection pads in the manufacturing method according to the first embodiment. FIG. 20 is a cross-sectional view illustrating a singulation step in the manufacturing method according to the first embodiment. FIG. 21 is a diagram showing a flowchart of the manufacturing method according to the first embodiment. FIG. 22 is a cross-sectional view illustrating a step of forming a laser modified portion in the manufacturing method according to the first modification. FIG. 23 is a cross-sectional view illustrating a step of forming a through-hole by etching in the manufacturing method according to the first modification. FIG. 24 is a diagram showing a flowchart of the manufacturing method according to the first modification.Fig. 25 is a diagram explaining the overlap rate of the laser modified portion and the through hole. Fig. 26 is a cross-sectional view showing a multilayer wiring board according to a second embodiment. Fig. 27 is a cross-sectional view showing an enlarged structure of a through electrode in a multilayer wiring board according to a third embodiment. Fig. 28 is a cross-sectional view showing a multilayer wiring board according to the third embodiment. Fig. 29 is a schematic perspective view of a multilayer wiring board. Fig. 30 is a schematic view showing a multilayer wiring base material substrate.

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the following description relates to an example of the present invention, and the present invention is not limited thereto. In addition, in the drawings, identical parts are denoted by the same reference numerals. The position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc., in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0012] In this disclosure, the term "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Furthermore, the terms "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing of a plate-shaped member or a layer contained in the plate-shaped member. The "upper surface" and "lower surface" may also be referred to as the "first surface" and "second surface."

[0013] Furthermore, "side" refers to the surface or thickness of a plate-like member or a layer contained in a plate-like member. Furthermore, a portion of the surface and the side may be collectively referred to as the "end." Furthermore, "upper" refers to the direction vertically upward when the plate-like member or layer is placed horizontally. Furthermore, "upper" and its opposite, "lower," may be referred to as the "positive z-axis direction" and the "negative z-axis direction," and the horizontal direction may be referred to as the "x-axis direction" and the "y-axis direction."

[0014] First Embodiment (Structure of Multilayer Wiring Board) A multilayer wiring board according to a first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view showing the multilayer wiring board according to the first embodiment. FIG. 2 is a cross-sectional view showing an enlarged structure of a through electrode in the multilayer wiring board according to the first embodiment. As shown in FIGS. 1 and 2, the multilayer wiring board 1 has a core substrate 10, which is a substrate made of glass. The core substrate 10 has a first wiring layer 21 formed on its upper surface in the positive z-axis direction (hereinafter also referred to as the "first surface 10a") and a second wiring layer 22 formed on its lower surface in the negative z-axis direction (hereinafter also referred to as the "second surface 10b").

[0015] The core substrate 10 has a first surface 10a, a second surface 10b opposite the first surface 10a, and a side surface 10c connecting the peripheral edge of the first surface 10a to the peripheral edge of the second surface 10b. Figures 1 and 2 show a cross-sectional view taken along a direction perpendicular to the first surface 10a and the second surface 10b. The side surface 10c bulges outward from the core substrate (in the positive or negative y-axis direction) relative to a line connecting the intersection of the first surface 10a and the side surface 10c with the intersection of the second surface 10b and the side surface 10c. The side surface 10c is covered by an insulating resin portion 24. In Figure 1, the side surface 10c is located at the end of the core substrate 10 in the y-axis direction and is the area surrounded by a dotted line. If the position where the side surface 10c bulges most between the first surface 10a and the second surface 10b is defined as the intermediate portion Pd, the side surface 10c of the core substrate 10 bulges from the core substrate 10 toward the insulating resin portion 24 at the intermediate portion Pd (in other words, a boundary line that is convex in the positive y-axis direction and a cross section that is convex in the negative y-axis direction are shown). Note that in this disclosure, the intermediate portion Pd is described as being located at half the thickness T3 of the core substrate 10, but the present disclosure is not limited to this case. The intermediate portion Pd may be located anywhere between the first surface 10a and the second surface 10b of the core substrate 10.

[0016] The core substrate 10 has through holes 11 formed therein, penetrating from the first surface 10a to the second surface 10b, i.e., penetrating both the front and back surfaces. The opening width of the through holes 11 on the first surface 10a decreases toward the middle portion Pd, and the opening width of the through holes 11 on the second surface 10b decreases toward the middle portion Pd. Specifically, FIG. 1 shows three through holes 11. As shown in FIG. 2, the through holes 11 are symmetrical about the middle portion Pd, resembling two truncated cones. If the opening widths of the through holes 11 on the first surface 10a and the second surface 10b are both D2, the opening width decreases toward the middle portion Pd, reaching D1 near the middle portion Pd. Through electrodes 12 are disposed on the through holes 11. The through electrode 12 includes a seed metal layer (hereinafter also simply referred to as "seed layer") formed on the inner wall surface of the through hole 11, and provides electrical continuity between the first surface 10a and the second surface 10b of the core substrate 10 through the through hole 11. As shown in FIG. 2, a capacitor electrode 13 is disposed above the through electrode 12 in the first wiring layer 21. It is also possible to incorporate circuit elements other than capacitors, such as inductors, in the first wiring layer 21. In reality, the through hole 11 may have a shape that resembles a combination of quadratic curves rather than a truncated cone. The figures show an idealized shape for ease of understanding. The same is true for the side surface 10c (separation groove 17) described above.

[0017] Next, the configuration of the first wiring layer 21, which is a wiring layer formed on the first surface 10a of the core substrate 10, will be described. The through electrode connection portion 41 (hereinafter also referred to as the "first conductive portion") is an electrode disposed within the first wiring layer 21 and connected to the through electrode 12. Note that the through electrode connection portion 41 and the through electrode 12 have a common configuration; the portion disposed on the first surface 10a is referred to as the through electrode connection portion 41, and the portion disposed within the through hole 11 is referred to as the through electrode 12. A conductive electrode 31 is provided on the through electrode connection portion 41. The capacitor electrode 13, the dielectric layer 14, and the through electrode connection portion 41 form an MIM (Metal Insulator Metal) structure. The wiring 16 is disposed within the first wiring layer 21 and connects to the through electrode 12, the conductive electrode 31, and the like. The through electrode connection portion 41, the conductive electrode 31, the capacitor electrode 13, the dielectric layer 14, and the wiring 16 are all protected by an insulating resin layer 25. Furthermore, when the multilayer wiring board 1 is used as a relay board for connecting multiple semiconductor elements, i.e., an interposer board, the semiconductor element bonding solder 52 is a bump used when mounting or connecting other semiconductor elements. The solder resist 55 is a film made of an insulating material for protecting the multilayer wiring board 1. Here, two conductive electrodes 31 are provided overlapping each other within the first wiring layer 21. This indicates that the first wiring layer 21 is formed by overlapping two wiring layers.

[0018] The configuration of the second wiring layer 22, which is a wiring layer formed on the second surface 10b of the core substrate 10, will be described. The through electrode connection portion 42 (hereinafter also referred to as the "second conductive portion") is an electrode disposed within the second wiring layer 22 and connected to the through electrode 12, and is formed to match the shape of the opening end of the through electrode 12. The through electrode connection portion 42 and the through electrode 12 also have a common configuration, with the portion formed on the second surface 10b being referred to as the through electrode connection portion 42 and the portion disposed within the through hole 11 being referred to as the through electrode 12. A conductive electrode 32 is connected to the through electrode connection portion 42. The combination of a predetermined through electrode connection portion between the through electrode connection portion 42 disposed on the second wiring layer 22 and the through electrode connection portion 41 disposed on the first wiring layer 21 is electrically connected via the through electrode 12. The board bonding solder 54 is a bump used for connecting to a printed wiring board. The solder resist 55 is a film made of an insulating material for protecting the multilayer wiring substrate 1. Here, the conductive electrodes 32 form conductive paths in the second wiring layer 22 by overlapping or via other wiring layers, which indicates that the second wiring layer 22 is formed by overlapping two wiring layers.

[0019] The first wiring layer 21 and the second wiring layer 22 include an insulating resin layer 25, and the insulating resin portion 24 covering the side surface 10c of the core substrate 10 is made of the same type of insulating resin material as that constituting the insulating resin layer 25. The side surface 10c of the core substrate 10 corresponds to the separation groove 17, which is the separation location when the multilayer wiring substrate is separated from the glass substrate 60, as described below. The insulating resin portion 24 may be the insulating resin material disposed in the separation groove 17, or may be part of the insulating resin layer 25 disposed in the separation groove 17. Also, as shown in FIG. 2 , the through electrode 12 is made up of a first through electrode 12a and a second through electrode 12b. At the center of the through hole 11, the seed layer of the first through electrode 12a and the seed layer of the second through electrode 12b are in contact with each other to form a layer structure.

[0020] (Dimensions and composition of multilayer wiring board) The relationship between the opening width D1 at the intermediate portion Pd of the through electrode 12 and the opening width D2 on the first surface 10a side or the second surface 10b side (intermediate portion opening width D1 / first surface side or second surface side opening width D2) is in the range of 0.35 to 0.65. The relationship between the intermediate portion opening width D1 and the opening width D2 on the first surface 10a side or the second surface 10b side can be set as appropriate as long as it is within the above range.

[0021] Furthermore, the thickness T3 of the core substrate 10 is in the range of 150 μm or more and 2000 μm or less, and can be set in accordance with the characteristic values ​​of the capacitor electrodes 13, inductors, resistors, etc. formed in the first wiring layer 21. More preferably, the thickness T3 of the core substrate 10 is in the range of 300 μm or more and 1000 μm or less.

[0022] The insulating resin layer 25 has a relative dielectric constant in the range of 3.1 to 3.5, and a dielectric loss tangent in the range of 0.002 to 0.012. The insulating resin layer 25 is made of a thermosetting resin. An insulating resin material having such a relative dielectric constant and dielectric loss tangent is used for the insulating resin layer 25. The thermosetting resin is an epoxy resin, a polyimide resin, a polyamide resin, or a composite material thereof, and contains at least SiO ２ The filler material containing SiO is used in an amount of 65% to 80%. ２ If the filling rate of the filler material is 65% or less, the relative permittivity and dielectric loss tangent will be outside the above ranges, which will cause a deterioration in transmission characteristics. ２ The filling rate of the filler material is 72% or more. ２ A material highly filled with the filler material has a low coefficient of linear expansion of the insulating resin, which is close to the coefficient of linear expansion of the glass material. Therefore, by using such a material, it is possible to reduce the stress that may occur when a wiring layer is formed on the core substrate 10. In this way, the values ​​of the relative permittivity and dielectric loss tangent can be kept within the above ranges, and it is possible to avoid affecting the transmission characteristics.

[0023] The insulating resin layer 25 included in the first wiring layer 21 and the second wiring layer 22 and the insulating resin portion 24 formed on the side of the core substrate 10 are exposed on the side of the multilayer wiring board 1. The thickness wi of the insulating resin on the side of the multilayer wiring board 1 (in other words, the thickness of the insulating resin portion 24 on the side 10c of the core substrate 10) is at least 50 μm when measured in the xy plane direction (the direction in which the multilayer wiring board 1 extends). Assuming a perpendicular line extending from the first surface 10a to the second surface 10b, the angle θ1 between the line and a line parallel to the side 10c of the core substrate 10 is 21° to 35°. The side 10c has a shape that is nearly line-symmetrical with respect to the line indicating the intermediate portion Pd, and an inclined surface is formed with θ1 extending in both the positive z-axis direction and the negative z-axis direction from the intermediate portion Pd. In other words, the shape of the side surface 10c of the core substrate 10 can be said to be a so-called X-shape.

[0024] An insulating resin layer 25 and an insulating resin portion 24 are disposed on the side surfaces of the multilayer wiring board 1, and as a result, the side surfaces of the multilayer wiring board 1 are protected by the insulating resin material. This makes it possible to disperse stress generated in the first wiring layer 21 or the second wiring layer 22 formed on the top and bottom surfaces of the core substrate 10 to the other wiring layer through the insulating resin portion 24 on the side surface c of the core substrate 10. Furthermore, the occurrence of μ-cracks at the ends of the core substrate 10 and chipping of the insulating resin material can be suppressed, thereby improving the reliability of the multilayer wiring board 1.

[0025] The capacitor formed in the first wiring layer 21 of the multilayer wiring substrate 1 has an MIM structure. From the viewpoints of insulation and dielectric constant, the dielectric layer 14 forming the capacitor can be made of at least one of alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate. Furthermore, the material used for the upper and lower electrodes of the MIM structure can be at least one of Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, and Cu. For example, Cu is a desirable material.

[0026] The core substrate 10 used in the multilayer wiring board 1 is made of a transparent glass material that is optically transparent. The glass components, the compounding ratio of each component contained in the glass, and the method for manufacturing the glass are not particularly limited. Examples of glass include alkali-free glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, and photosensitive glass, but any glass material containing silicate as a main component may be used. Furthermore, other so-called glass materials may also be used. However, it is desirable to use alkali-free glass in the multilayer wiring board according to this embodiment.

[0027] The core substrate 10 may be made of glass manufactured by a method such as the float method, downdraw method, fusion method, updraw method, or rollout method, but any glass material manufactured by any method may be used. The linear expansion coefficient of the glass is preferably in the range of -1 ppm / K to 15.0 ppm / K. This is because selecting a glass material is difficult when the coefficient is -1 ppm / K or less. On the other hand, when the coefficient is 15.0 ppm / K or more, the difference in thermal expansion coefficient with other layers becomes large, resulting in reduced reliability when used in a multilayer wiring board. Furthermore, when a silicon chip is mounted on the multilayer wiring board 1 of this embodiment, the connection reliability with the silicon chip is reduced. The linear expansion coefficient of the glass is more preferably in the range of 0.5 ppm / K to 8.0 ppm / K, and even more preferably in the range of 1.0 ppm / K to 4.0 ppm / K.

[0028] 3 to 15, a method for manufacturing a multilayer wiring substrate 1 according to a first embodiment will be described. Note that, for ease of understanding, the following figures illustrate only a portion of a glass substrate (described later) that includes one multilayer wiring substrate 1. A plurality of similar portions are arranged in the xy plane of the glass substrate.

[0029] (Preparation of Glass Substrate) First, a glass substrate preparation step will be described with reference to FIG. 3. FIG. 3 is a cross-sectional view illustrating the glass substrate preparation step in the manufacturing method according to the first embodiment. As shown in FIG. 1, a base substrate (hereinafter also referred to as a "glass substrate") 60 having a first surface 60a and a second surface 60b opposite to the first surface is prepared. The glass substrate 60 has a thickness T1. Note that, although the present disclosure will be described using the glass substrate 60, the present disclosure is not limited to the case of a glass substrate. The present disclosure can also be applied to cases where a material other than glass is used.

[0030] 4 and 5, the process of forming the laser modified portion on the first surface 60a (first process) will be described. The first process is a process of irradiating a laser from the first surface 60a side of the glass substrate 60 to form first modified portions at first through hole positions, which are positions where first through hole portions penetrating the glass substrate 60 from the first surface 60a to the second surface 60b are formed, and at first singulation line positions, which are positions where first separation groove portions extending from the first surface 60a to the intermediate portion Pd of the glass substrate 60 are formed, among the through holes penetrating the glass substrate 60 from the first surface 60a to the second surface 60b.

[0031] FIG. 4 is a cross-sectional view illustrating the step of forming a laser-modified portion in the manufacturing method according to the first embodiment. In FIG. 4, the dashed line indicates the laser-modified portion (first modified portion) 65a. As shown in FIG. 4, a laser is irradiated from the first surface 60a side of the glass substrate 60 to form the laser-modified portion 65a. The laser-modified portion 65a is formed at a position (first through-hole position) corresponding to the through-hole 11 in the core substrate 10. The laser-modified portion 65a extends, for example, in the vertical direction (z-axis direction) relative to the glass substrate 60, and is formed to a position reaching the vicinity of the intermediate portion Pd of the glass substrate 60. The intermediate portion Pd indicates the same position as the intermediate portion of the core substrate 10. Since the laser-modified portion 65a is used to form a through-hole that reaches the intermediate portion Pd, the depth to which the laser-modified portion 65a reaches the glass substrate 60 is adjusted depending on the through-hole formation process.

[0032] FIG. 5 is a diagram illustrating the location of the laser-modified portion 65a in the manufacturing method according to the first embodiment. FIG. 5(a) is a plan view of the glass substrate 60 viewed from the positive z-axis direction, i.e., the first surface 60a side, and FIG. 5(b) is an example showing an enlarged portion of the glass substrate 60. Here, the dashed-dotted lines indicate the singulation lines 64a. The singulation lines 64a indicate the positions (first singulation line positions) of the separation grooves 17 that separate the multilayer wiring substrate 1 from the glass substrate 60, where the first separation groove portions extending from the first surface 60a to the vicinity of the intermediate portion Pd of the glass substrate 60 are formed. The laser-modified portions 65a are formed along the singulation lines 64a in addition to the first through-hole positions. The laser-modified portions 65a formed at the first through-hole positions are indicated by black circles. By separating the glass substrate 60 along the singulation lines 64a, multiple multilayer wiring substrates 1 are obtained.

[0033] 5(c) is another example, showing an enlarged view of a portion of the glass substrate 60. As shown here, when forming the laser-modified portion 65a, it is also possible to shift the laser irradiation position to form multiple laser-modified portions to form the singulation lines 64a. FIG. 5(c) shows a case where two singulation lines 64a are formed in parallel.

[0034] (Formation of First Through Hole Portion by Etching) Next, with reference to FIG. 6 , the step of forming the first through hole portion by etching (second step) will be described. The second step is a step of removing the first modified portion 65a from the first surface 60a side by etching to form the first through hole portion and the first separation groove portion. FIG. 6 is a cross-sectional view illustrating the step of forming the first through hole portion by etching in the manufacturing method according to the first embodiment. FIG. 6 shows the shape of the glass substrate 60 after hydrofluoric acid etching. The hydrofluoric acid etching simultaneously forms the first through hole portion 11a and the first separation groove portion 17a described below. As shown here, the laser modified portion 65a is selectively removed by etching from the first surface 60a side of the glass substrate 60, thereby forming the first through hole portion 11a. Furthermore, the first surface 60a of the glass substrate 60 is etched to form a surface corresponding to the first surface 10a of the core substrate 10. Wet etching using a hydrogen fluoride solution is suitable for the etching. The etching amount by the hydrogen fluoride solution is set appropriately depending on the thickness of the glass multilayer wiring substrate. For example, when the thickness T1 of the glass substrate 60 is 1000 μm, the etching amount is preferably in the range of 125 μm to 437 μm.

[0035] (Formation of First Wiring Layer) Next, with reference to FIG. 7 , the steps of forming the first wiring layer 21 (third and fourth steps) will be described. The third step is a step of arranging a conductive member from the first surface side and forming a first through electrode and a first conductive portion. The fourth step is a step of depositing an insulating resin material on the first surface side to form the first wiring layer. FIG. 7 is a cross-sectional view illustrating the step of forming the first wiring layer in the manufacturing method according to the first embodiment. As shown in FIG. 7 , by arranging a conductive member in the first surface 10 a and the first through hole portion 11 a on the glass substrate 60, a first through electrode 12 a is formed along the first through hole portion 11 a, and a through electrode connection portion (first conductive portion) 41 is formed on the first surface 10 a. In addition, by arranging the conductive member, wiring 16 is also formed on the first surface 10 a. Note that a dielectric layer 14 and a capacitor electrode 13 are also formed on the first through electrode 12 a. The first wiring layer 21 includes a through-electrode connection 41 , a wiring 16 , a dielectric layer 14 and a capacitor electrode 13 .

[0036] Specifically, first, a seed layer is formed on the glass substrate 60 and the inner wall of the first through-hole portion 11a. The seed layer is a conductive metal film and is formed to a desired thickness. Examples of materials for the conductive metal film include Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, and Cu. ３ N ４ can be set appropriately from

[0037] The through electrode connection portion 41 (electrode) and the wiring 16 are formed by, for example, a semi-additive (SAP) process. In the semi-additive process, a photoresist is used to form a desired pattern. Generally, a dry film resist is used, but a liquid resist may also be used. After the resist is exposed and developed to form a desired pattern, a plating film having a thickness of 2 μm or more and 20 μm or less is formed by electroplating. The unnecessary resist pattern is peeled off, and the seed layer is etched to form the wiring 16 located between the through electrode connection portion 41 located above or around the first through-hole portion 11a and the first through-hole portion 11a.

[0038] The dielectric layer 14 on the through-electrode connection portion 41 is formed using at least one of alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate, from the viewpoints of insulation and dielectric constant. The thickness of the dielectric layer 14 is preferably in the range of 10 nm to 5 μm. If the thickness of the dielectric layer 14 is 10 nm or less, the insulation properties cannot be maintained and the function as a capacitor cannot be exhibited. If the thickness of the dielectric layer 14 is 5 μm or more, not only is the film formation time too long, which is unsuitable for mass production, but the process of removing unnecessary portions also takes additional time. The thickness of the dielectric layer 14 is more preferably in the range of 50 nm to 1 μm.

[0039] The capacitor electrode 13 is formed by dividing it into a lower electrode layer and an upper electrode layer. From the viewpoints of adhesion and electrical conductivity, the lower electrode layer is formed using at least one of Cu, Ni, Al, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, and Cu as its material. For example, Ti is excellent in terms of adhesion, electrical conductivity, ease of manufacturing, and cost.

[0040] A seed metal layer is formed on the upper electrode of the capacitor electrode 13, and then an electroplated layer is formed. The seed metal layer can be made of at least one of Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, and NiFe. Cu is preferred for ease of subsequent etching removal. The thickness of the seed metal layer is preferably in the range of 10 nm to 5 μm. If the seed metal layer is less than 100 nm, poor electrical conductivity may occur in the subsequent electroplating process. If the seed metal layer is more than 5 μm thick, etching removal will take a long time. The thickness of the seed metal layer is more preferably in the range of 100 nm to 500 nm.

[0041] Thereafter, an electrolytic plating layer is formed as the upper electrode of the capacitor electrode 13. Electrolytic copper plating is simple, inexpensive, and has good electrical conductivity. In addition to electrolytic copper plating, electrolytic nickel plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. may also be used. After the upper electrode is formed, the seed metal layer is removed. Methods such as wet etching and dry etching can be selected as appropriate depending on the application.

[0042] Finally, the insulating resin layer 25 is formed. The insulating resin layer 25 is made of a thermosetting resin, and the material thereof contains at least one of epoxy resin, polyimide resin, and polyamide resin, and SiO ２It is desirable that the insulating resin layer 25 contains a filler material and is in a liquid or film form. In the case of a liquid resin, the insulating layer can be formed by a spin coating method, and in the case of a film resin, the insulating layer can be formed by heating and pressurizing under vacuum using a vacuum laminator. The material of the insulating resin layer 25 can be appropriately selected as needed. However, when a photosensitive insulating resin material is used, SiO ２ Since it is difficult to fill the filler material, the material is limited to non-photosensitive thermosetting resin.

[0043] (Formation of laser modified portion on second surface) Next, referring to FIG. 8, the laser modified portion forming step (fifth step) will be described. In the fifth step, a laser is irradiated from the second surface 60b side of the glass substrate 60 to form a second modified portion at a second through hole position, which is a position where a second through hole portion penetrating from the second surface 60b to the intermediate portion Pd of the glass substrate 60 is formed among the through holes penetrating the glass substrate 60 from the first surface 60a toward the second surface 60b, and at a second singulation line position, which is a position where a second separation groove portion extending from the second surface 60b to the intermediate portion Pd of the glass substrate 60 is formed among the separation grooves 17 that separate the multilayer wiring substrate 1 from the glass substrate 60. FIG. 8 is a cross-sectional view illustrating the laser modified portion forming step in the manufacturing method according to the first embodiment. In FIG. 8, the dashed line indicates the laser modified portion (second modified portion) 65b. 8 , a laser is irradiated onto the glass substrate 60 from the second surface 60b side to form a laser-modified portion 65b. The laser-modified portion 65b is formed at a position (second through-hole position) corresponding to the through-hole 11 in the core substrate 10. The laser-modified portion 65b extends, for example, in the vertical direction (z-axis direction) relative to the glass substrate 60, and is formed up to a position reaching the vicinity of the intermediate portion Pd of the glass substrate 60.

[0044] The laser modified portion 65b is also formed at a position (second singulation line position) where a second separation groove portion extending from the second surface 60b to the vicinity of the intermediate portion Pd of the glass substrate 60 is formed, among the separation grooves that separate the multilayer wiring substrate 1 from the glass substrate 60. The second through hole position and the second singulation line position are located at positions corresponding to the first through hole position and the second singulation line position shown in Figures 5(a) and 5(b), respectively, and are positions on the second surface 60b symmetrical to the glass substrate 60. Note that the laser modified portion 65b can be formed using the same laser as that used to form the laser modified portion 65a.

[0045] (Bonding of First Support) Next, the bonding step of the first support will be described with reference to FIG. 9 . FIG. 9 is a cross-sectional view illustrating the bonding step of the first support in the manufacturing method according to the first embodiment. As shown in FIG. 9 , a first adhesive layer 71 is formed on the first wiring layer 21 of the glass substrate 60, and the first support 70 is bonded to the first adhesive layer 71. Note that the bonding step of the first support 70 is performed to fix the glass substrate 60 with the first support 70 to suppress the occurrence of warpage and perform the manufacturing process when the glass substrate 60 has a large amount of warpage and the manufacturing process described below cannot be performed properly. Therefore, this step is not necessary if the manufacturing process described below can be performed using only the glass substrate 60, and whether this step is necessary can be appropriately selected depending on the amount of warpage of the glass substrate 60. Note that in the present disclosure, a case will be described in which the bonding step of the first support is not performed because the glass substrate 60 has a sufficient thickness and the amount of warpage is kept within a predetermined range.

[0046] If a first support bonding step is performed, the first adhesive layer 71 can be appropriately selected from a resin that absorbs light such as UV light and becomes peelable by generating heat, sublimating, or changing properties, a resin that becomes peelable by foaming due to heat, or a functional group that temporarily fixes the glass substrate 60 and the first support 70. The first support 70 is preferably made of the same material as the glass substrate 60. If the glass substrate 60 is made of alkali-free glass, the first support 70 is also preferably made of alkali-free glass. The thickness of the first support can be appropriately set depending on the thickness of the glass substrate 60. However, a thickness that allows transport is desirable, for example, in the range of 300 μm to 1,500 μm.

[0047] (Formation of Second Through Hole Portion by Etching) Next, with reference to FIGS. 10 to 15 , the process of forming the second through hole portion by etching (sixth process) will be described. In the sixth process, the second modified portion 65b is removed from the second surface 60b side by etching to form the second through hole portion and the second separation groove portion. FIG. 10 is a cross-sectional view illustrating the process of forming the second through hole portion by etching in the manufacturing method according to the first embodiment. FIG. 10 shows the shape of the glass substrate 60 after hydrofluoric acid etching. The second through hole portion 11b and the second separation groove portion 17b are simultaneously formed by hydrofluoric acid etching. In the second through hole portion 11b, the through electrode 12 formed in the first through hole portion 11a is exposed in the negative z-axis direction, and in the second separation groove portion 17b, the insulating resin layer 25 is exposed in the negative z-axis direction. In addition, the second through hole portion 11b and the second separation groove portion 17b extend to a position reaching the intermediate portion Pd. As shown here, the laser-modified portion 65b is selectively removed from the second surface 60b of the glass substrate 60 by etching. This forms the second through-hole portion 11b. The second surface 60b of the glass substrate 60 is also etched to form a surface corresponding to the second surface 10b of the core substrate 10. Wet etching using a hydrogen fluoride solution is suitable for this etching method. The amount of etching using the hydrogen fluoride solution is appropriately determined depending on the thickness of the glass multilayer wiring substrate. For example, when the thickness T2 of the glass substrate 60 is 1000 μm, the amount of etching is preferably in the range of 125 μm to 437 μm. While the structure shown here exposes the insulating resin layer 25 at the middle of the second separation groove 17b, this structure is not limited thereto. If the seed layer of the first wiring layer 21 remains in the first separation groove 17a, the seed layer of the first wiring layer 21 will be exposed from the second separation groove 17b.

[0048] The glass substrate 60 is also etched in association with the etching of the laser modified portion 65. The thickness T3 of the glass substrate 60 after etching is preferably in the range of 150 μm to 2000 μm.

[0049] In conventional methods for manufacturing multilayer wiring boards, after forming separation grooves on a singulation line, it is necessary to attach the core substrate portions to a support to prevent separation of the individual core substrate portions, which results in an increase in the number of manufacturing steps and an increase in the manufacturing costs of the support and the like. In the first embodiment, even when the second separation groove 17 b is formed, the insulating resin layer 25 remains embedded in the first separation groove portion 17 a. Because the insulating resin layer 25 serves to bond the side walls of the core substrate portions together, separation of the core substrate portions can be prevented, eliminating the need to attach the core substrate portions to a support, and making it possible to suppress increases in the manufacturing steps and manufacturing costs.

[0050] Next, FIG. 11 is a bottom view of the glass substrate 60 when the second separation groove 17b is formed. FIG. 12 is a schematic enlarged view of a portion of the second separation groove. FIG. 12 is a view showing a portion of the range 60S in FIG. 11. FIG. 13 is a schematic view showing the side surfaces of the first separation groove 17a and the second separation groove 17b. FIG. 13 is a schematic view showing the range 60S in FIG. 11 as viewed from the second surface 10b side (the glass substrate 60 from the side). FIG. 13 can be obtained, for example, by an SEM (scanning electron microscope). As shown in FIG. 12, on the side surface of the glass substrate 60, a vertical ridge line is formed in which convex portions extending in the normal direction (z-axis direction) of the glass substrate 60 along the processing pitch of the laser modified section 65b for forming the second separation groove 17b are visually recognized as being connected in the xy plane direction. The solid lines in FIG. 13 indicate the ridgelines of the irregularities, which are composed of vertical ridgelines formed on the side surface of the glass substrate 60 and horizontal ridgelines that are approximately perpendicular to the vertical ridgelines. Therefore, a large number of approximately rectangular recesses are formed on the side surface of the glass substrate 60. For example, when the laser-modified portion 65b is processed at a pitch of 10 μm, the spacing R1 of the ridgelines formed in the second separation groove portion 17b shown in FIG. 12 or the spacing R1 of the ridgelines shown in FIG. 13 is 10 μm or less. The processing pitch of the laser-modified portion 65b can be arbitrarily set according to the spacing R1 of the ridgelines. Furthermore, in the second separation groove portion 17b shown in FIG. 12, the width of the irregularities formed along the ridgelines (hereinafter referred to as the "peak-to-valley (PV) of the ridgeline"; in other words, the distance between the protrusion and the recess in the Y-axis direction) is approximately 10 μm or less. Although the above description has been given with respect to the second separation groove portion 17b, if the insulating resin layer 25 is removed to expose the first separation groove portion 17a, the above description can also be applied to the first separation groove portion 17a.

[0051] Also, as shown in Figure 13, the side surface 10c of the core substrate 10 has a plurality of approximately rectangular recesses consisting of a plurality of vertical ridges and horizontal ridges, and the horizontal dimension of the approximately rectangular shape is, for example, in the range of 5 μm to 20 μm, the vertical dimension is in the range of 2 μm to 25 μm, and the depth of the multiple recesses is in the range of 0.5 μm to 11 μm.

[0052] The irregularities appearing on the surface of the glass substrate 60 where the first separation groove portion 17a and the second separation groove portion 17b are formed are minute, and have the effect of improving the adhesion between the insulating resin layer 25 of the first wiring layer 21 and the second wiring layer 22 (described later) and the glass substrate 60. Note that Fig. 10 is a cross-sectional view taken along line AA in Fig. 11 .

[0053] FIG. 14 is an enlarged schematic view of the separation groove 17. FIG. 14 is a cross-sectional view taken along the line B-B in FIG. 11. In the separation groove 17, as shown in FIG. 14, the relationship between the processing width 17B in the intermediate portion Pd and the opening width 17T of the opening on the first surface 10a or the second surface 10b (processing width 17B / opening width 17T) can be adjusted to a range of 0.85 to 1.0 by changing the pitch and number of the laser-modified portions. By processing the processing width 17B in the intermediate portion Pd of the separation groove 17 to the desired width, the amount of insulating resin material placed in the inclined portion of the separation groove 17 can be adjusted, making it easy to adjust the thickness of the insulating resin portion 24 covering the side surface of the multilayer wiring substrate after singulation to the desired thickness.

[0054] FIG. 15 is a schematic enlarged view of a portion of the bottom view of the separation groove 17. FIG. 15 is a view showing region 17E in FIG. 11. The insulating resin layer 25 exposed between the separation grooves 17 has transfer marks 65T of the laser-modified portions 65b, resulting in minute irregularities. These irregularities create an anchor effect when the wiring is subsequently formed and the insulating resin layer 25 of the second wiring layer 22 is formed. As a result, the insulating resin layer 25 is integrally formed between the first wiring layer 21 and the second wiring layer 22, improving adhesion between the insulating resin layer 25 and the core substrate 10 in the multilayer wiring board 1.

[0055] (Formation of Second Wiring Layer) Next, with reference to FIG. 16 , the steps of forming the second wiring layer (seventh and eighth steps) will be described. The seventh step is a step of arranging a conductive member from the second surface 60b side and forming second through electrodes and second conductive portions. The eighth step is a step of depositing a resin material on the second surface 60b side to form the second wiring layer. FIG. 16 is a cross-sectional view illustrating the step of forming the second wiring layer in the manufacturing method according to the first embodiment. As shown in FIG. 16 , the second wiring layer 22 including the second through electrodes 12b, the through electrode connection portions 42, and the insulating resin layer 25 is formed on the second surface 10b of the glass substrate 60. The second through electrodes 12b and the through electrode connection portions 42 are formed by forming a power supply seed layer, forming a resist pattern, and performing a plating process to form a plating having a thickness of 2 μm to 20 μm. Thereafter, the unnecessary resist pattern is peeled off, the seed layer is removed, and the second through electrodes 12b and the through electrode connection portions 42 are formed.

[0056] Here, when the seed layer is formed by a dry sputtering method or the like, if the thickness of the core substrate 10 is large, the adhesion of the seed layer to the through hole 11 during the formation of the through electrode in the core substrate 10 decreases, making it difficult to ensure the reliability of the multilayer wiring board. In the first embodiment, the second through electrode 12b is formed up to the middle portion Pd of the glass substrate 60, so the thickness of the core substrate 10 on which the seed layer is formed is essentially halved. As a result, the adhesion of the seed layer is improved compared to when a seed layer is formed on the side wall of a through hole the same thickness as the core substrate 10, making it possible to ensure the reliability of the multilayer wiring board 1.

[0057] Furthermore, in the process of forming the through electrodes 12 by plating, if the through electrodes 12 are formed by disposing only a conductive layer inside the through holes 11, the thicker the core substrate 10, the less the plating fills the through holes 11 during the plating process. This prevents the formation of a conductor layer entirely inside the through holes 11, making it difficult to ensure the reliability of the multilayer wiring board 1. In the first embodiment, the conductor layer of the first through electrodes 12a is formed up to the middle portion Pd of the through holes 11, so the thickness of the core substrate 10 on which the conductor layer is formed is essentially halved. This improves the filling of the plating film compared to forming a conductor layer in a through hole with the same depth as the thickness of the core substrate 10. Therefore, the conductor layer can be formed entirely inside the through holes 11 with good filling, ensuring the reliability of the multilayer wiring board. While the above description is for the second through electrodes 12b, a similar description can be applied to the first through electrodes 12a.

[0058] Finally, an insulating resin layer 25 is formed, and then the second wiring layer 22 is formed. In the example shown here, the insulating resin layers 25 formed on the first wiring layer 21 and the second wiring layer 22 are formed from the same material, but this is not limited to this. The insulating resin layers may be formed from different materials. The portion of the through hole 11 that does not become the through electrode 12 becomes the separation groove 17. The separation groove 17 is also filled with the insulating resin layer 25.

[0059] In the process of filling the separation grooves 17 with the insulating resin layer 25, if the thickness of the core substrate 10 is increased, the embedding property of the insulating resin layer 25 in the separation grooves 17 decreases, voids occur, and the insulating resin layer 25 is not sufficiently formed over the entire sidewall of the core substrate, making it difficult to avoid damage to the core substrate. In the first embodiment, the insulating resin layer 25 is formed up to the center of the separation grooves 17 (a position near the middle portion Pd), so the thickness of the core substrate 10 in which the insulating resin layer 25 is filled is essentially half. As a result, the embedding property is improved compared to when the insulating resin layer 25 is filled into the separation grooves 17 having the same thickness as the core substrate 10, so the occurrence of voids can be suppressed, the insulating resin layer 25 is formed over the entire sidewall of the core substrate, and damage to the core substrate 10 can be avoided.

[0060] (Removal of First Support) Next, with reference to FIG. 17 , the removal step of the first support 70 will be described. If the bonding step of the first support 70 shown in FIG. 9 has been performed, the removal step of the first support 70 will be performed after the formation step of the second wiring layer. FIG. 17 is a diagram illustrating the removal step of the first support 70 in the manufacturing method according to the first embodiment. As shown in FIG. 17 , the interface between the first wiring layer 21 and the first support 70 is removed, and the first support 70 and the first adhesive layer 71 are separated. This results in a glass substrate 60 having the first wiring layer 21 formed on the first surface 10 a of the glass substrate 60 and the second wiring layer 22 formed on the second surface 10 b of the glass substrate 60, as shown in FIG. 16 .

[0061] When separating the first support 70 from the first wiring layer 21, an appropriate peeling method can be selected from UV light irradiation, heat treatment, physical peeling, etc., depending on the material used for the first adhesive layer 71. Furthermore, if residues of the first adhesive layer 71 remain on the bonding surface between the first wiring layer 21 and the first adhesive layer 71, plasma cleaning, ultrasonic cleaning, water washing, solvent cleaning using alcohol, etc. may be performed.

[0062] (Formation of Build-up Layer) Next, a process for forming a build-up layer, in other words, a layer formed by stacking the first wiring layer 21 and the second wiring layer 22, will be described with reference to Fig. 18. Fig. 18 is a view for explaining the process for forming a build-up layer in the manufacturing method according to the first embodiment.

[0063] As shown in FIG. 18 , a conductive electrode 31 for electrically connecting the first wiring layer 21 on the first surface 10a of the glass substrate 60 and a conductive electrode 32 for electrically connecting the second wiring layer 22 on the second surface 10b are formed on the first wiring layer 21 on the first surface 10a and the second wiring layer 22 on the second surface 10b of the glass substrate 60. The conductive electrodes 31 and 32 are formed by forming vias in the insulating resin layer 25 with a laser, forming a seed layer on the vias, and then using a semi-additive process (i.e., a series of processes including resist pattern formation, plating, resist stripping, seed layer removal, and insulating resin layer formation). The first wiring layer 21 and the second wiring layer 22 each have at least one layer stacked, and the number of layers can be adjusted as needed. In FIG. 18 , two layers are stacked for each of the first wiring layer 21 and the second wiring layer 22.

[0064] The laser used to form the conductive electrodes 31 and 32 can be different from the laser used to form the laser modified portion 65. For example, it is desirable to use a pulsed laser such as a carbon dioxide laser or a UV-YAG laser, and a laser with a pulse width on the order of μs is suitable.

[0065] (Connection Pad Formation) Next, the formation of connection pads will be described with reference to FIG. 19 . FIG. 19 is a diagram illustrating the connection pad formation process in the manufacturing method according to the first embodiment. As shown in FIG. 19 , after forming an outer protective film such as solder resist 55 on the first wiring layer 21 and the second wiring layer 22, semiconductor element bond pads 51 are formed on the first wiring layer 21, and substrate bond pads 53 are formed on the second wiring layer 22. Surface treatments such as Ni / Au, Ni / Pd / Au, IT, and OSP (water-soluble preflux) are performed on the semiconductor element bond pads 51 and the substrate bond pads 53, and semiconductor element bond solder 52 and substrate bond solder 54 are formed as needed to complete the multilayer wiring board. Note that Ni / Au refers to the use of both Ni and Au, and Ni / Pd / Au refers to the use of all of Ni, Pd, and Au.

[0066] 19 can also be said to be a multilayer wiring base material substrate as an intermediate product of multilayer wiring board 1. That is, the multilayer wiring base material substrate includes glass substrate 60 having first surface 10a and second surface 10b, at least one first wiring layer region which is a region including a wiring layer (first wiring layer 21) formed on first surface 10a, at least one second wiring layer region which is a region including a wiring layer (second wiring layer 22) formed on second surface 10b, separation grooves 17 which penetrate from first surface 10a to second surface 10b and separate at least one multilayer wiring board 1 including the first wiring layer region and the second wiring layer region, and insulating resin portions 24 which are disposed in separation grooves 17 and bond adjacent multilayer wiring boards together, wherein separation grooves 17 are configured so that their width narrows from first surface 10a toward an intermediate portion Pd of glass substrate 60 and widens from intermediate portion Pd toward second surface 10b. In the xy plane, the multilayer wiring substrate 1 has a rectangular shape as shown in, for example, Figures 5 and 11, and the first wiring layer region and the second wiring layer region are regions having the same rectangular shape as the multilayer wiring substrate 1.

[0067] (Singulation) Next, with reference to FIG. 20 , the singulation step (ninth step) of the multilayer wiring substrate will be described. The ninth step is a step of separating the multilayer wiring substrate 1 by singulating along the separation grooves 17. FIG. 20 is a cross-sectional view illustrating the singulation step in the manufacturing method according to the first embodiment. The multilayer wiring substrate is singulated along singulation lines formed by laser and hydrofluoric acid etching, as shown in FIG. 20 . FIG. 20 illustrates a case where blade dicing using a blade 72 is assumed, but other methods such as laser and scribing may also be used instead of blade dicing. Furthermore, the singulation may be performed by combining blade dicing, laser, and scribing.

[0068] (Flowchart of the manufacturing method according to the first embodiment) The steps described above are summarized in a flowchart. Fig. 21 is a diagram showing a flowchart of the manufacturing method according to the first embodiment.

[0069] Step S1 is a process for forming the laser-modified portion 65a. The laser-modified portion 65a serves as the starting point for the through-hole and the separation groove. The laser-modified portion 65a is formed by irradiating a laser from the first surface 60a side of the glass substrate 60, and is formed up to the central portion (e.g., intermediate portion Pd) of the glass substrate 60. Step S2 is a process for forming the first through-hole portion 11a by etching. The first through-hole portion 11a is formed up to the central portion (e.g., intermediate portion Pd) of the glass substrate 60. The portion from which the laser-modified portion 65a is removed will later become the first through-hole portion 11a or the first separation groove portion 17a. Step S3 is a process for forming the first wiring layer 21. A first through-hole electrode 12a is formed in the first through-hole portion 11a of the glass substrate 60, and an electrode and a wiring electrically connected to the first through-hole electrode 12a are formed. Electrodes, wiring, capacitors, inductors, etc. can be formed in the first wiring layer 21. Step S4 is a process for forming the laser-modified portion 65b. The laser-modified portion 65b is formed by irradiating a laser from the second surface 60b side of the glass substrate 60, and is formed up to the central portion of the glass substrate 60 (e.g., the intermediate portion Pd). Step S5 is a process for forming the second through-hole portion 11b by etching. The portion from which the modified portion is removed becomes the second through-hole portion 11b or the second separation groove portion 17b. Step S6 is a process for forming the second wiring layer 22. Second through-hole electrodes 12b are formed in the second through-hole portions 11b of the glass substrate 60, and electrodes and wirings that are electrically connected to the second through-hole electrodes 12b are formed. Step S7 is a process for forming a build-up layer. Electrodes and wirings are formed in the first wiring layer 21 and the second wiring layer 22. Step S8 is a process for forming connection pads. After forming a protective film on the first wiring layer 21 and the second wiring layer 22, connection pads are formed. Step S9 is a singulation process. The glass substrate 60 is subjected to dicing or the like to separate the multilayer wiring substrate 1 .

[0070] <First Modification> Next, a manufacturing method as a first modification will be described with reference to Figures 21 to 24. The first modification differs from the first embodiment in that, in the laser-modified portion formation step, the laser-modified portion is formed all at once from the first surface 60a side to the second surface 60b side of the glass substrate 60. In the following description, components that are the same as or equivalent to those in the first embodiment described above are denoted by the same reference numerals, and their description will be simplified or omitted.

[0071] (Formation of Laser-Modified Portion) The step of forming the laser-modified portion in the first modified example will be described with reference to Fig. 22. Fig. 22 is a cross-sectional view illustrating the step of forming the laser-modified portion in the manufacturing method according to the first modified example. As shown here, a laser is irradiated from the first surface 60a side to form a laser-modified portion 65 extending from the first surface 60a side to the second surface 60b side. In this step, the laser-modified portion 65 is also formed along the singulation line of the multilayer wiring substrate 1, making it possible to obtain a shape identical to the side shape of the multilayer wiring substrate 1 described in the first embodiment.

[0072] (Formation of Through Holes by Etching) Next, with reference to FIG. 23 , the process of forming through holes by etching will be described. FIG. 23 is a cross-sectional view illustrating the process of forming through holes by etching in the manufacturing method according to the first modification. FIG. 23 shows the shape of the glass substrate 60 after hydrofluoric acid etching. By appropriately adjusting the concentration of hydrofluoric acid etching and the processing time, the first through hole portion 11a and the first separation groove portion 17a extending from the first surface 60a side of the glass substrate 60 to the intermediate portion Pd are simultaneously formed. Furthermore, a portion of the laser-modified portion 65 remains from the intermediate portion Pd to the second surface 60b side of the glass substrate 60. As shown here, the laser-modified portion 65 is selectively removed from the first surface 60a side of the glass substrate 60 by etching. This forms the first through hole portion 11a. Wet etching using a hydrogen fluoride solution is suitable for the etching.

[0073] (Processes after the formation of the first wiring layer) FIG. 24 is a diagram showing a flowchart of a manufacturing method according to the first modified example. In the first embodiment, as shown in FIG. 21, after the laser-modified portion forming process (step S1) and the etching through-hole forming process (step S2), the first wiring layer forming process (step S3) of the first embodiment shown in FIG. 7 is performed. On the other hand, in the first modified example, as shown in FIG. 22, a laser-modified portion 65 is also formed on the second surface 60b side in the laser-modified portion forming process (corresponding to step S1a in FIG. 24). Therefore, in the flowchart of the first modified example shown in FIG. 24, the etching through-hole forming process (step S2) and the first wiring layer forming process (step S3) are the same as steps S2 and S3 of the first embodiment shown in FIG. 21, but the second laser-modified portion forming process (step S4) shown in FIG. 21 can be omitted. The steps (steps S5 to S9) following the step of forming a through hole by etching shown in FIG. 24 (step S5) are the same as steps S5 to S9 of the manufacturing method according to the first embodiment shown in FIG.

[0074] <Actions and Effects> According to the first embodiment and first modification of the present invention, even when the core substrate is thick, by protecting the side surfaces of the core substrate of the multilayer wiring board, it is possible to avoid damage to the core substrate and ensure the reliability of the multilayer wiring board. It is also possible to reduce the manufacturing process and manufacturing costs of the multilayer wiring board. Below, detailed contents will be explained using examples and comparative examples. Note that each example shown below is an example of an example of the present invention, and the present invention should not be interpreted as being limited to these embodiments.

[0075] <Examples of the First Embodiment, First Modification, and Comparative Examples> For the examples and comparative examples, a mounting process was performed to separate the presence or absence of the insulating resin portion 24 on the side surface 10c of the core substrate 10 of the multilayer wiring substrate 1, and a temperature cycle test was then performed. Table 1 shows the manufacturing conditions, through-hole overlap rate, and ridge spacing for the examples and comparative examples. In examples 1 to 3, the processing pitch of the laser-modified portion was varied to achieve overlap rates of 40, 65, and 90% for the through-holes 11 in the glass substrate 60 formed by hydrofluoric acid etching. FIG. 25 illustrates the overlap rate between the laser-modified portion 65 and the through-holes 11. The overlap rate indicates the percentage of overlap between adjacent through-holes 11 when the laser-modified portion 65 is formed by hydrofluoric acid etching, as shown in FIG. 25 . A higher overlap rate indicates a higher percentage of overlap between adjacent through-holes 11. Figure 25(a) is a diagram showing the case where there are two laser-modified regions, and Figure 25(b) is a diagram showing the case where multiple laser-modified regions are formed and a separation groove is formed. As shown in Figure 25(a), in the separation groove 17, a through-hole 11-1 is formed in the laser-modified region 65-1, and a through-hole 11-2 is formed in the laser-modified region 65-2. The overlapping region between the through-hole 11-1 and the through-hole 11-2 is defined as DR. The overlapping ratio is the size of the overlapping region DR relative to the size of the through-hole 11-1 or the size of the through-hole 11-2. As shown in Figure 25(b), a separation groove 17 is formed by forming multiple laser-modified regions 65 and through-holes 11.

[0076] Examples 1 to 3 correspond to the multilayer wiring substrate 1 shown in FIG. 1 . In Comparative Example 1, the processing pitch of the laser-modified portion in the separation groove 17 was set to a larger value compared to Examples 1 to 3, and processing was performed so that the overlap rate of the through holes 11 formed by hydrofluoric acid etching was 30%. In Comparative Example 2, a multilayer wiring substrate was produced without forming the separation groove 17, and then diced to separate the substrates. Table 1 shows the examples and comparative examples. Table 1 shows the average ridge line spacing and PV for each example and comparative example, the average and variation of the upper opening width and middle processing width of the dividing groove when the upper opening width of the dividing groove was processed to 300 μm, the average middle processing width / upper opening width, and the average resin thickness on the side of the core substrate when the dividing groove was processed to have an upper opening width of 300 μm, and the average value of the resin thickness on the side of the core substrate. As an example of a measurement method, the side and top surfaces of the core substrate after hydrofluoric acid etching or singulation were observed using a SEM (scanning electron microscope), and each characteristic value was measured at any location for a sample number n = 20 or more, and the average value was calculated. Here, the spacing between ridgelines refers to ridgelines that occur in a direction perpendicular to the first surface 10a and the second surface 10b of the glass substrate 60. From Table 1, it can be seen that the spacing between ridgelines increases as the overlap rate decreases.

[0077] Next, the upper opening width (opening width of the opening on the first surface side or the opening on the second surface side), the processed width of the middle portion (opening width of the opening in the middle portion Pd), and the PV of the ridge line of each example and comparative example will be described with reference to Table 1. As mentioned above, the separation groove was processed so that the upper opening width was 300 μm. As shown in Table 1, it can be seen that as the overlap rate and the ridge line spacing increased, the average processed width of the middle portion Pd decreased and the variation (standard deviation) σ increased. It was also confirmed that as the overlap rate and the ridge line spacing increased, the PV of the ridge line increased and the side surface of the separation groove became rough. The above results suggest that setting the overlap rate and ridge line spacing wide roughens the side surface of the separation groove, reducing the smoothness of the side surface of the separation groove.

[0078] Next, the results of the temperature cycle test are shown. Generally, the occurrence of μ-cracks is caused by stress accumulation, particularly when the difference in linear expansion coefficient between the glass substrate and the wiring layer is large, or when temperature changes are large. Therefore, in the present disclosure, the quality of the multilayer wiring substrate was confirmed using a temperature cycle test. As shown in Table 1, Comparative Example 1 passed the temperature cycle test up to 500 cycles, but failed after 600 cycles. Comparative Example 2 failed the temperature cycle test after 50 cycles. In the cases where the test failed, defects such as the occurrence of microcracks were confirmed. Furthermore, Examples 1, 2, and 3 were able to pass the temperature cycle test even after 1,000 cycles. In Comparative Example 1, separation grooves were formed similarly to Examples 1 to 3, but the PV of the ridges was large, as shown in Table 1. Therefore, for example, when dicing along the separation grooves to separate the substrate, the dicing blade partially contacted the glass substrate 60, causing grinding marks, i.e., μ-cracks, on the glass substrate 60, which can be considered to be the reason for the failure of the temperature cycle test.

[0079] The dicing process along the dividing grooves, the temperature cycle test conditions, and the evaluation method are as follows: <Dicing process> Blade used: R07-SD600-BB200-75 54 x 0.15A2 x 40 Equipment used: DAD322 <Temperature cycle test> Test conditions: Changes from -55°C, RT (room temperature), to 125°C constitute one cycle, and each temperature is held for 30 minutes, after which the test is repeated up to 1000 cycles. Observation method: The side of the substrate is observed with a metallurgical microscope at 100x and 500x magnification to evaluate whether or not the glass substrate is broken.

[0080] From the above examples, it is more desirable that the overlap rate of the through holes in the separation groove be in the range of 40% or more and 90% or less, the thickness of the insulating resin portion 24 on the side surface 10c of the core substrate 10 be 52.8 μm or more, the processing width / opening width of the middle portion be in the range of 0.88 or more, and the PV of the vertical ridge line or horizontal ridge line be in the range of 1.8 μm or more and 10.6 μm or less.

[0081] Second Embodiment The second embodiment differs from the first embodiment in that an inductor is formed in the first wiring layer. Fig. 26 is a cross-sectional view showing a multilayer wiring substrate 100 according to the second embodiment. Fig. 26(a) shows a cross-sectional view of the entire multilayer wiring substrate 100, and Fig. 26(b) is a perspective view of circuit elements in a portion cl surrounded by a dashed line in Fig. 26(a). In the following description, components that are the same as or equivalent to those in the first embodiment described above are designated by the same reference numerals, and descriptions thereof will be simplified or omitted.

[0082] As shown in Fig. 26(a), the first wiring layer 121 is composed of three wiring layers, and the second wiring layer 122 is also composed of three wiring layers. Also, as shown in Fig. 26(b), adjacent conductive electrodes 31 are connected via wiring 16 and integrally form a coil. The coil is connected to, for example, a capacitor electrode 13 to exhibit the characteristics of an LC circuit. As a manufacturing method, in the step of forming the first wiring layer, the conductive electrodes 31 and wiring 16 are arranged so as to form an inductor.

[0083] <Functions and Effects> Even when the core substrate is thick, by protecting the side surfaces of the core substrate 10 of the multilayer wiring board with insulating resin, it is possible to prevent damage to the core substrate and ensure the reliability of the multilayer wiring board. It is also possible to reduce the manufacturing process and manufacturing costs for the multilayer wiring board. Furthermore, because the inductor is provided within the multilayer wiring board 100, the wiring distance can be shortened and good transmission characteristics can be obtained.

[0084] Third Embodiment The third embodiment differs from the first embodiment in that the interior of the through electrode 12 is filled with a conductive material. Fig. 27 is an enlarged cross-sectional view showing the structure of a through electrode in a multilayer wiring substrate according to the third embodiment. In the following description, components that are the same as or equivalent to those in the first embodiment are given the same reference numerals, and descriptions thereof will be simplified or omitted.

[0085] The through electrode 120 is filled with a conductive material. The capacitor electrode 13 is disposed above the through electrode 120.

[0086] <Functions and Effects> By using a structure in which the through electrode 120 is filled with a conductive material, the capacitor electrode 13 can be formed near or above the through hole, in other words, without being restricted by the position of the through hole. As in the third embodiment, it is also possible to provide the capacitor electrode 13 directly above the through hole. This shortens the transmission distance to the capacitor and prevents degradation of transmission characteristics. Furthermore, by forming a lower electrode layer when forming the capacitor electrode 13, it is possible to reduce variations in capacitor capacitance.

[0087] <Fourth Embodiment> The fourth embodiment differs from the first embodiment in that a hydrofluoric acid-resistant metal layer is used. Fig. 28 is a cross-sectional view showing a multilayer wiring substrate according to a third embodiment. Fig. 28(a) shows a cross-sectional view of the entire multilayer wiring substrate, and Fig. 28(b) is a cross-sectional view showing an enlarged view of the structure of the through electrode. In the following description, components that are the same as or equivalent to those in the first embodiment are given the same reference numerals, and descriptions thereof will be simplified or omitted.

[0088] The hydrofluoric acid-resistant metal layer 15 is disposed on the glass substrate 60 and between the inner wall of the through hole 11 and the seed layer. The hydrofluoric acid-resistant metal layer 15 is a metal layer containing at least one of chromium and nickel, and is formed by sputtering to a thickness of 10 nm to 1,000 nm. When the hydrofluoric acid-resistant metal layer 15 is used, the hydrofluoric acid-resistant metal layer 15 is exposed in addition to the insulating resin layer 25 shown in FIG.

[0089] 10 by hydrofluoric acid etching, it is necessary to appropriately control the amount of etching so that the etching stops in the middle of the glass substrate 60. On the other hand, in the fourth embodiment, since the hydrofluoric acid resistant metal layer 15 is provided, the etching stops at the hydrofluoric acid resistant metal layer 15, and it is possible to form a through hole having a desired X-shape without strictly controlling the amount of etching.

[0090] Fifth Embodiment The fifth embodiment differs from the first embodiment in that the intermediate product is treated as a multilayer wiring base substrate, which is a base substrate for a multilayer wiring board. Fig. 29 is a perspective view of a multilayer wiring board. Fig. 30 is a schematic view of a multilayer wiring base substrate. In the following description, components that are the same as or equivalent to those in the first embodiment are designated by the same reference numerals, and descriptions thereof will be simplified or omitted.

[0091] Fig. 29(a) shows a perspective view of a multilayer wiring board, and Fig. 29(b) shows a perspective view of a core substrate 10 included in the multilayer wiring board. Fig. 29 is a perspective view of the multilayer wiring board 1 of Fig. 1, but for ease of understanding, the outlines of the core substrate 10, the first wiring layer 21, the second wiring layer 22, and the insulating resin layer 25 are shown schematically.

[0092] 29(b), the core substrate 10 has a first surface 10a, a second surface 10b opposite the first surface 10a, and a side surface 10c connecting the peripheral edge of the first surface 10a with the peripheral edge of the second surface 10b. The first surface 10a and the second surface 10b are parallel to each other and are surrounded by the side surface 10c connecting the outer periphery (periphery) of the first surface 10a with the outer periphery (periphery) of the second surface 10b. When a cross section parallel to the xy plane is assumed, the cross-sectional area of ​​the side surface 10c increases from the first surface 10a toward the intermediate portion Pd and decreases from the intermediate portion Pd toward the second surface 10b. Although the side surface 10c is depicted as being flat, it may not be flat because it is formed by etching the first separation groove 17a and the second separation groove 17b.

[0093] FIG. 30 is a perspective view of the structure shown in FIG. 19 . For ease of understanding, FIG. 30 omits the configuration of connection pads and the like. The diagram shows three portions corresponding to the multilayer wiring board 1. The multilayer wiring board 1 corresponds to the portion surrounded by the dashed line, and is obtained by dividing the first wiring layer 21, the second wiring layer 22, and the core substrate 10, which are surrounded by the separation groove 17, in the zy-y plane. While FIG. 30 shows three portions corresponding to the multilayer wiring board 1, the x-y plane includes portions corresponding to multiple multilayer wiring boards. Note that one of the multilayer wiring boards is indicated by an outline.

[0094] 19 can also be said to be a multilayer wiring base material substrate as an intermediate product of multilayer wiring board 1. That is, the multilayer wiring base material substrate has first surface 10a and second surface 10b and is a multilayer wiring base material substrate including a plurality of multilayer wiring boards, the multilayer wiring base material substrate having a first wiring layer which is a wiring layer formed on first surface 10a, a second wiring layer which is a wiring layer formed on second surface 10b, and separation grooves 17 used to separate the plurality of multilayer wiring boards, the separation grooves 17 being formed such that when ends of separation groove 17 on first surface 10a and second surface 10b are connected by a straight line in a cross-sectional view, an end of intermediate portion Pd of the side surface of separation groove 17 is formed closer to the center of the separation groove than the straight line, and separation groove 17 is filled with insulating resin.

[0095] The scope of the present invention is not limited to the exemplary embodiments shown and described, but includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. Furthermore, the present invention also includes all embodiments that achieve effects equivalent to those intended by the present invention.

[0096] For example, although the present disclosure describes the formation of through-holes and separation grooves, the present disclosure is not limited to this. For example, it is also possible to form only separation grooves without forming through-holes.

[0097] The present invention is not limited to the following embodiments: (Aspect 1) A multilayer wiring board having a core substrate having a first surface, a second surface opposite to the first surface, and a side surface connecting a peripheral edge of the first surface and a peripheral edge of the second surface, a first wiring layer that is a wiring layer formed on the first surface, and a second wiring layer that is a wiring layer formed on the second surface, wherein, in a cross section seen when cut along a direction perpendicular to the first surface and the second surface, the side surface has a shape that bulges outward from the core substrate with respect to a straight line connecting an intersection of the first surface and the side surface and an intersection of the second surface and the side surface, and the side surface is covered with an insulating resin portion. (Aspect 2) When the position between the first surface and the second surface where the side surface bulges most is referred to as the intermediate portion, the core substrate further has a through hole penetrating from the first surface to the second surface, where, in the cross-sectional view, the opening width of the opening in the first surface becomes smaller toward the intermediate portion and the opening width of the opening in the second surface becomes smaller toward the intermediate portion, the multilayer wiring board further has a through electrode including a seed layer and providing electrical continuity between the first surface and the second surface through the through hole, a first conductive portion connected to the through electrode is arranged on the first wiring layer, and a second conductive portion connected to the through electrode is arranged on the second wiring layer, and the first conductive portion and the second conductive portion are electrically connected through the through electrode. (Aspect 3) The multilayer wiring board according to Aspect 1 or Aspect 2, wherein the first wiring layer and the second wiring layer include an insulating resin layer, and the insulating resin portion covering the side surface is made of the same type of insulating resin material as the insulating resin material constituting the insulating resin layer. (Aspect 4) The multilayer wiring board according to any one of Aspects 1 to 3, wherein the insulating resin portion covering the side surface of the core substrate has a thickness of 50 μm or more, the core substrate has a thickness in the range of 150 μm to 2000 μm, and the insulating resin layer has a relative dielectric constant in the range of 3.1 to 3.5 and a dielectric loss tangent in the range of 0.002 to 0.012.(Aspect 5) The multilayer wiring board according to any one of Aspects 1 to 4, wherein the side surface of the core substrate has a plurality of generally rectangular recesses formed by a plurality of vertical ridges and horizontal ridges, the horizontal dimension of the generally rectangular being 5 μm to 20 μm and the vertical dimension being 2 μm to 25 μm. (Aspect 6) The multilayer wiring board according to any one of Aspects 1 to 5, wherein the PV of the vertical ridges or the horizontal ridges is 1.8 μm to 10.6 μm. (Aspect 7) The multilayer wiring board according to any one of Aspects 1 to 6, wherein the depth of the plurality of recesses is 0.5 μm to 11 μm. (Aspect 8) The multilayer wiring board according to any one of Aspects 1 to 7, wherein the thickness of the insulating resin portion on the side surface of the core substrate is 52.8 μm or more.(Aspect 9) A method for manufacturing a multilayer wiring board using a base substrate having a first surface and a second surface opposite the first surface, comprising: a first step of irradiating a laser from the first surface side of the base substrate to form first modified portions at first through hole positions, where first through hole portions penetrating from the first surface to a middle portion of the base substrate are formed among through holes penetrating the base substrate from the first surface toward the second surface, and at first singulation line positions, where first separation groove portions extending from the first surface to the middle portion of the base substrate are formed among separation grooves separating the multilayer wiring board from the base substrate; a second step of removing the first modified portions by etching from the first surface side to form the first through hole portions and the first separation groove portions; a third step of arranging a conductive member from the first surface side to form first through electrodes and first conductive portions; and a fourth step of depositing an insulating resin material on the first surface side to form a first wiring layer. a fifth step of irradiating a laser from the second surface side of the base substrate to form second modified portions at second through hole positions, which are positions where second through hole portions that penetrate from the second surface to the intermediate portion of the base substrate are formed, among the through holes, and at second singulation line positions, which are positions where second separation groove portions that extend from the second surface to the intermediate portion of the base substrate are formed, among the separation grooves; a sixth step of removing the second modified portions by etching from the second surface side to form the second through hole portions and the second separation groove portions; a seventh step of arranging a conductive member from the second surface side to form second through electrodes and second conductive portions; an eighth step of depositing the insulating resin material on the second surface side to form a second wiring layer; and a ninth step of separating the multilayer wiring substrate by singulating along the separation grooves. (Aspect 10) The method for manufacturing a multilayer wiring board according to aspect 9, wherein a side surface of each of the divided multilayer wiring boards is covered with the insulating resin material.(Aspect 11) The method for manufacturing a multilayer wiring board according to Aspect 9 or Aspect 10, wherein in the sixth step, the thickness of the base substrate is in the range of 150 μm or more and 2000 μm or less by the etching, the thickness of the insulating resin material covering the side surfaces of the multilayer wiring board is 50 μm or more, and the insulating resin material has a relative dielectric constant in the range of 3.1 or more and 3.5 or less and a dielectric loss tangent in the range of 0.002 or more and 0.012 or less. (Aspect 12) The method for manufacturing a multilayer wiring board according to any one of Aspects 9 to Aspect 11, wherein the first separation groove portion in the first step and the second separation groove portion in the fifth step have an overlap rate of the through holes in the separation grooves of 40% or more and 90% or less. and a separation groove configured to separate at least one of the first and second wiring layer regions, the separation groove including the first and second wiring layer regions, and an insulating resin portion disposed in the separation groove and bonding adjacent multilayer wiring substrates together, the separation groove being configured so that the width of the separation groove narrows from the first surface toward the intermediate portion of the base substrate and widens from the intermediate portion toward the second surface.(Aspect 15) A multilayer wiring base substrate having a first surface and a second surface and including a plurality of multilayer wiring boards, the multilayer wiring base substrate having: a first wiring layer which is a wiring layer formed on the first surface; a second wiring layer which is a wiring layer formed on the second surface; and a separation groove used to separate the plurality of multilayer wiring boards, wherein when a straight line is drawn between the ends of the separation groove on the first surface and the second surface in a cross-sectional view, the end of the central portion of the side of the separation groove is formed closer to the center of the separation groove than the straight line, and the separation groove is filled with insulating resin.

[0098] 1, 100: multilayer wiring substrate, 10: core substrate, 11: through hole, 11a: first through hole portion, 11b: second through hole portion, 12: through electrode, 12a: first through electrode, 12b: second through electrode, 13: capacitor electrode, 14: dielectric layer, 15: hydrofluoric acid resistant metal layer, 16: wiring, 17: separation groove, 17a: first separation groove portion, 17b: second separation groove portion, 17T: opening width of separation groove, 17B: processing width of central portion of separation groove, 21, 121: first wiring layer, 22, 122 : second wiring layer, 24: insulating resin portion, 25: insulating resin layer, 31, 32: conductive electrodes, 41, 42: through-electrode connection portion, 51: semiconductor element bonding pad, 52: semiconductor element bonding solder, 53: substrate bonding pad, 54: substrate bonding solder, 55: solder resist, 60: glass substrate, 65, 65a, 65b, 65-1, 65-2: laser modified portion, 65T: transfer marks of laser modified portion, 70: first support, 71: first adhesive layer, 72: blade

Claims

1. A multilayer wiring board having a core substrate having a first surface, a second surface facing the first surface, and side surfaces connecting the peripheral edge of the first surface and the peripheral edge of the second surface, a first wiring layer which is a wiring layer formed on the first surface, and a second wiring layer which is a wiring layer formed on the second surface, wherein in a cross-sectional view taken along a direction perpendicular to the first surface and the second surface, the side surface has a shape bulging outward of the core substrate more than a straight line connecting an intersection of the first surface and the side surface and an intersection of the second surface and the side surface, and the side surface is covered with an insulating resin portion.

2. When a position where the side surface bulges most between the first surface and the second surface is referred to as an intermediate portion, the core substrate has a through hole penetrating from the first surface to the second surface, and in the cross-sectional view, the opening width of the opening in the first surface becomes smaller as it approaches the intermediate portion, and the opening width of the opening in the second surface becomes smaller as it approaches the intermediate portion. The multilayer wiring board further includes a seed layer and a through electrode that electrically connects between the first surface and the second surface through the through hole. A first conductive portion connected to the through electrode is disposed in the first wiring layer, a second conductive portion connected to the through electrode is disposed in the second wiring layer, and the first conductive portion and the second conductive portion are electrically connected through the through electrode. The multilayer wiring board according to claim 1, characterized in that.

3. The first wiring layer and the second wiring layer include an insulating resin layer, and the insulating resin portion covering the side surface is made of the same type of insulating resin material as the insulating resin material constituting the insulating resin layer. The multilayer wiring board according to claim 1.

4. The thickness of the insulating resin portion covering the side surface of the core substrate is 50 μm or more, the thickness of the core substrate is included in the range of 150 μm or more and 2000 μm or less, and the insulating resin layer has a relative permittivity included in the range of 3.1 or more and 3.5 or less, and a dielectric tangent included in the range of 0.002 or more and 0.012 or less. The multilayer wiring board according to claim 3.

5. The side surface of the core substrate has a plurality of substantially rectangular recesses formed by a plurality of vertical ridge lines and horizontal ridge lines, the lateral dimension of the substantially rectangle being 5 μm or more and 20 μm or less, and the longitudinal dimension being 2 μm or more and 25 μm or less. The multilayer wiring board according to claim 1, characterized in that.

6. The PV of the vertical ridge line or the horizontal ridge line is 1.8 μm or more and 10.6 μm or less. The multilayer wiring board according to claim 5.

7. The depth of the plurality of recesses is 0.5 μm or more and 11 μm or less. The multilayer wiring board according to claim 5.

8. The thickness of the insulating resin portion on the side surface of the core substrate is 52.8 μm or more. The multilayer wiring board according to claim 1.

9. In a manufacturing method for manufacturing a multilayer wiring board using a base material substrate having a first surface and a second surface facing the first surface, among the through holes penetrating the base material substrate from the first surface toward the second surface, a first through hole portion penetrating from the first surface to the middle portion of the base material substrate is formed at a first through hole position, and among the separation grooves for separating the multilayer wiring board from the base material substrate, a first fragmentation line position indicating a position where a first separation groove portion extending from the first surface to the middle portion of the base material substrate is formed. A first step of irradiating a laser from the first surface side of the base material substrate to form a first modified portion; A second step of removing the first modified portion by etching from the first surface side to form the first through hole portion and the first separation groove portion; A third step of disposing a conductive member from the first surface side to form a first through electrode and a first conductive portion; A fourth step of depositing an insulating resin material on the first surface side to form a first wiring layer; Among the through holes, a second through hole portion penetrating from the second surface to the middle portion of the base material substrate is formed at a second through hole position, and among the separation grooves, a second fragmentation line position indicating a position where a second separation groove portion extending from the second surface to the middle portion of the base material substrate is formed. A fifth step of irradiating a laser from the second surface side of the base material substrate to form a second modified portion; A sixth step of removing the second modified portion by etching from the second surface side to form the second through hole portion and the second separation groove portion; A seventh step of disposing a conductive member from the second surface side to form a second through electrode and a second conductive portion; An eighth step of depositing the insulating resin material on the second surface side to form a second wiring layer; A ninth step of fragmenting according to the separation groove to separate the multilayer wiring board; A manufacturing method for a multilayer wiring board having the above steps.

10. A manufacturing method for a multilayer wiring board according to claim 9, wherein a side surface of the fragmented multilayer wiring board is covered with the insulating resin material.

11. A method for manufacturing a multilayer wiring board according to claim 10, wherein in the sixth step, the thickness of the base substrate becomes in the range of 150 μm or more and 2000 μm or less by the etching, the thickness of the insulating resin material covering the side surface of the multilayer wiring board is 50 μm or more, and the insulating resin material has a relative permittivity in the range of 3.1 or more and 3.5 or less and a dielectric tangent in the range of 0.002 or more and 0.012 or less. A method for manufacturing a multilayer wiring board.

12. A method for manufacturing a multilayer wiring board according to claim 9, wherein in the first separation groove portion in the first step and the second separation groove portion in the fifth step, the overlapping ratio of the through holes in the separation groove is 40% or more and 90% or less. A method for manufacturing a multilayer wiring board.

13. A method for manufacturing a multilayer wiring board according to claim 9, wherein in the second step and the sixth step, the processing width / opening width of the intermediate portion of the through holes in the separation groove is 0.88 or more. A method for manufacturing a multilayer wiring board.

14. A multilayer wiring base substrate comprising: a base substrate having a first surface and a second surface; at least one first wiring layer region which is a region including a wiring layer formed on the first surface; at least one second wiring layer region which is a region including a wiring layer formed on the second surface; a separation groove that penetrates from the first surface to the second surface and separates at least one multilayer wiring board including the first wiring layer region and the second wiring layer region; and an insulating resin portion that is disposed in the separation groove and bonds adjacent multilayer wiring boards to each other. The separation groove is configured such that the width narrows as it goes from the first surface toward the intermediate portion of the base substrate and widens as it goes from the intermediate portion toward the second surface.

15. A multilayer wiring base substrate having a first surface and a second surface and including a plurality of multilayer wiring boards, comprising: a first wiring layer which is a wiring layer formed on the first surface; a second wiring layer which is a wiring layer formed on the second surface; and a separation groove used for separating the plurality of multilayer wiring boards. When the ends of the separation groove on the first surface and the second surface in a cross-sectional view are connected by a straight line, the end portion at the center of the side surface of the separation groove is formed closer to the center of the separation groove than the straight line, and the separation groove is filled with an insulating resin. A multilayer wiring base substrate characterized by this.

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