Oscillator, production method for same, information processing device

Abstract

The present disclosure provides an oscillator that uses a ferroelectric transistor but is small in size and has a low production cost, a production method for the oscillator, and an information processing device. An oscillator (100) comprises a semiconductor substrate (1), a ferroelectric FET (20) that is formed on the semiconductor substrate (1) and includes a ferroelectric film (4) as a gate insulation film, a paraelectric FET (30) that is formed on the semiconductor substrate (1) and includes a paraelectric insulation film (12) as a gate insulation film, and a capacitor (40) that is formed on the semiconductor substrate (1). The capacitor (40) is configured such that an electrode (3) and an electrode (11) are opposite across at least one of the ferroelectric film that is the gate insulation film of the ferroelectric FET (20) and the paraelectric film that is the gate insulation film of the paraelectric FET (30).

Description

Oscillator, manufacturing method thereof, and information processing device

[0001] The present disclosure relates to an oscillator using a ferroelectric transistor, a manufacturing method thereof, and an information processing device.

[0002] In recent years, devices (information processing devices) directly equipped with AI processing functions, known as edge AI (Artificial Intelligence), have been attracting attention. In particular, in edge AI, it has been proposed to process some of the AI ​​processing by hardware rather than by software in order to achieve power saving and high speed. Regarding the processing of AI processing by hardware, a device using ferroelectric transistors is disclosed in Non-Patent Document 1.

[0003] Zheng Wang and 9 others, "Experimental Demonstration of Ferroelectric Spiking Neurons for Unsupervised Clustering", 2018 IEEE International Electron Devices Meeting (IEDM), December 2018

[0004] Non-Patent Document 1 discloses AI processing using an oscillator that uses a ferroelectric transistor. The disclosed oscillator includes a ferroelectric field effect transistor (FET), a discharge FET, and a capacitor. However, when manufacturing this oscillator, the ferroelectric FET, the discharge FET, and the capacitor must be formed separately on a substrate, which can result in a large size and high manufacturing costs.

[0005] Therefore, an object of the present disclosure is to provide an oscillator using a ferroelectric transistor that is small in size and inexpensive to manufacture, a manufacturing method thereof, and an information processing device.

[0006] An oscillator according to one embodiment of the present disclosure includes a substrate, a first field-effect transistor formed on the substrate and using a ferroelectric as a gate insulating film, a second field-effect transistor formed on the substrate and using a paraelectric as a gate insulating film, and a capacitor formed on the substrate. The first field-effect transistor includes a first gate electrode, a ferroelectric film formed to cover the first gate electrode, a first semiconductor film forming a first channel layer formed on the ferroelectric film, and a first source electrode and a first drain electrode formed on the first semiconductor film. The second field-effect transistor includes a second semiconductor film forming a second channel layer formed on the ferroelectric film, a second source electrode and a second drain electrode formed on the second semiconductor film, a paraelectric film formed to cover the second source electrode, the second drain electrode, and the second semiconductor film, and a second gate electrode formed on the paraelectric film. The paraelectric film is further formed to cover the first source electrode, the first drain electrode, and the first semiconductor film. The capacitor includes a first electrode electrically connected to the first source electrode, and a second electrode facing the first electrode via at least one of a ferroelectric film and a paraelectric film and electrically connected to the second source electrode. The first source electrode is electrically connected to the second drain electrode.

[0007] According to an embodiment of the present disclosure, there is provided a method for manufacturing an oscillator including a substrate, a first field-effect transistor formed on the substrate and having a ferroelectric film as a gate insulating film, a second field-effect transistor formed on the substrate and having a paraelectric film as a gate insulating film, and a capacitor formed on the substrate, the method including the steps of forming a first gate electrode of the first field-effect transistor and a first electrode of the capacitor on the substrate, forming a ferroelectric film covering the first gate electrode and the first electrode, forming a via in the ferroelectric film reaching the first electrode, forming a first semiconductor film on the ferroelectric film to form a first channel layer of the first field-effect transistor, and forming a second semiconductor film on the ferroelectric film to form a second channel layer of the second field-effect transistor. Furthermore, the method for manufacturing the oscillator includes the steps of forming a first source electrode and a first drain electrode of a first field effect transistor on the first semiconductor film, a second source electrode and a second drain electrode of a second field effect transistor on the second semiconductor film, a second electrode of a capacitor on the ferroelectric film, and a via conductor electrically connecting the first electrode and the first source electrode to the via; forming a paraelectric film covering the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, the second electrode, the first semiconductor film, and the second semiconductor film; and forming a second gate electrode of the second field effect transistor on the paraelectric film.

[0008] According to the present disclosure, the first field effect transistor includes a ferroelectric film formed to cover the first gate electrode, and the second field effect transistor includes a paraelectric film formed to cover the second semiconductor film formed on the ferroelectric film, and a second gate electrode formed on the paraelectric film, so that an oscillator using ferroelectric transistors that is small in size and inexpensive to manufacture can be configured.

[0009] FIG. 1 is a cross-sectional view for explaining a configuration of an oscillator according to an embodiment. FIG. 2 is a circuit diagram of an oscillator according to an embodiment. FIG. 3 is a diagram for explaining operation of an oscillator according to an embodiment. FIG. 4 is a cross-sectional view for explaining a method for manufacturing an oscillator according to an embodiment. FIG. 5 is a cross-sectional view for explaining a method for manufacturing an oscillator according to an embodiment. FIG. 6 is a cross-sectional view for explaining a method for manufacturing an oscillator according to an embodiment. FIG. 7 is a schematic diagram of a device using an oscillator according to an embodiment.

[0010] Hereinafter, oscillators according to embodiments of the present disclosure will be described in detail with reference to the drawings, in which the same reference numerals indicate the same or corresponding parts.

[0011] (Embodiment) In the embodiment, an oscillator used in, for example, an intermediate layer of an edge AI will be described with reference to the drawings. The oscillator is not limited to being used in the intermediate layer of an edge AI, and may be used for other purposes. Fig. 1 is a cross-sectional view for explaining the configuration of an oscillator 100 according to the embodiment. Fig. 2 is a circuit diagram of the oscillator 100 according to the embodiment.

[0012] The oscillator 100 shown in Fig. 1 includes a ferroelectric FET 20 (first field effect transistor), a paraelectric FET 30 (second field effect transistor), and a capacitor 40 formed on a semiconductor substrate 1. In Fig. 1, the capacitor 40 is provided between the ferroelectric FET 20 and the paraelectric FET 30, but the layout of the ferroelectric FET 20, the paraelectric FET 30, and the capacitor 40 on the semiconductor substrate 1 is not limited to this. Note that the semiconductor substrate 1 has a passivation film 1a formed on the surface on which the ferroelectric FET 20, the paraelectric FET 30, and the capacitor 40 are provided.

[0013] The ferroelectric FET 20 has a gate electrode 2 (first gate electrode), a ferroelectric film 4 (gate insulating film), a channel forming film 5a (first semiconductor film), a drain electrode 6 (first drain electrode), and a source electrode 7 (first source electrode). In the ferroelectric FET 20 shown in Fig. 1, the gate electrode 2 is formed on a semiconductor substrate 1, the ferroelectric film 4 and the channel forming film 5a are formed in this order to overlap the gate electrode 2, and the drain electrode 6 and the source electrode 7 are formed thereon, respectively. In other words, the ferroelectric FET 20 is a bottom-gate field effect transistor.

[0014] More specifically, the ferroelectric FET 20 is a metal ferroelectric semiconductor FET (MFSFET). The semiconductor substrate 1 is made of, for example, silicon (Si), and aluminum oxide (Al ２ O ３ A passivation film 1a of platinum (Pt) is formed on the passivation film 1a. The gate electrode 2 is formed in a predetermined pattern on the passivation film 1a using platinum (Pt). The gate insulating film is formed of a ferroelectric film 4 (Ce:HfO ２ The channel formation film 5a is made of, for example, an ITO film doped with Zr (Zr:ITO). In the ferroelectric FET 20, a drain electrode 6 and a source electrode 7 are formed of platinum (Pt) in a predetermined pattern on the channel formation film 5a.

[0015] The paraelectric FET 30 has a channel forming film 5b (second semiconductor film), a drain electrode 9 (second drain electrode), a source electrode 10 (second source electrode), an insulating film 12 (gate insulating film), and a gate electrode 13 (second gate electrode). In the paraelectric FET 30 shown in Fig. 1, the channel forming film 5b is formed on the ferroelectric film 4, and the drain electrode 9 and the source electrode 10 are formed thereon, respectively, and further the insulating film 12 and the gate electrode 13 are formed in this order. In other words, the paraelectric FET 30 is a top-gate type field effect transistor. The insulating film 12 is a paraelectric film.

[0016] More specifically, the paraelectric FET 30 is a MISFET (Metal Insulator Semiconductor FET). The paraelectric FET 30 is formed on a ferroelectric film 4. A channel formation film 5b is formed on the ferroelectric film 4, for example, using an ITO film with Zr added (Zr:ITO). The channel formation film 5b is made of the same material as the channel formation film 5a and is formed as a single film common to the channel formation film 5a. However, the channel formation film 5b may be made of a different material from the channel formation film 5a, or may be formed as a film different from the channel formation film 5a. Furthermore, although the channel formation film 5a and the channel formation film 5b are separate in the oscillator 100 shown in FIG. 1, the channel formation film 5a and the channel formation film 5b may be connected.

[0017] In the paraelectric FET 30, a drain electrode 9 and a source electrode 10 are formed of platinum (Pt) in a predetermined pattern on the channel forming film 5b. The gate insulating film is made of, for example, aluminum oxide (Al ２ O ３ ) is used as an insulating film 12. The gate electrode 13 is formed in a predetermined pattern on the insulating film 12 using platinum (Pt). The insulating film 12 (paraelectric film) not only covers the drain electrode 9, the source electrode 10, and the channel formation film 5b, but also covers the drain electrode 6, the source electrode 7, and the channel formation film 5a. Therefore, the insulating film 12 functions as a gate insulating film in the paraelectric FET 30, but also functions as a passivation film that protects the channel formation film 5a in the ferroelectric FET 20. Since the insulating film 12 is formed on the channel formation film 5a, it is preferable to form the insulating film 12 using a film formation method that does not generate plasma so as not to damage the channel formation film 5a when forming the insulating film 12.

[0018] The capacitor 40 includes an electrode 3 (first electrode) electrically connected to the source electrode 7, and an electrode 11 (second electrode) facing the electrode 3 via a ferroelectric film 4 and electrically connected to the source electrode 10. The capacitor 40 has a configuration in which the ferroelectric film 4 is sandwiched between the electrodes 3 and 11, but may also have a configuration in which at least one of the ferroelectric film 4 and an insulating film 12 (paraelectric film) is sandwiched between the electrodes 3 and 11. Note that the ferroelectric film 4 has a higher dielectric constant than the insulating film 12, so the area of ​​the capacitor 40 can be reduced. Specifically, when a hafnium-based ferroelectric film (dielectric constant: approximately 30) is used as a ferroelectric film between the electrodes 3 and 11, the area of ​​the capacitor 40 can be reduced to approximately 1 / 7.5 times that of when a silicon dioxide paraelectric film (dielectric constant: approximately 4) is used between the electrodes 3 and 11, assuming the same film thickness.

[0019] The electrode 3 is formed on the passivation film 1a using platinum (Pt) in a predetermined pattern. The electrode 3 may be formed in the same process as the gate electrode 2. The electrode 3 has a via conductor 8 provided in the ferroelectric film 4 to electrically connect to the source electrode 7. The electrode 11 is formed on the ferroelectric film 4 using platinum (Pt) in a predetermined pattern. The electrode 11 may be formed in the same process as the drain electrodes 6, 9 and the source electrodes 7, 10. The electrode 11 may be formed in part or in whole on the channel formation film 5b.

[0020] As shown in FIG. 2, the oscillator 100 applies a power supply voltage V ＤＤ is supplied to the drain electrode 6 of the ferroelectric FET 20, and the source electrode of the ferroelectric FET 20 is electrically connected to the drain electrode of the paraelectric FET 30. Therefore, the power supply voltage V ＤＤ is supplied to the source electrode 7 and the drain electrode 9, and the source electrode 7 and the drain electrode 9 are electrically connected to each other.

[0021] 2, the oscillator 100 has the source electrode of the ferroelectric FET 20 electrically connected to one electrode of the capacitor 40, and the other electrode electrically connected to the source electrode of the paraelectric FET 30 via GND. Therefore, the electrode 3 of the capacitor 40 is electrically connected to the source electrode 7 shown in FIG. 1, and the source electrode 10 and the electrode 11 of the capacitor 40 are electrically connected to GND.

[0022] Next, the operation of the oscillator 100 will be described. Fig. 3 is a diagram for explaining the operation of the oscillator 100 according to the embodiment. Fig. 3(a) shows the current I Ｄ and the output voltage V of the oscillator 100 Ｓ 3(b) is a graph showing the relationship between the output voltage V of the oscillator 100 and time t, with the vertical axis representing the current and the horizontal axis representing the voltage. Ｓ This is a graph showing the change in voltage, with the vertical axis being voltage and the horizontal axis being time.

[0023] In FIG. 3, the power supply voltage V ＤＤ , the gate voltage V of the paraelectric FET 30 ＧＭ , the capacitance of the capacitor 40 is C, and the gate voltage of the ferroelectric FET 20 is V ＧＦ V ＧＦ１ , V ＧＦ２ (V ＧＦ１ <V ＧＦ２ ) and waveforms (schematic diagrams) when the

[0024] The oscillator 100 generates a current I as shown in FIG. Ｄ and output voltage V Ｓ The relationship between the gate voltage V and the gate capacitance is a hysteresis curve. ＧＦ As the output voltage V Ｓ Specifically, the gate voltage V ＧＦ V ＧＦ１ In this case, the current I Ｄ flows through the drain electrode and source electrode of the ferroelectric FET 20 to the capacitor 40, charging the capacitor 40 and generating an output voltage V Ｓ The current I Ｄ is the output voltage V Ｓ As the current increases, it becomes difficult to flow, and the output voltage VＳ Furthermore, the output voltage V Ｓ V ｔ１ At point B, a current I flows between the drain electrode and the source electrode of the ferroelectric FET 20. Ｄ stops flowing (point C). Current I Ｄ When the current stops flowing, the capacitor 40 is discharged and the output voltage V Ｓ V ｔ２ (point D). The output voltage V Ｓ V ｔ２ When the current drops to I Ｄ begins to flow, and at point E, charging of the capacitor 40 begins, and the output voltage V Ｓ rises.

[0025] In this way, the gate voltage V ＧＦ V ＧＦ１ In this case, the current I Ｄ and output voltage V Ｓ As a result, the oscillator 100 generates a hysteresis curve from point B to point E, as shown in FIG. Ｓ V ｔ１ The state where (point B, point C) and the output voltage V Ｓ V ｔ２ In other words, the oscillator 100 repeats the state where the output voltage V Ｓ V ｔ１ and V ｔ２ The oscillating signal is output.

[0026] On the other hand, the gate voltage V ＧＦ V ＧＦ２ In this case, a current I flows between the drain electrode and the source electrode of the ferroelectric FET 20. Ｄ Before the current I stops flowing (point P), the current I flows between the drain electrode and the source electrode of the paraelectric FET 30. Ｍ Therefore, the oscillator 100 operates at a gate voltage V ＧＦ V ＧＦ１ In this case, there is no oscillation and the output voltage V Ｓ V Ｐ It outputs a signal that is a constant voltage.

[0027] Next, a manufacturing method of the oscillator 100 will be described with reference to the drawings. FIGS. 4 to 6 are cross-sectional views for explaining a manufacturing method of the oscillator 100 according to the embodiment. First, in FIG. 4( a), a platinum (Pt) gate electrode 2 and electrode 3 are formed on one surface of a prepared silicon (Si) semiconductor substrate 1. Note that in FIGS. 4 to 6, the left side of the figure is the region where the capacitor 40 is formed, and the right side of the figure is the region where the ferroelectric FET 20 and paraelectric FET 30 are formed. Also, although the gate electrode 2 and electrode 3 are formed directly on the semiconductor substrate 1, a passivation film 1a may be provided on the semiconductor substrate 1, and the gate electrode 2 and electrode 3 may be formed on the passivation film 1a.

[0028] Specifically, when forming the gate electrode 2 and the electrode 3, first, a photoresist having a predetermined pattern is formed using photolithography technology on one surface of the semiconductor substrate 1. Thereafter, for example, a platinum (Pt) film is formed on one surface of the semiconductor substrate 1 by radio frequency (RF) sputtering, and the photoresist is removed by lift-off, thereby forming the gate electrode 2 and the electrode 3.

[0029] 4B, a ferroelectric film 4 is formed on the surface of the semiconductor substrate 1 on which the gate electrode 2 and the electrode 3 are formed. The ferroelectric film 4 on the gate electrode 2 constitutes the gate insulating film of the ferroelectric FET 20, and the ferroelectric film 4 on the electrode 3 constitutes the insulator of the capacitor 40. Specifically, the ferroelectric film 4 is formed by depositing Ce:HfO ２ A film is formed.

[0030] 4C, in the region where the capacitor 40 is to be formed, a via hole 4a is formed in the ferroelectric film 4 on the electrode 3. Specifically, a photoresist having a predetermined pattern is formed on the ferroelectric film 4 using photolithography, and the ferroelectric film 4 is removed by dry etching to form the via hole 4a.

[0031] 5(a), a channel formation film 5 (including the channel formation films 5a and 5b shown in FIG. 1) is formed on the ferroelectric film 4 in the region where the ferroelectric FET 20 and the paraelectric FET 30 are to be formed. Specifically, the channel formation film 5 is formed by depositing an ITO film on the ferroelectric film 4 using sputtering. Note that, in FIG. 5(a), the channel formation film 5 is formed only in the region where the ferroelectric FET 20 and the paraelectric FET 30 are to be formed, but the channel formation film 5 may also be formed in the region where the capacitor 40 is to be formed.

[0032] 5(b), in the region where the ferroelectric FET 20 and the paraelectric FET 30 are to be formed, platinum (Pt) drain electrodes 6 and 9 and source electrodes 7 and 10 are formed on the channel formation film 5. Also, in the region where the capacitor 40 is to be formed, platinum (Pt) electrodes 7a and 11 are formed on the ferroelectric film 4, and a platinum (Pt) via conductor 8 is formed in the via hole 4a. The electrode 7a is electrically connected to the via conductor 8 and the electrode 3, and is a portion that electrically connects the via conductor 8 and the electrode 3 to the source electrode 7 and the drain electrode 9.

[0033] Specifically, when forming the drain electrodes 6 and 9 and the source electrodes 7 and 10, first, a photoresist having a predetermined pattern is formed on the channel formation film 5 using photolithography. Then, for example, a platinum (Pt) film is formed by radio frequency (RF) sputtering, and the photoresist is removed by lift-off, thereby forming the drain electrodes 6 and 9 and the source electrodes 7 and 10. Note that in FIG. 5B , the source electrode 7 and the drain electrode 9 are electrically connected, and are therefore illustrated as a single electrode. When forming the electrodes 7a and 11 and the via hole 4a, first, a photoresist having a predetermined pattern is formed on the ferroelectric film 4 using photolithography. Then, for example, a platinum (Pt) film is formed by radio frequency (RF) sputtering, and the photoresist is removed by lift-off, thereby forming the electrodes 7a and 11 and the via hole 4a.

[0034] 6A, in the region where the ferroelectric FET 20 and the paraelectric FET 30 are to be formed, an insulating film 12 is formed over the channel forming film 5 on which the drain electrodes 6 and 9 and the source electrodes 7 and 10 are formed. Also, in the region where the capacitor 40 is to be formed, the insulating film 12 is formed over the ferroelectric film 4 on which the electrodes 7a and 11 are formed. Specifically, the insulating film 12 is formed by, for example, depositing Al by ECR (Electron Cyclotron Resonance) sputtering, which is a film forming method that does not generate plasma. ２ O ３ By forming the insulating film 12 on the channel formation film 5 by a film formation method that does not generate plasma, the insulating film 12 can be formed without damaging the channel formation film 5.

[0035] 6B, a platinum (Pt) gate electrode 13 is formed on the insulating film 12 that covers the drain electrode 9 and the source electrode 10. Specifically, when forming the gate electrode 13, first, a photoresist having a predetermined pattern is formed on the insulating film 12 using photolithography. Thereafter, for example, a platinum (Pt) film is formed by radio frequency (RF) sputtering, and the photoresist is removed by lift-off, thereby forming the gate electrode 13.

[0036] As explained in FIGS. 4 to 6 , the oscillator 100 has a configuration in which three elements, the ferroelectric FET 20, the paraelectric FET 30, and the capacitor 40, can be simultaneously formed on the same semiconductor substrate 1 using a common material. In particular, the insulating film 12 functions as a passivation film that protects the channel portion of the bottom-gate type ferroelectric FET 20, and also functions as a gate insulating film for the top-gate type paraelectric FET 30. Furthermore, the ferroelectric film 4 functions as a gate insulating film for the ferroelectric FET 20, and also functions as an insulator for the capacitor 40. Therefore, in the oscillator 100, the ferroelectric FET 20 includes a ferroelectric film 4 formed to cover the gate electrode 2, and the paraelectric FET 30 includes an insulating film 12 formed to cover the channel formation film 5b formed on the ferroelectric film 4, and a gate electrode 13 formed on the insulating film 12, thereby making it possible to reduce the size and manufacturing costs.

[0037] The oscillator 100 is a film in which part of Hf in hafnium oxide is replaced with Ce (Ce:HfO ２ In this example, a ferroelectric film 4 made of a metal oxide and a channel formation film 5 (5a) made of a metal oxide are used, and an ITO film (Zr:ITO) with Zr added thereto is used as the channel formation film 5 (5a) is used. By combining the ferroelectric film 4 made of a metal oxide and the channel formation film 5 (5a) made of a metal oxide in this way, high interface quality can be obtained at the interface between the ferroelectric film 4 and the channel formation film 5 (5a).

[0038] The material used for the ferroelectric film 4 is a film in which part of the Hf in hafnium oxide is replaced with Ce (Ce:HfO ２ ), but this is merely an example and is not limiting. For example, the ferroelectric film 4 may be a hafnium oxide-based ferroelectric or BIT (Bi ４ Ti ３ O １２ ) or a laminated film including these films. More specifically, the material used for the ferroelectric film 4 is a hafnium oxide-based ferroelectric (Ce:HfO ２ , Hf ０．５ Zr ０．５ O ２ , La:HfO２ , Si:HfO ２ , Gd:HfO ２ etc.), PZT (Pb(Zr Ｘ , Ti １－Ｘ ) O ３ ), BLT (Bi ４－Ｘ La Ｘ Ti ３ O １２ ), SBT (SrBi ２ Ta ２ O ９ ), BFO (BiFeO ３ ), or BIT (Bi ４ Ti ３ O １２ ) or a laminated film including such a film.

[0039] Although the material used for the channel formation film 5 (5a, 5b) has been described as an ITO film with added Zr (Zr:ITO), this is merely an example and is not intended to be limiting. For example, the material used for the channel formation film 5 (5a, 5b) may be indium tin oxide (ITO), LSCO (La Ｘ Sr １－Ｘ CuO ４ ), tin oxide (SnO Ｘ ), zinc oxide (ZnO Ｘ ), indium oxide (InO Ｘ ), indium gallium zinc oxide (InGaZnO), or indium tin zinc oxide (InSnZnO), or a laminated film including these films may be used.

[0040] The material used for the insulating film 12 is aluminum oxide (Al ２ O ３ However, this is merely an example and is not limiting. For example, the material used for the insulating film 12 may be silicon oxide (SiO ２ ), silicon nitride (SiN), hafnium oxide (HfO ２ ), or Parylene C (polymer coating film), or a laminated film containing these films.

[0041] Although the material used for the gate electrodes 2 and 13, the drain electrodes 6 and 9, the source electrodes 7 and 10, and the electrodes 3, 7a, and 11 has been described as platinum (Pt), this is an example and is not limiting. For example, the material used for the gate electrodes 2 and 13, the drain electrodes 6 and 9, the source electrodes 7 and 10, and the electrodes 3, 7a, and 11 may be iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), iridium oxide (IrO Ｘ ) or lanthanum nickel oxide (LaNiO Ｘ ) or a laminated film including such a film.

[0042] A device 200 (information processing device) directly equipped with a function for performing AI processing using the oscillator 100 described above will be described. FIG. 7 is a schematic diagram of the device 200 using the oscillator 100 according to the embodiment. The device 200 does not access the cloud to perform AI processing, but performs AI processing independently. The device 200 has a neural network within it in order to perform AI processing independently.

[0043] The neural network includes an input layer 201 that accepts input of data (information), an intermediate layer 202 that processes the data, and an output layer 203 that outputs the data. In device 200, in order to achieve low power consumption and high speed, AI processing is not performed entirely by software, but rather the intermediate layer 202 is configured and processed by hardware. Although not shown, device 200 also has a computing unit that processes the software portion of the neural network. The computing unit is configured by a processor such as a CPU, MPU, TPU, or GPU, or a hardwired circuit such as an ASIC or FPGA.

[0044] Specifically, the intermediate layer 202 is configured by hardware, and each node 210 has the oscillator 100 shown in Fig. 1. Each node 210 may be provided with not only the oscillator 100 but also a storage means, for example, at the preceding stage.

[0045] In a neural network, data is input to the input layer 201 and is multiplied by a predetermined weight. The value output from the input layer 201 is input to the intermediate layer 202 and is further multiplied by a predetermined weight. The value output from the intermediate layer 202 is AI-processed and output as data (e.g., an estimation result) via the output layer 203. As described above, the intermediate layer 202 is configured by hardware having the oscillator 100, and therefore the weight at each node 210 is fixed.

[0046] However, because the input layer 201 and the output layer 203 are configured by software, it is possible to update the weights in the portion from the intermediate layer 202 to the output layer 203, for example. In a neural network, by updating the weights in the portion from the intermediate layer 202 to the output layer 203, the computational accuracy of AI processing is ensured while the software calculation load is significantly reduced, realizing power saving and high speed.

[0047] For example, when an inference result is obtained from data using device 200, training data to be used for training a neural network is prepared. The neural network is trained, for example, by supervised learning. In Fig. 7, training data including ground truth data is prepared, and the neural network adjusts the weights of the portion from intermediate layer 202 to output layer 203 based on the degree of agreement between the inference result calculated from the training data and the ground truth data, thereby training so that the degree of agreement between the inference result estimated by itself and the ground truth data exceeds a reference value.

[0048] (Aspects) (1) An oscillator according to the present disclosure comprises: a substrate; a first field effect transistor formed on the substrate and using a ferroelectric as a gate insulating film; a second field effect transistor formed on the substrate and using a paraelectric as a gate insulating film; and a capacitor formed on the substrate, wherein the first field effect transistor includes: a first gate electrode; a ferroelectric film formed to cover the first gate electrode; a first semiconductor film forming a first channel layer formed on the ferroelectric film; a first source electrode and a first drain electrode formed on the first semiconductor film; the second field effect transistor includes: a second semiconductor film forming a second channel layer formed on the ferroelectric film; a second source electrode and a second drain electrode formed on the second semiconductor film; a paraelectric film formed to cover the second source electrode, the second drain electrode, and the second semiconductor film; and a second gate electrode formed on the paraelectric film, wherein the paraelectric film is formed to further cover the first source electrode, the first drain electrode, and the first semiconductor film; and the capacitor includes: The semiconductor device includes a first electrode electrically connected to the first source electrode, and a second electrode facing the first electrode via at least one of a ferroelectric film and a paraelectric film and electrically connected to the second source electrode, wherein the first source electrode is electrically connected to the second drain electrode.

[0049] (2) In the oscillator described in (1), the second semiconductor film is made of the same material as the first semiconductor film.

[0050] (3) In the oscillator according to (2), the second semiconductor film is formed as a single film common to the first semiconductor film.

[0051] (4) In the oscillator according to any one of (1) to (3), the capacitor has a first electrode and a second electrode facing each other with a ferroelectric film interposed therebetween.

[0052] (5) In the oscillator according to any one of (1) to (4), the ferroelectric film is a hafnium oxide-based ferroelectric or BIT (Bi ４ Ti ３ O １２) or a laminated film including these films.

[0053] (6) A method for manufacturing an oscillator according to the present disclosure is a method for manufacturing an oscillator including a substrate, a first field effect transistor formed on the substrate and having a ferroelectric film as a gate insulating film, a second field effect transistor formed on the substrate and having a paraelectric film as a gate insulating film, and a capacitor formed on the substrate, the method comprising the steps of: forming a first gate electrode of the first field effect transistor and a first electrode of the capacitor on the substrate; forming a ferroelectric film covering the first gate electrode and the first electrode; forming a via in the ferroelectric film reaching the first electrode; forming a first semiconductor film on the ferroelectric film to form a first channel layer of the first field effect transistor; forming a second semiconductor film on the ferroelectric film to form a second channel layer of the second field effect transistor; and forming a first source electrode and a first drain electrode of the first field effect transistor on the first semiconductor film, a second source electrode and a second drain electrode of the second field effect transistor on the second semiconductor film, a second electrode of the capacitor on the ferroelectric film, and forming via conductors in the vias to electrically connect the first electrode and the first source electrode. forming a paraelectric film covering the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, the second electrode, the first semiconductor film, and the second semiconductor film; and forming a second gate electrode of the second field effect transistor on the paraelectric film.

[0054] (7) In the method for manufacturing an oscillator according to (6), the first semiconductor film and the second semiconductor film are formed in the same film formation process.

[0055] (8) In the method for manufacturing an oscillator according to (6) or (7), the step of forming the paraelectric film forms the paraelectric film by a film formation method that does not generate plasma.

[0056] (9) An information processing device according to the present disclosure is an information processing device that processes information using a neural network, the neural network including an input layer, an intermediate layer, and an output layer, the intermediate layer being configured with hardware, and each node having an oscillator described in any one of (1) to (5).

[0057] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0058] 1 semiconductor substrate, 1a passivation film, 2, 13 gate electrode, 3, 7a, 11 electrode, 4 ferroelectric film, 4a via hole, 5, 5a, 5b channel forming film, 6, 9 drain electrode, 7, 10 source electrode, 8 via conductor, 12 insulating film, 20 ferroelectric FET, 30 paraelectric FET, 40 capacitor, 100 oscillator.

Claims

1. A substrate, a first field-effect transistor formed on the substrate and having a ferroelectric as a gate insulating film, a second field-effect transistor formed on the substrate and having a paraelectric as a gate insulating film, and a capacitor formed on the substrate, wherein the first field-effect transistor includes a first gate electrode, a ferroelectric film formed to cover the first gate electrode, a first semiconductor film that forms a first channel layer formed on the ferroelectric film, and a first source electrode and a first drain electrode formed on the first semiconductor film; the second field-effect transistor includes a second semiconductor film that forms a second channel layer formed on the ferroelectric film, a second source electrode and a second drain electrode formed on the second semiconductor film, a paraelectric film formed to cover the second source electrode, the second drain electrode, and the second semiconductor film, and a second gate electrode formed on the paraelectric film; the paraelectric film is further formed to cover the first source electrode, the first drain electrode, and the first semiconductor film; the capacitor includes a first electrode electrically connected to the first source electrode, and a second electrode that faces the first electrode through at least one of the ferroelectric film and the paraelectric film and is electrically connected to the second source electrode; and the first source electrode is electrically connected to the second drain electrode, an oscillator.

2. The oscillator according to claim 1, wherein the second semiconductor film is made of the same material as the first semiconductor film.

3. The oscillator according to claim 2, wherein the second semiconductor film is formed as one common film with the first semiconductor film.

4. The oscillator according to any one of claims 1 to 3, wherein the first electrode and the second electrode of the capacitor face each other through the ferroelectric film.

5. The ferroelectric film is a hafnium oxide-based ferroelectric, or a film composed of BIT (Bi ４ Ti ３ O １２ ), or a laminated film containing those films. The oscillator according to any one of claims 1 to 4.

6. A method of manufacturing an oscillator including a substrate, a first field-effect transistor formed on the substrate and having a ferroelectric as a gate insulating film, a second field-effect transistor formed on the substrate and having a paraelectric as a gate insulating film, and a capacitor formed on the substrate, the method comprising: forming a first gate electrode of the first field-effect transistor and a first electrode of the capacitor on the substrate; forming a ferroelectric film covering the first gate electrode and the first electrode; forming a via reaching the first electrode in the ferroelectric film; forming a first semiconductor film for forming a first channel layer of the first field-effect transistor on the ferroelectric film; forming a second semiconductor film for forming a second channel layer of the second field-effect transistor on the ferroelectric film; forming a first source electrode and a first drain electrode of the first field-effect transistor on the first semiconductor film, a second source electrode and a second drain electrode of the second field-effect transistor on the second semiconductor film, a second electrode of the capacitor on the ferroelectric film, and a via conductor electrically connecting the first electrode and the first source electrode to the via; forming a paraelectric film covering the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, the second electrode, the first semiconductor film, and the second semiconductor film; and forming a second gate electrode of the second field-effect transistor on the paraelectric film.

7. The method of manufacturing an oscillator according to claim 6, wherein the first semiconductor film and the second semiconductor film are formed by the same film formation process.

8. The method of manufacturing an oscillator according to claim 6 or 7, wherein the step of forming the paraelectric film forms the paraelectric film by a film formation method that does not generate plasma.

9. An information processing apparatus that processes information using a neural network, the neural network including an input layer, an intermediate layer, and an output layer, wherein the intermediate layer is configured by hardware and each node has an oscillator according to any one of claims 1 to 5.

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