54 results about "Ferroelectric crystal" patented technology

The application discloses a method for preparing a ferroelectric crystal optical superlattice by using a pyroelectric effect, a superlattice and application, and belongs to the field of electronic and optical devices. The method comprises the following steps: preparing a ferroelectric crystal material carrying an electrode pattern; heating the ferroelectric crystal material carrying the electrode pattern, and the heating temperature is 50-200 DEG C; in the temperature range, the ferroelectric crystal material carrying the electrode pattern is excited in the reverse direction of polarization by using the pyroelectric property of the ferroelectric crystal material itself; then, an annealing step is performed, and the annealing rate is 50-150 DEG C / h; after 1-10 times of heating and annealing cycles, the superlattice is obtained. The application breaks through the limitation of the external electric field polarization method for different electrode structures by creating a new polarization process, realizes the preparation of different superlattice crystals based on various structure electrodes, and further expands the application scenarios and application fields of the ferroelectric crystal material.

This application discloses a method and device for fabricating a periodically polarized ultrathin lithium niobate / lithium tantalate device, belonging to the field of nonlinear optical device manufacturing. The method includes: fabricating and polarizing periodic electrodes on a provided ferroelectric crystal wafer to form a periodically polarized master wafer; bonding the master wafer to a carrier substrate using optical resin-assisted bonding or direct bonding to form a composite structure; thinning and polishing the side of the master wafer away from the carrier substrate to obtain an ultrathin periodically polarized crystal functional layer; and fabricating the structure of the ultrathin periodically polarized crystal functional layer to obtain a periodically polarized ultrathin lithium niobate / lithium tantalate device. This method avoids the inherent problems of high-voltage breakdown and poor domain quality in existing technologies when directly polarizing ultrathin crystals by placing the high-risk polarization step on a thick, stable wafer.

The application relates to the technical field of semiconductors, and provides a logic operation method and device based on a ferroelectric transistor and electronic equipment, the logic operation method based on the ferroelectric transistor comprises the following steps: obtaining an operation instruction to be executed, the operation instruction comprising input variables and the type of the logic operation to be executed; determining an assignment relationship between the input variables and logic variables of a target logic gate according to the working principle of the target logic gate and the type of the logic operation to be executed, wherein the target logic gate comprises at least one ferroelectric transistor; assigning the values of the input variables to the logic variables according to the assignment relationship; controlling the ferroelectric transistor to execute the logic operation according to the logic variables, and storing the result of the logic operation in situ by using the polarization state of the ferroelectric transistor. The method realizes the integration of storage and calculation based on the Boolean logic gate of the ferroelectric transistor, breaks through the limitations of the storage wall and the power consumption wall, and improves the flexibility of the Boolean logic gate of the ferroelectric transistor when performing the logic operation.

Disclosed in the present invention is a domain wall straightening method for a periodically poled ferroelectric crystal. In the present invention, by means of testing a piezoelectric coefficient of a poled sample, the poling situation of the sample can be non-destructively determined, and regions with uniform poling can be selected; moreover, whether to continue poling or terminate poling and restart poling after single-domain formation can be determined on the basis of a duty cycle calculation result; and the straightness of domain walls is determined on the basis of the variation of the piezoelectric coefficient, such that the magnitude and duration of a poling voltage are adjusted in a timely manner, thereby accurately controlling a poling process, and thus obtaining a high-quality periodically poled crystal.

The application belongs to the technical field of organic semiconductor electronic devices, and discloses a flexible threshold value adjustable negative capacitance transistor and a preparation method, and a small logic circuit. The flexible threshold value adjustable negative capacitance transistor comprises a flexible substrate, an organic semiconductor layer, an organic dielectric layer, a source-drain electrode and two gate electrodes. The preparation method is as follows: a bottom gate electrode is prepared on the surface of the flexible substrate and an organic ferroelectric film is spin-coated; an organic polymer film is spin-coated on the surface of the organic dielectric layer as a semiconductor channel layer; a source / drain metal electrode is prepared; finally, an organic ferroelectric film is spin-coated and a top gate electrode is prepared. The application utilizes the negative capacitance principle of the organic ferroelectric transistor to reduce the working voltage and power consumption, and the double-gate structure is made to make the threshold voltage of the transistor adjustable, which has a great effect in the flexible logic circuit based on the unipolar device.

Memory device with series-connected ferroelectric transistor and capacitor, associated electronic circuit, programming method and reading method. The present invention relates to a memory device (14) comprising: - a ferroelectric field-effect transistor (20) having a gate electrode (21) and first (22) and second (23) conduction electrodes; - a ferroelectric capacitor (25) having first (27) and second (28) charge electrodes; the transistor (20) and the ferroelectric capacitor (25) being connected according to a first connection configuration (C1) in which the first conduction electrode (22) is connected to a reference potential (GND) and the second conduction electrode (23) is connected to the first charge electrode (27);or according to a second connection configuration in which the first conduction electrode (22) is connected to the first charging electrode (27) and the second conduction electrode (23) is connected to the second charging electrode (28). Figure for the abbreviation: Figure 2;

The invention relates to an embedded low-voltage nano-gate ferroelectric transistor structure and a preparation method thereof, and relates to the field of memory devices, the embedded low-voltage nano-gate ferroelectric transistor structure comprises a silicon-based CMOS logic circuit, the silicon-based CMOS logic circuit is provided with a first insulating dielectric layer and a plurality of horizontally arranged nano-gate ferroelectric transistors, a second insulating medium layer is arranged between every two adjacent nano-gate ferroelectric transistors; the nanometer gate ferroelectric transistor comprises a gate metal interconnection, a third insulating dielectric layer, a ferroelectric layer, a metal floating gate, a gate dielectric layer, a channel material layer and a source and drain electrode which are arranged from bottom to top, and the bottom of the gate metal interconnection is connected with the silicon-based CMOS logic circuit through a connecting line penetrating through the first insulating dielectric layer; metal nano-gates are vertically arranged on the two sides of the gate metal interconnection and the third insulating dielectric layer, the tops of the metal nano-gates are in contact with the ferroelectric layer, and side walls are arranged between the metal nano-gates and the second insulating dielectric layer. According to the invention, ultra-low power consumption edge computing application can be met, and storage and computing integrated operation is supported.

The invention provides a PVDF-based elastic ferroelectric material and a preparation method and application thereof, and relates to the technical field of ferroelectric materials. A ferroelectric crystal phase region of the PVDF-based elastic ferroelectric material is protected to the maximum extent, and a uniform three-dimensional elastic network structure formed by firm C-C bonds is constructed in an amorphous region by a PVDF-based ferroelectric polymer and a crosslinking sensitizer through radiation crosslinking; the PVDF-based elastic ferroelectric material has excellent ferroelectricity, great flexibility and elasticity, proper strength and excellent fatigue resistance at the same time. According to the preparation method of the PVDF-based elastic ferroelectric material, the technical bottlenecks of thermal crosslinking and photo-crosslinking are fundamentally overcome through a mild, pure and uniform radiation process, so that controllable preparation of the PVDF-based elastic ferroelectric material with excellent ferroelectricity, great flexibility and elasticity, proper strength and excellent fatigue resistance becomes reality; the preparation method is simple, efficient and high in universality, and is very suitable for large-scale industrial production.

The application discloses a transparent ferroelectric transistor and a preparation method thereof, and relates to the technical field of electronic devices, which comprises a substrate, a gate electrode arranged on the upper surface of the substrate, a metal oxide interlayer arranged on the upper surface of the gate electrode, a metal interlayer arranged on the upper surface of the metal oxide interlayer, wherein the metal interlayer is made of at least one of Ti, Ni or Cr elements, a ferroelectric layer arranged on the upper surface of the metal interlayer, an insulating layer arranged on the upper surface of the ferroelectric layer, a drain electrode and a source electrode arranged on the left and right ends of the upper surface of the insulating layer respectively, and the substrate, the gate electrode, the insulating layer, the drain electrode and the source electrode are all transparent materials; the transparent ferroelectric transistor provided by the application can guarantee a high ferroelectric polarization strength under the condition that the annealing temperature is not more than 400 DEG C.

The invention discloses a method for calculating the potential of an intermediate node of a ferroelectric transistor. The method comprises the following steps: according to a charge conservation relationship between a gate oxide layer and a semiconductor part in the ferroelectric transistor, determining a first function relationship between an intermediate node potential and a channel average surface potential under the condition of averaging a channel potential; determining a second function relationship among the average surface potential of the channel, the potential of the intermediate node, the voltage of the grid electrode, the voltage of the source electrode, the voltage of the drain electrode, the ferroelectric polarization state and the defect occupancy state by combining the charge conservation relationship of the ferroelectric layer; and on the basis of the second function relationship and by utilizing the first function relationship elimination, calculating the channel average surface potential and the intermediate node potential. According to the application, the potential of the middle node of the ferroelectric transistor can be quickly and accurately calculated, so that the direct-current conduction current of the channel of the ferroelectric transistor can be quickly calculated.

The application discloses a method for preparing a large-area two-dimensional indium selenide film crystal material based on a rapid cooling chemical vapor deposition method, and a product and application thereof, and relates to the technical field of two-dimensional material preparation. In the method, the vertical distance between a precursor and a substrate is about 3 millimeters or about 1 millimeter, and compared with a distance of more than 10 cm required by a traditional chemical vapor deposition method, the super-short transmission distance can provide a stable, uniform and continuous gas source supply on a growth substrate, so that a large-size indium selenide film is obtained. The two-dimensional indium selenide film prepared by the method has high electron mobility, high quality and a relatively wide band gap, and the beta prime and alpha phases have ferroelectric effects, so that the two-dimensional indium selenide film has a wide prospect in applications of ferroelectric transistors and photoelectric detectors.

The application belongs to the field of functional material preparation, and particularly relates to a Na and Ta co-doped potassium boron niobate antiferroelectric crystal material and a preparation and processing method thereof. 3‑x Na x Nb 3‑y Ta y B2O 12 , wherein x=0.05-0.45, y=0.05-0.5, the Na and Ta co-doped potassium boron niobate antiferroelectric crystal material has a dielectric coefficient increased from 9.85K to 11K at the time of gamma to beta phase transition, and Pmax is increased to 3 times of the original value; through optimization of crystal growth and processing technology, cleavage of the potassium boron niobate antiferroelectric crystal is obviously improved, and no obvious cleavage phenomenon occurs at a temperature of 600 DEG C.

Provided in the present invention is a capacitor-less non-volatile dynamic memory, comprising: a first transistor and a second transistor, wherein the first transistor is a vertical channel transistor, and the second transistor is a ferroelectric transistor; and the second transistor is located above the first transistor. In the 2T0C non-volatile dynamic memory provided in the present invention, one of the transistors is a ferroelectric transistor, such that the non-volatile dynamic random access memory obtained by introducing a ferroelectric material can solve the problems of storage density and energy consumption of a current dynamic random access memory, and can realize high-density and high-efficiency storage. In addition, in the manufacturing process for the other vertical channel transistor, a gate surrounding a channel is formed by means of metal induction, so that the gate control capability is stronger. The present invention realizes wafer-level three-dimensional integration, and has a higher integration density and lower costs compared with conventional semiconductor processes, thereby achieving wide application prospects.

The invention discloses a lead salt single crystal sensitized thin film, a preparation method thereof and application of the lead salt single crystal sensitized thin film in an infrared detector, and relates to the technical field of optoelectronic semiconductor materials. The preparation method of the lead salt single crystal sensitized thin film comprises the following steps: S1, growing a lead salt thin film on a substrate; s2, performing oxygen high-temperature pre-sensitization treatment on the lead salt thin film to form an oxygen-doped lead salt thin film; and S3, the oxygen-doped lead salt thin film reacts with iodine steam, a sensitized lead salt thin film is formed, and the lead salt single crystal sensitized thin film is obtained. The sensitized lead salt thin film prepared through the method has high black body photothermoelectric response, a 500 K black body can generate 1.2 * 10 < 4 > V / W responsivity, the photoelectric response of a lead salt device is improved, and the lead salt single crystal sensitized thin film prepared through the method is high in crystallization quality, low in defect density, uniform in surface and good in bonding stability with a PMN-PT ferroelectric crystal substrate.

Described herein is a method of fabricating a ferroelectric material, comprising the steps of: providing a semiconductor substrate; treating the semiconductor substrate with an oxidant to form an oxidized surface; depositing a metal on top of the oxidized surface to provide a film; and annealing the film at a temperature between 700°C and 900°C, thereby forming a metal oxide layer on top of the semiconductor substrate, wherein the interface between the semiconductor substrate and the metal oxide layer does not contain any remnant oxidized surface, and a ferroelectric material and a ferroelectric transistor or capacitor comprising said ferroelectric material.

Disclosed in the present application are a ferroelectric transistor cell supporting index-free sparse training, and in-memory computing hardware. The ferroelectric transistor cell comprises: a first non-volatile transistor, which comprises a first source electrode, a first drain electrode and a first gate electrode; a second non-volatile transistor, which comprises a second source electrode, a second drain electrode and a second gate electrode; a sparsity line, which is connected to the first gate electrode; a bit line, which is connected to the first source electrode; a data input line, which is connected to the second source electrode; and a data output line, which is connected to the second drain electrode, wherein the first drain electrode is connected to the second gate electrode, the first non-volatile transistor is used for controlling, on the basis of a signal of the sparsity line, the turning on / off of the second non-volatile transistor, and the second non-volatile transistor is used for weight update and data processing and storage. The present application realizes the in-situ storage of sparsity information, enabling the sparsity information to participate in a sparse training process together with weight information, thereby eliminating an external indexing process, and supporting sparse training involving any unstructured and any coarse-grained or fine-grained pruning, and thus realizing theoretical advantages in energy consumption and latency.

This invention relates to the field of semiconductor memory technology, providing a ferroelectric transistor device, its manufacturing method, and a non-volatile memory. The ferroelectric transistor device includes a substrate and a gate stack. The substrate is doped with source and drain regions, with a channel region between them. The gate stack is disposed on the channel region and includes alternating layers of multiple ferroelectric and dielectric layers. Multiple polarization domains are formed in the ferroelectric layers, with adjacent polarization domains separated by polarization domain walls. Heterogeneous interfaces are formed between adjacent ferroelectric and dielectric layers, and these interfaces form a stepped energy barrier distribution. When different programming voltages are applied to the top of the gate stack, the energy barrier distribution creates a pinning effect on the movement of the polarization domain walls, resulting in multiple distinguishable metastable states in the net polarization intensity distribution of the gate stack. Each metastable state corresponds to a threshold voltage of the ferroelectric transistor device. This invention provides a high-density, high-reliability non-volatile memory.

The application discloses a power-off data saving and recovery circuit, which comprises a ferroelectric transistor, a write control module, a data recovery module and a transmission gate. The data state input end of the write control module is connected with the data output end, the power supply association end is connected with the power supply end, and the gate control output end is connected with the gate of the ferroelectric transistor. The write control module comprises a first NMOS tube, the gate of which is used as the power supply association end, and the write enable moment is bound to the power voltage drop event. Before power-off, the first NMOS tube is turned on, and the resistance state of the ferroelectric transistor is kept; at the moment of power-off, the first NMOS tube is cut off, the gate charge of the ferroelectric transistor is locked as the charge corresponding to the input state before power-off, and the source voltage drops, so that the resistance state is changed or kept once according to the locked charge. After power-on again, the data recovery module recovers the output according to the saved state. The application only performs single write at the moment of power-off, and avoids the problem of poor durability of the ferroelectric transistor caused by frequent write.

The present application relates to a kind of multifunctional storage computing unit based on ferroelectric transistor, array and its fault-tolerant method.The unit is composed of two N-type FeFET and two NMOS transistor, by configuring peripheral control signal / circuit can realize three kinds of working mode: memory mode supports the non-volatile storage and read-write operation of data;Memory logic computing mode supports the Boolean logic operation to the storage word;Three-state content addressable memory mode supports high-speed parallel search and "irrelevant" bit matching operation.Further, the present application proposes a kind of anti-radiation reinforced three-state content addressable memory unit.The unit is based on the original multifunctional unit, access single-cycle storage module DICE and four storage transistors, realizes single node flip recovery.The present application integrates storage, computing and search function in single compact unit structure, improves energy efficiency and functional density, and the anti-radiation reinforced unit has good soft error tolerance ability and process robustness.

A memory device may include processing circuitry connected to a ferroelectric transistor through a word line and a bit line. The ferroelectric transistor may include an interfacial layer between a gate electrode and a semiconductor layer, and a ferroelectric layer between the interfacial layer and the gate electrode. The processing circuitry may be configured to perform an operation to reduce disturb in the ferroelectric transistor by applying a mitigation pulse to the gate electrode of the ferroelectric transistor using the word line and then applying a program pulse to the gate electrode of the ferroelectric transistor using the word line. The mitigation pulse and the program pulse may have opposite polarities. A level of the program pulse may be sufficient to program a desired program state in the ferroelectric transistor. A level of the mitigation pulse may be sufficient to detrap electrons in the ferroelectric transistor.

The invention discloses a high-performance large-size 1t; 111gt, 111gt; the invention relates to a c-oriented PST single crystal and a preparation method thereof, and belongs to the technical field of relaxor ferroelectric crystal materials, the preparation method comprises the following steps: filling PST-cosolvent mixed powder into a platinum crucible with a cover, compacting and sealing, putting the platinum crucible into a crystal growth furnace, and using a corundum crucible, the whole crystal growth process being an oxygen introduction mode; growing in a high-purity oxygen protection atmosphere at the temperature of 1220-1250 DEG C by adopting a cosolvent method, regulating and controlling the degree of supercooling through gradient cooling, and growing the pseudo-cubic PST crystal until the size is not smaller than a set size; the atmosphere in the furnace is switched into argon protection, and the temperature is reduced to the room temperature in a segmented gradient mode; performing staged ordered annealing treatment on the crystal to obtain an annealed pseudo-cubic PST crystal; performing cutting, crystal orientation, grinding and polishing on the annealed pseudo-cubic PST crystal in sequence to obtain 1t; 111gt, 111gt; c, orienting the PST single crystal; large-size growth is realized, and B-site ions are highly ordered; 111gt, 111gt; and c, coordinated regulation and control of accurate orientation acquisition.

This invention discloses a storage-computing-display driving array of sub-10 nanometer gate-length ferroelectric transistors and its fabrication method, relating to the field of display driving technology. The array structure includes a supporting substrate, vertical sub-10 nanometer gate-length ferroelectric transistors, and micro-light-emitting diodes (LEDs). The vertical sub-10 nanometer gate-length ferroelectric transistors serve as the driving units of the array, and the micro-LEDs serve as the light-emitting units. The light-emitting units and their corresponding driving units are directly stacked and integrated in the vertical direction. This invention natively integrates storage and computing functions into the display pixel unit, enabling in-situ data processing and feature extraction on the display module, thereby breaking through the physical bottleneck of data transport and opening up a new display strategy integrating storage, computing, and display.

The invention relates to the technical field of semiconductor storage, and provides a ferroelectric transistor device and a manufacturing method thereof, and a nonvolatile memory, the ferroelectric transistor device comprises a substrate and a gate stack; a source region and a drain region are doped in the substrate, and a channel region is arranged between the source region and the drain region; the gate stack is arranged on the channel region and comprises a plurality of ferroelectric layers and a plurality of dielectric layers which are alternately stacked; a plurality of polarization domains are formed in the ferroelectric layer, and the adjacent polarization domains are separated by polarization domain walls; heterogeneous interfaces are formed between the adjacent ferroelectric layers and dielectric layers, and the multiple heterogeneous interfaces are used for forming stepped energy barrier distribution; when different programming voltages are applied to the top end of the gate stack, the energy barrier distribution forms a pinning effect on the movement of the polarization domain wall, so that the net polarization intensity distribution of the gate stack forms a plurality of distinguishable metastable states; each metastable state corresponds to a threshold voltage of the ferroelectric transistor device. The invention is used for providing the nonvolatile memory with high density and high reliability.

The invention relates to a method for rapidly detecting microdefects of a ferroelectric crystal material based on reverse voltage pulses, which comprises the following steps of: preparing the ferroelectric crystal material to be detected, connecting an aluminum electrode on a + Z surface of the ferroelectric crystal material to be detected with a negative electrode of an external electric field, connecting an evaporation transparent indium tin oxide conductive layer on a-Z surface of the ferroelectric crystal material to be detected with a positive electrode of the external electric field, and placing in silicone oil; voltage pulse is applied, the condition of the to-be-detected ferroelectric crystal material is observed through the real-time monitoring device, the to-be-detected ferroelectric crystal material with point defects can be excited by reverse voltage and has contrast display in the real-time monitoring device, and the to-be-detected ferroelectric crystal material without point defects has no phenomenon in the real-time monitoring device after being excited by the reverse voltage. By adopting the method for detecting the microdefect of the ferroelectric crystal material by applying the reverse pulse, the quality of the wafer can be quickly detected in a lossless manner, and a high-quality ferroelectric crystal can be developed and guaranteed for subsequent crystal devices.

The invention discloses a ferroelectric transistor read-write method with high durability and high current reliability. A used ferroelectric transistor comprises a P-type doped semiconductor substrate, an N-type doped source electrode, a P-type doped drain electrode, a ferroelectric gate stack and a control gate. Corresponding level or floating operation is applied to the source electrode, the drain electrode and the control gate respectively in the write-in and read-out operation processes. The source electrode is floated in the writing process, so that excessive electron trapping is avoided, electrons required by ferroelectric flipping are provided by utilizing a band-to-band tunneling mechanism at the drain electrode, the increase of interface traps is reduced, and the durability is improved. In the read-out stage, the band-to-band tunneling current at the source electrode is used for reading out, and the current is not influenced by an interface state generated at the drain electrode in the writing process, so that excellent current reliability is obtained. The method does not involve the change of the gate stack material and structure of the ferroelectric transistor, does not need to introduce additional recovery cycle and corresponding area and delay cost, and is high in practical value.

The invention discloses a rhombohedral phase manganese-zirconium co-doped hafnium oxide ferroelectric film material and a preparation method thereof. The ferroelectric film material structure sequentially comprises a single crystal substrate layer, a bottom electrode layer and a ferroelectric material layer from bottom to top, wherein the ferroelectric material layer is composed of a single-layer uniform film, and the material forming the ferroelectric material layer is manganese-zirconium co-doped hafnium oxide with a ferroelectric stable rhombohedral phase structure. The preparation method comprises the following steps: annealing a single crystal substrate, and sequentially preparing the bottom electrode layer and the ferroelectric material layer on the annealed single crystal substrate layer by using a pulse laser deposition method. The stable rhombohedral phase is prepared, regulated and controlled in the hafnium oxide-based thin film for the first time through component and substrate stress design, and due to unique manganese-zirconium co-doping and stress conditions provided by the substrate, the ferroelectric phase structure can stably maintain the rhombohedral phase, so that the excellent stable ferroelectric performance can be maintained; and development and application of devices such as ferroelectric transistors and ferroelectric tunnel junctions mainly made of hafnium oxide ferroelectric materials are facilitated.

The application provides a ferroelectric transistor array for constructing a neural Turing machine and a preparation method thereof, and relates to the technical field of integrated circuits. The ferroelectric transistor array comprises a plurality of ferroelectric transistor units and interconnection lines, each ferroelectric transistor unit is formed by stacking a substrate, a semiconductor channel layer, an insulating layer, an intermediate metal layer, a ferroelectric layer and an upper gate electrode in sequence, and the plurality of ferroelectric transistor units form the ferroelectric transistor array through the interconnection lines. The ferroelectric transistor array outputs a multiply-accumulate result based on a voltage input by a source line and a multi-threshold state in a first calculation mode, and outputs a multiply-accumulate result based on a voltage input by a bit line and a multi-threshold state in a second calculation mode. The ferroelectric transistor array provided by the application can realize high-density, multi-threshold storage and in-memory calculation, support high-precision attention weight generation and memory access calculation of the neural Turing machine, and significantly improve the calculation efficiency and data reliability.

The invention discloses a spiking neuron circuit with temperature stability and a regulation and control method thereof, and relates to the technical field of semiconductors. According to the spiking neuron circuit, the drain electrode of a ferroelectric transistor FeFET is connected with a power supply, and the source electrode of the ferroelectric transistor FeFET is connected with the drain electrode of an MOSFET device; the source electrode of the MOSFET device is grounded; one end of the capacitor C is connected with the source electrode of the ferroelectric transistor FeFET and the drain electrode of the MOSFET device, and the other end of the capacitor C is grounded. The method comprises the following steps: introducing a carrier mobility temperature empirical model and a threshold voltage empirical model into a pre-constructed regulation and control model; by adjusting the grid voltage of the FeFET and the grid voltage of the MOSFET, the pulse neuron circuit and the emission frequency are independently controlled. The carrier mobility temperature empirical model and the threshold voltage empirical model are introduced, so that the functional stability of the whole spiking neuron circuit in a certain temperature range is ensured.

The application belongs to the technical field of microelectronic devices, and discloses an oxide semiconductor-based ferroelectric vertical transistor and a preparation method thereof.The ferroelectric vertical transistor comprises a substrate, a gate metal electrode, a gate ferroelectric layer, a gate insulating dielectric layer, an island-shaped source electrode, an oxide semiconductor, a source contact electrode and a top drain electrode.The application uses hafnium oxide-based ferroelectric material as the gate ferroelectric material, can realize information writing and reading, amplify the regulation effect of the gate voltage on the channel, reduce the ratio of the gate capacitance to the channel capacitance, reduce the working voltage of the transistor, and reduce the power consumption of the ferroelectric vertical transistor.In addition, a gate insulating dielectric layer is further prepared on the gate ferroelectric film to promote the formation of the ferroelectric phase, and the introduction of the insulating dielectric layer can inhibit the injection of charges, thereby adjusting the polarization state of the hafnium oxide-based ferroelectric material and improving the overall performance of the ferroelectric transistor.

A memory device including a ferroelectric field-effect transistor including a gate electrode and first and second conduction electrodes; a ferroelectric capacitor including first and second charge electrodes; the transistor and the ferroelectric capacitor being connected according to a first connection configuration, wherein the first conduction electrode is connected to a reference potential and the second conduction electrode is connected to the first charge electrode, or according to a second connection configuration, wherein the first conduction electrode is connected to the first charge electrode and the second conduction electrode is connected to the second charge electrode.