115 results about "Ferroelectric crystal" patented technology

The invention belongs to the technical field of semiconductor devices, and discloses a novel semiconductor nonvolatile memory and a preparation method and application thereof. The memory comprises a substrate, a bottom electrode, an amorphous oxide interface layer, a ferroelectric dielectric layer and a top electrode which are sequentially arranged from bottom to top, the preparation method comprises the steps of (1) cleaning the substrate, (2) depositing the bottom electrode, (3) forming the amorphous oxide interface layer, (4) depositing the ferroelectric medium layer, and forming the ultrathin ferroelectric medium layer with uniform composition and good ferroelectricity on the amorphous MoO3 interface layer, (5) patterning and depositing the top electrode, and (6) performing rapid thermal annealing treatment. The memory is applied to a three-dimensional stacked nonvolatile memory array or construction of a back gate type ferroelectric transistor structure. According to the invention, the formation of a non-ferroelectric phase is effectively inhibited, the preferred orientation arrangement of the ferroelectric phase is promoted, the polarization intensity is enhanced, and the ferroelectric performance of the device is improved. The material has the advantages of low thermal budget, high process compatibility and excellent ferroelectric performance.

The invention discloses a ferroelectric transistor capable of generating thousands of polarization states and a preparation and use method thereof, the ferroelectric transistor is prepared based on a Gr / hBN heterojunction, the top layer of the heterojunction is a Gr sheet, the bottom layer of the heterojunction is an hBN sheet, the rotation angle between Gr and hBN is controlled within 1 degree through dry transfer, and the Gr / hBN heterojunction is fixed on a silicon wafer substrate (SiO2 / Si); and further depositing a source electrode and a drain electrode through electron beam exposure and electron beam evaporation processes to construct the Gr / hBN ferroelectric transistor. A single device can generate dozens of discrete polarization states through source-drain pulse modulation; meanwhile, the Fermi level of the graphene can be reversibly adjusted among dozens of nonvolatile doping levels by overlapping the grid voltage while the source-drain pulse acts, and the polarization state can be modulated through the source-drain pulse at each doping level; the number of stable polarization states reaches thousands at room temperature; different polarization states may be retained for more than 105 seconds, and may be maintained for more than 10 years according to linear extrapolation.

The invention designs and provides a plurality of all-digital in-memory computing circuits based on ferroelectric transistors, and belongs to the field of integrated circuits. According to the invention, a plurality of all-digital in-memory computing circuits based on ferroelectric transistors are designed, weight data can be stored in the computing circuits to carry out all Boolean logic operations based on FEFET logic gate structures, and the all-digital in-memory computing circuit has important significance for breaking through a memory wall and a power consumption wall of a Von. Noiemann architecture. According to the FEFET in-memory calculation unit provided by the invention, relatively fixed weight data can be stored in a calculation circuit, so that the repeated transmission of the weight data is reduced, and the power consumption can be greatly reduced; meanwhile, due to full-digital calculation, multi-bit calculation precision cannot be sacrificed, the accuracy can be effectively improved, and the method is a potential technology applied to an artificial intelligence chip and an AI neural network.

The invention provides a capacitance-free nonvolatile dynamic memory. The capacitance-free nonvolatile dynamic memory comprises a first transistor and a second transistor, the first transistor adopts a vertical channel transistor; the second transistor is a ferroelectric transistor; the second transistor is over the first transistor. According to the 2T0C nonvolatile dynamic memory provided by the invention, one transistor adopts a ferroelectric transistor, and the nonvolatile dynamic random access memory obtained by introducing a ferroelectric material can solve the problems of storage density and energy consumption of a current dynamic random access memory, and can realize high-density and high-energy-efficiency storage; besides, in the preparation process of the vertical channel transistor adopted by the other transistor, the grid electrode surrounding the channel is formed through metal induction, the grid control capacity is higher, wafer-level three-dimensional integration is achieved, and compared with a traditional semiconductor process, the integrated density is high, the cost is low, and the wide application prospect is achieved.

The invention provides a preparation method of a flexible HZO ferroelectric memristor based on an all-solution method. The preparation method comprises the steps that S1, a mica sheet is used as a flexible substrate layer after being cleaned; s2, mixing a graphene conductive coating and ethanol according to a mass ratio of 1: 1000, stirring, carrying out ultrasonic treatment, layering graphene to obtain a mixture, uniformly dispensing the obtained mixture on the upper surface of the flexible substrate layer prepared in the S1, and heating and curing to prepare a bottom electrode layer; s3, mixing and stirring HfCl4 powder, ZrCl4 powder, an ethanol solution and deionized water according to a weight ratio of 1: 1: 10: 5, and performing ultrasonic treatment to obtain an HZO precursor solution; spin-coating the HZO precursor solution on the upper surface of the bottom electrode layer, and performing high-temperature annealing to form a nerve bionic layer; and S4, uniformly coating Pt conductive slurry on the upper surface of the nerve bionic layer prepared in the S3, and heating and curing to form the top electrode. The method effectively overcomes the problems of film forming difficulty and ferroelectric crystal structure regulation and control in the prior art, and has the advantages of simplicity, convenience and low cost.

Described herein is a method of fabricating a ferroelectric material, comprising the steps of: providing a semiconductor substrate; treating the semiconductor substrate with an oxidant to form an oxidized surface; depositing a metal on top of the oxidized surface to provide a film; and annealing the film at a temperature between 700°C and 900°C, thereby forming a metal oxide layer on top of the semiconductor substrate, wherein the interface between the semiconductor substrate and the metal oxide layer does not contain any remnant oxidized surface, and a ferroelectric material and a ferroelectric transistor or capacitor comprising said ferroelectric material.

The invention provides a gate annealing method for a ferroelectric transistor, and the method comprises the steps: forming an N / P well layer, a source electrode and a drain electrode on a substrate, and enabling the source electrode and the drain electrode to be formed at the two sides of the N / P well layer; through an atomic layer deposition process, ferroelectric materials are deposited in a grid region where a grid is to be formed, a ferroelectric layer is formed, titanium oxide is deposited on the surface of the ferroelectric layer to serve as a stress layer, amorphous silicon is deposited on the surface of the stress layer to serve as a sacrificial layer, and laser annealing treatment is carried out on the surface of the sacrificial layer to induce the ferroelectric layer to generate a ferroelectric phase. The stress layer provides stress for the ferroelectric layer to stabilize the ferroelectric phase; the sacrificial layer is removed, titanium nitride is deposited on the surface of the stress layer after laser annealing to serve as a work function layer, conductive metal is deposited on the work function layer to form a conductive layer, and the gate metal lamination layer is obtained. The invention further provides a gate structure obtained based on the gate annealing method and a ferroelectric transistor.

The application discloses a method for preparing a ferroelectric crystal optical superlattice by using a pyroelectric effect, a superlattice and application, and belongs to the field of electronic and optical devices. The method comprises the following steps: preparing a ferroelectric crystal material carrying an electrode pattern; heating the ferroelectric crystal material carrying the electrode pattern, and the heating temperature is 50-200 DEG C; in the temperature range, the ferroelectric crystal material carrying the electrode pattern is excited in the reverse direction of polarization by using the pyroelectric property of the ferroelectric crystal material itself; then, an annealing step is performed, and the annealing rate is 50-150 DEG C / h; after 1-10 times of heating and annealing cycles, the superlattice is obtained. The application breaks through the limitation of the external electric field polarization method for different electrode structures by creating a new polarization process, realizes the preparation of different superlattice crystals based on various structure electrodes, and further expands the application scenarios and application fields of the ferroelectric crystal material.

This application discloses a method and device for fabricating a periodically polarized ultrathin lithium niobate / lithium tantalate device, belonging to the field of nonlinear optical device manufacturing. The method includes: fabricating and polarizing periodic electrodes on a provided ferroelectric crystal wafer to form a periodically polarized master wafer; bonding the master wafer to a carrier substrate using optical resin-assisted bonding or direct bonding to form a composite structure; thinning and polishing the side of the master wafer away from the carrier substrate to obtain an ultrathin periodically polarized crystal functional layer; and fabricating the structure of the ultrathin periodically polarized crystal functional layer to obtain a periodically polarized ultrathin lithium niobate / lithium tantalate device. This method avoids the inherent problems of high-voltage breakdown and poor domain quality in existing technologies when directly polarizing ultrathin crystals by placing the high-risk polarization step on a thick, stable wafer.

The invention provides a semiconductor device and a manufacturing method thereof, electronic equipment and a tri-state content addressing method of the semiconductor device, and belongs to the technical field of semiconductors. The semiconductor device includes: a first ferroelectric transistor and a second ferroelectric transistor; the first ferroelectric transistor has a first polarity, and the second ferroelectric transistor has a second polarity; a first electrode of the first ferroelectric transistor and a second electrode of the second ferroelectric transistor are electrically connected with a ground wire; a third electrode of the first ferroelectric transistor and a fourth electrode of the second ferroelectric transistor are electrically connected with the matching line; a first gate electrode of the first ferroelectric transistor is electrically connected to the first signal line, and a second gate electrode of the second ferroelectric transistor is electrically connected to the second signal line. According to the scheme, the ternary content addressable storage function can be realized.

The present invention discloses a hardware implementation method for a reservoir computing network. This method realizes the mask layer, reservoir layer, and readout layer of the reservoir computing network only through ferroelectric transistors. The mask layer, reservoir layer, and readout layer are all composed of multiple ferroelectric transistors. The gates of the ferroelectric transistors in the mask layer are connected to triangular pulses, the sources of the ferroelectric transistors in the mask layer are connected to the input voltage, the mask layer is fully connected to the reservoir layer, the gates of the ferroelectric transistors in the reservoir layer and the readout layer are both connected to the preset voltage, the reservoir layer is connected to the readout layer one by one, and the drains of all the ferroelectric transistors in the readout layer are connected in series. The current output by the connected drains is the output of the reservoir computing network. The mask layer utilizes the non-volatile storage characteristics and randomness of the ferroelectric transistors to realize the function of the mask layer. Based on the regulation of the channel current by the gates of the ferroelectric transistors, the collection of node states and the adjustment of weights are realized.

The present invention discloses a method for constructing a ferroelectric transistor simulation model, including: calculating a first nonlinear function based on the voltage across a ferroelectric layer in a ferroelectric transistor at a certain moment, the gate voltage of the ferroelectric transistor, the body voltage of the ferroelectric transistor, the drain voltage of the ferroelectric transistor, and the source voltage of the ferroelectric transistor; obtaining each parameter value in a simulation model formula through a logistic function and the first nonlinear function; obtaining the upper limit and lower limit of the polarization of the ferroelectric transistor, and fitting a second nonlinear function based on the voltage of the ferroelectric polarization layer, the upper limit and lower limit of the polarization of the ferroelectric transistor, and deriving a ferroelectric transistor simulation model based on the first nonlinear function, the second nonlinear function, the truncated Gaussian distribution function, and each parameter value in the simulation model formula. The ferroelectric transistor simulation model provided by the present application can meet the simulation requirements of ferroelectric transistors in storage-computation integrated circuit design.

A vertical ferroelectric transistor comprises an upper source / drain region and a lower source / drain region having a channel region vertically there-between. A gate is laterally aside the channel region. Ferroelectric material is laterally aside and laterally between the gate and the channel region. Insulator material of different composition from that of the ferroelectric material is laterally aside and laterally between the gate and the ferroelectric material. The insulator material comprising (a) and (b) that are laterally aside one another and described herein. Ferroelectric memory and method are also disclosed.

This invention discloses a ferroelectric transistor capable of generating thousands of polarization states and its fabrication and application method. The ferroelectric transistor is fabricated based on a Gr / hBN heterojunction, with a Gr sheet as the top layer and an hBN sheet as the bottom layer. The rotation angle between Gr and hBN is controlled within 1° using a dry transfer method. The Gr / hBN heterojunction is fixed on a silicon substrate (SiO2 / Si). Source and drain electrodes are further deposited using electron beam lithography and electron beam evaporation processes to construct the Gr / hBN ferroelectric transistor. A single device can generate dozens of discrete polarization states through source-drain pulse modulation. Simultaneously, by superimposing a gate voltage while applying source-drain pulses, the Fermi level of graphene can be reversibly tuned between dozens of non-volatile doping levels, and the polarization state can be modulated by source-drain pulses at each doping level. The number of stable polarization states reaches thousands at room temperature; different polarization states can be retained for more than 10^6 times. 5 Seconds, and based on linear extrapolation, it could last for more than 10 years.

The application relates to the technical field of semiconductors, and provides a logic operation method and device based on a ferroelectric transistor and electronic equipment, the logic operation method based on the ferroelectric transistor comprises the following steps: obtaining an operation instruction to be executed, the operation instruction comprising input variables and the type of the logic operation to be executed; determining an assignment relationship between the input variables and logic variables of a target logic gate according to the working principle of the target logic gate and the type of the logic operation to be executed, wherein the target logic gate comprises at least one ferroelectric transistor; assigning the values of the input variables to the logic variables according to the assignment relationship; controlling the ferroelectric transistor to execute the logic operation according to the logic variables, and storing the result of the logic operation in situ by using the polarization state of the ferroelectric transistor. The method realizes the integration of storage and calculation based on the Boolean logic gate of the ferroelectric transistor, breaks through the limitations of the storage wall and the power consumption wall, and improves the flexibility of the Boolean logic gate of the ferroelectric transistor when performing the logic operation.

Disclosed in the present invention is a domain wall straightening method for a periodically poled ferroelectric crystal. In the present invention, by means of testing a piezoelectric coefficient of a poled sample, the poling situation of the sample can be non-destructively determined, and regions with uniform poling can be selected; moreover, whether to continue poling or terminate poling and restart poling after single-domain formation can be determined on the basis of a duty cycle calculation result; and the straightness of domain walls is determined on the basis of the variation of the piezoelectric coefficient, such that the magnitude and duration of a poling voltage are adjusted in a timely manner, thereby accurately controlling a poling process, and thus obtaining a high-quality periodically poled crystal.

The application belongs to the technical field of organic semiconductor electronic devices, and discloses a flexible threshold value adjustable negative capacitance transistor and a preparation method, and a small logic circuit. The flexible threshold value adjustable negative capacitance transistor comprises a flexible substrate, an organic semiconductor layer, an organic dielectric layer, a source-drain electrode and two gate electrodes. The preparation method is as follows: a bottom gate electrode is prepared on the surface of the flexible substrate and an organic ferroelectric film is spin-coated; an organic polymer film is spin-coated on the surface of the organic dielectric layer as a semiconductor channel layer; a source / drain metal electrode is prepared; finally, an organic ferroelectric film is spin-coated and a top gate electrode is prepared. The application utilizes the negative capacitance principle of the organic ferroelectric transistor to reduce the working voltage and power consumption, and the double-gate structure is made to make the threshold voltage of the transistor adjustable, which has a great effect in the flexible logic circuit based on the unipolar device.

A neuromorphic computing device according to the present disclosure may have a plurality of artificial neurons connected to a synapse array, and each of the plurality of artificial neurons may include: a ferroelectric transistor having a gate connected to a first node, and connected between a power terminal and a second node configured to output an output spike, a first input transistor having a gate configured to receive a first input spike, and connected between a first input power terminal and the first node, a second input transistor having a gate configured to receive a second input spike, and connected between a second input power terminal and the first node, an adjustment transistor having a gate receiving an adjustment voltage and connected between the second node and ground terminal, and a reset transistor having a gate receiving a reset voltage, and connected between the first node and ground terminal.

Memory device with series-connected ferroelectric transistor and capacitor, associated electronic circuit, programming method and reading method. The present invention relates to a memory device (14) comprising: - a ferroelectric field-effect transistor (20) having a gate electrode (21) and first (22) and second (23) conduction electrodes; - a ferroelectric capacitor (25) having first (27) and second (28) charge electrodes; the transistor (20) and the ferroelectric capacitor (25) being connected according to a first connection configuration (C1) in which the first conduction electrode (22) is connected to a reference potential (GND) and the second conduction electrode (23) is connected to the first charge electrode (27);or according to a second connection configuration in which the first conduction electrode (22) is connected to the first charging electrode (27) and the second conduction electrode (23) is connected to the second charging electrode (28). Figure for the abbreviation: Figure 2;

The invention relates to an embedded low-voltage nano-gate ferroelectric transistor structure and a preparation method thereof, and relates to the field of memory devices, the embedded low-voltage nano-gate ferroelectric transistor structure comprises a silicon-based CMOS logic circuit, the silicon-based CMOS logic circuit is provided with a first insulating dielectric layer and a plurality of horizontally arranged nano-gate ferroelectric transistors, a second insulating medium layer is arranged between every two adjacent nano-gate ferroelectric transistors; the nanometer gate ferroelectric transistor comprises a gate metal interconnection, a third insulating dielectric layer, a ferroelectric layer, a metal floating gate, a gate dielectric layer, a channel material layer and a source and drain electrode which are arranged from bottom to top, and the bottom of the gate metal interconnection is connected with the silicon-based CMOS logic circuit through a connecting line penetrating through the first insulating dielectric layer; metal nano-gates are vertically arranged on the two sides of the gate metal interconnection and the third insulating dielectric layer, the tops of the metal nano-gates are in contact with the ferroelectric layer, and side walls are arranged between the metal nano-gates and the second insulating dielectric layer. According to the invention, ultra-low power consumption edge computing application can be met, and storage and computing integrated operation is supported.

The application provides a niobium phosphate nonlinear optical crystal and preparation and application thereof. 12 Nb3P7O 31 , belongs to an orthorhombic system, a space group is Pna21, is a non-central symmetric structure, cell parameters are: a=0.5 nm, b=1.0 nm, c=0.5 nm, and Z=4, has a large nonlinear optical effect (3xKDP), is phase-matched, a theoretical indirect band gap is 5.11 eV, has a large laser damage threshold, a wide transmission range, stable physical and chemical properties, good mechanical properties, is not easy to deliquesce, and is easy to preserve, and can be used as a ferroelectric crystal, a pyroelectric crystal or a laser substrate material, and is widely applied in preparation of middle infrared laser nonlinear optical composite functional devices, piezoelectric devices, laser frequency conversion devices and the like.

The present disclosure relates to a ferroelectric transistor, memory circuitry including a ferroelectric transistor, and a method for forming memory circuitry including memory cells individually including horizontal ferroelectric transistors. The ferroelectric transistor comprises two source electrode / drain electrode regions, and a channel region is horizontally arranged between the two source electrode / drain electrode regions. The channel region has opposite front and back sides along a horizontal current flow direction through the channel region. A front gate is on the front side of the channel region. A front gate insulator is horizontally between the front gate and the front side of the channel region. The front gate insulator includes a dielectric material and a ferroelectric material each directly abutting the front gate. The ferroelectric material directly against the front gate is more than the dielectric material. Other embodiments including the methods are disclosed.

The invention provides a PVDF-based elastic ferroelectric material and a preparation method and application thereof, and relates to the technical field of ferroelectric materials. A ferroelectric crystal phase region of the PVDF-based elastic ferroelectric material is protected to the maximum extent, and a uniform three-dimensional elastic network structure formed by firm C-C bonds is constructed in an amorphous region by a PVDF-based ferroelectric polymer and a crosslinking sensitizer through radiation crosslinking; the PVDF-based elastic ferroelectric material has excellent ferroelectricity, great flexibility and elasticity, proper strength and excellent fatigue resistance at the same time. According to the preparation method of the PVDF-based elastic ferroelectric material, the technical bottlenecks of thermal crosslinking and photo-crosslinking are fundamentally overcome through a mild, pure and uniform radiation process, so that controllable preparation of the PVDF-based elastic ferroelectric material with excellent ferroelectricity, great flexibility and elasticity, proper strength and excellent fatigue resistance becomes reality; the preparation method is simple, efficient and high in universality, and is very suitable for large-scale industrial production.

The application discloses a transparent ferroelectric transistor and a preparation method thereof, and relates to the technical field of electronic devices, which comprises a substrate, a gate electrode arranged on the upper surface of the substrate, a metal oxide interlayer arranged on the upper surface of the gate electrode, a metal interlayer arranged on the upper surface of the metal oxide interlayer, wherein the metal interlayer is made of at least one of Ti, Ni or Cr elements, a ferroelectric layer arranged on the upper surface of the metal interlayer, an insulating layer arranged on the upper surface of the ferroelectric layer, a drain electrode and a source electrode arranged on the left and right ends of the upper surface of the insulating layer respectively, and the substrate, the gate electrode, the insulating layer, the drain electrode and the source electrode are all transparent materials; the transparent ferroelectric transistor provided by the application can guarantee a high ferroelectric polarization strength under the condition that the annealing temperature is not more than 400 DEG C.

The invention relates to a ferroelectric transistor-based Transform model acceleration in-memory calculation circuit and method, belongs to the technical field of in-memory calculation, and solves the problems of large power consumption of a core area, long delay and low storage density of a storage calculation array of a traditional Transform in-memory calculation accelerator SIMD (Single Instruction Multiple Data). The circuit comprises a storage array used for executing score matrix calculation and scaling operation in parallel, and each storage unit comprises a ferroelectric transistor; one end of each word line is connected with the word line decoding circuit and the multiplexer, and the other end of each word line is connected with the grid electrode of the corresponding row ferroelectric transistor; one end of each bit line and one end of each source line are connected to the bit line and source line decoding circuit and the multiplexer, and the other end of each bit line and one end of each source line are connected to drain electrodes and source electrodes of the corresponding columns of ferroelectric transistors; the word line driving circuit and the read-write driving circuit are used for enhancing the signal driving capability, and the scaling voltage generating circuit is used for generating scaling voltage and applying the scaling voltage to a plurality of source lines. According to the invention, the ferroelectric transistor is utilized to realize the # imgabs0 # operator, the area power consumption overhead and delay of the SIMD core are saved, and the storage density of the storage array is improved.

The invention provides a ferroelectric capacitor storage unit, a ferroelectric tunnel junction storage unit, a ferroelectric transistor storage unit, a ferroelectric memory and electronic equipment, relates to the technical field of electronics, and aims to solve the problem of poor durability of data stored by ferroelectricity. The ferroelectric capacitor storage unit comprises a transistor and a ferroelectric capacitor, the ferroelectric capacitor comprises a first electrode layer, a second electrode layer and a first ferroelectric layer, and the first ferroelectric layer is arranged between the first electrode layer and the second electrode layer; the first ferroelectric layer is made of an anion-doped hafnium oxide-based ferroelectric material; the transistor is electrically connected to the first electrode layer. The ferroelectric capacitor storage unit is used for storing data.

The invention discloses a method for calculating the potential of an intermediate node of a ferroelectric transistor. The method comprises the following steps: according to a charge conservation relationship between a gate oxide layer and a semiconductor part in the ferroelectric transistor, determining a first function relationship between an intermediate node potential and a channel average surface potential under the condition of averaging a channel potential; determining a second function relationship among the average surface potential of the channel, the potential of the intermediate node, the voltage of the grid electrode, the voltage of the source electrode, the voltage of the drain electrode, the ferroelectric polarization state and the defect occupancy state by combining the charge conservation relationship of the ferroelectric layer; and on the basis of the second function relationship and by utilizing the first function relationship elimination, calculating the channel average surface potential and the intermediate node potential. According to the application, the potential of the middle node of the ferroelectric transistor can be quickly and accurately calculated, so that the direct-current conduction current of the channel of the ferroelectric transistor can be quickly calculated.

A ferroelectric transistor comprises two source / drain regions having a channel region horizontally there-between. The channel region has opposing front and back sides along a horizontal current-flow direction through the channel region. A front gate is on the front side of the channel region. A front-gate insulator is horizontally between the front gate and the front side of the channel region. The front-gate insulator comprises a dielectric material and a ferroelectric material that are each directly against the front gate. More of the ferroelectric material is directly against the front gate than is the dielectric material. Other embodiments, including methods, are disclosed.

The invention discloses a single power supply storage and calculation integrated data selector with extensible selection data, which comprises a pre-charging circuit of which the input end is connected to a power supply signal input end, the control end is connected with a pre-charging control signal, and the output end is connected with the input end of an output driving circuit; each basic data input circuit is composed of a ferroelectric transistor, an nMOS transistor and a pMOS transistor, the drain electrode of the ferroelectric transistor is connected with the input end of the output driving circuit, the source electrode of the ferroelectric transistor is connected with the drain electrode of the nMOS transistor and the drain electrode of the pMOS transistor, and a data selection control signal is connected to the grid electrode of the ferroelectric transistor; a source electrode of the nMOS transistor is connected with a data input signal, a grid electrode is connected with a data selection control signal, a source electrode of the pMOS transistor is connected with a power supply signal input end, and a grid electrode is connected with a data selection control signal; the circuit has the advantages that a single power supply mode is adopted, the complexity of an external power supply circuit is reduced, the expansion of an input end can be conveniently realized, and a one-out-of-multiple data selection function is further realized.