Doherty amplifier

Abstract

This Doherty amplifier includes a carrier amplifier and a peak amplifier. A carrier amplifier bias circuit supplies a bias to the carrier amplifier. A peak amplifier bias circuit supplies a bias to the peak amplifier. A current-drawing circuit draws out a portion of the bias current supplied to the peak amplifier from the peak amplifier bias circuit. The current-drawing circuit includes a cascode circuit in which a base ground transistor and an emitter ground transistor are cascode-connected. The collector of the base ground transistor is connected to the peak amplifier, and the base of the emitter ground transistor is connected to an input node of the carrier amplifier.

Description

Doherty Amplifier

[0001] The present invention relates to a Doherty amplifier.

[0002] A Doherty amplifier that operates in two operating modes, a low power mode and a high power mode, is known (see Non-Patent Document 1). This Doherty amplifier operates in the low power mode when the output power level is equal to or lower than a certain threshold, for example, 20 dBm, and operates in the high power mode when the output power level is equal to or higher than that threshold. By differentiating the bias of the peak amplifier between the low power mode and the high power mode, a decrease in power-added efficiency (PAE) when operating in the low power mode can be suppressed.

[0003] Seongjun Bae et. al., “Bias-Switching Quasi-Doherty-Type Amplifier for CDMA Handset Applications”, IEEE Radio Frequency Integrated Circuits Symposium Digest, pp.137-140, 2003

[0004] For example, when handling high-frequency signals with a high peak-to-average power ratio (PAPR), such as those used in cyclic prefix orthogonal frequency division multiplexing (CP-OFDM) for fifth-generation mobile communication systems (5G), even if the output power is relatively low, the device must operate in high-power mode assuming the input of high-power signals. In this case, the gain of the peak amplifier does not become completely zero, resulting in a decrease in PAE.

[0005] An object of the present invention is to provide a Doherty amplifier that can suppress a decrease in PAE even when amplifying a high-frequency signal with a high PAPR.

[0006] According to one aspect of the present invention, there is provided a Doherty amplifier comprising: a carrier amplifier; a peak amplifier; a carrier amplifier bias circuit that supplies a bias to the carrier amplifier; a peak amplifier bias circuit that supplies a bias to the peak amplifier; and an extraction circuit that extracts a portion of the bias current supplied to the peak amplifier from the peak amplifier bias circuit, wherein the extraction circuit includes a cascode circuit in which a common-base transistor and a common-emitter transistor are cascode-connected, the collector of the common-base transistor being connected to the peak amplifier, and the base of the common-emitter transistor being connected to an input node of the carrier amplifier.

[0007] According to another aspect of the present invention, there is provided a Doherty amplifier comprising: a carrier amplifier; a peak amplifier; a carrier amplifier bias circuit that supplies a bias to the carrier amplifier; a peak amplifier bias circuit that supplies a bias to the peak amplifier; and an extraction circuit that extracts, from the bias current supplied to the peak amplifier from the peak amplifier bias circuit, a current that depends on the amplitude of an input current input to the carrier amplifier.

[0008] When the amplitude of the input current input to the input node of the carrier amplifier increases, the current flowing through the common-emitter transistor increases due to the self-bias effect, and the current flowing through the cascode circuit also increases. As a result, the bias current supplied to the peak amplifier decreases, and the increase in gain due to the self-bias effect of the peak amplifier is suppressed.

[0009] By suppressing the increase in the gain of the peak amplifier, the decrease in the PAE of the Doherty amplifier is suppressed.

[0010] FIG. 1 is a block diagram of a Doherty amplifier according to a first embodiment. FIG. 2 is an equivalent circuit diagram of the carrier amplifier, peak amplifier, and extraction circuit of the Doherty amplifier according to the first embodiment. FIG. 3 is an equivalent circuit diagram of the peak amplifier bias circuit. FIG. 4 is a graph showing the relationship between gain and extraction current and output power Pout. The upper graph shows the relationship between the output power Pout and gain of the Doherty amplifier, and the lower graph shows the relationship between the output power Pout and extraction current Is of the Doherty amplifier. FIG. 5 is a block diagram of a Doherty amplifier according to a second embodiment. FIG. 6 is an equivalent circuit diagram of the carrier amplifier, peak amplifier, and extraction circuit of the Doherty amplifier according to the second embodiment. FIG. 7 is a graph showing an example of the waveforms of one cycle of the high-frequency current Ibd, Iinc1, and Ioutc1 (FIG. 6) supplied to the base of the common-emitter transistor 30Qd. FIG. 8 is a graph showing the relationship between gain and extraction current and output power Pout. The upper graph shows the relationship between the output power Pout of the Doherty amplifier and the gain of the peaking amplifier, and the lower graph shows the relationship between the output power Pout of the Doherty amplifier and the extraction current Is. FIG. 9 is a graph showing the relationship between gain and output power Pout. The upper graph shows the gain when the load impedance ZL is the design value (e.g., 50Ω), i.e., when the impedance is matched between the Doherty amplifier and the load impedance ZL and the VSWR is 1. The middle graph shows the gain of the Doherty amplifier according to the comparative example when the load impedance ZL is higher than 50Ω. The lower graph shows the gain of the Doherty amplifier according to the second embodiment when the load impedance ZL is higher than 50Ω. FIG. 10 is an equivalent circuit diagram of the peaking amplifier and extraction circuit of the Doherty amplifier according to the third embodiment. FIG. 11 is a diagram showing the layout of some elements of the peaking amplifier and extraction circuit of the Doherty amplifier according to the third embodiment. Fig. 12 is a diagram showing a layout of some elements of a peak amplifier and extraction circuit of a Doherty amplifier according to a modification of Example 3. Fig. 13 is a diagram showing a layout of some elements of a peak amplifier and extraction circuit of a Doherty amplifier according to another modification of Example 3. Fig. 14 is an equivalent circuit diagram of a Doherty amplifier according to Example 4.

[0011] [First Embodiment] A Doherty amplifier according to a first embodiment will be described with reference to Figures 1 to 4. Figure 1 is a block diagram of the Doherty amplifier according to the first embodiment. An input signal RFin is input to one input terminal of a divider 50. The other input terminal of the divider 50 is grounded via a non-reflective termination resistor 51. The divider 50 outputs a peak amplifier input signal RFinp from one output terminal and outputs a carrier amplifier input signal RFinc from the other output terminal. The phase of the carrier amplifier input signal RFinc leads the phase of the peak amplifier input signal RFinp by 90°. For example, a 90° hybrid circuit is used as the divider 50.

[0012] A peak amplifier input signal RFinp is input to the peak amplifier 20, and a carrier amplifier input signal RFinc is input to the carrier amplifier 10. A peak amplifier bias circuit 21 outputs a peak amplifier bias current Ibp. The bias current Ibp is set so as to cause the peak amplifier to operate in class C. A carrier amplifier bias circuit 11 supplies a carrier amplifier bias current Ibc to the carrier amplifier 10. The bias current Ibc is set so as to cause the carrier amplifier 10 to operate in class AB.

[0013] A part of the high frequency current (hereinafter referred to as high frequency current Iinc1) of the carrier amplifier input signal RFinc (hereinafter referred to as input current Iinc) is input to the extraction circuit 30. The current level (e.g., amplitude) of the high frequency current Iinc1 is determined depending on the current level of the input current Iinc, the input impedance of the carrier amplifier 10, and the input impedance of the extraction circuit 30. Therefore, the current level of the high frequency current Iinc1 can be adjusted by adjusting the capacitance of the capacitor 30C.

[0014] The extraction circuit 30 generates an extraction current Is that depends on the current level of the input current Iinc. More specifically, it generates an extraction current Is that depends on the current level of the high-frequency current Iinc1. A current equivalent to the extraction current Is is extracted from the bias current Ibp output from the peak amplifier bias circuit 21, and the remaining current serves as an effective bias current to operate the peak amplifier 20.

[0015] The output signal of the peak amplifier 20 and the output signal of the carrier amplifier 10 are combined in a combiner 60. For example, the combiner 60 includes a 90° phase shifter 61. The 90° phase shifter 61 is configured, for example, by a transmission line with a line length of ¼ wavelength. The combiner 60 combines the output signal from the peak amplifier 20 and the signal output from the carrier amplifier 10 and passed through the 90° phase shifter 61. The combined high-frequency signal is output as an output signal RFout via an impedance matching circuit 70. The output signal RFout is supplied to a load 71 with a load impedance ZL. The load 71 is, for example, a transmitting antenna.

[0016] 2 is an equivalent circuit diagram of the carrier amplifier 10, peak amplifier 20, and extraction circuit 30 of the Doherty amplifier according to the first embodiment. The peak amplifier 20 includes a peak amplifier transistor 20Q, a base ballast resistor element 20R, and an input capacitor 20C. The peak amplifier transistor 20Q may be, for example, a heterojunction bipolar transistor.

[0017] The collector of the peak amplifier transistor 20Q is connected to the combiner 60, and the emitter is grounded. The base of the peak amplifier transistor 20Q is connected to the peak amplifier bias circuit 21 via a base ballast resistor element 20R, and is also connected to the distributor 50 via an input capacitor 20C. In other words, the base ballast resistor element 20R is inserted in the supply path of the bias current from the peak amplifier bias circuit 21 to the base of the peak amplifier transistor 20Q. Furthermore, the base of the peak amplifier transistor 20Q is connected to the extraction circuit 30.

[0018] The peak amplifier input signal RFinp output from the distributor 50 is input to the base of the peak amplifier transistor 20Q via the input capacitor 20C. The bias current Ibp output from the peak amplifier bias circuit 21 passes through the base ballast resistor element 20R, with a portion (pulling current Is) flowing into the pulling circuit 30 and the remainder (effective bias current Ibpe) being supplied to the base of the peak amplifier transistor 20Q.

[0019] The carrier amplifier 10 includes a carrier amplifier transistor 10Q, a base ballast resistor element 10R, and an input capacitor 10C. The carrier amplifier transistor 10Q is, for example, a heterojunction bipolar transistor formed from the same compound semiconductor material as the peak amplifier transistor 20Q.

[0020] The collector of the carrier amplifier transistor 10Q is connected to the combiner 60, and the emitter is grounded. The base of the carrier amplifier transistor 10Q is connected to the carrier amplifier bias circuit 11 via a base ballast resistor element 10R, and is also connected to the distributor 50 via an input capacitor 10C.

[0021] The carrier amplifier input signal RFinc output from the distributor 50 is input to the base of the carrier amplifier transistor 10Q via the input capacitor 10C. The bias current Ibc output from the carrier amplifier bias circuit 11 is supplied to the base of the carrier amplifier transistor 10Q via the base ballast resistor element 10R.

[0022] The extraction circuit 30 includes a cascode-connected common-base transistor 30Qs and a common-emitter transistor 30Qd. The common-base transistor 30Qs and the common-emitter transistor 30Qd are, for example, heterojunction bipolar transistors formed from the same compound semiconductor material as the peak amplifier transistor 20Q. A current flowing through the cascode circuit including the common-base transistor 30Qs and the common-emitter transistor 30Qd is the extraction current Is.

[0023] The collector of the common-base transistor 30Qs is connected to the base of the peak amplifier transistor 20Q. The base of the common-emitter transistor 30Qd is connected to the input node of the carrier amplifier 10 via a capacitor 30C. Furthermore, the base of the common-emitter transistor 30Qd is connected to the carrier amplifier bias circuit 11 via a resistor element 30Rd.

[0024] A constant bias current is supplied from the constant current source 30CC to the common-base transistor 30Qs via the resistor element 30Rs. The value of this constant bias current determines the maximum value of the collector current of the common-base transistor 30Qs, i.e., the maximum value of the pull-out current Is.

[0025] A bias current is supplied from the carrier amplifier bias circuit 11 to the base of the common-emitter transistor 30Qd via a resistor element 30Rd. The current value of the bias current supplied to the base of the common-emitter transistor 30Qd is the same as the current value of the bias current Ibc supplied to the base of the carrier amplifier transistor 10Q. The common-emitter transistor 30Qd is biased to class AB, similar to the carrier amplifier 10. Furthermore, a high-frequency current Iinc1, which is a portion of the input current Iinc input to the carrier amplifier 10, is supplied to the base of the common-emitter transistor 30Qd via a capacitor 30C.

[0026] When the high frequency current Iinc1 supplied to the base of the common-emitter transistor 30Qd increases, the collector current of the common-emitter transistor 30Qd increases due to the self-bias effect.

[0027] Next, a brief explanation of the self-bias effect will be given. When the input signal level to a transistor increases, resulting in an increase in the output signal level, the amplitude of the collector current increases. As will be explained later with reference to FIG. 3, the carrier amplifier bias circuit 11 includes an emitter-follower transistor, and a bias current is supplied from the emitter of the emitter-follower transistor. When the amplitude of the input signal increases, the carrier amplifier bias circuit 11 attempts to maintain a constant potential difference between the base and emitter of the emitter-follower transistor, thereby raising the average bias point. At this time, the increase in amplitude in the positive direction is not limited, resulting in an increase in the DC current component flowing through the collector and base of the common-emitter transistor 30Qd. In other words, an effect similar to a substantial increase in the base bias current is obtained. This effect is called the self-bias effect.

[0028] The increase in the collector current of the common-emitter transistor 30Qd due to the self-bias effect is limited by the maximum value of the collector current of the common-base transistor 30Qs. That is, the extraction current Is increases as the signal level of the carrier amplifier input signal RFinc increases, and becomes approximately constant when it reaches the maximum value of the collector current of the common-base transistor 30Qs. The change in the value of the extraction current Is will be described in detail later with reference to FIG. 4.

[0029] 3 is an equivalent circuit diagram of the peak amplifier bias circuit 21. The circuit configuration of the carrier amplifier bias circuit 11 (FIGS. 1 and 2) is the same as the circuit configuration of the peak amplifier bias circuit 21, so a description of the configuration of the carrier amplifier bias circuit 11 will be omitted.

[0030] The peak amplifier bias circuit 21 includes an emitter-follower transistor 21Q, a diode circuit 21D, a resistor element 21R, and a capacitor 21C. The diode circuit 21D includes two diodes connected in series. Each of the two diodes is formed, for example, by a diode-connected heterojunction bipolar transistor.

[0031] One end of the resistor 21R is connected to the anode node of the diode circuit 21D. The cathode node of the diode circuit 21D is grounded. A capacitor 21C is connected in parallel to the diode circuit 21D. A constant current Icont is supplied to the resistor 21R from the other end of the resistor 21R. A constant voltage corresponding to the forward voltage of the diode is generated at the interconnection point between the resistor 21R and the diode circuit 21D. The interconnection point between the resistor 21R and the diode circuit 21D is connected to the base of the emitter-follower transistor 21Q.

[0032] A constant battery voltage VBAT is applied to the collector of the emitter-follower transistor 21Q. The emitter of the emitter-follower transistor 21Q is connected to the base of the peak amplifier transistor 20Q via the base ballast resistor element 20R. A substantially constant bias current Ibp is supplied from the emitter-follower transistor 21Q to the base ballast resistor element 20R of the peak amplifier 20Q.

[0033] A current equivalent to the extraction current Is generated in the extraction circuit 30 is extracted from the bias current Ibp, and the remaining effective bias current Ibpe is supplied to the base of the peak amplifier transistor 20Q.

[0034] Next, the operation of the Doherty amplifier according to the first embodiment will be described with reference to FIG. 4 . FIG. 4 is a graph showing the relationship between gain, extraction current, and output power Pout. The upper graph in FIG. 4 shows the relationship between the output power Pout and gain of the Doherty amplifier, and the lower graph shows the relationship between the output power Pout and extraction current Is of the Doherty amplifier. The horizontal axis of the upper and lower graphs in FIG. 4 represents the output power Pout, the vertical axis of the upper graph represents gain, and the vertical axis of the lower graph represents the current value of the extraction current Is. The dashed line in the upper graph represents the gain Gp of the peak amplifier 20 ( FIG. 1 ), the thin solid line represents the gain Gc of the carrier amplifier 10 ( FIG. 1 ), and the thick solid line represents the gain Gt of the Doherty amplifier, i.e., the total gain of the peak amplifier 20 and the carrier amplifier 10.

[0035] The output power Pout is at the power level P １In the following range, the power level of the carrier amplifier input signal RFinc is also low, and the common-emitter transistor 30Qd (FIG. 2) of the extraction circuit 30 flows an extraction current Is corresponding to a constant bias current from the carrier amplifier bias circuit 11 (FIG. 2).

[0036] The output power Pout is at the power level P １ When the output power Pout exceeds 100 kV, the common-emitter transistor 30Qd becomes self-biased, and the draw current Is increases as the output power Pout increases. When the draw current Is reaches the maximum collector current Ismax of the common-base transistor 30Qs, the draw current Is becomes approximately constant. When the draw current Is becomes approximately constant, the gain Gp of the peak amplifier 20 reaches the target value.

[0037] The gain Gc of the carrier amplifier 10 (FIG. 2) is determined by the power level P ２ The output power Pout is approximately constant in the range ２ When the power level P exceeds the limit, the gain Gc decreases as the output power Pout increases. ２ can be considered as the output power Pout when the gain Gc indicates a 1 dB gain compression level (P1 dB), for example.

[0038] When the output power Pout increases, the bias current of the peak amplifier transistor 20Q (FIG. 2) increases due to the self-bias effect. As a result, the gain Gp of the peak amplifier 20 rises. However, since the draw current Is also increases with the increase in the output power Pout, the increase in the effective bias current Ibpe of the peak amplifier transistor 20Q is suppressed. In this way, the rise in the gain of the peak amplifier 20 is inhibited by the increase in the power level of the carrier amplifier input signal RFinc. As a result, the power level P of the output power Pout when the gain Gp of the peak amplifier 20 rises is lower than in a configuration in which the draw current Is does not flow. ３ shifts to the high power side.

[0039] Next, the excellent effects of the first embodiment will be described in comparison with a comparative example. As an example, in the comparative example, when the output power Pout is ３In the above range, the power level P ３ Increasing the bias current of the peak amplifier increases the gain of the peak amplifier, thereby compensating for the decrease in the gain of the carrier amplifier and maintaining the gain of the Doherty amplifier constant.

[0040] However, when amplifying a high frequency signal with a high PAPR, for example, the output power Pout is at a power level P １ More than P ３ Even if the output power Pout is within the range of the power level P ３ It is preferable to increase the bias current of the peak amplifier in anticipation of the possibility that the output power Pout will be higher than the power level P １ More than P ３ The peak amplifier has a certain gain in the range: １ More than P ３ In the following ranges, the PAE decreases.

[0041] In the first embodiment, the output power Pout is set to a power level P １ More than P ３ The gain Gp of the peak amplifier 20 (FIG. 2) is almost zero when operating in the range ３ When the output power Pout exceeds the power level P, the gain Gp of the peak amplifier 20 automatically rises, so that the gain Gt (FIG. 4) of the Doherty amplifier can be kept almost constant by sufficiently following the change in the output power Pout even for high-frequency signals with high PAPR. １ More than P ３ Since the peak amplifier 20 (FIG. 1) hardly operates within the following range, the decrease in PAE is suppressed.

[0042] In the first embodiment, the amplitude of the high frequency current input to the base of the common-emitter transistor 30Qd can be adjusted by adjusting the capacitance of the capacitor 30C (FIG. 2) and the emitter dimensions of the common-emitter transistor 30Qd, thereby adjusting the shape of the gain of the peak amplifier 20. This allows the total gain of the Doherty amplifier to approach flatness.

[0043] Next, a Doherty amplifier according to a modification of the first embodiment will be described. In the first embodiment, a current combiner is used as the combiner 60 (FIG. 1), but a voltage combiner may also be used. Furthermore, in the first embodiment, a portion of the input current Iinc to the carrier amplifier 10 is input to the extraction circuit 30, but instead of the input current Iinc, a portion of the input current Iinp to the peak amplifier may also be input to the extraction circuit 30.

[0044] In the first embodiment, the common-emitter transistor 30Qd of the extraction circuit 30 and the carrier amplifier transistor 10Q share the carrier amplifier bias circuit 11 (FIG. 2). As a modified example, a bias current may be supplied to the common-emitter transistor 30Qd of the extraction circuit 30 from a bias circuit different from the carrier amplifier bias circuit 11. This configuration increases the degree of freedom in setting the bias current of the common-emitter transistor 30Qd of the extraction circuit 30.

[0045] In the first embodiment, a constant bias current is supplied from a constant current source 30CC to the base of the common-base transistor 30Qs of the extraction circuit 30. When the supply of this bias current is stopped, the extraction current Is becomes zero. As a result, the effective bias current Ibpe of the peak amplifier transistor 20Q becomes equal to the bias current Ibp output from the peak amplifier bias circuit 21. This allows the peak amplifier 20 to operate with a fixed bias.

[0046] Second Embodiment Next, a Doherty amplifier according to a second embodiment will be described with reference to Figures 5 to 9. Below, a description of the configuration common to the Doherty amplifier according to the first embodiment described with reference to Figures 1 to 4 will be omitted.

[0047] 5 is a block diagram of a Doherty amplifier according to a second embodiment. In the first embodiment, a high-frequency current Iinc1, which is a portion of the input current Iinc to the carrier amplifier 10, is input to the extraction circuit 30. In contrast, in the second embodiment, in addition to the high-frequency current Iinc1, a high-frequency current Ioutc1, which is a portion of the output current Ioutc from the carrier amplifier 10, is also input to the extraction circuit 30. The current level of the high-frequency current Ioutc1 is determined by the current level of the output current Iout, the input impedance of the combiner 60 as seen from the output port of the carrier amplifier 10, and the input impedance of the extraction circuit 30 as seen from the output port of the carrier amplifier 10.

[0048] As in the first embodiment, the extraction circuit 30 increases the extraction current Is when the input current Iinc to the carrier amplifier 10 increases. In the second embodiment, the extraction circuit 30 further adjusts the extraction current Is in accordance with the current level of the output current Ioutc from the carrier amplifier 10. Specifically, when the current level of the output current Ioutc, for example, the amplitude, increases, the degree of increase in the extraction current Is is reduced.

[0049] 6 is an equivalent circuit diagram of the carrier amplifier 10, peak amplifier 20, and extraction circuit 30 of the Doherty amplifier according to the second embodiment. The base of the common-emitter transistor 30Qd of the extraction circuit 30 is connected to the output port of the carrier amplifier 10 via an attenuator 35. The attenuator 35 supplies a high-frequency current Ioutc1, which is a reduced current level of the output current Ioutc from the carrier amplifier 10, to the base of the common-emitter transistor 30Qd. A capacitor, for example, is used as the attenuator 35. The attenuator 35 may also be configured using a plurality of other passive elements. For example, the attenuator 35 may be configured as a circuit in which a capacitor and a resistor are connected in series.

[0050] The current level (e.g., amplitude) of the high-frequency current Ioutc1 is determined according to the input impedance when the carrier amplifier 10 sees the combiner 60 and the input impedance when the carrier amplifier 10 sees the extraction circuit 30. By changing the impedance of the attenuator 35, the current level of the high-frequency current Ioutc1 can be adjusted.

[0051] A high-frequency current Ibd obtained by combining a high-frequency current Iinc1 supplied from the input port of the carrier amplifier 10 and a high-frequency current Ioutc1 supplied from the output port of the carrier amplifier 10 is supplied to the base of the common-emitter transistor 30Qd.

[0052] 7 is a graph showing an example of waveforms of one cycle of the high-frequency current Ibd supplied to the base of the common-emitter transistor 30Qd, and the high-frequency currents Iinc1 and Ioutc1. The phase of the output current Ioutc from the carrier amplifier 10 is inverted relative to the phase of the input current Iinc to the carrier amplifier. Furthermore, at a junction P between the current path from the input node of the carrier amplifier 10 to the base of the common-emitter transistor 30Qd and the current path from the output node of the carrier amplifier 10 to the base of the common-emitter transistor 30Qd, the phases of the high-frequency current Iinc1 and the high-frequency current Ioutc1 are inverted relative to each other.

[0053] The circuit constants of the capacitor 30C (FIG. 6) and the attenuator 35 (FIG. 6) are set so that the amplitude of the high-frequency current Ioutc1 is smaller than that of the high-frequency current Iinc1. The phase of the high-frequency current Ibd is the same as that of the high-frequency current Iinc1, but its amplitude is smaller than that of the high-frequency current Iinc1. That is, when the first embodiment (FIG. 2) and the second embodiment (FIG. 6) are compared under the same operating conditions, the amplitude of the high-frequency current Ibd supplied to the base of the common-emitter transistor 30Qd is smaller in the second embodiment than in the first embodiment. When the amplitude of the high-frequency current Ibd decreases, the self-bias effect on the common-emitter transistor 30Qd weakens, thereby reducing the pull-out current Is.

[0054] 8 is a graph showing the relationship between the gain and the extracted current and the output power Pout. The upper graph in Fig. 8 shows the relationship between the output power Pout of the Doherty amplifier and the gain of the peak amplifier 20, and the lower graph shows the relationship between the output power Pout of the Doherty amplifier and the extracted current Is.

[0055] Assume that a sink current Is0 is obtained for output power Pout when the load impedance ZL ( FIG. 1 ) matches the design value and the voltage standing wave ratio (VSWR) is 1. In the second embodiment, the amplitude of the high-frequency current Ibd ( FIG. 6 ) supplied to the base of the common-emitter transistor 30Qd is smaller than in the first embodiment ( FIG. 4 ). Therefore, the degree of increase in sink current Is0 when output power Pout increases is suppressed compared to the degree of increase in sink current Is shown in FIG. 4 .

[0056] When the load impedance ZL (FIG. 1) becomes higher than the design value, the amplitude of the output current Ioutc from the carrier amplifier 10 increases. When the amplitude of the output current Ioutc increases, the amplitude of the high-frequency current Ioutc1 (FIG. 6) after passing through the attenuator 35 also increases. When the amplitude of the high-frequency current Ioutc1 increases, the amplitude of the high-frequency current Ibd supplied to the base of the common-emitter transistor 30Qd decreases, as described with reference to FIG. 7.

[0057] This reduces the self-bias effect appearing in the grounded-emitter transistor 30Qd, resulting in the draw-out current Is1 being smaller than the draw-out current Is0 when the VSWR is 1. In the range up to when the draw-out current Is0 reaches its maximum value Ismax, the amount of decrease in the draw-out current Is1 relative to the draw-out current Is0 increases as the output power Pout increases.

[0058] When the sink current Is1 becomes lower than the sink current Is0, the effect of reducing the effective bias current Ibpe ( FIG. 5 ) of the peak amplifier 20 weakens. As a result, the power level of the output power Pout at which the gain Gp1 of the peak amplifier 20 rises shifts to the lower power side compared to the gain Gp0 of the peak amplifier 20 when the VSWR is 1. Furthermore, the gain Gp1 reaches a sufficiently large level even at a lower output power Pout compared to the gain Gp0.

[0059] When the load impedance ZL (FIG. 1) becomes lower than the design value, the amplitude of the output current Ioutc from the carrier amplifier 10 becomes smaller. Therefore, contrary to the case of the draw-out current Is1 when the load impedance ZL (FIG. 1) becomes higher than the design value, the draw-out current Is2 becomes larger than the draw-out current Is0 when the VSWR is 1.

[0060] An increase in the sink current Is2 strengthens the effect of reducing the effective bias current Ibpe (FIG. 5) of the peak amplifier 20. As a result, the power level of the output power Pout at which the gain Gp2 of the peak amplifier 20 rises shifts to the higher power side relative to the gain Gp0 of the peak amplifier 20 when the VSWR is 1.

[0061] Next, the excellent effects of the second embodiment will be described with reference to FIG. 9 . FIG. 9 is a graph showing the relationship between gain and output power Pout. The upper graph in FIG. 9 shows the gain when the load impedance ZL is a design value (e.g., 50 Ω), i.e., when the impedance is matched between the Doherty amplifier and the load impedance ZL and the VSWR is 1. The middle graph shows the gain of the Doherty amplifier according to the comparative example when the load impedance ZL is higher than 50 Ω. The lower graph shows the gain of the Doherty amplifier according to the second embodiment when the load impedance ZL is higher than 50 Ω. In these graphs, the horizontal axis represents the output power Pout of the Doherty amplifier, and the vertical axis represents the gain. In addition, the dashed line in each graph represents the gain Gp of the peak amplifier, the thin solid line represents the gain Gc of the carrier amplifier, and the thick solid line represents the total gain Gt of the Doherty amplifier.

[0062] When the impedance is matched, as shown in the upper graph, the gain Gp of the peak amplifier is adjusted to the power level P １ This ensures sufficient flatness of the gain Gt of the Doherty amplifier.

[0063] When the load impedance ZL becomes higher than 50Ω, impedance matching cannot be achieved, and the power level P of the output power Pout when the gain Gc of the carrier amplifier begins to decrease is ２ is the power level P when the impedance is matched. １ Furthermore, the amount of decrease in the gain Gc of the carrier amplifier when the output power Pout increases becomes larger than the amount of decrease when the impedance is matched.

[0064] In the comparative example shown in the middle of FIG. 9, even if the load impedance ZL becomes higher than 50Ω, the gain Gc of the carrier amplifier remains constant at the power level P １ Therefore, the gain Gt of the Doherty amplifier rises when the output power Pout rises to the power level P ２ In this range, the impedance is significantly reduced compared to when the impedance is matched. That is, the linearity of the input / output characteristics is not maintained when the output power Pout increases.

[0065] In the second embodiment, when the load impedance ZL becomes higher than 50Ω, as described with reference to FIG. 8, the gain Gp1 of the peak amplifier 20 (FIG. 6) rises earlier than the gain Gp0 when the impedance is matched, and the gain Gp1 reaches a sufficiently high level even in a range where the output power Pout is low. For example, when the gain Gp of the peak amplifier 20 becomes higher than the power level P ２ Therefore, when the gain Gc of the carrier amplifier 10 (FIG. 6) starts to decrease, the output power Pout rises from the power level P ２ Even if the gain Gt of the carrier amplifier 10 drops to 1000 kHz, the drop in the gain Gc of the carrier amplifier 10 can be compensated for. By this operation, it is possible to ensure sufficient flatness of the gain Gt of the Doherty amplifier.

[0066] As described above, in the second embodiment, when the VSWR changes due to fluctuations in the load impedance ZL ( FIG. 1 ), the power level at which the gain of the peak amplifier 20 ( FIGS. 5 and 6 ) rises shifts in accordance with the change in VSWR. This allows the peak amplifier 20 to appropriately compensate for the drop in gain of the carrier amplifier 10 ( FIGS. 5 and 6 ) caused by changes in the load impedance ZL, ensuring sufficient flatness of the gain Gt of the Doherty amplifier.

[0067] [Third Embodiment] Next, a Doherty amplifier according to a third embodiment will be described with reference to Fig. 10 and Fig. 11. Below, description of the configuration common to the Doherty amplifier according to the second embodiment described with reference to Figs. 5 to 9 will be omitted.

[0068] 10 is an equivalent circuit diagram of the peak amplifier 20 and extraction circuit 30 of the Doherty amplifier according to the third embodiment. In the Doherty amplifier according to the third embodiment, the peak amplifier 20 is composed of a plurality of cells 20a connected in parallel with each other. Each of the plurality of cells 20a includes a peak amplifier transistor 20Q, a base ballast resistor element 20R, and an input capacitor 20C, similar to the peak amplifier 20 of the Doherty amplifier according to the first embodiment (FIG. 2).

[0069] The collector of the peak amplifier transistor 20Q of each of the multiple cells 20a is connected to the combiner 60 via a common collector wiring 22. One end of the base ballast resistor element 20R of each of the multiple cells 20a is connected to a peak amplifier bias circuit 21 via a common bias wiring 23. One electrode of the input capacitor 20C of each of the multiple cells 20a is connected to a common input wiring 24. A peak amplifier input signal RFinp is input from the common input wiring 24 to the base of the peak amplifier transistor 20Q via the input capacitors 20C of each of the multiple cells 20a.

[0070] The extraction circuit 30 includes a plurality of common-base transistors 30Qs provided for each cell 20a. The collectors of the plurality of common-base transistors 30Qs are connected to the bases of the peak amplifier transistors 20Q of the corresponding cells 20a. The emitters of the plurality of common-base transistors 30Qs are bundled and connected to the collector of a single common-emitter transistor 30Qd.

[0071] 11 is a diagram showing the layout of elements constituting a part of the peak amplifier and extraction circuit of the Doherty amplifier according to Example 3. In Fig. 11, thin solid lines indicate conductor patterns arranged in the first wiring layer, and thick solid lines and hatched patterns surrounded by thick solid lines indicate conductor patterns arranged in the second wiring layer.

[0072] A plurality of peak amplifier transistors 20Q are arranged in a line on the surface of a semiconductor substrate, for example, a GaAs substrate. An xy Cartesian coordinate system is defined on the surface of the semiconductor substrate, with the direction in which the plurality of peak amplifier transistors 20Q are arranged being the x-axis direction. A plurality of input capacitors 20C and a plurality of common-base transistors 30Qs are also arranged in a line in the x-direction. Furthermore, a second common wiring 26, a first common wiring 25, a bias wiring 23, and a collector wiring 22 are arranged extending in the x-direction.

[0073] The collector wiring 22, the row of peak amplifier transistors 20Q, the row of input capacitors 20C, the row of common-base transistors 30Qs, the second common wiring 26, the first common wiring 25, and the bias wiring 23 are arranged in this order in the positive direction of the y-axis.

[0074] Each of the multiple input capacitors 20C is formed in an overlapping region between an input capacitor lower wiring 23b arranged in the first layer and an input wiring 24 arranged in the second layer. Each of the multiple input capacitor lower wirings 23b is connected to the base of a peak amplifier transistor 20Q via a wiring in the first layer. The input wiring 24 extends in the x direction and is shared by the multiple input capacitors 20C.

[0075] The plurality of input capacitor lower wirings 23b are each connected to a common bias wiring 23 via a base ballast resistor element 20R and a bias individual wiring 23a. The base ballast resistor element 20R is arranged in the first wiring layer between the second common wiring 26 and the row of input capacitors 20C, and the bias individual wiring 23a is arranged in the second wiring layer. The bias individual wiring 23a intersects with the first common wiring 25 and the second common wiring 26 in the first layer.

[0076] The collectors of the common-base transistors 30Qs are connected to the input capacitor lower wiring 23b via the first wiring layer. The bases of the common-base transistors 30Qs are connected to a common second common wiring 26 via resistor elements 30Rs. The resistor elements 30Rs are disposed in the first wiring layer between the second common wiring 26 and the row of common-base transistors 30Qs. The second common wiring 26 is connected to a constant current source 30CC (FIG. 2).

[0077] The emitters of the common-base transistors 30Qs are connected to a common first common wiring 25 via first individual wiring 25a. The first individual wiring 25a is arranged in the second wiring layer and intersects with the second common wiring 26 in the first wiring layer. The first common wiring 25 is connected to the collector of the common-emitter transistor 30Qd (FIG. 10).

[0078] The matching circuit 52 is disposed on the positive side of the y-axis relative to the bias wiring 23. The input wiring 24 in the second layer is connected to the matching circuit 52 at a position that does not overlap with the row of the plurality of common-base transistors 30Qs in the x-direction. The input wiring 24 in the second layer intersects with the second common wiring 26, the first common wiring 25, and the bias wiring 23 in the first layer. A peak amplifier input signal RFinp is input to each of the input capacitors 20C via the matching circuit 52 and the input wiring 24. Note that in FIG. 2 , a matching circuit is not inserted between the peak amplifier 20 and the divider 50. In this configuration where a matching circuit is not inserted, the divider 50 is disposed at the position of the matching circuit 52 in FIG. 11 . Also, in FIG. 2 , a matching circuit may be inserted between the peak amplifier 20 and the divider 50.

[0079] The collectors of the plurality of peak amplifier transistors 20Q are connected via individual collector wirings 22a to a common collector wiring 22. The individual collector wirings 22a and the common collector wiring 22 are arranged in the first wiring layer.

[0080] A ground pad 40 extending in the x direction is arranged so as to overlap with the row of the plurality of peak amplifier transistors 20Qs. The ground pad 40 is arranged in the second wiring layer and is connected to the emitters of the plurality of peak amplifier transistors 20Q. A ground bump (not shown) is arranged so as to overlap with the ground pad 40. The ground bump has the function of applying a ground potential GND to the ground pad 40 and also functions as a heat dissipation path from the peak amplifier transistor 20Q. In order to ensure stability of the ground potential GND and sufficient heat dissipation characteristics, it is preferable that the dimensions of the ground bump and the ground pad 40 in the y direction be larger than the dimensions of the peak amplifier transistor 20Q in the y direction.

[0081] Next, the reason why the common-base transistor 30Qs of the extraction circuit 30 is provided for each cell 20a will be explained. If there is temperature variation among the multiple cells 20a, current will concentrate in the relatively hotter cell 20a, causing the temperature of the hotter cell 20a to rise further. In this way, current may concentrate in a specific cell 20a, leading to thermal runaway. If the bias current of a specific cell 20a increases, the voltage drop due to the base ballast resistor element 20R increases. This increased voltage drop reduces the collector current, suppressing thermal runaway. In this way, the voltage drop due to the base ballast resistor element 20R must occur independently for each cell 20a.

[0082] In a configuration in which only one common-base transistor 30Qs of the extraction circuit 30 is provided for each of the plurality of cells 20a, one end of the base ballast resistor element 20R of each of the plurality of cells 20a is connected to the collector of the single common-base transistor 30Qs. In this configuration, the plurality of base ballast resistor elements 20R are connected in parallel with each other, and the voltage drop due to the base ballast resistor element 20R becomes the same among the plurality of cells 20a. This makes it impossible to suppress thermal runaway caused by current concentration in a specific cell 20a.

[0083] By providing a common-base transistor 30Qs for each cell 20a, the voltage drop due to the base ballast resistor element 20R occurs independently for each cell 20a, thereby maintaining the effect of suppressing thermal runaway.

[0084] Like the peak amplifier 20, the carrier amplifier 10 (FIG. 1) is also composed of a plurality of cells connected in parallel with each other.

[0085] Next, the advantageous effects of the third embodiment will be described. In the third embodiment, the peak amplifier 20 is composed of a plurality of cells 20a, and the carrier amplifier 10 (FIG. 1) is also composed of a plurality of cells, so that the output power can be increased.

[0086] Next, a Doherty amplifier according to a modification of the third embodiment will be described with reference to Fig. 12. Fig. 12 is a diagram showing the layout of some elements of the peak amplifier and extraction circuit of the Doherty amplifier according to the modification of the third embodiment.

[0087] The Doherty amplifier according to the third embodiment ( FIG. 11 ) has two wiring layers. In contrast, the Doherty amplifier according to a modification of the third embodiment shown in FIG. 12 has three wiring layers. In FIG. 12 , thin solid lines indicate conductor patterns arranged in the first wiring layer, thick solid lines and patterns with hatching that slopes upward to the right and surrounded by the thick solid lines indicate conductor patterns arranged in the second wiring layer, and patterns with hatching that slopes downward to the right and surrounded by thick dashed lines indicate conductor patterns arranged in the third wiring layer.

[0088] In the third embodiment (FIG. 11) shown in FIG. 11, the input wiring 24 is arranged in the second wiring layer. In contrast, in the modified example of the third embodiment shown in FIG. 12, the input wiring 24 is composed of a second-layer input wiring 24A arranged in the second wiring layer and a third-layer input wiring 24B arranged in the third wiring layer. The second-layer input wiring 24A overlaps with multiple input capacitor lower wirings 23b, and input capacitors 20C are formed in the overlapping portions. The third-layer input wiring 24B extends in the positive direction of the y-axis from the point where it overlaps with the second-layer input wiring 24A, intersects with the row of common-base transistors 30Qs, the second common wiring 26, the first common wiring 25, and the bias wiring 23, and reaches the matching circuit 52. The second-layer input wiring 24A and the third-layer input wiring 24B are connected to each other in the overlapping region.

[0089] In the third embodiment ( FIG. 11 ), the ground pad 40 is arranged on the second wiring layer. In contrast, in a modification of the third embodiment shown in FIG. 12 , the ground pad 40B is arranged on the third wiring layer. The ground pad 40B on the third layer is connected to the emitters of the plurality of peak amplifier transistors 20Q via a conductor pattern 40A arranged on the second wiring layer. The dimension in the y direction of the conductor pattern 40A on the second layer is smaller than the dimension in the y direction of the ground pad 40B on the third layer.

[0090] A portion of the second-layer input wiring 24A on the negative side of the y-axis overlaps a portion of the third-layer ground pad 40B on the positive side of the y-axis. Furthermore, a portion of the input capacitor lower wiring 23b on the negative side of the y-axis also overlaps a portion of the ground pad 40B on the positive side of the y-axis. That is, a portion of the input capacitor 20C overlaps a portion of the ground pad 40B. Therefore, in the modification of the third embodiment shown in FIG. 12 , the distance in the y-direction between the peak amplifier transistor 20Q and the input capacitor 20C is narrower than in the third embodiment shown in FIG. 11 .

[0091] The modified example of the third embodiment shown in Figure 12 has three wiring layers, which is disadvantageous in terms of manufacturing cost compared to the third embodiment (Figure 11) which has two wiring layers. However, since the input wiring 24B can cross the row of common-base transistors 30Qs, the dimension of the input wiring 24 in the x direction can be reduced compared to the third embodiment. Furthermore, since the distance in the y direction between the input capacitor 20C and the peak amplifier transistor 20Q can be reduced compared to the third embodiment, the dimension of the Doherty amplifier in the y direction can be reduced.

[0092] Furthermore, since the third-layer input wiring 24B connecting the second-layer input wiring 24A and the matching circuit 52 is arranged at a position where it intersects with the common-base transistor 30Qs, the bias wiring 23, the first common wiring 25, and the second common wiring 26, it is possible to reduce the dimension of the Doherty amplifier in the x-direction.

[0093] Next, a Doherty amplifier according to another modification of the third embodiment will be described with reference to Fig. 13. Fig. 13 is a diagram showing the layout of some elements of the peak amplifier and extraction circuit of the Doherty amplifier according to another modification of the third embodiment.

[0094] 13, a column of a plurality of common-base transistors 30Qs, a first common wiring 25, and a second common wiring 26 are arranged in the y direction between a column of a plurality of peak amplifier transistors 20Q and a column of a plurality of input capacitors 20C. The first common wiring 25 and the second common wiring 26 intersect with the first-layer wiring that connects the input capacitor lower wiring 23b to the bases of the peak amplifier transistors 20Q, and therefore the first common wiring 25 and the second common wiring 26 are arranged in the second wiring layer.

[0095] Similar to the configuration of the third embodiment ( FIG. 11 ), bias wiring 23 is arranged between the column of input capacitors 20C and matching circuit 52. Base ballast resistor 20R is arranged between the column of input capacitors 20C and bias wiring 23. Bias wiring 23 and base ballast resistor 20R, which are arranged between the column of input capacitors 20C and matching circuit 52, are both arranged in the first wiring layer. Input wiring 24, which is arranged in the second wiring layer, extends in the y direction from a region overlapping with the column of input capacitors 20C, passing through a region overlapping with bias wiring 23 and base ballast resistor 20R without passing through another wiring layer, and reaches matching circuit 52.

[0096] The first individual wiring 25a, which connects the emitters of the plurality of common base transistors 30Qs to the common first common wiring 25, is disposed in the first wiring layer. The resistance elements 30Rs and wiring, which connect the bases of the plurality of common base transistors 30Qs to the common second common wiring 26, are disposed in the first wiring layer.

[0097] The plurality of common-base transistors 30Qs are arranged at positions overlapping the ground pad 40.

[0098] Next, an explanation will be given of the advantageous effects of the modification of the third embodiment shown in Fig. 13. In the modification of the third embodiment shown in Fig. 13, a plurality of commoned base transistors 30Qs are arranged in positions that overlap with the ground pad 40. This prevents an increase in the area required to arrange the commoned base transistors 30Qs, etc.

[0099] Furthermore, in the third embodiment ( FIG. 11 ), the row of common-base transistors 30Qs, the second common wiring 26, the first common wiring 25, and the bias wiring 23 are arranged between the row of input capacitors 20C and the matching circuit 52. In contrast, in the modified example of the third embodiment shown in FIG. 13 , the row of common-base transistors 30Qs, the second common wiring 26, and the first common wiring 25 are not arranged between the row of input capacitors 20C and the matching circuit 52. This shortens the dimension in the y direction of the portion of the input wiring 24 that connects the portion extending in the x direction and functioning as the upper electrode of the input capacitor 20C to the matching circuit 52. This shortens the wiring length from the matching circuit 52 to the input capacitor 20C. As a result, an increase in parasitic inductance caused by the wiring is suppressed.

[0100] 13, the portion of input wiring 24 that overlaps with input capacitor 20C and that connects matching circuit 52 is arranged to overlap bias wiring 23 and base ballast resistor element 20R. Therefore, similar to the modification of the third embodiment shown in FIG. 12, it is possible to reduce the dimension of the Doherty amplifier in the x direction.

[0101] [Fourth Embodiment] Next, a Doherty amplifier according to a fourth embodiment will be described with reference to Fig. 14. Below, description of the configuration common to the Doherty amplifier according to the second embodiment described with reference to Figs.

[0102] 14 is an equivalent circuit diagram of the Doherty amplifier according to Example 4. The Doherty amplifier according to Example 2 amplifies a single-ended signal, but the Doherty amplifier according to Example 4 amplifies a differential signal.

[0103] The Doherty amplifier according to the fourth embodiment includes a first carrier amplifier 10A, a first peak amplifier 20A, a second carrier amplifier 10B, and a second peak amplifier 20B. The first carrier amplifier 10A and the second carrier amplifier 10B configure a differential amplifier, and the first peak amplifier 20A and the second peak amplifier 20B configure a differential amplifier.

[0104] The configurations of the first carrier amplifier 10A and the second carrier amplifier 10B are the same as the carrier amplifier 10 (FIG. 6) of the Doherty amplifier according to the second embodiment. The configurations of the first peak amplifier 20A and the second peak amplifier 20B are the same as the peak amplifier 20 (FIG. 6) of the Doherty amplifier according to the second embodiment.

[0105] Non-inverting input signal RFinc for carrier amplifier ＋ and carrier amplifier inverting input signal RFinc － are input to the first carrier amplifier 10A and the second carrier amplifier 10B, respectively. ＋ and the peak amplifier inverting input signal RFinp － are input to the first peak amplifier 20A and the second peak amplifier 20B, respectively.

[0106] Non-inverting input signal RFinc for carrier amplifier ＋ is the non-inverting input signal RFinp for the peak amplifier ＋ The phase is delayed by 90° with respect to the carrier amplifier inverting input signal RFinc － is the non-inverting input signal RFinc for the carrier amplifier ＋ Similarly, the phase of the inverted input signal RFinp for the peak amplifier is inverted. － is the non-inverting input signal RFinp for the peak amplifier ＋ The phase is inverted relative to

[0107] Output current Ioutc from the first carrier amplifier 10A ＋ and the output current Ioutp from the first peak amplifier 20A. ＋ is input to the first combiner 60A. The output current Ioutc from the second carrier amplifier 10B － and the output current Ioutp from the second peak amplifier 20B － is input to the second combiner 60B.

[0108] The first extraction circuit 30A is connected to the input node and the output node of the first carrier amplifier 10A, and outputs an extraction current Is for a non-inverted signal. ＋A non-inverted signal extraction current Is is generated from the bias current Ibp supplied to the first peak amplifier 20A. ＋ is drawn out, and the remaining effective bias current Ibpe ＋ is supplied to the base of the peak amplifier transistor 20Q of the first peak amplifier 20A.

[0109] Similarly, a second extraction circuit 30B is connected to the input node and the output node of the second carrier amplifier 10B, and outputs an extraction current Is for an inverted signal. － The bias current Ibp supplied to the second peak amplifier 20B is used to generate a subtraction current Is for the inverted signal. － is drawn out, and the remaining effective bias current Ibpe － is supplied to the base of the peak amplifier transistor 20Q of the second peak amplifier 20B.

[0110] Next, the advantageous effects of the fourth embodiment will be described. In the fourth embodiment, a low-noise Doherty amplifier is configured by using differential amplifiers for the carrier amplifier 10 (FIG. 1) and the peak amplifier 20 (FIG. 1). Furthermore, in the fourth embodiment, the first extraction circuit 30A extracts the carrier amplifier non-inverting input signal RFinc input to the input node of the first carrier amplifier 10A. ＋ The second extraction circuit 30B adjusts the bias current supplied to the first peak amplifier 20A based on the high frequency current of the carrier amplifier inverted input signal RFinc input to the input node of the second carrier amplifier 10B. － The bias current supplied to the second peak amplifier 20B is adjusted based on the high-frequency current of the first peak amplifier 20. Therefore, similar to the first embodiment described with reference to FIGS. 1 to 4, it is possible to suppress a decrease in PAE when amplifying a signal with a high PAPR.

[0111] Furthermore, in the fourth embodiment, the first extraction circuit 30A extracts the output signal RFoutc output from the output node of the first carrier amplifier 10A. ＋ The bias current supplied to the first peak amplifier 20A is adjusted based on the high frequency current of the second carrier amplifier 10B, and the second extraction circuit 30B adjusts the bias current supplied to the first peak amplifier 20A based on the high frequency current of the second carrier amplifier 10B. －The bias current supplied to the second peak amplifier 20B is adjusted based on the high-frequency current of the second peak amplifier 20B. Therefore, similar to the second embodiment described with reference to FIGS. 5 to 9, it is possible to ensure sufficient flatness of the gain of the Doherty amplifier even when the load impedance ZL fluctuates.

[0112] The above-described embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects resulting from similar configurations of multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the above-described embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible.

[0113] 10 Carrier amplifier 10A First carrier amplifier 10B Second carrier amplifier 10C Input capacitor 10Q Carrier amplifier transistor 10R Base ballast resistor element 11 Carrier amplifier bias circuit 20 Peak amplifier 20a Peak amplifier cell 20A First peak amplifier 20B Second peak amplifier 20C Input capacitor 20Q Peak amplifier transistor 20R Base ballast resistor element 21 Peak amplifier bias circuit 21C Capacitor 21D Diode circuit 21Q Emitter follower transistor 21R Resistor element 22 Collector wiring 22a Collector individual wiring 23 Bias wiring 23a Bias individual wiring 23b Input capacitor lower wiring 24 Input wiring 24A Second layer input wiring 24B Third layer input wiring 25 First common wiring 25a First individual wiring 26 Second common wiring 30 Pull-out circuit 30A First extraction circuit 30B Second extraction circuit 30C Capacitor 30CC Constant current source 30Qd Common-emitter transistor 30Qs Common-base transistor 30Rd, 30Rs Resistor element 35 Attenuator 40 Second-layer ground pad 40A Second-layer conductor pattern 40B Third-layer ground pad 50 Divider 51 Non-reflective termination resistor element 52 Matching circuit 60 Combiner 60A First combiner 60B Second combiner 61 90° phase shifter 70 Impedance matching circuit 71 Load

Claims

1. A Doherty amplifier comprising: a carrier amplifier; a peak amplifier; a bias circuit for the carrier amplifier that supplies a bias to the carrier amplifier; a bias circuit for the peak amplifier that supplies a bias to the peak amplifier; and a extraction circuit that extracts a part of the bias current supplied from the bias circuit for the peak amplifier to the peak amplifier, wherein the extraction circuit includes a cascode circuit in which a base-grounded transistor and an emitter-grounded transistor are cascode-connected, a collector of the base-grounded transistor is connected to the peak amplifier, and a base of the emitter-grounded transistor is connected to an input node of the carrier amplifier.

2. The Doherty amplifier according to claim 1, wherein a current flowing through the cascode circuit is extracted from the bias current supplied from the bias circuit for the peak amplifier to the peak amplifier.

3. The Doherty amplifier according to claim 1 or 2, wherein the base of the emitter-grounded transistor is further connected to an output node of the carrier amplifier.

4. The Doherty amplifier according to claim 3, wherein the extraction circuit includes an attenuator that makes an amplitude of a high-frequency current input to the base of the emitter-grounded transistor among output currents output from an output node of the carrier amplifier smaller than an amplitude of a high-frequency current input to the base of the emitter-grounded transistor among input currents input to an input node of the carrier amplifier.

5. The Doherty amplifier according to any one of claims 1 to 4, wherein the carrier amplifier includes a first carrier amplifier and a second carrier amplifier that constitute a differential amplifier, the peak amplifier includes a first peak amplifier and a second peak amplifier that constitute a differential amplifier, the bias circuit for the peak amplifier supplies a bias current to the second peak amplifier and the first peak amplifier, and the extraction circuit includes a first extraction circuit that is connected to an input node of the first carrier amplifier and extracts a part of the bias current supplied to the first peak amplifier, and a second extraction circuit that is connected to an input node of the second carrier amplifier and extracts a part of the bias current supplied to the second peak amplifier.

6. The Doherty amplifier according to claim 5, wherein the first extraction circuit is further connected to the output node of the first carrier amplifier, and the second extraction circuit is further connected to the output node of the second carrier amplifier.

7. The Doherty amplifier according to any one of claims 1 to 6, wherein the peak amplifier includes a plurality of cells connected in parallel with each other, and each of the plurality of cells includes a transistor for the peak amplifier and a base ballast resistor element inserted in a bias supply path from the bias circuit for the peak amplifier to the base of the transistor for the peak amplifier, and the base-grounded transistor of the extraction circuit is provided for each of the plurality of cells.

8. A Doherty amplifier comprising: a carrier amplifier; a peak amplifier; a bias circuit for the carrier amplifier that supplies a bias to the carrier amplifier; a bias circuit for the peak amplifier that supplies a bias to the peak amplifier; and an extraction circuit that extracts a current depending on the amplitude of an input current input to the carrier amplifier from a bias current supplied from the bias circuit for the peak amplifier to the peak amplifier.

9. The Doherty amplifier according to claim 8, wherein the extraction circuit further extracts a current depending on the amplitude of an input current input to the carrier amplifier and the amplitude of an output current from a bias current supplied from the bias circuit for the peak amplifier to the peak amplifier.

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