Signal transmission system and signal transmission method

Abstract

A signal transmission system (200) comprises: a plurality of control units (220-1, 220-2..., 220-n); and a signal distribution device (210) for distributing, to the plurality of control units (220-1, 220-2..., 220-n), a clock signal (CK) and a long-period signal (LP) synchronized with the clock signal (CK) and having a period that is at least double the period of the clock signal (CK). The signal distribution device (210) is provided with a modulation circuit that generates a modulation signal (MD) in which the long period signal (LP) is superimposed on the clock signal (CK) by modulating the long period signal (LP) with the clock signal (CK), and distributes the modulation signal (MD) to the plurality of control units (220-1, 220-2..., 220-n) via transmission paths (230-1, 230-2..., 230-n), respectively.

Description

Signal transmission system and signal transmission method

[0001] The present invention relates to a signal transmission system and a signal transmission method.

[0002] In large-scale computer systems such as large-scale quantum computer systems, multiple control units must operate in high-precision synchronization based on a low-jitter clock signal. For long-term stable operation of such large-scale computer systems, it is necessary to distribute a low-jitter clock signal and a long-period signal synchronized with that clock signal to the multiple control units.

[0003] 1 shows the configuration of a signal transmission system 100 in a conventional large-scale computer system. The signal transmission system 100 includes a signal distribution device 110 and multiple control units 120-1, 120-2, ..., 120-n (n is an integer equal to or greater than 2) connected to the signal distribution device 110. The signal distribution device 110 generates a low-jitter clock signal CK and a long-cycle signal LP, and distributes the clock signal CK and the long-cycle signal LP to the multiple control units 120-1, 120-2, ..., 120-n via separate transmission paths (cables) (see, for example, Patent Document 1).

[0004] Patent No. 7303506

[0005] In the conventional signal transmission system 100, the clock signal CK and the long-period signal LP were transmitted to each control unit via separate transmission paths. This required adjustment of cable length and temperature control of the distribution mechanism to suppress fluctuations between the clock signal CK and the long-period signal LP, which presented difficulties. Furthermore, low-loss transmission is required to distribute the long-period signal LP to multiple control units over long distances. However, the long period of the long-period signal LP is so long that it is virtually impossible to transmit it even using an optical cable designed for long-distance, low-loss transmission. Furthermore, increasing the number and length of cables required to build a large-scale computer system makes solving the above-mentioned problems even more difficult and increases costs.

[0006] The present invention has been made in view of the above-mentioned problems, and aims to provide a signal transmission system and a signal transmission method that can easily and inexpensively distribute a clock signal and a long-period signal synchronized with the clock signal.

[0007] A signal transmission system according to the present invention includes a plurality of control units, and a signal distribution device for distributing a clock signal and a long-cycle signal synchronized with the clock signal and having a cycle at least twice that of the clock signal to the plurality of control units. The signal distribution device includes a modulation circuit that modulates the long-cycle signal with the clock signal to generate a modulated signal in which the long-cycle signal is superimposed on the clock signal, and distributes the modulated signal to the plurality of control units via a transmission path.

[0008] The signal transmission method of the present invention is a method for distributing a clock signal and a long-period signal synchronized with the clock signal and having a period at least twice that of the clock signal to a plurality of control units using a signal distribution device, in which a modulation circuit of the signal distribution device modulates the long-period signal with the clock signal to generate a modulated signal in which the long-period signal is superimposed on the clock signal, and the signal distribution device distributes the modulated signal to the plurality of control units via a transmission path.

[0009] According to the present invention, a modulated signal is generated by superimposing a long-cycle signal on a clock signal, and the modulated signal is transmitted via a transmission path, so that the clock signal and the long-cycle signal are distributed to each control unit via the same path. This reduces transmission fluctuations and enables the clock signal and the long-cycle signal to be distributed easily and at low cost.

[0010] 1 is a block diagram showing the configuration of a conventional signal transmission system; FIG. 2 is a block diagram showing the configuration of a signal transmission system according to an embodiment of the present invention; FIG. 3 is a configuration diagram of a modulation circuit of a signal distribution device; FIG. 4 is a configuration diagram showing an example of a distribution method for modulated signals in a signal distribution device; FIG. 5 is a configuration diagram showing another example of a distribution method for modulated signals in a signal distribution device; FIG. 6 is a timing chart of a modulation circuit when a phase shift amount δ of a clock signal is 0°<δ≦90°; FIG. 7 is a timing chart of a modulation circuit when 90°<δ<180°; FIG. 8 is a timing chart of a modulation circuit when 180°<δ≦270°; FIG. 9 is a timing chart of a modulation circuit when 270°<δ<360°; FIG. 10 is a configuration diagram of a demodulation circuit of each control unit; FIG. 11 is a timing chart of a clock signal recovery circuit; FIG. 12 is an example of a configuration diagram of a long cycle signal recovery circuit; FIG. 13 is a timing chart of the long cycle signal recovery circuit shown in FIG. 7A; FIG. 14 is a configuration diagram of a long cycle signal recovery circuit as a modification of FIG. 7A; FIG. 15 is a timing chart of the long cycle signal recovery circuit shown in FIG. 16A; FIG. 17 is a configuration diagram showing another example of a long cycle signal recovery circuit; FIG. 18 is a timing chart of the long cycle signal recovery circuit shown in FIG. 19A.

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. The present embodiments are directed to a signal transmission system and a signal transmission method that are applied to a large-scale computer system such as a large-scale quantum computer system.

[0012] 2 shows the configuration of a signal transmission system 200 according to this embodiment. The signal transmission system 200 includes a signal distribution device 210 and a plurality of control units 220-1, 220-2, ..., 220-n connected to the signal distribution device 210 via transmission paths 230-1, 230-2, ..., 230-n (n is an integer of 2 or greater), respectively.

[0013] The signal distribution device 210 is a device for distributing a low-jitter clock signal CK and a long-cycle signal LP synchronized with the clock signal CK to a plurality of control units 220-1, 220-2, ..., 220-n. The frequency range of the clock signal CK is 10 MHz to 100 GHz. The frequency range of the long-cycle signal LP is 1 Hz or more and less than half the frequency of the clock signal CK (more than twice the cycle of the clock signal CK). In this embodiment, the long-cycle signal LP has the same pulse width as the clock signal CK, but is not limited to this.

[0014] The signal distribution device 210 includes a modulation circuit 310 (FIG. 3A) for generating a modulated signal MD in which the long-period signal LP is superimposed on the clock signal CK by modulating the long-period signal LP with the clock signal CK by pulse width modulation (PWM). The modulated signal MD is distributed to the control units 220-1, 220-2, ..., 220-n via transmission paths 230-1, 230-2, ..., 230-n, respectively.

[0015] As shown in FIG. 3A, the modulation circuit 310 includes a clock generation source 312 , a long-period signal generation circuit 314 , a phase shift circuit 316 , an OR gate 318 , and an AND gate 320 .

[0016] A clock generation source 312 generates a clock signal CK. The clock signal CK from the clock generation source 312 is output to a long cycle signal generation circuit 314, a phase shift circuit 316, and an AND gate 320. The long cycle signal generation circuit 314 generates a long cycle signal LP from the clock signal CK. The phase shift circuit 316 obtains a phase-shifted signal M1 by shifting the phase of the clock signal CK. The range of the phase shift amount of the clock signal CK will be described later (see FIGS. 4A to 4D).

[0017] The OR gate 318 performs an OR operation on the phase shift signal M1 and the long cycle signal LP to output a composite signal M2 of the phase shift signal M1 and the long cycle signal LP. The AND gate 320 performs an AND operation on the composite signal M2 and the clock signal CK to output a modulated signal MD.

[0018] At least some of the functions of the modulation circuit 310 can be implemented by a programmable logic device such as a Field Programmable Gate Array (FPGA) or an application specific integrated circuit (ASIC).

[0019] In this embodiment, the modulated signal MD can be distributed using any distribution method. For example, the signal distribution device 210 includes n modulation circuits 310, and the n modulated signals MD generated by the n modulation circuits 310 can be transmitted to the control units 220-1, 220-2, ..., 220-n via the transmission paths 230-1, 230-2, ..., 230-n, respectively.

[0020] If the transmission paths 230-1, 230-2, ..., 230-n are optical cables, a converter that converts the modulated signal MD, which is an electrical signal, into an optical signal may be provided at the output stage of each modulation circuit 310. In this case, the n optical signals output from the n converters are transmitted to the control units 220-1, 220-2, ..., 220-n via the transmission paths 230-1, 230-2, ..., 230-n, respectively.

[0021] As another distribution method, one modulated signal MD generated by one modulation circuit 310 may be divided into n modulated signals MD by a passive divider.

[0022] 3B, an amplifier 332 amplifies the modulated signal MD generated by the modulation circuit 310 by a gain of n times, and a divider 334 divides the amplified signal into n signals. Although the n signals are attenuated by the division by the divider 334, because the original modulated signal MD was amplified before attenuation, the n signals have the same signal level as the original modulated signal MD.

[0023] 3C, a divider 342 may divide the modulated signal MD generated by the modulation circuit 310 into n signals, and n amplifiers 344-1, 344-2, ..., 344-n may amplify each of the n signals by a gain of n. Although the n signals are attenuated by the division by the divider 342, the signal level of the original modulated signal MD is maintained because the n signals are amplified by the n amplifiers 344-1, 344-2, ..., 344-n.

[0024] If the transmission paths 230-1, 230-2, ..., 230-n are electrical cables, a radio frequency (RF) distributor can be used as the distributor. If the transmission paths 230-1, 230-2, ..., 230-n are optical cables, an optical amplifier and an optical distributor can be used as the amplifier and distributor, respectively. In this case, a converter that converts the modulated signal MD, which is an electrical signal, into an optical signal is provided at the output stage of the modulation circuit 310, and the optical signal output from the converter is input to the circuit of Figure 3B or Figure 3C. Note that other circuit configurations may be used as long as they can output an optical signal to an optical cable. For example, a converter may be provided between the amplifier and the distributor.

[0025] By using the dividers 334 and 342 shown in Figures 3B and 3C, the signal distribution device 210 only needs to include one modulation circuit 310, and can obtain n modulated signals MD with a simple configuration. Furthermore, amplifiers and dividers are less expensive and easier to obtain than AND gates, and are less susceptible to phase noise degradation. Therefore, the configurations shown in Figures 3B and 3C are superior in cost, availability, and performance to a configuration including n modulation circuits 310 each having an AND gate 320.

[0026] 1 includes a divider for dividing one clock signal CL into n clock signals CK and a divider for dividing one long cycle signal LP into n long cycle signals LP, there is a risk of skew occurring between these two dividers. On the other hand, in the configurations of Figures 3B and 3C, the signal distribution device 210 only needs to include one divider, so such skew does not occur.

[0027] Next, the range of the phase shift amount δ of the clock signal CK in the phase shift circuit 316 will be described with reference to the timing charts of FIGS. 4A to 4D.

[0028] When 0<δ≦90° (FIG. 4A), the frequency of the modulation signal MD is kept constant based on the falling edge, just like the clock signal CK, but the frequency based on the rising edge is not constant (see the dotted double arrow in FIG. 4A).

[0029] As shown in FIGS. 4A to 4D, a pulse W (hereinafter referred to as a long-period pulse) having a relatively long pulse width appears in the modulation signal MD in the cycle of the long-period signal LP, and the pulse width of the long-period pulse W is the same as that of the clock signal CK and the long-period signal LP.

[0030] Even when 90°<δ<180° (FIG. 4B), the frequency of the modulation signal MD based on the falling edge is kept constant, just like the clock signal CK, but the frequency based on the rising edge is not constant (see the dotted double arrow in FIG. 4B).

[0031] On the other hand, when 180°<δ≦270° (FIG. 4C) and when 270°<δ<360° (FIG. 4D), the frequency of the modulated signal MD based on the rising edge is kept constant with jitter accuracy equivalent to that of the clock signal CK.

[0032] Therefore, by setting δ to 180°<δ<360° (FIGS. 4C and 4D), it is possible to superimpose the long-period signal LP on the clock signal CK while maintaining the jitter accuracy of the clock signal CK, and to generate a modulated signal MD in which long-period pulses W appear in the cycle of the long-period signal LP. The actual range of δ is determined depending on the hold time required by the phase-locked loop (PLL) IC (described later) of each control unit on the demodulation side. Considering the hold time on the demodulation side, it is preferable to set δ to 225°≦δ<270°.

[0033] Each of the plurality of control units 220-1, 220-2, ..., 220-n includes a demodulation circuit 510 (Fig. 5) for demodulating the modulated signal MD. As shown in Fig. 5, the demodulation circuit 510 includes a clock signal recovery circuit 520 that obtains a clock signal RECK recovered from the modulated signal MD based on a local clock, and a long-cycle signal recovery circuit 530 that obtains a long-cycle signal RELP recovered from the modulated signal MD.

[0034] In addition, when the transmission paths 230-1, 230-2, ..., 230-n are optical cables, each of the multiple control units 220-1, 220-2, ..., 220-n is equipped with a converter that converts the modulated signal MD as an optical signal input via the optical cable into an electrical signal, and the modulated signal MD as an electrical signal output from the converter is input to the demodulation circuit 510.

[0035] The clock signal recovery circuit 520 includes a PLL. As shown in FIG. 6, the rising edge of the modulated signal MD is input to the PLL, which then outputs a recovered clock signal RECK having the same period as the rising edge of the modulated signal MD and a pulse width half that period. The recovered clock signal RECK is branched into two signals, one of which serves as an operating clock for the control unit and the other of which is output to the long-period signal recovery circuit 530.

[0036] Figure 7A shows the configuration of a long cycle signal recovery circuit 530-1 as one example of the long cycle signal recovery circuit 530, Figure 8A shows the configuration of a long cycle signal recovery circuit 530-2 as a modification of Figure 7A, and Figure 9A shows the configuration of a long cycle signal recovery circuit 530-3 as another example of the long cycle signal recovery circuit 530. Figure 7B shows a timing chart of the long cycle signal recovery circuit 530-1 shown in Figure 7A, Figure 8B shows a timing chart of the long cycle signal recovery circuit 530-2 shown in Figure 8A, and Figure 9B shows a timing chart of the long cycle signal recovery circuit 530-3 shown in Figure 9A.

[0037] The long-period signal recovery circuit 530-1 shown in FIG. 7A includes a phase shift circuit 710, a multiplier 712, sampling circuits 714 and 716, and an AND gate 718.

[0038] The phase shift circuit 710 generates a phase shift signal R1 by shifting the phase of the recovered clock signal RECK by δ / 4 or more but less than 90°, where δ is the amount of phase shift in the phase shift circuit 316 of the modulation circuit 310.

[0039] The multiplier 712 generates a high-frequency signal R2 having a frequency N times that of the phase-shifted signal R1 (N is an integer equal to or greater than 2). Fig. 7B shows an example in which the frequency of the high-frequency signal R2 is four times that of the phase-shifted signal R1.

[0040] The sampling circuit 714 is a D flip-flop that receives the modulated signal MD at the rising edge of the high-frequency signal R2 and outputs a first sampling signal R3. The sampling circuit 716 is also a D flip-flop that receives the first sampling signal R3 at the rising edge of the high-frequency signal R2 and outputs a second sampling signal R4. As shown in FIG. 7B , the second sampling signal R4 is a signal obtained by shifting the first sampling signal R3 by one period of the high-frequency signal R2.

[0041] The AND gate 718 performs an AND operation on the first sampling signal R3 and the second sampling signal R4, and outputs the reproduced long-period signal RELP.

[0042] The long-cycle signal recovery circuit 530-2 shown in FIG. 8A has the same configuration as that of FIG. 7A, in which the phase shift circuit 710 and the multiplier 712 are interchanged, and includes a multiplier 810, a phase shift circuit 812, sampling circuits 814 and 816, and an AND gate 818.

[0043] The multiplier 810 generates a first high frequency signal R11 having a frequency N times that of the recovered clock signal RECK (N is an integer equal to or greater than 2). Fig. 8B shows an example in which the frequency of the first high frequency signal R11 is four times that of the recovered clock signal RECK.

[0044] The phase shift circuit 812 generates the second high frequency signal R12 by shifting the phase of the first high frequency signal R11 by δ or more and less than 360°.

[0045] The sampling circuit 814 is a D flip-flop that captures the modulated signal MD at the rising edge of the second high-frequency signal R12 and outputs a first sampling signal R13. The sampling circuit 816 is also a D flip-flop that captures the first sampling signal R13 at the rising edge of the second high-frequency signal R12 and outputs a second sampling signal R14. As shown in FIG. 8B , the second sampling signal R14 is a signal obtained by shifting the first sampling signal R13 by one period of the second high-frequency signal R12.

[0046] The AND gate 818 performs an AND operation on the first sampling signal R13 and the second sampling signal R14, and outputs the reproduced long cycle signal RELP.

[0047] The long-cycle signal recovery circuit 530-3 shown in FIG. 9A is a circuit that outputs a long-cycle signal RELP recovered by finding a long-cycle pulse W from a modulated signal MD, and includes a multiplier 910, a counter 912, and a pulse output circuit 914.

[0048] The multiplier 910 generates a high-frequency signal R21 having a frequency N times that of the recovered clock signal RECK (N is an even number equal to or greater than 2). As shown in FIG. 9B, if the pulse width of the long-period pulse W of the modulation signal MD is 1, the pulse widths of the pulses other than the long-period pulse W are (δ-180°) / 180°. The value of N is set so that the pulse width 1 and the pulse width (δ-180°) / 180° can be distinguished (for example, N=8, N=16, etc.). An example where N=8 is shown in FIG. 9B.

[0049] The counter 912 counts the number of consecutive high level periods of the modulation signal MD at the rising edge of the high frequency signal R21 to obtain a count value R22, and outputs the count value R22 to the pulse output circuit 914. In the example of FIG. 9B , the count value R22 of the long-cycle pulse W is 4, and the count value R22 of the pulses other than the long-cycle pulse W is 3.

[0050] The pulse output circuit 914 uses the high-frequency signal R21 to output a pulse having a pulse width equivalent to the predetermined value as a pulse of the regenerated long-cycle signal RELP when the count value R22 reaches a relatively large predetermined value (i.e., when a slot having a relatively long pulse width is found). Specifically, the pulse output circuit 914 generates a pulse having a pulse width equivalent to R22=N / 2 when the count value R22 reaches half the multiplication factor (R22=N / 2). In this way, the regenerated long-cycle signal RELP is obtained.

[0051] At least some of the functions of the long-period signal recovery circuits 530-1, 530-2, and 530-3 shown in FIGS. 7A, 8A, and 9A, respectively, can be realized by a programmable logic device such as an FPGA, or an ASIC.

[0052] According to the signal transmission system 200 of this embodiment, the long-period signal LP is modulated with a low-jitter clock signal CK to generate a modulated signal MD in which the long-period signal LP is superimposed on the clock signal CK, and the modulated signal MD is distributed to the control units 220-1, 220-2, ..., 220-n via transmission paths 230-1, 230-2, ..., 230-n, respectively.

[0053] This allows the clock signal CK and the long-period signal LP to be transmitted over the same path, eliminating, in principle, any synchronization error between the clock signal CK and the long-period signal LP due to wiring length or temperature. Furthermore, compared to the conventional signal transmission system 100 shown in Figure 1, the number of transmission paths (cables) can be reduced by half, thereby reducing costs. Furthermore, since optical cables can be used in addition to electrical cables, the cable length can be increased for long-distance transmission of the long-period signal LP in large-scale computer systems.

[0054] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the spirit of the present invention. Other embodiments and modifications made by those skilled in the art are also included in the present invention.

[0055] 200 Signal transmission system 210 Signal distribution device 220-1, 220-2, 220-n Control unit 230-1, 230-2, 230-n Transmission path 310 Modulation circuit 312 Clock generation source 314 Long-period signal generation circuit 316 Phase shift circuit 318 OR gate 320 AND gate 332, 344-1, 344-2, 344-n Amplifier 334, 342 Distributor 510 Demodulation circuit 520 Clock signal recovery circuit 530, 530-1, 530-2, 530-3 Long-period signal recovery circuit 710, 812 Phase shift circuit 712, 810 Multiplier 714, 716, 814, 816 Sampling circuit 718, 818 AND gate 910 Multiplier 912 Counter 914 Pulse output circuit CK Clock signal LP Long cycle signal MD Modulation signal M1 Phase shift signal M2 Synthesized signal RECK Regenerated clock signal RELP Regenerated long cycle signal R1 Phase shift signal R2, R21 High frequency signal R3, R13 First sampling signal R4, R14 Second sampling signal R11 First high frequency signal R12 Second high frequency signal R22 Count value

Claims

1. A signal transmission system comprising a plurality of control units, a clock signal, and a signal distribution device for distributing to the plurality of control units a long-period signal having a period that is two times or more that of the clock signal and synchronized with the clock signal, wherein the signal distribution device includes a modulation circuit that generates a modulation signal in which the long-period signal is superimposed on the clock signal by modulating the long-period signal with the clock signal, and distributes the modulation signal to the plurality of control units via a transmission path.

2. The signal transmission system according to claim 1, wherein the signal distribution device generates the modulation signal by pulse width modulation.

3. The modulation circuit according to claim 1, wherein the modulation circuit obtains a phase shift signal by shifting the phase of the clock signal, obtains a composite signal of the phase shift signal and the long-period signal by performing an OR operation on the phase shift signal and the long-period signal, and generates the modulation signal by performing an AND operation on the composite signal and the clock signal.

4. The signal transmission system according to claim 3, wherein the modulation circuit obtains the phase shift signal by shifting the phase of the clock signal within a range greater than 180° and less than 360°.

5. Each of the plurality of control units includes a demodulation circuit that obtains a reproduced clock signal and a reproduced long-period signal from the modulation signal, and the demodulation circuit includes a clock signal recovery circuit that obtains the reproduced clock signal based on a rising edge of the modulation signal, and a long-period signal recovery circuit that obtains the reproduced long-period signal from the modulation signal and the reproduced clock signal.

6. The long-period signal recovery circuit generates a high-frequency signal by phase-shifting the reproduced clock signal to multiply the frequency or by multiplying the frequency of the reproduced clock signal and then phase-shifting it, samples the modulation signal with the high-frequency signal to obtain a first sampling signal, samples the first sampling signal with the high-frequency signal to obtain a second sampling signal, and performs an AND operation on the first sampling signal and the second sampling signal to obtain the reproduced long-period signal. The signal transmission system according to claim 5.

7. The long-period signal recovery circuit generates a high-frequency signal by multiplying the frequency of the reproduced clock signal, counts the number of times the modulation signal is continuously at a high level at the rising edge of the high-frequency signal to obtain a count value, and when the count value reaches a relatively large predetermined value, outputs a pulse having a pulse width corresponding to the predetermined value as a pulse of the reproduced long-period signal using the high-frequency signal. The signal transmission system according to claim 5.

8. The signal distribution device further includes a distributor that divides the modulation signal generated by the modulation circuit into a plurality of modulation signals, and the plurality of modulation signals are respectively transmitted to the plurality of control units. The signal transmission system according to claim 1.

9. A signal transmission method for distributing a clock signal and a long-period signal having a period of two or more times that of the clock signal and synchronized with the clock signal to a plurality of control units by a signal distribution device, wherein the modulation circuit of the signal distribution device modulates the long-period signal with the clock signal to generate a modulation signal in which the long-period signal is superimposed on the clock signal, and the signal distribution device distributes the modulation signal to the plurality of control units via a transmission path.

10. The modulation signal is generated by pulse width modulation. The signal transmission method according to claim 9.

11. The generation of the modulation signal includes obtaining a phase shift signal by shifting the phase of the clock signal, obtaining a composite signal of the phase shift signal and the long period signal by performing an OR operation on the phase shift signal and the long period signal, and generating the modulation signal by performing an AND operation on the composite signal and the clock signal. The signal transmission method according to claim 9.

12. The phase shift signal is obtained by shifting the phase of the clock signal in a range exceeding 180° and less than 360°. The signal transmission method according to claim 11.

13. Each demodulation circuit of the plurality of control units obtains a clock signal regenerated based on the rising edge of the modulation signal, and obtains a long period signal regenerated from the modulation signal and the regenerated clock signal. The signal transmission method according to claim 9.

14. When obtaining the regenerated long period signal, a high frequency signal is generated by shifting the phase of the regenerated clock signal to multiply the frequency or by multiplying the frequency of the regenerated clock signal and then shifting the phase. A first sampling signal is obtained by sampling the modulation signal with the high frequency signal. A second sampling signal is obtained by sampling the first sampling signal with the high frequency signal. The regenerated long period signal is obtained by performing an AND operation on the first sampling signal and the second sampling signal. The signal transmission method according to claim 13.

15. When obtaining the regenerated long period signal, a high frequency signal is generated by multiplying the frequency of the regenerated clock signal. The number of times the modulation signal is continuously at a high level at the rising edge of the high frequency signal is counted to obtain a count value. When the count value reaches a relatively large predetermined value, a pulse having a pulse width corresponding to the predetermined value is output as the pulse of the regenerated long period signal using the high frequency signal. The signal transmission method according to claim 13.

16. The modulation signal generated by the modulation circuit is divided into a plurality of modulation signals by a distributor, and the plurality of modulation signals are respectively transmitted to the plurality of control units. The signal transmission method according to claim 9.

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