Memory element

Abstract

The present invention prevents diffusion of constituent elements of an electrode. This memory element has a storage part, a first electrode, a second electrode, and a block layer. The storage part includes a storage layer that is a magnetic layer the magnetization direction of which is variable, a reference layer that is a magnetic layer the magnetization direction of which is invariable, and a first non-magnetic layer that is disposed between the storage layer and the reference layer. The first electrode and the second electrode apply write voltage and read voltage to the storage part. The block layer is a non-magnetic layer disposed between the second electrode and the storage part and comprises a non-crystalline material.

Description

memory element

[0001] The present disclosure relates to memory devices.

[0002] In MRAM (Magnetoresistive RAM), which uses a magnetic memory element as a nonvolatile memory element, a voltage-driven magnetic memory element has been proposed in which data is written by applying a pulse voltage. Such MRAM uses a magnetic memory element with a magnetic tunnel junction (MTJ) structure in which a tunnel barrier layer is sandwiched between two magnetic layers (a storage layer and a reference layer).

[0003] This magnetic memory element is in a high resistance state when the magnetization directions of the two magnetic layers are different, and in a low resistance state when the magnetization directions of the two magnetic layers are the same. MRAM uses this change in resistance to store data.

[0004] Such MRAM memory elements can be manufactured using the same process steps as CMOS (Complementary Metal Oxide Semiconductor), but suffer from the problem of lower heat resistance than CMOS. When using a memory element as a storage device for an imaging element, an element in which an imaging element chip and a memory element chip are stacked is used. In this case, a process of bonding an imaging element wafer and a memory element wafer is required. Typically, this bonding process exposes the memory element wafer to high temperatures of 350 to 400 degrees. To enable such high-temperature processes, magnetoresistive elements with improved heat resistance have been proposed (see, for example, Patent Document 1).

[0005] This magnetoresistive element has a first laminated structure formed by laminating a first layer made of a metal nitride and a second layer made of ruthenium or a ruthenium compound, and a second laminated structure formed by a memory layer, an intermediate layer, and a reference layer. This magnetoresistive element is configured by connecting first wiring and second wiring that apply voltage to an element portion formed by laminating the first laminated structure and the second laminated structure in this order. The first wiring and second wiring correspond to electrodes of the element portion.

[0006] Japanese Patent Application Laid-Open No. 2017-157662

[0007] However, the above-mentioned conventional technology has a problem in that when the memory element is exposed to high temperatures, the constituent elements of the electrode diffuse into the memory layer, causing deterioration of the characteristics.

[0008] Therefore, the present disclosure proposes a memory element that prevents the diffusion of constituent elements of the electrodes.

[0009] The memory element of the present disclosure has a memory section including a memory layer which is a magnetic layer whose magnetization direction is variable, a reference layer which is a magnetic layer whose magnetization direction is invariable, and a first non-magnetic layer disposed between the memory layer and the reference layer, a first electrode and a second electrode which apply a write voltage and a read voltage to the memory section, and a block layer which is a non-magnetic layer disposed between the second electrode and the memory section and made of an amorphous material.

[0010] FIG. 1 is a diagram showing an example configuration of a memory system according to an embodiment of the present disclosure. FIG. 2 is a diagram showing an example configuration of a memory cell according to a first embodiment of the present disclosure. FIG. 3 is a diagram showing an example configuration of a memory element according to a second embodiment of the present disclosure. FIG. 4 is a diagram showing an example configuration of a memory element according to a second embodiment of the present disclosure. FIG. 5 is a diagram showing an example configuration of a memory element according to a second embodiment of the present disclosure. FIG. 6 is a diagram showing an example configuration of a memory element according to a second embodiment of the present disclosure. FIG. 7 is a diagram showing an example configuration of a memory element according to a second embodiment of the present disclosure. FIG. 8 is a diagram showing an example configuration of a memory element according to a second embodiment of the present disclosure.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order. In the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted. 1. First embodiment 2. Second embodiment

[0012] 1. First Embodiment [Configuration of Memory System] FIG. 1 is a diagram illustrating an example configuration of a memory system according to an embodiment of the present disclosure. This diagram is a block diagram illustrating an example configuration of a memory system 1. The memory system 1 includes an interface unit 2, a memory control unit 3, a memory cell array 10, a word line address decoder 60, a word line control circuit 20, a bit line address decoder 50, a bit line control circuit 30, and a sense amplifier 40. The memory system 1 also includes a voltage generation circuit 70. Note that this embodiment describes an example in which the memory system 1 includes a memory interface for connecting to a host system. However, the memory system 1 can also be applied to an embedded memory, an integrated memory, or an integrated storage device having an I / O for connecting to an internal bus or logic circuit integrated in a SoC (System on a Chip). Note that the memory system 1 can also be considered as a semiconductor device. The memory cell array 10 , word line address decoder 60 , word line control circuit 20 , bit line address decoder 50 , bit line control circuit 30 , voltage generating circuit 70 and sense amplifier 40 of the memory system 1 constitute a memory device 4 .

[0013] The interface unit 2 is used to communicate with a host system or the like that uses the memory system 1 .

[0014] The memory control unit 3 communicates with a host system or the like. This memory control unit 3 receives commands from the host system or the like and controls the writing and reading of data based on the received commands. The memory control unit 3 in FIG. 1 outputs write and read addresses to the word line address decoder 60 and the bit line address decoder 50. The memory control unit 3 also outputs control signals to the word line control circuit 20 and the voltage generation circuit 70. The memory control unit 3 also sends write data to the sense amplifier 40 and obtains read data from the sense amplifier 40.

[0015] The memory cell array 10 is configured by arranging memory cells 100 for storing data in a two-dimensional matrix. Each memory cell 100 includes a memory element 120 and a selection element 110.

[0016] The memory element 120 has a magnetic tunnel junction (MTJ) structure in which a tunnel barrier layer is sandwiched between two magnetic layers (a storage layer and a reference layer). The resistance of the memory element 120 varies depending on the magnetization direction of the two magnetic layers. The memory element 120 is in a high-resistance state when the magnetization directions of the two ferromagnetic layers are different, and in a low-resistance state when the magnetization directions are the same. The state in which the magnetization directions are the same is called a parallel state, and the state in which the magnetization directions are different is called an anti-parallel state. This magnetization direction can be changed by applying a write voltage to the MTJ element. For example, values ​​"0" and "1" can be associated with the low-resistance state and the high-resistance state of the MTJ element to store one bit of data. The values ​​"0" and "1" can also be referred to as low-level voltage (L) and high-level voltage (H).

[0017] The selection element 110 is an element that is connected to one end of the memory element 120 and controls the application of a voltage to the memory element 120. For example, an n-channel MOS transistor can be used for this selection element 110.

[0018] In the memory cell 100, word lines 11, bit lines 12, and source lines 13 are arranged. The word lines 11 are made up of a plurality of word lines WL. The bit lines 12 are made up of a plurality of bit lines BL. The source lines 13 are made up of a plurality of source lines SL. The word lines WL and bit lines BL transmit control signals. The source lines SL transmit signals from the memory elements 120. In the memory cell array 10, a plurality of word lines WL are wired in the row direction, and a plurality of bit lines BL and source lines SL are wired in the column direction.

[0019] The word line address decoder 60 selects a word line WL of the memory cell array 10 based on a control signal from the memory control unit 3 .

[0020] The word line control circuit 20 outputs a control signal to the word line WL selected by the word line address decoder 60 .

[0021] The bit line address decoder 50 selects a bit line BL of the memory cell array 10 based on a control signal from the memory control unit 3 .

[0022] The bit line control circuit 30 outputs a control signal to the bit line BL selected by the bit line address decoder 50 .

[0023] The sense amplifier 40 reads data by detecting the current flowing through the memory cell 100 during reading. The read data is output to the memory control unit 3. The sense amplifier 40 also applies a write voltage to the memory cell 100 during writing.

[0024] The voltage generating circuit 70 is a circuit that generates a voltage to be applied when writing to and reading from the memory cell 100 .

[0025] Writing to the memory cell 100 is performed when the data stored in the memory cell 100 differs from the write data. That is, data is read from the memory cell 100 and the read data is compared with the write data. If the comparison shows that the two data differ, writing is performed. In this case, writing can be performed by inverting the data stored in the memory cell 100. That is, writing can be performed by inverting the memory state of the memory element 120. The memory state of the memory element 120 can be inverted by applying a predetermined write voltage to the memory element 120.

[0026] Reading can be performed by applying a predetermined read voltage to the memory element 120 of the memory cell 100 and detecting the current flowing through the memory cell 100. The read voltage is preferably lower than the write voltage.

[0027] 2 is a diagram showing a configuration example of a memory cell according to the first embodiment of the present disclosure. The diagram is a schematic cross-sectional view showing a configuration example of the memory cell 100. As described above, the memory cell 100 includes a selection element 110 and a memory element 120.

[0028] The memory cell 100 is formed on a semiconductor substrate 180. This semiconductor substrate 180 is a semiconductor substrate on which the selection element 110 and the like are formed. A wiring region 190 is arranged adjacent to the semiconductor substrate 180. This wiring region 190 is an area where wiring and the like of elements are arranged. The wiring region 190 includes insulating layers (insulating layers 191 to 194) and wiring. The wiring transmits signals and the like to the elements of the semiconductor substrate 180. Wiring 195 and 196 are shown in the wiring region 140 in FIG. 2. This wiring can be made of, for example, copper (Cu). The insulating layer insulates the wiring and the like. This insulating layer can be made of, for example, silicon oxide (SiO ２ ) The insulating layer can be formed in multiple layers. In FIG. 2, insulating layers 191 to 194 are shown stacked in order.

[0029] The selection element 110 is formed on a semiconductor substrate 180. Specifically, the selection element 110 is composed of semiconductor regions 181 and 182 formed on the semiconductor substrate 180 and a gate electrode 184 arranged with a gate insulating film 183 interposed therebetween. The semiconductor region 181 corresponds to one of the drain region and the source region, and the semiconductor region 182 corresponds to the other of the drain region and the source region. For convenience, the semiconductor region 181 is considered to be the source region, and the semiconductor region 182 is considered to be the drain region.

[0030] The memory element 120 is disposed in a wiring region 190 formed on a semiconductor substrate 180. The memory element 120 in Fig. 2 represents an example in which the memory element 120 is disposed on an insulating layer 193. In addition, a first electrode 121 and a second electrode 122 are disposed on the memory element 120.

[0031] The first electrode 121 of the memory element 120 and the drain region of the selection element 110 are connected by a contact plug 197. The second electrode 122 of the memory element 120 and the wiring 196 are connected by a via plug 199. The source region of the selection element 110 and the wiring 195 are connected by a contact plug 198. The wiring 196 is connected to a bit line BL. The wiring 195 is connected to a source line SL. The gate electrode 184 of the selection element 110 is connected to a word line WL (not shown).

[0032] [Memory Element] Fig. 3 is a diagram showing a configuration example of a memory element according to the first embodiment of the present disclosure. This diagram is a cross-sectional view showing a configuration example of a memory element 120. The memory element 120 includes a first electrode 121, a fixed layer 123, a spacer layer 124, a reference layer 125, a tunnel barrier layer 126, a memory layer 151, a cap layer 131, a block layer 141, and a second electrode 122. The memory element 120 is configured by sequentially stacking the first electrode 121, the fixed layer 123, the spacer layer 124, the reference layer 125, the tunnel barrier layer 126, the memory layer 151, the cap layer 131, the block layer 141, and the second electrode 122. The memory layer 151, the tunnel barrier layer 126, and the reference layer 125 in Fig. 3 constitute a memory unit 200. The storage section 200 is a portion that controls the storage of data in the memory element 120 , and includes a storage layer 151 , a tunnel barrier layer 126 and a reference layer 125 .

[0033] The first electrode 121 and the second electrode 122 are electrodes of the memory element 120. The first electrode 121 and the second electrode 122 are electrodes that apply a write voltage and a read voltage to the memory unit 200. The first electrode 121 and the second electrode 122 can be made of, for example, Cu, Al, Au, Pt, Ti, and Ru. It is assumed that the first electrode 121 and the second electrode 122 in FIG. 3 are made of Ru.

[0034] The memory layer 151 is a magnetic layer with a variable magnetization direction. The states in which the magnetization direction of the memory layer 151 is the same as and different from the magnetization direction of the reference layer 125 correspond to a parallel alignment state and an antiparallel alignment state, respectively. The memory element 120 is in a low resistance state in the parallel alignment state and in a high resistance state in the antiparallel alignment state.

[0035] The memory layer 151 includes any one of Ti, V, Cr, Mn, Fe, Co, and Ni. For example, the memory layer 151 can be made of CoFe. Furthermore, other elements can be added to the memory layer 151. The elements added to the memory layer 151 can be, for example, at least one of B, Ir, Os, Pt, Rh, Hf, Zr, Ti, Ta, W, Re, Au, Mo, Ru, Pd, Y, V, Sc, Gd, Tb, La, Mg, Al, Ag, Cu, and Cr. The memory layer 151 in FIG. 3 is assumed to be made of CoFe to which B has been added. The memory layer 151 in FIG. 3 can be configured to have a thickness of, for example, 0.8 nm.

[0036] The thickness of the memory layer 151 is preferably 3 nm or less, because the magnetization direction due to interface magnetic anisotropy during standby can be controlled to a direction perpendicular to the film surface.

[0037] Tunnel barrier layer 126 is a layer that separates storage layer 151 and reference layer 125. This tunnel barrier layer 126 can be made of, for example, MgO (thickness: 2.0 nm).

[0038] The tunnel barrier layer 126 may be made of an oxide of at least one element selected from the group consisting of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba. The tunnel barrier layer 126 may also be made of a nitride of at least one element selected from the group consisting of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba. The tunnel barrier layer 126 may also be made of MgF ２ , CaF, SrTiO ２ , AlLaO ３ The tunnel barrier layer 126 may also be formed using an insulator, a dielectric, or a semiconductor, such as AlNO. The tunnel barrier layer 126 is also referred to as an insulating layer. The tunnel barrier layer 126 is an example of a "first nonmagnetic layer" in the present disclosure.

[0039] The reference layer 125 is a magnetic layer whose magnetization direction is invariable. This reference layer 125 can be made of a ferromagnetic layer containing at least one of Fe, Co, Ni, and Mn. The reference layer 125 in FIG. 3 can be made of, for example, CoFe (thickness: 1.0 nm).

[0040] The pinned layer 123 is a magnetic layer having a fixed magnetization direction. The magnetization direction of this pinned layer 123 is controlled perpendicular to the film surface by magnetic anisotropy. The magnetization direction of the pinned layer 123 is configured antiparallel to the magnetization direction of the reference layer 125. This pinned layer 123 can cancel out the leakage magnetic field applied from the reference layer 125 to the memory layer 151. The pinned layer 123 contains Co and at least one element selected from Ni, Pt, and Pd, and can be formed of an alloy or an artificial lattice of CoPt, CoNi, and CoPd. The pinned layer 123 in FIG. 3 can be formed, for example, of PtCo (thickness 2.0 nm).

[0041] The spacer layer 124 is a film that separates the reference layer 125 and the fixed layer 123. The spacer layer 124 can be made of at least one of Ru, Ir, Rh, and Re.

[0042] The cap layer 131 is a layer that prevents metal diffusion from the wiring member. This cap layer 131 can be made of, for example, MgO (thickness: 2.0 nm). The cap layer 131 is an example of the "second nonmagnetic layer" of the present disclosure. Furthermore, when the tunnel barrier layer 126 contains B, the cap layer 131 can be configured to contain a higher concentration of B than the tunnel barrier layer 126.

[0043] The block layer 141 is a non-magnetic layer disposed between the second electrode 122 and the memory section 200. This block layer 141 is made of an amorphous material. The block layer 141 prevents atomic diffusion of elements constituting the second electrode 122 into the memory layer 151. When exposed to high temperatures, Ru constituting the second electrode 122 diffuses toward the memory layer 151. However, the cap layer 131 described above cannot sufficiently prevent the diffusion of Ru contained in the second electrode 122. For this reason, the block layer 141 is disposed between the second electrode 122 and the cap layer 131 to prevent the diffusion of Ru into the memory layer 151. The block layer 141 can be made of a high-melting-point element, such as Mo, Ta, W, Re, or Nb. The block layer 141 may also contain magnetic elements such as Co, Fe, and Ni. The block layer 141 is made of these materials and is in a non-crystalline (amorphous) state. An amorphization promoter such as B, Al, or Zr may be added to the block layer 141 in an amount on the order of several atomic percent. The block layer 141 can be formed to a thickness of 2 nm or more.

[0044] 3 is assumed to be made of amorphous Mo. The block layer 141 may also be made of amorphous MoB. The block layer 141 may also be made of amorphous MoTmB, where Tm is any of Co, Fe, and Ni.

[0045] By forming the block layer 141 from an amorphous high-melting point element, the ability to prevent Ru diffusion can be improved. When a high-melting point element such as Mo crystallizes, grain boundaries are formed. Ru moves along these grain boundaries, resulting in Ru diffusion. Therefore, by forming the block layer 141 from an amorphous material, it becomes possible to prevent Ru diffusion.

[0046] Writing and reading of the memory element 120 will now be described. As described above, the direction of magnetization of the storage layer 151 can be reversed by applying a voltage to the memory element 120. The open arrows in FIG. 3 represent the current that flows through the memory element 120 when a write voltage is applied. A write voltage of the opposite direction is applied when writing a value "0" and a value "1". Furthermore, the thin-line arrows in FIG. 3 represent the current that flows through the memory element 120 when a read voltage is applied. As described above, the read voltage can be lower than the write voltage.

[0047] As described above, the memory element 120 according to the first embodiment of the present disclosure has the block layer 141 made of an amorphous material disposed between the electrode (second electrode 122) and the memory unit 200 including the memory layer 151. This makes it possible to prevent the element (Ru) constituting the electrode from diffusing into the memory layer 151.

[0048] 2. Second Embodiment A variation of the memory device 120 of the first embodiment will be described.

[0049] 4 to 15 are diagrams illustrating an example of the configuration of a memory element according to a second embodiment of the present disclosure. Similar to FIG. 3, FIG. 4 to 15 are cross-sectional views illustrating an example of the configuration of a memory element 120.

[0050] The memory element 120 of Fig. 4 differs from the memory element 120 of Fig. 3 in that a block layer 142 is disposed instead of the block layer 141. This block layer 142 is composed of amorphous Mo, Ta, W, Re, and Nb. The block layer 142 may also be composed of an amorphous material containing any of Mo, Ta, W, Re, and Nb and B. The block layer 142 may also be composed of an amorphous material containing any of Mo, Ta, W, Re, and Nb, Tm, and B. Here, Tm is any of Co, Fe, and Ni.

[0051] The memory element 120 of FIG. 5 differs from the memory element 120 of FIG. 3 in that a protective layer 127 is further disposed between the memory section 200 and the cap layer 131. This protective layer 127 protects the memory layer 151. The protective layer 127 protects the memory layer 151 by preventing oxidation of the memory layer 151. The protective layer 127 can be composed of, for example, Sc, Ti, V, Cr, Y, Zr, Nb, Mo, Hf, Ta, W, and lanthanoids. The protective layer 127 can be configured to have a thickness of 0.4 nm or more. The protective layer 127 is an example of a "third non-magnetic layer" in the present disclosure.

[0052] The memory element 120 of Fig. 6 differs from the memory element 120 of Fig. 3 in that a cap layer 132 is disposed instead of the cap layer 131. The cap layer 132 can be made of an oxide. The cap layer 132 can also be made of a nitride. The cap layer 132 can also be made of a fluoride. In this way, the cap layer 132 can be made of an insulating layer.

[0053] The memory element 120 of FIG. 7 shows an example in which a protective layer 127 is further disposed on the memory element 120 of FIG.

[0054] 8 differs from the memory element 120 of Fig. 3 in that the cap layer 131 is omitted. If the block layer 141 can sufficiently prevent the diffusion of Ru in the second electrode 122, the cap layer 131 can be omitted.

[0055] The memory element 120 in Fig. 9 differs from the memory element 120 in Fig. 3 in that two memory layers are arranged. The memory element 120 in Fig. 9 includes a memory layer 151 and a memory layer 152. The memory element 120 in Fig. 9 further includes an isolation layer 128 that isolates the memory layer 151 from the memory layer 152. The isolation layer 128 can be made of an oxide, a nitride, or a fluoride.

[0056] The memory element 120 of FIG. 10 shows an example in which a cap layer 132 is further disposed on the memory element 120 of FIG.

[0057] The memory element 120 in Fig. 11 differs from the memory element 120 in Fig. 3 in that three or more memory layers are arranged. The memory element 120 in Fig. 11 includes a memory layer 151 (#1), a memory layer 152 (#2) to a memory layer 153 (#n). Separation layers are arranged between the memory layers.

[0058] The memory element 120 of FIG. 12 shows an example in which a cap layer 132 is further disposed on the memory element 120 of FIG.

[0059] 13 differs from the memory element 120 of FIG. 3 in that it further includes a block layer 142. The block layer 142 is a block layer disposed between the first electrode 121 and the memory unit 200. The block layer 142 can be made of an amorphous material similar to the block layer 141. The block layer 142 is an example of a "second block layer" in the present disclosure.

[0060] The memory element 120 in Fig. 14 has a stacking order of the layers different from that of the memory element 120 in Fig. 3. That is, the memory element 120 in Fig. 14 is configured by stacking a second electrode 122, a block layer 141, a cap layer 131, a memory layer 151, a tunnel barrier layer 126, a reference layer 125, a spacer layer 124, a fixed layer 123, and a first electrode 121 in this order.

[0061] The memory element 120 in FIG. 15 represents an example in which a block layer 142 is further disposed in addition to the memory element 120 in FIG.

[0062] The configuration of the memory element 120 other than that described above is the same as the configuration of the memory element 120 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0063] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0064] The present technology can also be configured as follows. (1) A memory element having a memory unit including a memory layer that is a magnetic layer with a variable magnetization direction, a reference layer that is a magnetic layer with an invariable magnetization direction, and a first non-magnetic layer disposed between the memory layer and the reference layer, a first electrode and a second electrode that apply a write voltage and a read voltage to the memory unit, and a block layer that is a non-magnetic layer disposed between the second electrode and the memory unit and is made of an amorphous material. (2) The memory element according to (1), wherein the block layer is configured to contain any of Mo, Ta, W, Re, and Nb. (3) The memory element according to (1) or (2), wherein the block layer is configured to contain any of Co, Fe, and Ni. (4) The memory element according to any of (1) to (3), wherein the block layer is configured to have a thickness of 2 nm or more. (5) The memory element according to any one of (1) to (4), wherein the memory layer contains any one of Ti, V, Cr, Mn, Fe, Co, and Ni. (6) The memory element according to any one of (1) to (5), wherein the memory layer contains B. (7) The memory element according to any one of (1) to (6), further comprising a second nonmagnetic layer disposed between the memory layer and the block layer. (8) The memory element according to (7), wherein the second nonmagnetic layer contains an oxide, a nitride, and a fluoride. (9) The memory element according to (7), further comprising a third nonmagnetic layer disposed between the memory layer and the second nonmagnetic layer. (10) The memory element according to (9), wherein the third nonmagnetic layer contains any one of Sc, Ti, V, Cr, Y, Zr, Nb, Mo, Hf, Ta, W, and a lanthanoid. (11) The memory element according to (9), wherein the third nonmagnetic layer is configured to have a thickness of 0.4 nm or more. (12) The memory element according to (7), wherein the first nonmagnetic layer contains B, and the second nonmagnetic layer contains B at a concentration higher than that of the first nonmagnetic layer. (13) The memory element according to any one of (1) to (12), further including a second block layer, which is a nonmagnetic layer disposed between the first electrode and the storage section and is configured of an amorphous material.

[0065] REFERENCE SIGNS LIST 1 memory system 4 memory device 100 memory cell 120 memory element 121 first electrode 122 second electrode 125 reference layer 126 tunnel barrier layer 127 protective layer 131, 132 cap layer 141, 142 block layer 151 to 153 memory layer 200 memory section

Claims

1. A memory element comprising a memory layer which is a magnetic layer with a variable magnetization direction, a reference layer which is a magnetic layer with an invariant magnetization direction, and a first non-magnetic layer disposed between the memory layer and the reference layer; a first electrode and a second electrode for applying a write voltage and a read voltage to the memory element; and a block layer which is a non-magnetic layer disposed between the second electrode and the memory element and is composed of an amorphous material.

2. The memory element according to claim 1, wherein the block layer is composed of any one of Mo, Ta, W, Re, and Nb.

3. The memory element according to claim 1, wherein the block layer is composed of any one of Co, Fe, and Ni.

4. The memory element according to claim 1, wherein the block layer is configured to have a thickness of 2 nm or more.

5. The memory element according to claim 1, wherein the memory layer is composed of any one of Ti, V, Cr, Mn, Fe, Co, and Ni.

6. The memory element according to claim 1, wherein the memory layer is composed of B.

7. The memory element according to claim 1, further comprising a second non-magnetic layer disposed between the memory layer and the block layer.

8. The memory element according to claim 7, wherein the second non-magnetic layer is composed of an oxide, a nitride, and a fluoride.

9. The memory element according to claim 7, further comprising a third non-magnetic layer disposed between the memory layer and the second non-magnetic layer.

10. The memory element according to claim 9, wherein the third non-magnetic layer is composed of any one of Sc, Ti, V, Cr, Y, Zr, Nb, Mo, Hf, Ta, W, and lanthanoid.

11. The memory element according to claim 9, wherein the third non-magnetic layer is configured to have a thickness of 0.4 nm or more.

12. The memory element according to claim 7, wherein the first non-magnetic layer is composed of B, and the second non-magnetic layer is composed of B with a higher concentration than the first non-magnetic layer.

13. The memory element according to claim 1, further comprising a second block layer which is a non-magnetic layer disposed between the first electrode and the memory element and is composed of an amorphous material.

Images