Semiconductor device

Abstract

This semiconductor device includes: a chip having a main surface; and a trench electrode-type gate structure formed on the main surface. The gate structure includes: a trench formed on the main surface; an insulating film that includes a first film section which covers a wall surface of an inner section of the trench, and a second film section which covers a wall surface of an end section of the trench and which is thicker than the first film section; and an embedded electrode that is embedded in the trench with the insulating film interposed therebetween.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2023-221770 filed with the Japan Patent Office on December 27, 2023, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2003 / 0227051A1) discloses a semiconductor device having an active groove formed in an n-type semiconductor layer, in which a p-type buried region is disposed on the bottom side of the active groove, and a gate electrode is disposed on the opening side of the active groove via a gate insulating film.

[0003] US Patent Application Publication No. 2003 / 0227051

[0004] SUMMARY The present disclosure provides a semiconductor device having a novel layout.

[0005] The present disclosure provides a semiconductor device including a chip having a main surface and a trench electrode type gate structure formed on the main surface, the gate structure including a trench formed on the main surface, an insulating film including a first film portion covering a wall surface of an inner portion of the trench, and a second film portion covering a wall surface of an end portion of the trench and having a thickness greater than a thickness of the first film portion, and a buried electrode buried in the trench across the insulating film.

[0006] The present disclosure provides a semiconductor device including a chip having a main surface, a trench electrode type gate structure formed on the main surface, a first surface film portion covering the periphery of the gate structure on the main surface, and a surface insulating film including a second surface film portion covering the periphery of the first surface film portion on the main surface and having a thickness greater than a thickness of the first surface film portion.

[0007] The present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type gate structure formed on the main surface; a gate wiring electrically connected to an end of the gate structure on the main surface; an insulating interlayer film covering the gate structure and the gate wiring; a pad electrode disposed on the interlayer film and facing the gate structure and the gate wiring across the interlayer film; a gate finger electrode disposed on the interlayer film at a distance from the pad electrode and facing the gate wiring across the interlayer film; and a slit portion partitioned in a region between the pad electrode and the gate finger electrode and overlapping the main surface in a stacking direction.

[0008] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a plan view showing a semiconductor device according to a specific embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of an active region. FIG. 5 is a cross-sectional view taken along line VV in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 4. FIG. 10 is an enlarged cross-sectional view showing a main portion of an active region. FIG. 11 is an enlarged cross-sectional view showing a main portion of an active region. FIG. 12 is a cross-sectional perspective view showing a main portion of an active region. FIG. 13 is a cross-sectional perspective view showing a main portion of an active region. FIG. 14 is a cross-sectional view showing a peripheral region. FIG. 15 is a cross-sectional perspective view showing a first modified example of the semiconductor device. FIG. 16 is a cross-sectional view showing a second modified example of the semiconductor device. FIG. 17 is a cross-sectional view showing a third modified example of the semiconductor device. 18, 19, and 20 are cross-sectional views showing a fourth, fifth, and sixth modified examples of the semiconductor device, respectively.

[0010] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0011] In this specification, open language such as "including" and "having" is described as a concept that encompasses closed language such as "consisting of." When the term "substantially" is used in this specification, this term not only includes a numerical value (form) that is equal to the numerical value (form) of the comparison target, but also includes a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target.

[0012] In this specification, terms such as "first," "second," and "third" are used, but these are symbols added to the names of each structure to clarify the order of explanation, and are not added with the intention of limiting the names of each structure.

[0013] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type."

[0014] "P-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0015] FIG. 1 is a plan view showing a semiconductor device 1 according to a specific embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface 3. FIG. 4 is an enlarged plan view showing a main portion of an active region 8. FIG. 5 is a cross-sectional view taken along line VV shown in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 4. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 4.

[0016] Fig. 10 is an enlarged cross-sectional view showing a main portion of the active region 8. Fig. 11 is an enlarged cross-sectional view showing a main portion of the active region 8. Fig. 12 is a cross-sectional perspective view showing a main portion of the active region 8. Fig. 13 is a cross-sectional perspective view showing a main portion of the active region 8. Fig. 14 is a cross-sectional view showing the peripheral region 9.

[0017] 1 to 14, a semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate vertical structure.

[0018] The semiconductor device 1 includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "wide bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0019] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device."

[0020] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0021] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0022] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0023] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0024] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. The first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0025] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-angle from a vertical line along the vertical direction Z toward the off-direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off-angle with respect to the horizontal plane.

[0026] The off-direction is preferably the a-axis direction of the SiC single crystal (second direction Y in this embodiment). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0027] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0028] The semiconductor device 1 includes an n-type first semiconductor layer 6 formed in a surface layer portion of the second main surface 4. A drain potential is applied to the first semiconductor layer 6 as a first potential (high potential). The first semiconductor layer 6 may also be referred to as a "semiconductor region (layer)," a "base region (layer)," a "drain region (layer)," or the like.

[0029] The first semiconductor layer 6 extends in a layered form along the second main surface 4, forming the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor layer 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and has the second main surface 4 and first to fourth side surfaces 5A to 5D. The first semiconductor layer 6 (substrate) has the off direction and off angle described above. The first semiconductor layer 6 may have a substantially uniform n-type impurity concentration (substantially constant n-type impurity concentration) in the thickness direction.

[0030] The first semiconductor layer 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or more, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0031] The semiconductor device 1 includes an n-type second semiconductor layer 7 formed in a surface layer portion of the first main surface 3. The second semiconductor layer 7 may be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor layer 7 has an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor layer 6. The second semiconductor layer 7 may have an n-type impurity concentration that is approximately uniform in the thickness direction (an approximately constant n-type impurity concentration). The n-type impurity concentration of the second semiconductor layer 7 may increase from the bottom toward the first main surface 3.

[0032] The second semiconductor layer 7 is formed in a region on the first main surface 3 side of the first semiconductor layer 6 in a cross-sectional view, and is electrically connected to the first semiconductor layer 6. The second semiconductor layer 7 extends in a layered form along the first main surface 3, and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor layer 7 is made of an n-type semiconductor layer.

[0033] Specifically, the second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal), and has a first main surface 3 and first to fourth side surfaces 5A to 5D. The second semiconductor layer 7 (epitaxial layer) has the off direction and off angle described above. The second semiconductor layer 7 preferably has a thickness less than that of the first semiconductor layer 6. The thickness of the second semiconductor layer 7 may be greater than that of the first semiconductor layer 6.

[0034] The thickness of the second semiconductor layer 7 may be 5 μm or more and 15 μm or less. The thickness of the second semiconductor layer 7 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0035] The semiconductor device 1 includes an active region 8 set in a chip 2. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in an inner portion of the chip 2 at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).

[0036] The active region 8 is set to a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The active region 8 has a rectangular recessed portion along the center of the third side surface 5C toward the fourth side surface 5D. The ratio (area ratio) of the planar area of ​​the active region 8 to the planar area of ​​the first main surface 3 may be 0.5 to 0.95. The area ratio may be 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, 0.8 to 0.9, or 0.9 to 0.95.

[0037] The semiconductor device 1 includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is a region that does not include a device structure (transistor structure Tr). The peripheral region 9 is set on the periphery of the chip 2. That is, the peripheral region 9 is provided in a region between the periphery of the chip 2 and the active region 8 in a planar view. The peripheral region 9 extends in a strip shape along the active region 8 in a planar view, and is set in a polygonal ring shape (a square ring shape in this embodiment) that surrounds the active region 8.

[0038] The semiconductor device 1 includes a transistor structure Tr formed in an active region 8. The configuration within the active region 8 as the configuration of the transistor structure Tr will be described below.

[0039] The semiconductor device 1 includes a p-type body region 10 formed in the active region 8 (inner portion of the first main surface 3) in a surface layer portion of the first main surface 3. The body region 10 may be referred to as a "channel region" or the like. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential.

[0040] The body region 10 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The body region 10 is formed in an inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer peripheral region 9. In this embodiment, the body region 10 is formed over the entire active region 8. The body region 10 is formed in a surface layer portion of the second semiconductor layer 7 and extends in a layered form along the first main surface 3.

[0041] The body region 10 is formed at a distance from the bottom of the second semiconductor layer 7 (the first semiconductor layer 6) toward the first major surface 3, and faces the first semiconductor layer 6 across a part of the second semiconductor layer 7. The body region 10 is formed at a distance from a depth position of the middle part of the second semiconductor layer 7 toward the first major surface 3.

[0042] The body region 10 is formed in a region on the first major surface 3 side of the second semiconductor layer 7 in a cross-sectional view, and is electrically connected to the second semiconductor layer 7. The body region 10 forms a pn junction (body diode) with the second semiconductor layer 7. The body region 10 spreads a depletion layer into the second semiconductor layer 7 when a reverse bias voltage is applied. The depletion layer originating from the body region 10 spreads in the horizontal direction and thickness direction within the second semiconductor layer 7.

[0043] The semiconductor device 1 includes a plurality of trench-type (trench electrode-type) gate structures 15 formed in an inner portion of the first main surface 3. The gate structures 15 may also be referred to as "trench structures," "trench gate structures," or the like. A gate potential (gate signal) serving as a control potential is applied to the plurality of gate structures 15. The plurality of gate structures 15 controls inversion and non-inversion of the channel CH in the body region 10 in response to the gate potential (see FIG. 10 ).

[0044] The multiple gate structures 15 are formed in the inner part of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 9. The multiple gate structures 15 are arranged at intervals in the first direction X (= m-axis direction) in plan view, and extend in a strip shape in the second direction Y (= a-axis direction). The multiple gate structures 15 are arranged in a strip shape extending in the second direction Y in plan view.

[0045] The extension direction of the multiple gate structures 15 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both end portions of the multiple gate structures 15 are located inward from the periphery of the body region 10. Both end portions of the multiple gate structures 15 may be located outward from the periphery of the body region 10. The multiple gate structures 15 may be arranged at intervals in the second direction Y in a plan view, and each extend in a strip shape in the first direction X.

[0046] The plurality of gate structures 15 penetrate the body region 10 to reach the second semiconductor layer 7. The plurality of gate structures 15 are formed at intervals from the depth position of the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 with a part of the second semiconductor layer 7 interposed therebetween.

[0047] The multiple gate structures 15 may be formed at intervals from a depth position of an intermediate portion of the second semiconductor layer 7 toward the first major surface 3, or may be located on the bottom side of the second semiconductor layer 7 (the second major surface 4 side) with respect to the depth position of the intermediate portion of the second semiconductor layer 7. The multiple gate structures 15 are formed approximately perpendicular to the first major surface 3. The multiple gate structures 15 may be formed in a shape that tapers toward the bottom of the second semiconductor layer 7.

[0048] The side walls (long sides) of the plurality of gate structures 15 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the plurality of gate structures 15 may be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 15. The side walls of the plurality of gate structures 15, together with the first main surface 3, define an opening end curved in an arc shape (circular arc shape).

[0049] The bottom walls of the gate structures 15 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the gate structures 15 preferably extend substantially flat in the horizontal direction. The bottom walls of the gate structures 15 may be curved in an arc shape toward the second main surface 4.

[0050] The inclination angle (absolute value) of the sidewall (long side) of the gate structure 15 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0051] The gate structure 15 may have a width of 0.1 μm to 2 μm. The width of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm. The width of the gate structure 15 is preferably 1 μm or less.

[0052] The gate structure 15 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the gate structure 15 is measured from the first main surface 3. The depth of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less.

[0053] The gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0054] The multiple gate structures 15 may be arranged at intervals of 0.1 μm to 2 μm. The interval between the gate structures 15 is the distance between the multiple gate structures 15 in the horizontal direction (first direction X). The interval between the gate structures 15 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm. The interval between the gate structures 15 is preferably 1 μm or less.

[0055] The plurality of gate structures 15 each include a trench 16, an insulating film 17, a buried electrode 18, and a buried insulator 19. The trench 16 may be referred to as a "gate trench," the insulating film 17 may be referred to as a "gate insulating film," the buried electrode 18 may be referred to as a "gate electrode," and the buried insulator 19 may be referred to as a "cap insulator (film)." The trench 16 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 15.

[0056] The insulating film 17 covers the wall surface of the trench 16. In this embodiment, the insulating film 17 has an upper end portion positioned on the bottom wall side of the trench 16 relative to the height position of the first main surface 3, and exposes a part of the chip 2 from the wall surface of the opening end of the trench 16. The upper end portion of the insulating film 17 is preferably positioned on the opening side of the trench 16 relative to the depth position of the intermediate part of the trench 16.

[0057] The insulating film 17 includes a first film portion 20 and a second film portion 21. The first film portion 20 has a relatively small first thickness and covers the wall surfaces of the inner portion of the trench 16. The first film portion 20 is formed as a main body portion of the insulating film 17 (gate insulating film). The first film portion 20 covers the wall surfaces of the inner portion of the trench 16 at a distance inward from the longitudinal ends of the trench 16 (both ends in this embodiment). The first film portion 20 covers the side walls and bottom wall of the trench 16.

[0058] The ratio of the covering area (hiding area) of the first film portion 20 to the surface area of ​​the wall surface of the trench 16 may be 0.5 or more and less than 1. The ratio of the first film portion 20 may have a value belonging to at least one of the ranges of 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and less than 1.

[0059] In this embodiment, the first film portion 20 has an upper end portion positioned on the bottom wall side of the trench 16 relative to the height position of the first main surface 3, and exposes a part of the chip 2 from the wall surface of the opening end of the trench 16. The upper end portion of the first film portion 20 forms the upper end portion of the insulating film 17 in the inner part of the trench 16. It is preferable that the upper end portion of the first film portion 20 is positioned on the opening side of the trench 16 relative to the depth position of the intermediate part of the trench 16.

[0060] The first film portion 20 has a single-layer structure made of a first insulating film 22. The first insulating film 22 directly covers the wall surfaces of the trench 16 in a film form. The first insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0061] In this embodiment, the first insulating film 22 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of a silicon oxide film without impurities, a silicon oxide film containing phosphorus, or a silicon oxide film containing both phosphorus and boron.

[0062] A silicon oxide film without added impurities may be called an NSG film (nondoped silicate glass film), a silicon oxide film containing phosphorus may be called a PSG film (phosphorus silicon glass film), and a silicon oxide film containing both phosphorus and boron may be called a BPSG film (boron phosphorus silicon glass film).

[0063] The first film portion 20 preferably contains an oxide other than the oxide of the chip 2. In this embodiment, the first insulating film 22 is made of an NSG film. Of course, the first film portion 20 (first insulating film 22) may also be made of a silicon oxide film made of the oxide of the chip 2.

[0064] The first thickness of the first film portion 20 (i.e., the thickness of the first insulating film 22) may be 10 nm to 250 nm. The first thickness may have a value belonging to at least one of the ranges of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, 175 nm to 200 nm, 200 nm to 225 nm, and 225 nm to 250 nm.

[0065] The second film portion 21 has a second thickness different from the first thickness of the first film portion 20, and covers the wall surfaces of the ends (both ends in this embodiment) of the trench 16. The second film portion 21 covers the area outside the first film portion 20 on the wall surfaces on the end sides of the trench 16, and is continuous with the first film portion 20. The second film portion 21 covers the side walls and bottom wall of the trench 16.

[0066] The ratio of the coverage area (concealment area) of the second film portion 21 to the surface area of ​​the wall surface of the trench 16 is less than the ratio of the coverage area (concealment area) of the first film portion 20 to the surface area of ​​the wall surface of the trench 16. The ratio of the second film portion 21 may be greater than 0 and less than 0.5. The ratio of the second film portion 21 may have a value belonging to at least one of the ranges greater than 0 and less than 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to less than 0.5.

[0067] In this embodiment, the second film portion 21 has an upper end portion located on the bottom wall side of the trench 16 relative to the height position of the first main surface 3, and exposes a part of the chip 2 from the wall surface of the opening end of the trench 16. The upper end portion of the second film portion 21 forms the upper end portion of the insulating film 17 at the end of the trench 16. It is preferable that the upper end portion of the second film portion 21 is located on the opening side of the trench 16 relative to the depth position of the intermediate part of the trench 16.

[0068] The second film portion 21 has a layered structure including a second insulating film 23 and a third insulating film 24 layered in this order from the bottom wall side of the trench 16. In other words, the second film portion 21 has a different number of layers than the first film portion 20. The number of layers in the second film portion 21 is greater than the number of layers in the first film portion 20. The second insulating film 23 directly covers the wall surface of the trench 16 at the end of the trench 16 in a film-like manner. The second insulating film 23 covers the sidewalls and bottom wall of the trench 16 in a film-like manner.

[0069] The second insulating film 23 is formed in the trench 16 in an end-like shape and defines the end of the second film portion 21. That is, the second insulating film 23 has ends on the sidewalls and bottom wall of the trench 16. The end of the second insulating film 23 may have an inclined portion that is obliquely inclined with respect to the wall surface of the trench 16.

[0070] The second insulating film 23 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second insulating film 23 may include an insulator that is the same as or different from that of the first insulating film 22. In this embodiment, the second insulating film 23 has a single-layer structure made of a silicon oxide film.

[0071] The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. The second film portion 21 preferably contains an oxide other than the oxide of the chip 2. In this embodiment, the second insulating film 23 is made of an NSG film. The thickness of the second insulating film 23 may be greater or smaller than the first thickness of the first insulating film 22 (first film portion 20). The thickness of the second insulating film 23 may be approximately equal to the first thickness of the first insulating film 22 (first film portion 20).

[0072] The thickness of the second insulating film 23 may be 10 nm or more and 250 nm or less. The thickness of the second insulating film 23 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0073] The third insulating film 24 directly covers the second insulating film 23 in the trench 16. The third insulating film 24 covers the sidewalls and bottom wall of the trench 16 with the second insulating film 23 in between. The third insulating film 24 has a covering portion for the end of the second insulating film 23, and is connected to the first insulating film 22 at the end of the second insulating film 23.

[0074] The third insulating film 24 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The third insulating film 24 may include an insulator that is the same as or different from that of the first insulating film 22. The third insulating film 24 may include an insulator that is the same as or different from that of the second insulating film 23.

[0075] In this embodiment, the third insulating film 24 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. In this embodiment, the third insulating film 24 is made of an NSG film.

[0076] In this embodiment, the third insulating film 24 is made of the same insulating film as the first insulating film 22 and is formed integrally with the first insulating film 22. That is, the third insulating film 24 is formed by a portion of the first insulating film 22 that covers the second insulating film 23. In other words, the first insulating film 22 extends from the wall surface of the trench 16 onto the second insulating film 23 as the third insulating film 24, and covers the second insulating film 23 in a film-like manner.

[0077] The thickness of the third insulating film 24 is approximately equal to the first thickness of the first insulating film 22 (first film portion 20). The thickness of the third insulating film 24 may be greater or smaller than the thickness of the first insulating film 22. The thickness of the third insulating film 24 may be greater or smaller than the thickness of the second insulating film 23. The thickness of the third insulating film 24 may be approximately equal to the thickness of the second insulating film 23.

[0078] The thickness of the third insulating film 24 may be 10 nm or more and 250 nm or less. The thickness of the third insulating film 24 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0079] The second thickness of the second film portion 21 (i.e., the total thickness of the second insulating film 23 and the third insulating film 24) may be 20 nm to 500 nm. The second thickness may have a value belonging to at least one of the ranges of 20 nm to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0080] The buried electrode 18 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried electrode 18 is preferably made of n-type conductive polysilicon. The buried electrode 18 is buried in the trench 16 with the insulating film 17 interposed therebetween, and faces the second semiconductor layer 7 and the body region 10 with the insulating film 17 interposed therebetween.

[0081] Specifically, the buried electrode 18 is buried in the trench 16 with the first film portion 20 and the second film portion 21 sandwiched therebetween, and is in contact with the first film portion 20 and the second film portion 21 within the trench 16. In other words, the buried electrode 18 is in contact with the first insulating film 22 and the third insulating film 24. The buried electrode 18 has a portion that is in contact with the step between the first film portion 20 and the second film portion 21.

[0082] The buried electrode 18 faces the second semiconductor layer 7 and the body region 10 at the inner part of the trench 16, with the first film portion 20 sandwiched therebetween, and faces the second semiconductor layer 7 and the body region 10 at the end of the trench 16, with the second film portion 21 sandwiched therebetween.

[0083] The buried electrode 18 has an electrode surface exposed from the trench 16. The electrode surface is located on the bottom wall side of the trench 16 at a distance from the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the intermediate portion of the trench 16. The electrode surface may also be located on the bottom wall side of the trench 16 with respect to the depth position of the intermediate portion of the trench 16.

[0084] The electrode surface is located closer to the bottom wall of the trench 16 than the upper end of the insulating film 17, and exposes a portion of the insulating film 17 that covers the side wall at the opening side of the trench 16. The electrode surface may be located closer to the first main surface 3 than the upper end of the insulating film 17. The electrode surface and the side wall of the trench 16 define a recess space within the trench 16.

[0085] The electrode surface is located in the inner part of the trench 16 closer to the bottom wall of the trench 16 than the upper end of the first film portion 20. The electrode surface may be located closer to the first main surface 3 than the upper end of the first film portion 20. The electrode surface is located at the end of the trench 16 closer to the bottom wall of the trench 16 than the upper end of the second film portion 21. The electrode surface may be located closer to the first main surface 3 than the upper end of the second film portion 21.

[0086] The buried insulator 19 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The buried insulator 19 may have a single-layer structure including a single silicon oxide film or a stacked structure including multiple silicon oxide films. The single or multiple silicon oxide films may include at least one of an NSG film, a PSG film, and a BPSG film.

[0087] The buried insulator 19 is buried above the buried electrode 18 in the trench 16 and covers the buried electrode 18. In this embodiment, the buried insulator 19 is buried in the trench 16 with the insulating film 17 sandwiched therebetween, and is in contact with the insulating film 17 and the buried electrode 18 within the trench 16. The buried insulator 19 has a portion that faces the chip 2 in the horizontal direction with the insulating film 17 sandwiched therebetween, and exposes the first main surface 3.

[0088] Specifically, the buried insulator 19 is buried in the trench 16 with the first film portion 20 and the second film portion 21 sandwiched therebetween, and is in contact with the first film portion 20 and the second film portion 21 within the trench 16. In other words, the buried insulator 19 is in contact with the first insulating film 22 and the third insulating film 24. The buried insulator 19 has a portion that is in contact with the step between the first film portion 20 and the second film portion 21.

[0089] The buried insulator 19 faces the second semiconductor layer 7 and the body region 10 at the inner part of the trench 16 with the first film portion 20 therebetween, and faces the second semiconductor layer 7 and the body region 10 at the end of the trench 16 with the second film portion 21 therebetween. The buried insulator 19 is buried in the trench 16 at a distance from the height position of the first main surface 3 toward the bottom wall of the trench 16, and exposes a part of the chip 2 from the opening end of the trench 16.

[0090] The buried insulator 19 has an insulating surface exposed from the trench 16. The insulating surface is located on the bottom wall side of the trench 16 relative to the height of the first main surface 3. The insulating surface is located on the opening side of the trench 16 relative to the depth of the intermediate portion of the trench 16. The insulating surface may also be located on the bottom wall side of the trench 16 relative to the depth of the intermediate portion of the trench 16.

[0091] The insulating surface exposes the upper end of the insulating film 17. In this embodiment, the insulating surface is continuous and flat with the upper end of the insulating film 17. That is, the insulating surface is formed flush with the upper end of the insulating film 17. The insulating surface may be formed flush with the first main surface 3 together with the upper end of the insulating film 17. The insulating surface may be located closer to the first main surface 3 or closer to the bottom wall of the trench 16 than the upper end of the insulating film 17.

[0092] In this embodiment, the insulating surface has a raised portion that rises from the sidewall of the trench 16 toward the inside of the trench 16. The raised portion of the insulating surface is located closer to the bottom wall of the trench 16 than the height position of the first main surface 3. The raised portion of the insulating surface may protrude above the height position of the first main surface 3. Instead of the raised portion, the insulating surface may have a recess that sinks from the sidewall of the trench 16 toward the inside of the trench 16. The insulating surface may be formed flush with the first main surface 3.

[0093] In this embodiment, the buried insulator 19 has a thickness greater than the thickness of the insulating film 17 in the depth direction of the trench 16. The thickness of the buried insulator 19 is preferably greater than the second thickness of the second film portion 21. The thickness of the buried insulator 19 is preferably less than the thickness of the buried electrode 18.

[0094] The ratio of the thickness of the buried insulator 19 to the depth of the trench 16 may be greater than 0 and less than or equal to 0.5. The thickness ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than or equal to 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to 0.5.

[0095] The semiconductor device 1 includes a plurality of mesas 27 defined on the first main surface 3 in the active region 8. The mesas 27 are defined in regions between adjacent gate structures 15. The mesas 27 are defined at intervals in the first direction X, following the layout of the gate structures 15, and extend in a strip-like manner in the second direction Y. The mesas 27 extend in a strip-like manner in the second direction Y. The width of each mesa 27 corresponds to the spacing between the gate structures 15.

[0096] The semiconductor device 1 includes a plurality of p-type well regions 30 formed in the chip 2 (second semiconductor layer 7). The plurality of well regions 30 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7, and convert the conductivity type of the second semiconductor layer 7 from n-type to p-type. A source potential is applied to the plurality of well regions 30.

[0097] The multiple well regions 30 are formed in the second semiconductor layer 7 in regions below (specifically, directly below) the multiple gate structures 15, spaced apart from one another in the horizontal direction (first direction X). The multiple well regions 30 are formed in the thickness range between the bottom of the second semiconductor layer 7 and the bottom walls of the multiple gate structures 15, and overlap the multiple gate structures 15 in a one-to-one correspondence in the thickness direction.

[0098] The multiple well regions 30 each extend in a strip shape in the second direction Y in plan view, following the extension direction of the corresponding gate structures 15. The multiple well regions 30 are arranged in a stripe shape extending in the second direction Y in plan view. The extension direction of the multiple well regions 30 coincides with the off-direction of the SiC single crystal.

[0099] With respect to the second direction Y, both ends of the multiple well regions 30 may be located on the inner side of the multiple gate structures 15 relative to both ends of the multiple gate structures 15, or may be located on the peripheral side of the active region 8. The multiple well regions 30 may extend in the first direction X according to the extending direction of the multiple gate structures 15. In this case, the multiple well regions 30 intersect (specifically, perpendicular to) the off direction.

[0100] The multiple well regions 30 are formed at intervals from the bottom of the second semiconductor layer 7 to the bottom wall sides of the multiple gate structures 15, and face the first semiconductor layer 6 across a part of the second semiconductor layer 7. Each of the multiple well regions 30 has an upper end located on the bottom wall side of the corresponding gate structure 15, and a bottom located on the bottom side of the second semiconductor layer 7.

[0101] The upper ends of the multiple well regions 30 are formed at intervals from the bottom of the body region 10 toward the bottom wall of the corresponding gate structure 15. The upper ends of the multiple well regions 30 are connected to the bottom wall of the corresponding gate structure 15 and face the buried electrode 18 via the insulating film 17.

[0102] In this embodiment, the multiple well regions 30 each have a portion that is aligned with the first film portion 20 and a portion that is aligned with the second film portion 21. That is, the multiple well regions 30 each have a portion that faces the buried electrode 18 across the first film portion 20, and a portion that faces the buried electrode 18 across the second film portion 21.

[0103] The upper ends of the multiple well regions 30 may have portions that extend along the side walls of the corresponding gate structures 15. That is, the multiple well regions 30 may each have a portion that extends along the first film portion 20 and a portion that extends along the second film portion 21 on the side walls of the corresponding gate structures 15. The upper ends of the multiple well regions 30 may be formed at an interval from the bottom wall of the corresponding gate structure 15 toward the bottom of the second semiconductor layer 7.

[0104] The bottoms of the multiple well regions 30 may be located on the bottom wall side of the multiple gate structures 15 or on the bottom side (second main surface 4 side) of the second semiconductor layer 7 relative to the depth position of the intermediate portion of the second semiconductor layer 7. The bottoms of the multiple well regions 30 are directly connected to the second semiconductor layer 7. The multiple well regions 30 form a JFET region Tj (Junction Field-Effect Transistor region) together with the second semiconductor layer 7 in the region below the gate structure 15.

[0105] In this embodiment, the depth of the well region relative to the bottom wall of the gate structure 15 is smaller than the depth of the gate structure 15 relative to the first main surface 3. The depth of the well region 30 may be larger than the depth of the gate structure 15 relative to the first main surface 3.

[0106] The depth of the well region 30 may be 0.5 μm or more and 5 μm or less. The depth of the well region 30 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0107] The multiple well regions 30 each include a first well region 31 located on the bottom wall side of the gate structure 15 and a second well region 32 located on the bottom side of the second semiconductor layer 7. The first well region 31 is located on the bottom wall side of the gate structure 15 with respect to the depth position of the middle part of the well region 30, and forms the upper end part of the well region 30.

[0108] In the second direction Y, both ends of the first well region 31 may be located inward of both ends of the gate structure 15 relative to the gate structure 15, or may be located on the peripheral edge side of the active region 8. The first well region 31 may face the buried electrode 18 via the insulating film 17. The first well region 31 may have a portion facing the buried electrode 18 with the first film portion 20 interposed therebetween, and a portion facing the buried electrode 18 with the second film portion 21 interposed therebetween.

[0109] In this embodiment, the first well region 31 has a portion that is aligned with the first film portion 20 and a portion that is aligned with the second film portion 21. In other words, the first well region 31 has a portion that faces the buried electrode 18 across the first film portion 20, and a portion that faces the buried electrode 18 across the second film portion 21.

[0110] The first well region 31 may have a portion that extends along the sidewall of the gate structure 15. That is, the first well region 31 may have a portion that extends along the first film portion 20 and a portion that extends along the second film portion 21 on the sidewall of the gate structure 15. The first well region 31 may be formed at a distance from the bottom wall of the gate structure 15 toward the bottom of the second semiconductor layer 7.

[0111] The ratio of the depth of the first well region 31 to the depth of the well region 30 (first depth ratio) may be greater than 0 and less than 0.5. The first depth ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to 0.5. The first depth ratio is preferably less than 0.5.

[0112] The depth of the first well region 31 is smaller than the depth of the gate structure 15. The depth of the first well region 31 may be greater than 0 μm and less than or equal to 1 μm. The depth of the first well region 31 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.5 μm to 0.6 μm, 0.6 μm to 0.7 μm, 0.7 μm to 0.8 μm, 0.8 μm to 0.9 μm, and 0.9 μm to 1 μm. The depth of the first well region 31 is preferably less than or equal to 0.5 μm.

[0113] The second well region 32 is located closer to the bottom of the second semiconductor layer 7 than the first well region 31, and forms the bottom of the well region 30. The second well region 32 extends in a strip shape in the second direction Y following the extension direction of the gate structure 15. With respect to the second direction Y, both ends of the second well region 32 may be located on the inner side of the gate structure 15 relative to both ends of the gate structure 15, or may be located on the peripheral side of the active region 8.

[0114] In this embodiment, the second well region 32 has a portion located on the bottom wall side of the gate structure 15 corresponding to the depth position of the middle part of the well region 30, and a portion located on the bottom side of the second semiconductor layer 7 corresponding to the depth position of the middle part of the well region 30.

[0115] In this embodiment, the second well region 32 has a portion that is aligned with the first film portion 20 and a portion that is aligned with the second film portion 21. In other words, the second well region 32 has a portion that faces the first film portion 20 across the first well region 31, and a portion that faces the second film portion 21 across the first well region 31.

[0116] The depth of the second well region 32 is obtained by subtracting the depth of the first well region 31 from the depth of the well region 30. The depth of the second well region 32 is measured from the bottom of the first well region 31. The ratio of the depth of the second well region 32 to the depth of the well region 30 (second depth ratio) is calculated by "1 - first depth ratio."

[0117] The second depth ratio is preferably equal to or greater than 0.5. It is particularly preferable that the second depth ratio is greater than 0.5. In this embodiment, the depth of the second well region 32 is smaller than the depth of the gate structure 15. The depth of the second well region 32 may be greater than the depth of the gate structure 15.

[0118] The depth of the second well region 32 may be 0.5 μm or more and 5 μm or less. The depth of the second well region 32 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0119] The semiconductor device 1 includes a plurality of n-type source regions 40 formed in the body region 10 in the active region 8. The source regions 40 have a higher n-type impurity concentration than the p-type impurity concentration of the body region 10, thereby converting the conductivity type of the body region 10 from p-type to n-type. The n-type impurity concentration of the source regions 40 is higher than the n-type impurity concentration of the second semiconductor layer 7.

[0120] The plurality of source regions 40 are formed in the plurality of mesa portions 27 in the surface layer portion of the body region 10. In this embodiment, the plurality of source regions 40 are formed at intervals in the second direction Y in a one-to-many correspondence with the plurality of mesa portions 27, and are adjacent to two gate structures 15 corresponding to the first direction X. In this embodiment, the plurality of source regions 40 each extend in a strip shape in the second direction Y following the extension direction of the plurality of gate structures 15 in a plan view.

[0121] The plurality of source regions 40 on one side in the first direction X face the plurality of source regions 40 on the other side in the first direction X, with a corresponding gate structure 15 sandwiched between them. That is, the plurality of source regions 40 are arranged in a line in the first direction X in a planar view. In this embodiment, the plurality of source regions 40 are arranged in a matrix with intervals in the first direction X and the second direction Y in a planar view.

[0122] The plurality of source regions 40 on one side in the first direction X may face regions between the plurality of source regions 40 on the other side in the first direction X, with a corresponding gate structure 15 sandwiched therebetween. In other words, the plurality of source regions 40 may be arranged in a staggered pattern at intervals in the first direction X and the second direction Y in a plan view.

[0123] The source regions 40 each have a thickness (depth) less than the thickness (depth) of the body region 10, and are formed at intervals from the bottom of the body region 10 toward the first main surface 3. The source regions 40 face the second semiconductor layer 7 with a part (bottom) of the body region 10 between them.

[0124] The plurality of source regions 40 each have a bottom located on the bottom side of the body region 10 relative to the height position of the electrode surfaces of the plurality of buried electrodes 18. Specifically, the plurality of source regions 40 each have a portion located on the bottom wall side of the plurality of trenches 16 relative to the electrode surfaces of the plurality of buried electrodes 18, and a portion located on the first main surface 3 side relative to the electrode surfaces of the plurality of buried electrodes 18.

[0125] Each of the plurality of source regions 40 has a portion that faces the corresponding buried electrode 18 in the horizontal direction, with the corresponding insulating film 17 interposed therebetween, and a portion that faces the buried insulator 19 in the horizontal direction, with the corresponding insulating film 17 interposed therebetween. Each of the plurality of source regions 40 has a portion that faces the buried electrode 18, with the corresponding first film portion 20 interposed therebetween, and a portion that faces the buried insulator 19, with the corresponding first film portion 20 interposed therebetween.

[0126] In this embodiment, the multiple source regions 40 are formed in portions along the first film portion 20, spaced apart inward from the second film portion 21. That is, in this embodiment, the multiple outermost source regions 40 are each formed inward from the second film portion 21, spaced apart, and do not have portions along the second film portion 21. Of course, one or more of the outermost source regions 40 may have a portion facing the buried electrode 18 across the corresponding second film portion 21, and a portion facing the buried insulator 19 across the corresponding second film portion 21.

[0127] The plurality of source regions 40 each have a portion located on the bottom wall side of the plurality of trenches 16 with respect to the insulating surfaces of the plurality of buried insulators 19, and a portion located on the first main surface 3 side with respect to the insulating surfaces of the plurality of buried insulators 19. In this embodiment, the plurality of source regions 40 each have a portion exposed from the opening end of the corresponding trench 16.

[0128] The source region 40 has a thickness (depth) greater than the thickness between the bottom of the body region 10 and the bottom of the source region 40. The thickness of the source region 40 may be less than the thickness between the bottom of the body region 10 and the bottom of the source region 40. The thickness (depth) of the peripheral portions of the multiple source regions 40 gradually decreases from the bottom side of the body region 10 toward the first main surface 3 along the second direction Y. The multiple source regions 40, together with the second semiconductor layer 7, define a channel CH that serves as a current path on the bottom side of the body region 10 (see FIG. 10 ).

[0129] The channel CH may have a channel length greater than 0 nm and less than or equal to 300 nm. The channel length is the shortest distance between the bottom of the body region 10 and the bottom of the source region 40. The channel length may have a value belonging to at least one of the following ranges: greater than 0 nm and less than or equal to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, and 250 nm to 300 nm.

[0130] The semiconductor device 1 includes a plurality of contact regions 42 formed in the chip 2 (second semiconductor layer 7) in the active region 8. A source potential is applied to the contact regions 42. The contact regions 42 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the contact regions 42 is higher than the p-type impurity concentration of the body region 10.

[0131] The p-type impurity concentration of the contact region 42 is higher than the p-type impurity concentration of the second well region 32. The p-type impurity concentration of the contact region 42 may be higher or lower than the p-type impurity concentration of the first well region 31. The p-type impurity concentration of the contact region 42 may be higher or lower than the n-type impurity concentration of the source region 40.

[0132] The plurality of contact regions 42 are respectively formed in regions along the plurality of gate structures 15. The plurality of contact regions 42 are formed at intervals in the second direction Y in a one-to-many correspondence with the plurality of gate structures 15. In this embodiment, the plurality of contact regions 42 are formed in a portion along the first film portion 20 at intervals inward from the second film portion 21.

[0133] Specifically, the plurality of contact regions 42 are respectively interposed in regions between the plurality of source regions 40. The plurality of contact regions 42 may be connected to the plurality of source regions 40 in the second direction Y. The plurality of contact regions 42 may be formed at intervals from the plurality of source regions 40 in the second direction Y. In this case, the plurality of contact regions 42 may face the plurality of source regions 40 with a part of the body region 10 sandwiched therebetween.

[0134] With respect to one and the other gate structures 15, the plurality of contact regions 42 along one gate structure 15 face the plurality of contact regions 42 along the other gate structure 15 in the first direction X in a plan view. In other words, the plurality of contact regions 42 are generally arranged in a matrix at intervals in the first direction X and the second direction Y in a plan view.

[0135] In plan view, one of the plurality of contact regions 42 may face a region between the other of the plurality of contact regions 42 in the first direction X. In other words, the plurality of contact regions 42 may be generally arranged in a staggered pattern with intervals in the first direction X and the second direction Y in plan view.

[0136] The contact regions 42 may extend in a strip-like shape in the second direction Y in a plan view, following the extension direction of the gate structures 15. The lengths of the contact regions 42 in the second direction Y may be equal to each other or may be different from each other. The lengths of the contact regions 42 in the second direction Y are adjusted depending on the area of ​​the channel to be formed.

[0137] The channel area is the total area of ​​the portions of the source regions 40 exposed from the regions between the gate structures 15. That is, the channel area increases or decreases depending on the ratio of the total planar area of ​​the contact regions 42. The total planar area of ​​the contact regions 42 is preferably less than the channel area. That is, in the regions between the gate structures 15, the total planar area of ​​the contact regions 42 is preferably less than the planar area of ​​the source regions 40.

[0138] The length of the contact region 42 may be greater or smaller than the width of the gate structure 15. The length of the contact region 42 may be greater or smaller than the spacing between the multiple gate structures 15 (the width of the mesa portion 27). The spacing between the multiple contact regions 42 may be greater or smaller than the width of the gate structure 15. The spacing between the contact regions 42 may be greater or smaller than the spacing between the multiple gate structures 15.

[0139] The contact regions 42 each include a first region 42A, a second region 42B, and a third region 42C. The first region 42A extends along the bottom wall of the corresponding gate structure 15. The first region 42A is interposed in a region between the bottom wall of the corresponding gate structure 15 and the bottom of the corresponding well region 30, and is connected to the bottom wall of the corresponding gate structure 15 and the corresponding well region 30.

[0140] The first region 42A faces the buried electrode 18 via the insulating film 17. In this embodiment, the first region 42A faces the buried electrode 18 across the first film portion 20. Of course, if the contact region 42 is formed in a portion along the second film portion 21, the first region 42A may face the buried electrode 18 across the second film portion 21.

[0141] The first region 42A has a thickness greater than that of the first well region 31, and has a bottom located closer to the bottom of the second well region 32 than the depth position of the lower end (bottom) of the first well region 31. The thickness of the first region 42A is the thickness of the first region 42A in the vertical direction Z, with the bottom wall of the gate structure 15 as the reference.

[0142] The bottom of the first region 42A is formed at a distance from the bottom of the second well region 32 toward the bottom wall of the gate structure 15, and faces the second semiconductor layer 7 across a part of the second well region 32. The bottom of the first region 42A may be located on the bottom wall side of the gate structure 15 with respect to the depth position of the intermediate portion of the second well region 32. The bottom of the first region 42A may be located on the bottom side of the second well region 32 with respect to the depth position of the intermediate portion of the second well region 32.

[0143] The first region 42A has a width greater than that of the gate structure 15, and extends horizontally from a region directly below the corresponding gate structure 15 to both sides of the corresponding gate structure 15. The first region 42A is connected to the first well region 31 and the second well region 32, and increases the p-type impurity concentration of the first well region 31 and the p-type impurity concentration of the second well region 32.

[0144] The first region 42A may have a thickness less than that of the first well region 31, and may be formed at a distance from the depth position of the lower end of the first well region 31 toward the bottom wall of the gate structure 15. In this case, the first region 42A may face the second well region 32 with a part of the first well region 31 in between.

[0145] The second region 42B is a portion that extends along the sidewall of the gate structure 15. In this embodiment, the second region 42B faces the buried electrode 18 across the first film portion 20. Of course, if the contact region 42 is formed in a portion that extends along the second film portion 21, the second region 42B may face the buried electrode 18 across the second film portion 21.

[0146] The second region 42B has a thickness less than that of the first region 42A. The thickness of the second region 42B is the horizontal thickness of the second region 42B based on the sidewall of the gate structure 15. The second region 42B is connected to the first region 42A on the bottom wall side of the gate structure 15, and is connected to the body region 10 on the first main surface 3 side.

[0147] That is, the second region 42B electrically connects the corresponding well region 30 to the body region 10. This prevents the well region 30 from being electrically floating, and improves the electrical response characteristics of the well region 30.

[0148] The third region 42C is a portion that extends in a layer shape along the first main surface 3 in the surface layer portion of the first main surface 3 and is exposed from the first main surface 3. In other words, the third region 42C forms the upper end portion of the contact region 42. In this embodiment, the upper end portion of the third region 42C is exposed from the sidewall of the trench 16 at the opening end of the trench 16.

[0149] The third region 42C is formed integrally with the third region 42C of the adjacent contact region 42. That is, the multiple contact regions 42 are electrically connected to each other via the multiple third regions 42C. The third region 42C has a thickness (depth) less than the thickness (depth) of the body region 10, and faces the second semiconductor layer 7 with a part (bottom) of the body region 10 sandwiched therebetween. The thickness of the third region 42C is the thickness of the third region 42C in the vertical direction Z, with the first main surface 3 as the reference.

[0150] The third region 42C has a bottom located on the bottom side of the body region 10 relative to the height position of the electrode surfaces of the plurality of buried electrodes 18. Specifically, the third region 42C has a portion located on the bottom wall side of the plurality of trenches 16 relative to the electrode surfaces of the plurality of buried electrodes 18, and a portion located on the first main surface 3 side relative to the electrode surfaces of the plurality of buried electrodes 18.

[0151] The third region 42C has a portion facing the corresponding buried electrode 18 across the corresponding insulating film 17, and a portion facing the buried insulator 19 across the corresponding insulating film 17. The third region 42C has a portion facing the buried electrode 18 across the corresponding first film portion 20, and a portion facing the buried insulator 19 across the corresponding first film portion 20.

[0152] Of course, when the contact region 42 is formed in a portion along the second film portion 21, the third region 42C may have a portion facing the buried electrode 18 across the corresponding second film portion 21, and a portion facing the buried insulator 19 across the corresponding second film portion 21.

[0153] The third region 42C has a portion located on the bottom wall side of the trenches 16 with respect to the insulating surfaces of the buried insulators 19, and a portion located on the first main surface 3 side with respect to the insulating surfaces of the buried insulators 19. In this embodiment, the third region 42C has a portion exposed from the opening end of the corresponding trench 16.

[0154] The thickness of the third region 42C is greater than the thickness of the second region 42B. The thickness of the third region 42C may be approximately equal to the thickness of the first region 42A. The thickness of the third region 42C may be greater or less than the thickness of the first region 42A. The thickness of the third region 42C is less than the thickness (depth) of the source region 40. The third region 42C has a bottom located closer to the first main surface 3 than the bottom of the source region 40.

[0155] The thickness of the third region 42C may be greater than the thickness of the source region 40. The thickness of the third region 42C may be less than the thickness between the bottom of the body region 10 and the bottom of the third region 42C. The thickness of the third region 42C may be less than the thickness between the bottom of the body region 10 and the bottom of the third region 42C.

[0156] 9 and 14 , semiconductor device 1 includes a p-type outer well region 45 formed in a surface layer portion of first main surface 3 in peripheral region 9 (the peripheral portion of first main surface 3). A source potential is applied to outer well region 45. Outer well region 45 has a p-type impurity concentration higher than the n-type impurity concentration of second semiconductor layer 7. The p-type impurity concentration of outer well region 45 may be higher or lower than the p-type impurity concentration of body region 10.

[0157] The p-type impurity concentration of the outer well region 45 is lower than the p-type impurity concentration of the contact region 42. The p-type impurity concentration of the outer well region 45 is lower than the p-type impurity concentration of the first well region 31. The p-type impurity concentration of the outer well region 45 may be higher or lower than the p-type impurity concentration of the second well region 32.

[0158] The outer well region 45 is formed in a surface layer portion of the second semiconductor layer 7. The outer well region 45 extends in a layered manner along the first main surface 3. The outer well region 45 is formed at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the multiple gate structures 15. The outer well region 45 extends in a band shape along the periphery (periphery of the active region 8) of the first main surface 3 in a plan view.

[0159] In this embodiment, the outer well region 45 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 8) of the first main surface 3. In other words, the outer well region 45 collectively surrounds the multiple gate structures 15.

[0160] The outer well region 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The outer well region 45 has an inner edge portion on the side of the multiple gate structures 15 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer well region 45 defines the boundary between the active region 8 and the outer periphery region 9.

[0161] The inner edge of the outer well region 45 is connected to the ends of the multiple gate structures 15 in a portion extending in the first direction X. The inner edge of the outer well region 45 faces the buried electrode 18 across the insulating film 17. The outer well region 45 has a portion that extends along the second film portion 21, and faces the buried electrode 18 across the second film portion 21.

[0162] The inner edge of the outer well region 45 may be located closer to the inner side of the plurality of gate structures 15 than the ends of the plurality of gate structures 15. The inner edge of the outer well region 45 may have a portion located in a region between the plurality of gate structures 15 and connected to the body region 10. The outer edge of the outer well region 45 is formed spaced inward from the periphery of the chip 2 and extends approximately parallel to the inner edge of the outer well region 45.

[0163] The outer well region 45 may have a width greater than 0 μm and less than 300 μm. The width of the outer well region 45 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0164] The outer well region 45 is formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 across a part of the second semiconductor layer 7. The outer well region 45 may be formed at a distance from the depth position of the intermediate portion of the second semiconductor layer 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor layer 7 (toward the second main surface 4) with respect to the depth position of the intermediate portion of the second semiconductor layer 7.

[0165] In this embodiment, the outer well region 45 is formed at an interval toward the first main surface 3 from the depth position of the bottom walls of the plurality of gate structures 15. The depth of the outer well region 45 may be greater or smaller than the depth of the body region 10.

[0166] The outer well region 45 may have a portion located on the bottom side of the second semiconductor layer 7 with respect to the depth positions of the bottom walls of the plurality of gate structures 15. In this case, the outer well region 45 may be connected to either one or both of the first well region 31 and the second well region 32.

[0167] The outer well region 45 forms a pn junction with the second semiconductor layer 7. The outer well region 45 spreads a depletion layer into the second semiconductor layer 7 when a reverse bias voltage is applied. The depletion layer in the outer well region 45 spreads in the horizontal and thickness directions and integrates with the depletion layers spreading from the body region 10 and the well region 30. The outer well region 45 expands the depletion layers spreading from the body region 10 and the well region 30 toward the peripheral edge of the first main surface 3, thereby reducing the electric field intensity (electric field concentration) in the peripheral portion (peripheral region 9) of the first main surface 3.

[0168] The semiconductor device 1 includes a p-type outer contact region 46 formed in a surface layer portion of the outer well region 45. The outer contact region 46 has a p-type impurity concentration higher than the p-type impurity concentration of the outer well region 45. The p-type impurity concentration of the outer contact region 46 is higher than the p-type impurity concentration of the body region 10.

[0169] The p-type impurity concentration of the outer contact region 46 may be approximately equal to the p-type impurity concentration of the contact region 42. The p-type impurity concentration of the outer contact region 46 may be higher or lower than the p-type impurity concentration of the contact region 42.

[0170] The outer contact region 46 is formed at a distance from the bottom of the outer well region 45 toward the first main surface 3, and faces the second semiconductor layer 7 across a part of the outer well region 45. The outer contact region 46 extends in a strip shape along the outer well region 45 (active region 8) in a plan view.

[0171] In this embodiment, the outer contact region 46 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the multiple gate structures 15 (active regions 8). The outer contact region 46 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0172] The semiconductor device 1 may include a plurality of outer contact regions 46 arranged at intervals along the extension direction of the outer well region 45 so as to surround the plurality of gate structures 15. In this case, the plurality of outer contact regions 46 may each extend in a strip shape along the extension direction of the outer well region 45.

[0173] The outer contact region 46 has a width less than the width of the outer well region 45, and is formed within the outer well region 45. The outer contact region 46 is formed in the inner portion of the outer well region 45 with a gap between both edges of the outer well region 45. The outer contact region 46 is biased toward the outer edge of the outer well region 45 relative to the central portion of the outer well region 45. The outer contact region 46 may be formed in the central portion of the outer well region 45.

[0174] The semiconductor device 1 includes at least one (in this embodiment, multiple) p-type field region 47 formed in the surface layer portion of the first main surface 3 in the peripheral region 9 (the peripheral portion of the first main surface 3). The multiple field regions 47 may be formed in an electrically floating state. The multiple field regions 47 may be fixed to the source potential.

[0175] The number of field regions 47 is arbitrary. The number of field regions 47 may be 1 or more and 20 or less. The number of field regions 47 may be a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less. The number of field regions 47 is typically 1 or more and 8 or less. In this embodiment, the semiconductor device 1 includes five field regions 47.

[0176] The plurality of field regions 47 are formed at intervals from one another in the surface layer portion of the second semiconductor layer 7. The plurality of field regions 47 are formed at intervals inward from the periphery of the first main surface 3 in regions between the periphery of the first main surface 3 and the plurality of gate structures 15 (active regions 8). Specifically, the plurality of field regions 47 are formed in regions between the periphery of the first main surface 3 and the outer well region 45.

[0177] The field regions 47 extend in a strip shape along the gate structures 15 (active regions 8) in a plan view. Specifically, the field regions 47 extend in a strip shape along the outer well region 45. Each of the field regions 47 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y.

[0178] In this embodiment, the plurality of field regions 47 are formed in polygonal ring shapes (square ring shapes in this embodiment) surrounding the plurality of gate structures 15 (active regions 8) in plan view. The plurality of field regions 47 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0179] The plurality of field regions 47 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 across a part of the second semiconductor layer 7. The plurality of field regions 47 may be formed at intervals from a depth position of the intermediate portion of the second semiconductor layer 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor layer 7 (toward the second main surface 4) with respect to the depth position of the intermediate portion of the second semiconductor layer 7.

[0180] In this embodiment, the field regions 47 are formed at intervals from the depth position of the bottom walls of the gate structures 15 toward the first main surface 3. The depth of the field regions 47 may be greater or smaller than the depth of the body region 10. The field regions 47 may have portions located on the bottom side of the second semiconductor layer 7 relative to the depth position of the bottom walls of the gate structures 15.

[0181] The plurality of field regions 47 form pn junctions with the second semiconductor layer 7. The plurality of field regions 47 spread a depletion layer in the second semiconductor layer 7 when a reverse bias voltage is applied. The depletion layers in the plurality of field regions 47 spread in the horizontal direction and the thickness direction, and merge with the depletion layers spreading from the body region 10 and the outer well region 45.

[0182] The multiple field regions 47 expand the depletion layer extending from the body region 10 and the outer well region 45 toward the peripheral side of the first main surface 3, thereby reducing the electric field strength (electric field concentration) in the peripheral portion (peripheral region 9) of the first main surface 3.

[0183] The width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 47 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 47 may be substantially uniform or non-uniform. The width of the multiple field regions 47 may gradually increase toward the periphery of the first main surface 3. The width of the multiple field regions 47 may gradually decrease toward the periphery of the first main surface 3.

[0184] The depth of the multiple field regions 47 may be approximately constant or non-uniform. The depth of the multiple field regions 47 may gradually increase toward the peripheral edge of the first main surface 3. The depth of the multiple field regions 47 may gradually decrease toward the peripheral edge of the first main surface 3. Of course, the multiple field regions 47 may have a relatively shallow portion and a deep portion that is deeper than the shallow portion. The shallow portion may be formed on the inward side, and the deep portion may be formed on the peripheral edge side. The shallow portion may be formed on the peripheral edge side, and the deep portion may be formed on the inward side.

[0185] The spacing between the multiple field regions 47 may be substantially uniform or non-uniform. The spacing between the multiple field regions 47 may gradually increase toward the peripheral edge of the first main surface 3. The spacing between the multiple field regions 47 may gradually decrease toward the peripheral edge of the first main surface 3.

[0186] The p-type impurity concentrations of the multiple field regions 47 may be substantially constant or non-uniform. The p-type impurity concentrations of the multiple field regions 47 may gradually increase toward the periphery of the first main surface 3. The p-type impurity concentrations of the multiple field regions 47 may gradually decrease toward the periphery of the first main surface 3.

[0187] The plurality of field regions 47 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the plurality of body regions 10. The p-type impurity concentration of the plurality of field regions 47 may be higher or lower than the p-type impurity concentration of the plurality of body regions 10.

[0188] The plurality of field regions 47 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the contact region 42. The p-type impurity concentration of the plurality of field regions 47 may be higher or lower than the p-type impurity concentration of the contact region 42.

[0189] The plurality of field regions 47 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the outer well region 45. The p-type impurity concentration of the plurality of field regions 47 may be higher or lower than the p-type impurity concentration of the outer well region 45.

[0190] The semiconductor device 1 includes a surface insulating film 50 that selectively covers the first main surface 3. The surface insulating film 50 may also be referred to as a "main surface insulating film" or an "outer surface insulating film," etc. The surface insulating film 50 covers the first main surface 3 in the peripheral region 9 in a film-like manner.

[0191] Specifically, the surface insulating film 50 covers the outer well region 45, the outer contact region 46, and the plurality of field regions 47 in the peripheral region 9. The surface insulating film 50 is continuous with the first to fourth side surfaces 5A to 5D. The surface insulating film 50 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0192] The surface insulating film 50 extends from the peripheral region 9 to the active region 8 and covers the peripheries of the ends of the plurality of gate structures 15 in the active region 8. The surface insulating film 50 is connected to the insulating films 17 of the plurality of gate structures 15 and exposes the buried electrodes 18 and buried insulators 19. The surface insulating film 50 has portions located in regions between the plurality of gate structures 15. The surface insulating film 50 is connected to the insulating films 17 at both the portions of the ends of the plurality of gate structures 15 that extend in the first direction X and the portions that extend in the second direction Y.

[0193] The surface insulating film 50 includes a first surface film portion 51 and a second surface film portion 52. The first surface film portion 51 has a relatively small third thickness and covers the peripheries of the ends of the multiple gate structures 15. The first surface film portion 51 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. The first surface film portion 51 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the multiple gate structures 15 (active regions 8) in a plan view.

[0194] The first surface film portion 51 is connected to the second film portion 21 of the insulating film 17 at the ends of the plurality of gate structures 15, and exposes the buried electrodes 18 and the buried insulators 19. The first surface film portion 51 has a portion located in a region between the plurality of gate structures 15, and covers either or both of the body region 10 and the outer well region 45.

[0195] The first surface film portion 51 is connected to the second film portion 21 at both the portions of the ends of the multiple gate structures 15 that extend in the first direction X and the portions that extend in the second direction Y. The first surface film portion 51 may or may not be connected to the first film portion 20.

[0196] The first surface film portion 51 is formed in a region between the ends of the plurality of gate structures 15 and the plurality of field regions 47, and covers the outer well region 45. The first surface film portion 51 covers a region on the inner side of the first main surface 3 relative to the outer edge of the outer well region 45. The first surface film portion 51 covers a region between the ends of the plurality of gate structures 15 and the inner edge of the outer contact region 46. The first surface film portion 51 is formed at a distance from the inner edge of the outer contact region 46 towards the ends of the plurality of gate structures 15.

[0197] The first surface film portion 51 has a width greater than the width of the gate structure 15. Of course, the width of the first surface film portion 51 may be smaller than the width of the gate structure 15. The width of the first surface film portion 51 is the width from the end of the gate structure 15 toward the periphery of the first main surface 3.

[0198] The width of the first surface film portion 51 may be greater than 0 μm and less than 5 μm. The width of the first surface film portion 51 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4 μm to 5 μm.

[0199] The first surface film portion 51 has a laminated structure including a first surface insulating film 53 and a second surface insulating film 54 laminated in this order from the first main surface 3 side. In other words, the first surface film portion 51 has a number of laminated layers different from the number of laminated layers of the first film portion 20. The number of laminated layers of the first surface film portion 51 is greater than the number of laminated layers of the first film portion 20. The number of laminated layers of the first surface film portion 51 is equal to the number of laminated layers of the second film portion 21.

[0200] The first surface insulating film 53 covers the peripheries of the ends of the plurality of gate structures 15. The first surface insulating film 53 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. The first surface insulating film 53 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 15 (active regions 8) in plan view.

[0201] The first surface insulating film 53 is connected to the second insulating film 23 at ends of the plurality of gate structures 15, and exposes the buried electrodes 18 and the buried insulators 19. The first surface insulating film 53 has portions located in regions between the plurality of gate structures 15, and covers either or both of the body region 10 and the outer well region 45. The first surface insulating film 53 is connected to the second insulating film 23 at both portions of the ends of the plurality of gate structures 15 that extend in the first direction X and that extend in the second direction Y.

[0202] The first surface insulating film 53 is formed in regions between the ends of the multiple gate structures 15 and the multiple field regions 47, and covers the outer well region 45. The first surface insulating film 53 covers a region closer to the ends of the multiple gate structures 15 than the outer edge of the outer well region 45. The first surface insulating film 53 covers a region between the ends of the multiple gate structures 15 and the inner edge of the outer contact region 46. The first surface insulating film 53 is formed at a distance from the inner edge of the outer contact region 46 towards the ends of the multiple gate structures 15.

[0203] The first surface insulating film 53 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first surface insulating film 53 may include an insulator that is the same as or different from the first insulating film 22. The first surface insulating film 53 may include an insulator that is the same as or different from the second insulating film 23. The first surface insulating film 53 may include an insulator that is the same as or different from the third insulating film 24.

[0204] In this embodiment, the first surface insulating film 53 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. The first surface film portion 51 preferably contains an oxide other than the oxide of the chip 2. In this embodiment, the first surface insulating film 53 is made of an NSG film.

[0205] In this embodiment, the first surface insulating film 53 is made of the same insulating film as the second insulating film 23, and is formed integrally with the second insulating film 23. The first surface insulating film 53 is formed as an extension portion of the second insulating film 23, and is extended from the trench 16 onto the first main surface 3.

[0206] The thickness of the first surface insulating film 53 may be greater or less than the thickness of the first insulating film 22. The thickness of the first surface insulating film 53 may be greater or less than the thickness of the second insulating film 23. The thickness of the first surface insulating film 53 may be greater or less than the thickness of the third insulating film 24.

[0207] The thickness of the first surface insulating film 53 may be greater or smaller than the first thickness of the first film portion 20 (first insulating film 22). The thickness of the first surface insulating film 53 may be greater or smaller than the second thickness of the second film portion 21. In this embodiment, the thickness of the first surface insulating film 53 is approximately equal to the thickness of the second insulating film 23.

[0208] The thickness of the first surface insulating film 53 may be 10 nm or more and 250 nm or less. The thickness of the first surface insulating film 53 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0209] The second surface insulating film 54 directly covers the first surface insulating film 53 around the ends of the plurality of gate structures 15. The second surface insulating film 54 may have a portion extending in a strip shape in the first direction X following the extension direction of the first surface insulating film 53, and a portion extending in a strip shape in the second direction Y. The second surface insulating film 54 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 15 (active regions 8) in a plan view.

[0210] The second surface insulating film 54 is connected to the third insulating film 24 of the insulating film 17 at ends of the plurality of gate structures 15, and exposes the buried electrodes 18 and the buried insulators 19. The second surface insulating film 54 has portions located in regions between the plurality of gate structures 15, and covers either or both of the body region 10 and the outer well region 45 across the first surface insulating film 53. The second surface insulating film 54 is connected to the third insulating film 24 at both portions of the ends of the plurality of gate structures 15 that extend in the first direction X and that extend in the second direction Y.

[0211] The second surface insulating film 54 is formed in regions between ends of the plurality of gate structures 15 and the plurality of field regions 47, and covers the outer well region 45 across the first surface insulating film 53. The second surface insulating film 54 covers a region on the inner side of the first main surface 3 than the outer edge of the outer well region 45.

[0212] The second surface insulating film 54 covers the region between the ends of the multiple gate structures 15 and the inner edge of the outer contact region 46. The second surface insulating film 54 is formed at a distance from the inner edge of the outer contact region 46 toward the ends of the multiple gate structures 15.

[0213] The second surface insulating film 54 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second surface insulating film 54 may include an insulator that is the same as or different from that of the first insulating film 22. The second surface insulating film 54 may include an insulator that is the same as or different from that of the second insulating film 23. The second surface insulating film 54 may include an insulator that is the same as or different from that of the third insulating film 24.

[0214] The second surface insulating film 54 may contain the same or a different insulator as the first surface insulating film 53. In this embodiment, the second surface insulating film 54 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. In this embodiment, the second surface insulating film 54 is made of an NSG film.

[0215] In this embodiment, the second surface insulating film 54 is made of the same insulating film as the third insulating film 24, and is formed integrally with the first insulating film 22 and the third insulating film 24. The second surface insulating film 54 is formed as an extension portion of the third insulating film 24 (first insulating film 22), and is extended from the trench 16 onto the first main surface 3.

[0216] The thickness of the second surface insulating film 54 may be greater or less than the first thickness of the first film portion 20. The thickness of the second surface insulating film 54 may be greater or less than the second thickness of the second film portion 21. The thickness of the second surface insulating film 54 may be greater or less than the thickness of the second insulating film 23. The thickness of the second surface insulating film 54 may be greater or less than the thickness of the third insulating film 24.

[0217] The thickness of the second surface insulating film 54 may be greater or smaller than the thickness of the first surface insulating film 53. In this embodiment, the thickness of the second surface insulating film 54 is approximately equal to the thickness of the third insulating film 24.

[0218] The thickness of the second surface insulating film 54 may be 10 nm or more and 250 nm or less. The thickness of the second surface insulating film 54 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0219] The third thickness of the first surface film portion 51 (i.e., the total thickness of the first surface insulating film 53 and the second surface insulating film 54) is greater than the first thickness of the first film portion 20. In this embodiment, the third thickness is approximately equal to the second thickness of the second film portion 21. The third thickness may be greater or smaller than the second thickness of the second film portion 21.

[0220] The third thickness may be 20 nm to 500 nm. The third thickness may have a value belonging to at least one of the ranges of 20 nm to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0221] The second surface film portion 52 has a fourth thickness different from the third thickness, and directly covers the first main surface 3 around the first surface film portion 51. The second surface film portion 52 has a width greater than the width of the first surface film portion 51, and covers in a film-like manner an area on the peripheral side of the first main surface 3 relative to the first surface film portion 51. The distance between the multiple gate structures 15 and the second surface film portion 52 corresponds to the width of the first surface film portion 51.

[0222] The second surface film portion 52 covers the outer well region 45 and the plurality of field regions 47 across the first surface film portion 51. The second surface film portion 52 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y.

[0223] The second surface film portion 52 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 15 (active regions 8) in a plan view. The second surface film portion 52 is continuous with the first to fourth side surfaces 5A to 5D. The second surface film portion 52 may be formed at a distance inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0224] The second surface film portion 52 has a laminated structure including a third surface insulating film 55, a fourth surface insulating film 56 and a fifth surface insulating film 57 laminated in this order from the first main surface 3 side around the first surface film portion 51.

[0225] That is, the second surface film portion 52 has a different number of layers than the first surface film portion 51. The number of layers of the second surface film portion 52 is greater than the number of layers of the first surface film portion 51. Furthermore, the number of layers of the second surface film portion 52 is different from the number of layers of the first film portion 20 and the number of layers of the second film portion 21. The number of layers of the second surface film portion 52 is greater than the number of layers of the first film portion 20 and the number of layers of the second film portion 21.

[0226] The third surface insulating film 55 directly covers the first main surface 3 around the first surface film portion 51. The third surface insulating film 55 covers, in film form, the region on the peripheral side of the first main surface 3 relative to the first surface film portion 51. The third surface insulating film 55 covers the outer well region 45, the outer contact region 46, and the plurality of field regions 47.

[0227] The third surface insulating film 55 may have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y. The third surface insulating film 55 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 15 (active regions 8) in a plan view. The second surface film portion 52 is continuous with the first to fourth side surfaces 5A to 5D. The third surface insulating film 55 is continuous with the first to fourth side surfaces 5A to 5D. The third surface insulating film 55 may be formed at a distance inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0228] The third surface insulating film 55 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The third surface insulating film 55 may include an insulator that is the same as or different from that of the first insulating film 22. The third surface insulating film 55 may include an insulator that is the same as or different from that of the second insulating film 23. The third surface insulating film 55 may include an insulator that is the same as or different from that of the third insulating film 24.

[0229] The third surface insulating film 55 may contain the same or a different insulator as the first surface insulating film 53. The third surface insulating film 55 may contain the same or a different insulator as the second surface insulating film 54. In this embodiment, the third surface insulating film 55 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. It is preferable that the second surface film portion 52 contains an oxide other than the oxide of the chip 2. In this embodiment, the third surface insulating film 55 is made of an NSG film.

[0230] The thickness of the third surface insulating film 55 may be greater or less than the first thickness of the first film portion 20. The thickness of the third surface insulating film 55 may be greater or less than the second thickness of the second film portion 21. The thickness of the third surface insulating film 55 may be greater or less than the thickness of the second insulating film 23. The thickness of the third surface insulating film 55 may be greater or less than the thickness of the third insulating film 24.

[0231] The thickness of the third surface insulating film 55 may be greater or smaller than the third thickness of the first surface film portion 51. The thickness of the third surface insulating film 55 may be greater or smaller than the thickness of the first surface insulating film 53. The thickness of the third surface insulating film 55 may be greater or smaller than the thickness of the second surface insulating film 54. In this embodiment, the thickness of the third surface insulating film 55 is greater than the thicknesses of the first insulating film 22, the second insulating film 23, the third insulating film 24, the first surface insulating film 53, and the second surface insulating film 54.

[0232] The thickness of the third surface insulating film 55 may be 10 nm or more and 1000 nm or less. The thickness of the third surface insulating film 55 may have a value belonging to at least one of the ranges of 10 nm or more and 50 nm or less, 50 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, 250 nm or more and 300 nm or less, 300 nm or more and 350 nm or less, 350 nm or more and 400 nm or less, 400 nm or more and 450 nm or less, 450 nm or more and 500 nm or less, 500 nm or more and 600 nm or less, 600 nm or more and 700 nm or less, 700 nm or more and 800 nm or less, 800 nm or more and 900 nm or more and 900 nm or more and 1000 nm or less.

[0233] The fourth surface insulating film 56 directly covers the third surface insulating film 55 around the first surface film portion 51. The fourth surface insulating film 56 covers the third surface insulating film 55 in a film-like manner in a region on the peripheral side of the first main surface 3 relative to the first surface film portion 51. The fourth surface insulating film 56 covers the outer well region 45, the outer contact region 46, and the plurality of field regions 47 with the third surface insulating film 55 sandwiched therebetween.

[0234] The fourth surface insulating film 56 may have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y. The fourth surface insulating film 56 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 15 (active regions 8) in a plan view. The fourth surface insulating film 56 is continuous with the first to fourth side surfaces 5A to 5D. The fourth surface insulating film 56 may be formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge portion of the first main surface 3 and the third surface insulating film 55.

[0235] The fourth surface insulating film 56 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The fourth surface insulating film 56 may include an insulator that is the same as or different from that of the first insulating film 22. The fourth surface insulating film 56 may include an insulator that is the same as or different from that of the second insulating film 23. The fourth surface insulating film 56 may include an insulator that is the same as or different from that of the third insulating film 24.

[0236] The fourth surface insulating film 56 may contain the same or a different insulator as the first surface insulating film 53. The fourth surface insulating film 56 may contain the same or a different insulator as the second surface insulating film 54. The fourth surface insulating film 56 may contain the same or a different insulator as the third surface insulating film 55.

[0237] In this embodiment, the fourth surface insulating film 56 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. In this embodiment, the fourth surface insulating film 56 is made of an NSG film.

[0238] In this embodiment, the fourth surface insulating film 56 is made of the same insulating film as the first surface insulating film 53, and is connected to the first surface insulating film 53. In other words, the fourth surface insulating film 56 is formed integrally with the second insulating film 23 and the first surface insulating film 53. The fourth surface insulating film 56 is formed as an extension portion of the first surface insulating film 53, and is extended from above the first main surface 3 onto the third surface insulating film 55.

[0239] The thickness of the fourth surface insulating film 56 may be greater or less than the first thickness of the first film portion 20. The thickness of the fourth surface insulating film 56 may be greater or less than the second thickness of the second film portion 21. The thickness of the fourth surface insulating film 56 may be greater or less than the thickness of the second insulating film 23. The thickness of the fourth surface insulating film 56 may be greater or less than the thickness of the third insulating film 24.

[0240] The thickness of the third surface insulating film 55 may be greater or less than the third thickness of the first surface film portion 51. The thickness of the fourth surface insulating film 56 may be greater or less than the thickness of the first surface insulating film 53. The thickness of the fourth surface insulating film 56 may be greater or less than the thickness of the second surface insulating film 54. The thickness of the fourth surface insulating film 56 may be greater or less than the thickness of the third surface insulating film 55. In this embodiment, the thickness of the fourth surface insulating film 56 is approximately equal to the thickness of the second insulating film 23 and the thickness of the first surface insulating film 53.

[0241] The thickness of the fourth surface insulating film 56 may be 10 nm or more and 250 nm or less. The thickness of the fourth surface insulating film 56 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0242] The fifth surface insulating film 57 directly covers the fourth surface insulating film 56 around the first surface film portion 51. The fifth surface insulating film 57 covers the fourth surface insulating film 56 in a film-like manner in a region on the peripheral side of the first main surface 3 relative to the first surface film portion 51. The fourth surface insulating film 56 covers the outer well region 45, the outer contact region 46, and the plurality of field regions 47 with the third surface insulating film 55 and the fourth surface insulating film 56 sandwiched therebetween.

[0243] The fifth surface insulating film 57 is continuous with the first to fourth side surfaces 5A to 5D. The fifth surface insulating film 57 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose at least one of the peripheral portion of the first main surface 3, the third surface insulating film 55, and the fourth surface insulating film 56.

[0244] The fifth surface insulating film 57 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The fifth surface insulating film 57 may include an insulator that is the same as or different from the first insulating film 22. The fifth surface insulating film 57 may include an insulator that is the same as or different from the second insulating film 23. The fifth surface insulating film 57 may include an insulator that is the same as or different from the third insulating film 24.

[0245] The fifth surface insulating film 57 may include an insulator that is the same as or different from the first surface insulating film 53. The fifth surface insulating film 57 may include an insulator that is the same as or different from the second surface insulating film 54. The fifth surface insulating film 57 may include an insulator that is the same as or different from the third surface insulating film 55. The fifth surface insulating film 57 may include an insulator that is the same as or different from the fourth surface insulating film 56.

[0246] In this embodiment, the fifth surface insulating film 57 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. In this embodiment, the fifth surface insulating film 57 is made of an NSG film.

[0247] In this embodiment, the fifth surface insulating film 57 is made of the same insulating film as the second surface insulating film 54, and is connected to the second surface insulating film 54. In other words, the fifth surface insulating film 57 is formed integrally with the third insulating film 24 and the second surface insulating film 54. The fifth surface insulating film 57 is formed as an extension portion of the second surface insulating film 54, and is extended from above the first main surface 3 onto the fourth surface insulating film 56.

[0248] The thickness of the fifth surface insulating film 57 may be greater or less than the first thickness of the first film portion 20. The thickness of the fifth surface insulating film 57 may be greater or less than the second thickness of the second film portion 21. The thickness of the fifth surface insulating film 57 may be greater or less than the thickness of the second insulating film 23. The thickness of the fifth surface insulating film 57 may be greater or less than the thickness of the third insulating film 24.

[0249] The thickness of the fifth surface insulating film 57 may be greater or less than the third thickness of the first surface film portion 51. The thickness of the fifth surface insulating film 57 may be greater or less than the thickness of the first surface insulating film 53. The thickness of the fifth surface insulating film 57 may be greater or less than the thickness of the second surface insulating film 54. The thickness of the fifth surface insulating film 57 may be greater or less than the thickness of the third surface insulating film 55. In this embodiment, the thickness of the fifth surface insulating film 57 is approximately equal to the thickness of the third insulating film 24 and the thickness of the second surface insulating film 54.

[0250] The thickness of the fifth surface insulating film 57 may be 10 nm or more and 250 nm or less. The thickness of the fifth surface insulating film 57 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0251] The fourth thickness of the second surface film portion 52 (i.e., the total thickness of the third surface insulating film 55, the fourth surface insulating film 56, and the fifth surface insulating film 57) is greater than the first thickness, the second thickness, and the third thickness. The thickness ratio of the fourth thickness to the third thickness may be greater than 1 and less than or equal to 20. The thickness ratio may have a value belonging to at least one of the following ranges: greater than 1 and less than or equal to 2.5, 2.5 to 5, 5 to 7.5, 7.5 to 10, 10 to 12.5, 12.5 to 15, 15 to 17.5, and 17.5 to 20.

[0252] The fourth thickness may be equal to or greater than 30 nm and equal to or less than 1500 nm. The fourth thickness may have a value belonging to at least one of the ranges of 30 nm to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, 450 nm to 500 nm, 500 nm to 600 nm, 600 nm to 700 nm, 700 nm to 800 nm, 800 nm to 900 nm, 900 nm to 1000 nm, 1000 nm to 1100 nm, 1100 nm to 1200 nm, 1200 nm to 1300 nm, 1300 nm to 1400 nm, and 1400 nm to 1500 nm.

[0253] 3 and 4 , the semiconductor device 1 includes one or more (one in this embodiment) gate wirings 60 arranged on the first main surface 3 in the peripheral region 9. The gate wiring 60 applies a gate potential to the multiple gate structures 15. The gate wiring 60 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 60 preferably has the same conductivity type as the buried electrode 18.

[0254] The gate wiring 60 is disposed on the surface insulating film 50. The gate wiring 60 is selectively routed on the surface insulating film 50 at intervals from the periphery of the first main surface 3 toward the plurality of gate structures 15, and faces the outer well region 45 with the surface insulating film 50 in between.

[0255] The gate wiring 60 extends in a strip shape along the periphery of the plurality of gate structures 15. The gate wiring 60 has a portion extending in a first direction X and a portion extending in a second direction Y. The gate wiring 60 extends in a strip shape so as to intersect (specifically, perpendicular to) the ends (both ends in this embodiment) of the plurality of gate structures 15.

[0256] In this embodiment, the gate wiring 60 is formed in an endless polygonal ring shape (e.g., a square ring shape) having four sides parallel to the periphery of the first main surface 3, and surrounds the plurality of gate structures 15 (active regions 8). Of course, the gate wiring 60 may be formed in a strip shape with ends. The gate wiring 60 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a planar view in an arc shape (preferably a quarter arc shape).

[0257] The gate wiring 60 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 60 is disposed on the first surface film portion 51 and faces the outer well region 45 across the first surface film portion 51. The inner edge portion of the gate wiring 60 covers the ends (both ends in this embodiment) of the multiple gate structures 15 and is mechanically and electrically connected to the multiple gate structures 15.

[0258] Specifically, the inner edge of the gate wiring 60 is mechanically and electrically connected to the plurality of buried electrodes 18. In this embodiment, the inner edge of the gate wiring 60 is integrally formed with the plurality of buried electrodes 18. In other words, the gate wiring 60 is formed as an extension portion of the plurality of buried electrodes 18, and is extended from the trench 16 onto the first surface film portion 51.

[0259] The inner edge of the gate wiring 60 has a portion located in a region between the plurality of gate structures 15, and faces either one or both of the body region 10 and the outer well region 45 across the first surface film portion 51 (surface insulating film 50). The inner edge of the gate wiring 60 is formed at a distance from the outermost source regions 40 and contact regions 42 on the peripheral side of the first main surface 3.

[0260] The outer edge of the gate wiring 60 is formed as an extraction portion that is extracted from above the first surface film portion 51 onto the second surface film portion 52, and is disposed on the second surface film portion 52. The outer edge of the gate wiring 60 faces the outer well region 45 with the second surface film portion 52 in between.

[0261] The outer edge of the gate wiring 60 is formed at a distance from the plurality of field regions 47 toward the plurality of gate structures 15. Specifically, the outer edge of the gate wiring 60 is formed at a distance from the outer edge of the outer well region 45 toward the plurality of gate structures 15. The outer edge of the gate wiring 60 is formed at a distance from the inner edge of the outer contact region 46 toward the plurality of gate structures 15.

[0262] The outer concealing area of ​​the gate wiring 60 relative to the second surface film portion 52 is larger than the inner concealing area of ​​the gate wiring 60 relative to the first surface film portion 51. The area ratio of the outer concealing area to the inner concealing area may be greater than 1 and less than or equal to 25.

[0263] The area ratio may have a value belonging to at least one of the ranges of greater than 1 and 2.5 or less, 2.5 or more and 5 or less, 5 or more and 7.5 or less, 7.5 or more and 10 or less, 10 or more and 12.5 or less, 12.5 or more and 15 or less, 15 or more and 17.5 or less, 17.5 or more and 20 or less, 20 or more and 22.5 or less, and 22.5 or more and 25 or less. The area ratio is preferably 5 or more. The area ratio is preferably 15 or less.

[0264] The semiconductor device 1 may include a plurality of gate wirings 60. In this case, the plurality of gate wirings 60 may be arranged at least at both ends of the plurality of gate structures 15. One of the gate wirings 60 may have a portion extending in a strip shape in the first direction X and intersect (specifically, perpendicular to) one end of the plurality of gate structures 15. The other of the gate wirings 60 may have a portion extending in a strip shape in the first direction X and intersect (specifically, perpendicular to) the other end of the plurality of gate structures 15. Of course, the plurality of gate wirings 60 may have a portion extending in the second direction Y.

[0265] The semiconductor device 1 includes a gate pad wiring 61 arranged on the first main surface 3 in the peripheral region 9. The gate pad wiring 61 is electrically connected to the gate wiring 60 and applies a gate potential to the gate wiring 60. The gate pad wiring 61 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0266] The gate pad wiring 61 preferably has the same conductivity type as the conductivity type of the buried electrodes 18 of the multiple gate structures 15. The gate pad wiring 61 contains the same conductive material as the conductive material of the gate wiring 60, and has a thickness approximately equal to the thickness of the gate wiring 60.

[0267] In this embodiment, the gate pad wiring 61 is arranged in a region closer to the third side surface 5C than the center of the first main surface 3. In this embodiment, the gate pad wiring 61 is arranged in a portion along the center of the third side surface 5C in the first direction X. The gate pad wiring 61 may also be arranged in a region along any corner of the first main surface 3. In this embodiment, the gate pad wiring 61 is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.

[0268] The gate pad wiring 61 is disposed on the surface insulating film 50. In this embodiment, the gate pad wiring 61 is disposed in a region of the peripheral region 9 defined by a plurality of gate structures 15 adjacent to each other in the second direction Y in a plan view. In other words, the gate pad wiring 61 faces a plurality of gate structures 15 on both sides in the second direction Y and faces a plurality of gate structures 15 in the first direction X.

[0269] The peripheral portion of the gate pad wiring 61 is connected to a portion of the gate wiring 60 extending in the second direction Y on the third side surface 5C side. In this embodiment, the gate pad wiring 61 is disposed on the second surface film portion 52 and faces the outer well region 45 across the second surface film portion 52. The gate pad wiring 61 may be disposed on the first surface film portion 51 and have a portion facing the outer well region 45 across the first surface film portion 51.

[0270] The gate pad wiring 61 is formed at an interval from the plurality of field regions 47 toward the plurality of gate structures 15. Specifically, the gate pad wiring 61 is formed at an interval from the outer edge of the outer well region 45 toward the plurality of gate structures 15. The gate pad wiring 61 is drawn out toward the periphery of the first main surface 3 beyond the outer edge of the outer well region 45, and may have a portion facing the second semiconductor layer 7 with the surface insulating film 50 interposed therebetween.

[0271] The peripheral portion of the gate pad wiring 61 covers the ends of the plurality of gate structures 15 adjacent to each other in the second direction Y and is mechanically and electrically connected to the plurality of gate structures 15. In this embodiment, the peripheral portion of the gate pad wiring 61 is integrally formed with the plurality of buried electrodes 18 as an extension portion of the plurality of buried electrodes 18. In other words, the gate pad wiring 61 is made up of extension portions that are extended from the plurality of buried electrodes 18 onto the first surface film portion 51.

[0272] In this embodiment, the peripheral portion of the gate pad wiring 61 is located in a region between the plurality of gate structures 15, and faces either or both of the body region 10 and the outer well region 45 across the first surface film portion 51. The peripheral portion of the gate pad wiring 61 is formed at a distance from the plurality of source regions 40 and the plurality of contact regions 42 that are arranged outermost.

[0273] The peripheral portion of the gate pad wiring 61 may have a portion facing one or more source regions 40. The peripheral portion of the gate pad wiring 61 may have a portion facing one or more contact regions 42. In this embodiment, the configuration in which the peripheral portion of the gate pad wiring 61 is connected to a plurality of gate structures 15 has been shown. However, the peripheral portion of the gate pad wiring 61 may be formed spaced apart from the plurality of gate structures 15.

[0274] The semiconductor device 1 includes an insulating interlayer film 65 that covers the surface insulating film 50. The interlayer film 65 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 65 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0275] The interlayer film 65 may contain an insulator that is the same as or different from the first surface insulating film 53. The interlayer film 65 may contain an insulator that is the same as or different from the second surface insulating film 54. The interlayer film 65 may contain an insulator that is the same as or different from the third surface insulating film 55. The interlayer film 65 may contain an insulator that is the same as or different from the fourth surface insulating film 56. The interlayer film 65 may contain an insulator that is the same as or different from the fifth surface insulating film 57.

[0276] The interlayer film 65 may have a single-layer structure made of a single silicon oxide film or a multi-layer structure including multiple silicon oxide films. The single or multiple silicon oxide films may include at least one of an NSG film, a PSG film, and a BPSG film. The interlayer film 65 preferably includes the same type of insulator as the buried insulator 19.

[0277] The interlayer film 65 coats the surface insulating film 50 in the peripheral region 9. Specifically, the interlayer film 65 directly coats the second surface film portion 52 in the form of a film, and faces the outer well region 45, the outer contact region 46, and the plurality of field regions 47 with the second surface film portion 52 in between.

[0278] The interlayer film 65 covers the gate wiring 60 and the gate pad wiring 61. The interlayer film 65 covers the entire gate wiring 60 and the entire gate pad wiring 61. The interlayer film 65 has a portion facing the first surface film portion 51 with the gate wiring 60 interposed therebetween, and a portion facing the second surface film portion 52 with the gate wiring 60 interposed therebetween. The interlayer film 65 has a portion facing the outer well region 45 with the gate wiring 60 interposed therebetween, and a portion facing the outer well region 45 with the gate pad wiring 61 interposed therebetween.

[0279] The interlayer film 65 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the interlayer film 65 is disposed in the active region 8. The inner edge portion of the interlayer film 65 is positioned on the inner side of the first main surface 3 with respect to the inner edge portion of the gate wiring 60 and the peripheral edge portion of the gate pad wiring 61, and covers the ends of the multiple gate structures 15.

[0280] The inner edge of the interlayer film 65 covers the buried electrodes 18 at the ends of the multiple gate structures 15 and is connected to the buried insulator 19. In this embodiment, the interlayer film 65 is formed integrally with the buried insulator 19. The portion of the interlayer film 65 located inside the trench 16 is formed as the buried insulator 19. The connection portion of the interlayer film 65 to the buried insulator 19 may be considered as part of the buried insulator 19 or may be considered as part of the interlayer film 65.

[0281] The inner edge portion of the interlayer film 65 has a portion located in a region between the plurality of gate structures 15. The inner edge portion of the interlayer film 65 covers either or both of the body region 10 and the outer well region 45 in the region between the plurality of gate structures 15, with the surface insulating film 50 (first surface film portion 51) sandwiched therebetween.

[0282] The outer edge of the interlayer film 65 is continuous with the first to fourth side surfaces 5A to 5D. The outer edge of the interlayer film 65 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge of the first main surface 3 and the surface insulating film 50. The outer edge of the interlayer film 65 may expose at least one of the peripheral edge of the first main surface 3, the third surface insulating film 55, the fourth surface insulating film 56, and the fifth surface insulating film 57.

[0283] The thickness of the interlayer film 65 may be greater or less than the first thickness of the first film portion 20. The thickness of the interlayer film 65 may be greater or less than the second thickness of the second film portion 21. The thickness of the interlayer film 65 may be greater or less than the thickness of the first insulating film 22. The thickness of the interlayer film 65 may be greater or less than the thickness of the second insulating film 23. The thickness of the interlayer film 65 may be greater or less than the thickness of the third insulating film 24.

[0284] The thickness of the interlayer film 65 may be greater or less than the third thickness of the first surface film portion 51. The thickness of the interlayer film 65 may be greater or less than the fourth thickness of the second surface film portion 52. The thickness of the interlayer film 65 may be greater or less than the thickness of the first surface insulating film 53. The thickness of the interlayer film 65 may be greater or less than the thickness of the second surface insulating film 54. The thickness of the interlayer film 65 may be greater or less than the thickness of the third surface insulating film 55. The thickness of the interlayer film 65 may be greater or less than the thickness of the fourth surface insulating film 56. The thickness of the interlayer film 65 may be greater or less than the thickness of the fifth surface insulating film 57.

[0285] In this embodiment, the thickness of the interlayer film 65 is greater than the first thickness, the second thickness, the third thickness, and the fourth thickness. The thickness of the interlayer film 65 may be 0.01 μm or more and 5 μm or less. The thickness of the interlayer film 65 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, or 4.5 μm or more and 5 μm or less.

[0286] The semiconductor device 1 includes one or more (one in this embodiment) source openings 68 formed in the interlayer film 65. The source opening 68 penetrates the interlayer film 65 in the inner portion of the active region 8, collectively exposing the plurality of gate structures 15 and the plurality of mesa portions 27. In this embodiment, the source opening 68 is formed in a polygonal shape having four sides parallel to the periphery of the first main surface 3 in a plan view (in this embodiment, a quadrilateral shape having a recessed portion recessed along the gate pad wiring 61).

[0287] The source openings 68 are formed inwardly of the first main surface 3 at intervals from the ends (both ends in this embodiment) of the plurality of gate structures 15, and expose the inner portions of the plurality of gate structures 15 and the inner portions of the plurality of mesa portions 27. Specifically, the source openings 68 expose the insulating film 17 and the buried insulator 19 in the inner portions of the plurality of gate structures 15. The source openings 68 expose at least the first film portion 20 of the insulating film 17. The source openings 68 may also expose a portion of the second film portion 21 of the insulating film 17.

[0288] The semiconductor device 1 includes the aforementioned source pad electrode 70 disposed on the first main surface 3. The source pad electrode 70 may also be referred to as a "first main surface electrode," a "first terminal (electrode)," a "first pad (electrode)," a "source electrode," or the like. The source pad electrode 70 is disposed on the interlayer film 65.

[0289] In this embodiment, the source pad electrode 70 has a first pad portion 70a, a second pad portion 70b, and a third pad portion 70c. The first pad portion 70a has a relatively large planar area and forms the main body of the source pad electrode 70. In this embodiment, the first pad portion 70a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first main surface 3.

[0290] The second pad portion 70b has a planar area smaller than that of the first pad portion 70a, and is drawn out in a strip (rectangular) shape from one end of the first pad portion 70a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 70c has a planar area smaller than that of the first pad portion 70a, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion 70a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 70b in the second direction Y.

[0291] The planar area of ​​the third pad portion 70c may be approximately equal to the planar area of ​​the second pad portion 70b. The planar area of ​​the third pad portion 70c may be larger or smaller than the planar area of ​​the second pad portion 70b. Either or both of the second pad portion 70b and the third pad portion 70c may be used as a terminal portion for monitoring a current.

[0292] The source pad electrode 70 does not necessarily have to have both the second pad portion 70b and the third pad portion 70c at the same time. The source pad electrode 70 may have only one of the second pad portion 70b and the third pad portion 70c. The source pad electrode 70 may be composed of only the first pad portion 70a, and may not have both the second pad portion 70b and the third pad portion 70c.

[0293] The source pad electrode 70 covers the entire region of the interlayer film 65 where the source opening 68 is formed, and extends into the source opening 68 from above the interlayer film 65. The source pad electrode 70 has a portion that covers the interlayer film 65 in a film-like manner, a portion that covers the wall surface of the source opening 68 in a film-like manner, and a portion that covers the first main surface 3 within the source opening 68 in a film-like manner.

[0294] The source pad electrode 70 has a portion covering the plurality of gate structures 15 in the source opening 68 and a portion covering the plurality of mesa portions 27. The source pad electrode 70 directly covers the plurality of buried insulators 19 in the portion covering the plurality of gate structures 15, and is electrically separated from the plurality of buried electrodes 18 by the plurality of buried insulators 19.

[0295] In this embodiment, the source pad electrode 70 extends into the trenches 16 from above the first main surface 3 and covers the embedded insulators 19 in the trenches 16. The source pad electrode 70 has a portion that covers the insulating surfaces of the embedded insulators 19 in a region on the bottom wall side of the trenches 16 relative to the height position of the first main surface 3.

[0296] The source pad electrode 70 has portions that cover the sidewalls and open ends of the trenches 16 within the trenches 16. The source pad electrode 70 is mechanically and electrically connected to the source regions 40 and the contact regions 42 in the portions that cover the sidewalls and open ends of the trenches 16. The source pad electrode 70 is mechanically and electrically connected to the source regions 40 and the contact regions 42 in the portions that cover the mesas 27.

[0297] The source pad electrode 70 has a peripheral portion that faces the ends (both ends) of the plurality of gate structures 15 across the interlayer film 65. The peripheral portion of the source pad electrode 70 is drawn out from the active region 8 to the peripheral region 9, and faces a part of the gate wiring 60 across the interlayer film 65.

[0298] The peripheral portion of the source pad electrode 70 has a portion facing the first surface film portion 51 with the gate wiring 60 and the interlayer film 65 sandwiched therebetween, and a portion facing the second surface film portion 52 with the gate wiring 60 and the interlayer film 65 sandwiched therebetween. The peripheral portion of the source pad electrode 70 has a portion facing the outer well region 45 with the gate wiring 60 and the first surface film portion 51 sandwiched therebetween in the stacking direction, and a portion facing the outer well region 45 with the gate wiring 60 and the second surface film portion 52 sandwiched therebetween.

[0299] The peripheral edge of the source pad electrode 70 is formed at a distance from the plurality of field regions 47 toward the plurality of gate structures 15. Specifically, the peripheral edge of the source pad electrode 70 is formed at a distance from the outer edge of the outer well region 45 toward the plurality of gate structures 15. The peripheral edge of the source pad electrode 70 is formed at a distance from the inner edge of the outer contact region 46 toward the plurality of gate structures 15.

[0300] The peripheral edge of the source pad electrode 70 is formed at a distance from the outer edge of the gate wiring 60 toward the inner edge of the gate wiring 60. The peripheral edge of the source pad electrode 70 may be formed at a distance from the middle of the gate wiring 60 toward the inner edge of the gate wiring 60.

[0301] The peripheral edge of the source pad electrode 70 may be disposed on the inner side of the first main surface 3 with respect to the second surface film portion 52, and may face the first surface film portion 51 in the stacking direction. The peripheral edge of the source pad electrode 70 may be formed at a distance from the gate wiring 60 on the inner side of the first main surface 3.

[0302] The peripheral edge of the source pad electrode 70 may face a part of the gate pad wiring 61 across the interlayer film 65. In this embodiment, the peripheral edge of the source pad electrode 70 faces the peripheral edge of the gate pad wiring 61 across the interlayer film 65, exposing the inner part of the gate pad wiring 61. Of course, the peripheral edge of the source pad electrode 70 may be formed with a gap between it and the gate pad wiring 61.

[0303] In this embodiment, the source pad electrode 70 has a laminated structure including a lower electrode film 71 and a main electrode film 72 laminated in this order from the chip 2 side. In this embodiment, the lower electrode film 71 has a laminated structure including a first electrode film 73 and a second electrode film 74.

[0304] In this embodiment, the first electrode film 73 includes a Ti film, and the second electrode film 74 includes a TiN film. The lower electrode film 71 does not necessarily have to have a laminated structure, and may have a single-layer structure consisting of either the first electrode film 73 (Ti film) or the second electrode film 74 (TiN film).

[0305] The first electrode film 73 has a thickness less than the thickness of the interlayer film 65. The thickness of the first electrode film 73 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 73 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0306] The second electrode film 74 has a thickness less than that of the interlayer film 65. The thickness of the second electrode film 74 is preferably greater than that of the first electrode film 73. The thickness of the second electrode film 74 may be 50 nm or greater and 200 nm or less. The thickness of the second electrode film 74 may have a value belonging to at least one of the ranges of 50 nm or greater and 75 nm or less, 75 nm or greater and 100 nm or less, 100 nm or greater and 125 nm or less, 125 nm or greater and 150 nm or less, 150 nm or greater and 175 nm or less, and 175 nm or greater and 200 nm or less.

[0307] The first electrode film 73 covers the entire region of the interlayer film 65 where the source opening 68 is formed, and extends into the source opening 68 from above the interlayer film 65. The first electrode film 73 has a portion that covers the insulating surface of the interlayer film 65 in a film-like manner, a portion that covers the wall surface of the source opening 68 in a film-like manner, and a portion that covers the first main surface 3 within the source opening 68 in a film-like manner.

[0308] The first electrode film 73 has a portion covering the plurality of gate structures 15 in the source opening 68 and a portion covering the plurality of mesa portions 27. The first electrode film 73 directly covers the plurality of buried insulators 19 in the portion covering the plurality of gate structures 15, and is electrically isolated from the plurality of buried electrodes 18 by the plurality of buried insulators 19.

[0309] In this embodiment, the first electrode film 73 enters the trenches 16 from above the first main surface 3 and covers the embedded insulators 19 in the trenches 16. In this embodiment, the first electrode film 73 has a portion that covers the insulating surfaces of the embedded insulators 19 in a region on the bottom wall side of the trenches 16 relative to the height position of the first main surface 3.

[0310] The first electrode film 73 has portions that cover the sidewalls and open ends of the trenches 16 within the trenches 16. The first electrode film 73 is mechanically and electrically connected to the source regions 40 and the contact regions 42 in the portions that cover the sidewalls and open ends of the trenches 16. The first electrode film 73 is mechanically and electrically connected to the source regions 40 and the contact regions 42 in the portions that cover the mesa portions 27.

[0311] The first electrode film 73 has a peripheral portion that faces the ends (both ends) of the multiple gate structures 15 across the interlayer film 65. In this embodiment, the peripheral portion of the first electrode film 73 is drawn from the active region 8 to the peripheral region 9, and faces a part of the gate wiring 60 across the interlayer film 65.

[0312] The peripheral portion of the first electrode film 73 has a portion facing the first surface film portion 51 with the gate wiring 60 and the interlayer film 65 sandwiched therebetween, and a portion facing the second surface film portion 52 with the gate wiring 60 and the interlayer film 65 sandwiched therebetween. The peripheral portion of the first electrode film 73 has a portion facing the outer well region 45 with the gate wiring 60 and the first surface film portion 51 sandwiched therebetween in the stacking direction, and a portion facing the outer well region 45 with the gate wiring 60 and the second surface film portion 52 sandwiched therebetween.

[0313] The peripheral portion of the first electrode film 73 is formed at a distance from the plurality of field regions 47 toward the plurality of gate structures 15. Specifically, the peripheral portion of the first electrode film 73 is formed at a distance from the outer edge of the outer well region 45 toward the plurality of gate structures 15. The peripheral portion of the first electrode film 73 is formed at a distance from the inner edge of the outer contact region 46 toward the plurality of gate structures 15.

[0314] The peripheral portion of the first electrode film 73 is formed at a distance from the outer edge of the gate wiring 60 toward the inner edge of the gate wiring 60. The peripheral portion of the first electrode film 73 may be formed at a distance from the middle of the gate wiring 60 toward the inner edge of the gate wiring 60.

[0315] The peripheral portion of the first electrode film 73 may face a part of the gate pad wiring 61 across the interlayer film 65. In this embodiment, the peripheral portion of the first electrode film 73 faces the peripheral portion of the gate pad wiring 61 across the interlayer film 65, exposing the inner portion of the gate pad wiring 61. Of course, the peripheral portion of the first electrode film 73 may be formed with a gap between it and the gate pad wiring 61.

[0316] The second electrode film 74 directly covers the first electrode film 73. The second electrode film 74 collectively covers the region of the interlayer film 65 where the source opening 68 is formed, sandwiching the first electrode film 73 therebetween, and extends from above the interlayer film 65 into the source opening 68.

[0317] The second electrode film 74 has a portion that covers the interlayer film 65 in a film state with the first electrode film 73 sandwiched therebetween, a portion that covers the wall surface of the source opening 68 in a film state with the first electrode film 73 sandwiched therebetween, and a portion that covers the first main surface 3 in a film state with the first electrode film 73 sandwiched therebetween within the source opening 68. The second electrode film 74 has a portion that covers the plurality of gate structures 15 in the source opening 68 with the first electrode film 73 sandwiched therebetween, and a portion that covers the plurality of mesa portions 27 with the first electrode film 73 sandwiched therebetween.

[0318] The second electrode film 74 covers the plurality of embedded insulators 19 with the first electrode film 73 interposed therebetween, and is electrically isolated from the plurality of embedded electrodes 18. In this embodiment, the second electrode film 74 enters the plurality of trenches 16 from above the first main surface 3, and covers the plurality of embedded insulators 19 in the plurality of trenches 16 with the first electrode film 73 interposed therebetween.

[0319] In this embodiment, the second electrode film 74 covers the first electrode film 73 in regions on the bottom wall side of the plurality of trenches 16 relative to the height position of the first main surface 3. In this embodiment, the second electrode film 74 has portions that cover the side walls and opening ends of the plurality of trenches 16 with the first electrode film 73 sandwiched therebetween.

[0320] The second electrode film 74 is electrically connected to the source regions 40 and the contact regions 42 via the first electrode film 73 in a portion covering the sidewalls and opening ends of the trenches 16. The second electrode film 74 may be connected to the first electrode film 73 above the first main surface 3. The second electrode film 74 is electrically connected to the source regions 40 and the contact regions 42 via the first electrode film 73 in a portion covering the mesas 27.

[0321] The second electrode film 74 has a peripheral portion that faces the ends (both ends) of the plurality of gate structures 15, sandwiching the interlayer film 65 and the first electrode film 73. The peripheral portion of the second electrode film 74 is drawn out from the active region 8 to the peripheral region 9, and faces a part of the gate wiring 60, sandwiching the interlayer film 65 and the first electrode film 73.

[0322] The peripheral portion of the second electrode film 74 has a portion facing the first surface film portion 51 with the gate wiring 60 and the interlayer film 65 sandwiched therebetween, and a portion facing the second surface film portion 52 with the gate wiring 60 and the interlayer film 65 sandwiched therebetween. The peripheral portion of the second electrode film 74 has a portion facing the outer well region 45 with the gate wiring 60 and the first surface film portion 51 sandwiched therebetween in the stacking direction, and a portion facing the outer well region 45 with the gate wiring 60 and the second surface film portion 52 sandwiched therebetween.

[0323] The peripheral portion of the second electrode film 74 is formed at a distance from the plurality of field regions 47 toward the plurality of gate structures 15. Specifically, the peripheral portion of the second electrode film 74 is formed at a distance from the outer edge of the outer well region 45 toward the plurality of gate structures 15. The peripheral portion of the second electrode film 74 is formed at a distance from the inner edge of the outer contact region 46 toward the plurality of gate structures 15.

[0324] The peripheral portion of the second electrode film 74 is formed at a distance from the outer edge of the gate wiring 60 toward the inner edge of the gate wiring 60. The peripheral portion of the second electrode film 74 may also be formed at a distance from the middle of the gate wiring 60 toward the inner edge of the gate wiring 60.

[0325] The peripheral portion of the second electrode film 74 may face a part of the gate pad wiring 61 across the interlayer film 65 and the first electrode film 73. In this embodiment, the peripheral portion of the second electrode film 74 faces the peripheral portion of the gate pad wiring 61 across the interlayer film 65 and the first electrode film 73, exposing the inner portion of the gate pad wiring 61. Of course, the peripheral portion of the second electrode film 74 may be formed with a gap between it and the gate pad wiring 61.

[0326] The main electrode film 72 contains a metal material different from the metal material of the lower electrode film 71 (first electrode film 73 and second electrode film 74). The main electrode film 72 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film (Cu alloy film) may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 72 has a thickness greater than the thickness (total thickness) of the lower electrode film 71. The thickness of the main electrode film 72 is preferably greater than the thickness of the interlayer film 65.

[0327] The thickness of the main electrode film 72 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 72 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0328] The main electrode film 72 directly covers the lower electrode film 71 (second electrode film 74). The main electrode film 72 backfills the source opening 68 and collectively covers the region of the interlayer film 65 where the source opening 68 is formed. The main electrode film 72 has a portion that covers the interlayer film 65 with the lower electrode film 71 in between, a portion that covers the wall surface of the source opening 68 with the lower electrode film 71 in between, and a portion that covers the first main surface 3 with the lower electrode film 71 in between.

[0329] The main electrode film 72 has a portion that covers the plurality of gate structures 15 with the lower electrode film 71 sandwiched therebetween in the source opening 68, and a portion that covers the plurality of mesa portions 27 with the lower electrode film 71 sandwiched therebetween. The main electrode film 72 covers the plurality of buried insulators 19 with the lower electrode film 71 sandwiched therebetween, and is electrically isolated from the plurality of buried electrodes 18.

[0330] The main electrode film 72 may extend into the plurality of trenches 16 from above the first main surface 3 and cover the plurality of embedded insulators 19 in the plurality of trenches 16 with the lower electrode film 71 sandwiched therebetween. In this case, the main electrode film 72 may have a portion that covers the sidewalls and opening ends of the plurality of trenches 16 with the lower electrode film 71 sandwiched therebetween in a region on the bottom wall side of the plurality of trenches 16 with respect to the height position of the first main surface 3. The main electrode film 72 may be connected to the lower electrode film 71 above the first main surface 3.

[0331] The main electrode film 72 is electrically connected to the source regions 40 and the contact regions 42 via the lower electrode film 71 in a portion covering the sidewalls and opening ends of the trenches 16. The main electrode film 72 is electrically connected to the source regions 40 and the contact regions 42 via the lower electrode film 71 in a portion covering the mesa portions 27.

[0332] The main electrode film 72 has a peripheral portion facing the ends (both ends) of the plurality of gate structures 15, with the interlayer film 65 and the lower electrode film 71 sandwiched therebetween. The peripheral portion of the main electrode film 72 may be drawn from the active region 8 to the peripheral region 9, and may face a part of the gate wiring 60, with the interlayer film 65 and the lower electrode film 71 sandwiched therebetween.

[0333] The peripheral portion of the main electrode film 72 has a portion facing the first surface film portion 51 with the gate wiring 60 and the interlayer film 65 sandwiched therebetween, and a portion facing the second surface film portion 52 with the gate wiring 60 and the interlayer film 65 sandwiched therebetween. The peripheral portion of the main electrode film 72 has a portion facing the outer well region 45 with the gate wiring 60 and the first surface film portion 51 sandwiched therebetween in the stacking direction, and a portion facing the outer well region 45 with the gate wiring 60 and the second surface film portion 52 sandwiched therebetween.

[0334] The peripheral portion of the main electrode film 72 is formed at an interval from the plurality of field regions 47 toward the plurality of gate structures 15. Specifically, the peripheral portion of the main electrode film 72 is formed at an interval from the outer edge of the outer well region 45 toward the plurality of gate structures 15. The peripheral portion of the main electrode film 72 is formed at an interval from the inner edge of the outer contact region 46 toward the plurality of gate structures 15.

[0335] The peripheral portion of the main electrode film 72 is formed at a distance from the outer edge of the gate wiring 60 toward the inner edge of the gate wiring 60. The peripheral portion of the main electrode film 72 may also be formed at a distance from the middle of the gate wiring 60 toward the inner edge of the gate wiring 60.

[0336] The peripheral edge of the main electrode film 72 may face a part of the gate pad wiring 61 across the interlayer film 65 and the lower electrode film 71. In this embodiment, the peripheral edge of the main electrode film 72 faces the peripheral edge of the gate pad wiring 61 across the interlayer film 65 and the lower electrode film 71, exposing the inner part of the gate pad wiring 61. Of course, the peripheral edge of the main electrode film 72 may be formed with a gap between it and the gate pad wiring 61.

[0337] The semiconductor device 1 includes one or more (multiple in this embodiment) gate openings 79 formed in the interlayer film 65. The multiple gate openings 79 penetrate the interlayer film 65 and selectively expose the gate wiring 60. In this embodiment, the multiple gate openings 79 extend in a strip shape following the extension direction of the gate wiring 60.

[0338] The plurality of gate openings 79 may be formed at intervals along the extension direction of the gate wiring 60. The plurality of gate openings 79 may be formed in a polygonal or circular shape in a plan view. For example, the plurality of gate structures 15 may be formed in a quadrangular or hexagonal shape in a plan view.

[0339] The plurality of gate openings 79 may have a portion extending in a band shape in the first direction X in a plan view and a portion extending in a band shape in the second direction Y. The plurality of gate openings 79 may have an edge portion connecting the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view.

[0340] The semiconductor device 1 includes a gate pad electrode 80 disposed on the first main surface 3 at a distance from the source pad electrode 70. The gate pad electrode 80 may also be referred to as a "second main surface electrode," a "second terminal (electrode)," a "second pad (electrode)," a "gate electrode," or the like. The gate pad electrode 80 is disposed on the interlayer film 65 at a distance from the source pad electrode 70.

[0341] In this embodiment, the gate pad electrode 80 is disposed on a portion of the interlayer film 65 that covers the gate pad wiring 61, and faces the gate pad wiring 61 across the interlayer film 65. In this embodiment, the gate pad electrode 80 does not have a direct electrical connection to the gate pad wiring 61. Of course, the gate pad electrode 80 may be mechanically and electrically connected to the gate pad wiring 61 via one or more gate openings 79.

[0342] The gate pad electrode 80 is disposed in a region on the third side surface 5C side of the first pad portion 70a, and faces the center of the third side surface 5C and the first pad portion 70a in the first direction X. The gate pad electrode 80 is interposed in a region between the second pad portion 70b and the third pad portion 70c, and faces both the second pad portion 70b and the third pad portion 70c in the second direction Y.

[0343] The gate pad electrode 80 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 80 has a planar area smaller than the planar area of ​​the source pad electrode 70. The gate pad electrode 80 has a planar area smaller than the planar area of ​​the first pad portion 70a. The gate pad electrode 80 may have a planar area smaller than the planar area of ​​the second pad portion 70b (third pad portion 70c).

[0344] The gate pad electrode 80 faces the outer well region 45 across the interlayer film 65 and the gate pad wiring 61. In this embodiment, the gate pad electrode 80 is formed at a distance from the ends (both ends) of the plurality of gate structures 15. In other words, the gate pad electrode 80 does not face the plurality of gate structures 15 in the stacking direction. Of course, the gate structure 15 may have a portion that faces a part (for example, an end) of the gate structure 15 across the interlayer film 65.

[0345] Although not shown in the drawings, the gate pad electrode 80 includes a lower electrode film 71 and a main electrode film 72 laminated in this order from the interlayer film 65 side, similar to the source pad electrode 70. In this embodiment, the lower electrode film 71 has a laminated structure including a first electrode film 73 and a second electrode film 74.

[0346] The semiconductor device 1 includes a gate finger electrode 81 extending from the gate pad electrode 80 onto the first main surface 3. The gate finger electrode 81 may also be referred to as a "gate wiring" or a "gate finger." The gate finger electrode 81 transmits the gate potential applied to the gate pad electrode 80 to other regions.

[0347] The gate finger electrode 81 is drawn out from the gate pad electrode 80 onto a portion of the interlayer film 65 that covers the gate wiring 60. The gate finger electrode 81 is routed in a strip shape around the periphery of the first main surface 3 and in the region between the source pad electrode 70. The gate finger electrode 81 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in plan view.

[0348] In this embodiment, the gate finger electrode 81 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 70. The gate finger electrode 81 is arranged closer to the periphery of the first main surface 3 than both ends of the multiple gate structures 15. The gate finger electrode 81 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0349] The gate finger electrode 81 penetrates into the plurality of gate openings 79 from above the interlayer film 65, and is mechanically and electrically connected to the gate wiring 60 within the plurality of gate openings 79. As a result, the gate potential applied to the gate pad electrode 80 is applied to the plurality of gate structures 15 via the gate finger electrode 81.

[0350] The gate finger electrode 81 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate finger electrode 81 is formed at a distance from the ends of the multiple gate structures 15 toward the peripheral side of the first main surface 3. In other words, the gate finger electrode 81 does not face the multiple gate structures 15 in the stacking direction.

[0351] In this embodiment, the peripheral edge of the gate finger electrode 81 is disposed at a distance from the first surface film portion 51 toward the peripheral edge of the first main surface 3, and faces the second surface film portion 52 in the stacking direction. In other words, the gate finger electrode 81 does not face the first surface film portion 51 in the stacking direction. The inner edge of the gate finger electrode 81 may be disposed on the inward side of the first main surface 3 with respect to the second surface film portion 52, and face the first surface film portion 51 in the stacking direction.

[0352] The inner edge of the gate finger electrode 81 is disposed on the gate wiring 60. The inner edge of the gate finger electrode 81 faces the peripheral edge of the source pad electrode 70 in the horizontal direction above the gate wiring 60. The inner edge of the gate finger electrode 81 is formed at a distance from the middle of the gate wiring 60 towards the peripheral edge of the first main surface 3.

[0353] The outer edge of the gate finger electrode 81 is drawn out from above the gate wiring 60 toward the peripheral edge of the first main surface 3, and is disposed on the interlayer film 65 in a region outside the gate wiring 60. In other words, the outer edge of the gate finger electrode 81 does not face the gate wiring 60 in the stacking direction. The outer edge of the gate finger electrode 81 is disposed at a distance from the innermost field region 47 toward the inside of the first main surface 3.

[0354] The outer edge of the gate finger electrode 81 is disposed at a distance from the outer edge of the outer well region 45 toward the inside of the first main surface 3, and faces the outer well region 45 across the surface insulating film 50 and the interlayer film 65. The outer edge of the gate finger electrode 81 is disposed on the peripheral side of the first main surface 3 relative to the outer edge of the outer well region 45, and may face the second semiconductor layer 7 in the stacking direction.

[0355] In this embodiment, the gate finger electrode 81 has a laminated structure including a lower electrode film 71 and a main electrode film 72 laminated in this order from the chip 2 side, similar to the source pad electrode 70. In this embodiment, the lower electrode film 71 has a laminated structure including a first electrode film 73 and a second electrode film 74.

[0356] The first electrode film 73 collectively covers the region of the interlayer film 65 where the multiple gate openings 79 are formed, and extends into the multiple gate openings 79 from above the interlayer film 65. The first electrode film 73 has a portion that covers the insulating surface of the interlayer film 65 in a film form, a portion that covers the wall surfaces of the multiple gate openings 79 in a film form, and a portion that covers the gate wiring 60 in the multiple gate openings 79 in a film form. The first electrode film 73 is mechanically and electrically connected to the gate wiring 60 in the multiple gate openings 79.

[0357] The second electrode film 74 directly covers the first electrode film 73. The second electrode film 74 collectively covers the region of the interlayer film 65 where the multiple gate openings 79 are formed, sandwiching the first electrode film 73 therebetween, and extends from above the interlayer film 65 into the multiple gate openings 79.

[0358] The second electrode film 74 has a portion that covers the interlayer film 65 in a film state with the first electrode film 73 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of gate openings 79 in a film state with the first electrode film 73 sandwiched therebetween, and a portion that covers the first main surface 3 in a film state with the first electrode film 73 sandwiched therebetween within the plurality of gate openings 79. The second electrode film 74 is electrically connected to the gate wiring 60 with the first electrode film 73 sandwiched therebetween within the plurality of gate openings 79.

[0359] The main electrode film 72 directly covers the lower electrode film 71 (second electrode film 74). The main electrode film 72 backfills the gate openings 79 and collectively covers the region of the interlayer film 65 where the gate openings 79 are formed.

[0360] The main electrode film 72 has a portion that covers the interlayer film 65 with the lower electrode film 71 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of gate openings 79 with the lower electrode film 71 sandwiched therebetween, and a portion that covers the first main surface 3 with the lower electrode film 71 sandwiched therebetween. The main electrode film 72 is electrically connected to the gate wiring 60 within the plurality of gate openings 79 with the lower electrode film 71 sandwiched therebetween.

[0361] The semiconductor device 1 includes a first slit portion 82 defined in a region between the source pad electrode 70 and the gate finger electrode 81. The first slit portion 82 exposes the interlayer film 65. The first slit portion 82 is defined in a region between ends of the plurality of gate structures 15 and the plurality of field regions 47.

[0362] The first slit portions 82 are formed at intervals from the ends of the plurality of gate structures 15 toward the peripheral edge of the first main surface 3. The first slit portions 82 are defined at intervals from the outer edge of the outer well region 45 toward the inward side of the first main surface 3. The first slit portions 82 are defined at intervals from the inner edge of the outer contact region 46 toward the ends of the plurality of gate structures 15.

[0363] The first slit portions 82 overlap the first main surface 3 in the stacking direction. The first slit portions 82 are defined at intervals from the ends (both ends in this embodiment) of the plurality of gate structures 15 toward the peripheral edge of the first main surface 3, and do not overlap the plurality of gate structures 15 in the stacking direction. The first slit portions 82 overlap the gate wiring 60 in the stacking direction, with the interlayer film 65 sandwiched therebetween.

[0364] The first slit portion 82 overlaps the second surface film portion 52 in the stacking direction, sandwiching the gate wiring 60 and the interlayer film 65. The first slit portion 82 is defined at an interval from the first surface film portion 51 on the peripheral edge side of the first main surface 3, and does not overlap the first surface film portion 51 in the stacking direction. The first slit portion 82 exposes a flat portion of the interlayer film 65 that extends along the horizontal direction.

[0365] 14 , the semiconductor device 1 includes at least one outer opening 83 (one in this embodiment) formed in the interlayer film 65 in the peripheral region 9. The outer opening 83 is formed at a distance from the gate wiring 60 toward the peripheral edge of the first main surface 3. The outer opening 83 penetrates the surface insulating film 50 and the interlayer film 65 to expose the outer contact region 46.

[0366] The outer opening 83 has a width less than the width of the outer contact region 46 and is spaced apart from the inner and outer edges of the outer contact region 46 to expose an inner portion of the outer contact region 46. The outer opening 83 may expose the outer well region 45.

[0367] In this embodiment, the outer opening 83 extends in a strip shape following the extension direction of the outer contact region 46. In this embodiment, the outer opening 83 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the multiple gate structures 15 (active regions 8). The outer contact region 46 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0368] The semiconductor device 1 may have a plurality of outer openings 83. In this case, the plurality of outer openings 83 may be formed at intervals following the extension direction of the outer contact region 46. Furthermore, the plurality of outer openings 83 may each extend in a strip shape following the extension direction of the outer contact region 46.

[0369] The semiconductor device 1 includes source finger electrodes 85 extending from the source pad electrode 70 onto the first main surface 3. The source finger electrodes 85 may also be referred to as "source wiring," "source fingers," etc. The source finger electrodes 85 transmit the gate potential applied to the source pad electrode 70 to other regions.

[0370] The source finger electrodes 85 are arranged at intervals from the gate pad electrode 80 and the gate finger electrodes 81. The source finger electrodes 85 are arranged in regions on the peripheral side of the first main surface 3 relative to both ends of the plurality of gate structures 15. The source finger electrodes 85 are formed at intervals from the first surface film portion 51 on the peripheral side of the first main surface 3, and face the second surface film portion 52 in the stacking direction.

[0371] The source finger electrodes 85 are drawn out from the source pad electrode 70 onto a portion of the interlayer film 65 that covers the outer contact region 46. The source finger electrodes 85 are routed in a strip shape around the periphery of the first main surface 3 and in a region between the source pad electrodes 70. The source finger electrodes 85 have a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in plan view.

[0372] In this embodiment, the source finger electrode 85 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 70 and the gate finger electrode 81. The outer well region 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0373] The source finger electrodes 85 extend into the plurality of outer openings 83 from above the interlayer film 65, and are mechanically and electrically connected to the outer contact regions 46 within the plurality of outer openings 83. As a result, the gate potential applied to the source pad electrode 70 is applied to the plurality of gate structures 15 via the source finger electrodes 85.

[0374] The source finger electrodes 85 have inner edges on the inward side of the first main surface 3 and outer edges on the peripheral side of the first main surface 3. The inner edges of the source finger electrodes 85 are spaced apart from the gate finger electrodes 81 on the peripheral side of the first main surface 3, and face the gate finger electrodes 81 in the horizontal direction.

[0375] The inner edge of the source finger electrode 85 is formed at a distance from the middle of the outer contact region 46 toward the periphery of the first main surface 3. The inner edge of the source finger electrode 85 may be disposed on the outer well region 45 or on the outer contact region 46.

[0376] The outer edge of the source finger electrode 85 is drawn out from above the outer contact region 46 toward the peripheral edge of the first main surface 3, and is disposed on the interlayer film 65 in a region outside the outer contact region 46. The outer edge of the source finger electrode 85 is disposed at a distance from the innermost field region 47 toward the inside of the first main surface 3.

[0377] The outer edge of the source finger electrode 85 is disposed at a distance from the outer edge of the outer well region 45 toward the inside of the first main surface 3, and faces the outer well region 45 across the second surface film portion 52 and the interlayer film 65. The outer edge of the source finger electrode 85 may be drawn out from the outer edge of the outer well region 45 toward the periphery of the first main surface 3, and faces the second semiconductor layer 7 across the second surface film portion 52 and the interlayer film 65.

[0378] In this embodiment, the source finger electrode 85 has a laminated structure including a lower electrode film 71 and a main electrode film 72 laminated in this order from the chip 2 side, similar to the source pad electrode 70. In this embodiment, the lower electrode film 71 has a laminated structure including a first electrode film 73 and a second electrode film 74.

[0379] The first electrode film 73 covers the entire region of the interlayer film 65 where the outer opening 83 is formed, and extends into the outer opening 83 from above the interlayer film 65. The first electrode film 73 has a portion that covers the insulating surface of the interlayer film 65 in a film-like manner, a portion that covers the wall surface of the outer opening 83 in a film-like manner, and a portion that covers the first main surface 3 within the outer opening 83 in a film-like manner. The first electrode film 73 is mechanically and electrically connected to the outer contact region 46 within the outer opening 83.

[0380] The second electrode film 74 directly covers the first electrode film 73. The second electrode film 74 collectively covers the region of the interlayer film 65 where the outer opening 83 is formed, sandwiching the first electrode film 73 therebetween, and extends from above the interlayer film 65 into the outer opening 83.

[0381] The second electrode film 74 has a portion that covers the interlayer film 65 in a film-like manner with the first electrode film 73 sandwiched therebetween, a portion that covers the wall surface of the outer opening 83 in a film-like manner with the first electrode film 73 sandwiched therebetween, and a portion that covers the first main surface 3 in a film-like manner with the first electrode film 73 sandwiched therebetween within the outer opening 83. The second electrode film 74 is electrically connected to the outer contact region 46 within the outer opening 83 with the first electrode film 73 sandwiched therebetween.

[0382] The main electrode film 72 directly covers the lower electrode film 71 (second electrode film 74). The main electrode film 72 backfills the outer opening 83 and collectively covers the region of the interlayer film 65 where the outer opening 83 is formed.

[0383] The main electrode film 72 has a portion that covers the interlayer film 65 with the lower electrode film 71 in between, a portion that covers the wall surface of the outer opening 83 with the lower electrode film 71 in between, and a portion that covers the first main surface 3 with the lower electrode film 71 in between. The main electrode film 72 is electrically connected to the outer contact region 46 within the outer opening 83 with the lower electrode film 71 in between.

[0384] The semiconductor device 1 includes a second slit portion 86 defined in a region between the gate finger electrode 81 and the source finger electrode 85. The second slit portion 86 is defined in a region between the outer edge of the gate wiring 60 and the outer edge of the outer well region 45, and overlaps the first main surface 3 in the stacking direction.

[0385] The second slit portion 86 is defined at a distance from the first surface film portion 51 toward the peripheral edge of the first main surface 3, and overlaps the second surface film portion 52 with the interlayer film 65 sandwiched therebetween in the stacking direction. The second slit portion 86 exposes a flat portion of the interlayer film 65 that extends along the horizontal direction.

[0386] The semiconductor device 1 includes a drain pad electrode 87 covering the second main surface 4. The drain pad electrode 87 may also be referred to as a "third main surface electrode," a "third terminal (electrode)," a "third pad (electrode)," a "drain electrode," or the like. The drain pad electrode 87 is mechanically and electrically connected to the first semiconductor layer 6. The drain pad electrode 87 forms ohmic contact with the first semiconductor layer 6.

[0387] The drain pad electrode 87 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 87 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0388] A breakdown voltage that can be applied between source pad electrode 70 and drain pad electrode 87 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0389] As described above, the semiconductor device 1 may include the chip 2 and the trench electrode type gate structure 15. The chip 2 has a first main surface 3. The gate structure 15 is formed on the first main surface 3. The gate structure 15 includes a trench 16, an insulating film 17, and a buried electrode 18.

[0390] The trench 16 is formed on the first main surface 3. An insulating film 17 covers the wall surface of the trench 16. The insulating film 17 has a first film portion 20 that covers the wall surface of the inner part of the trench 16, and a second film portion 21 that covers the wall surface of the end of the trench 16. The second film portion 21 has a thickness greater than that of the first film portion 20. The buried electrode 18 is buried in the trench 16 with the insulating film 17 sandwiched therebetween.

[0391] This configuration provides the semiconductor device 1 having a novel layout. For example, in the semiconductor device 1, a portion of the insulating film 17 is thickened at the end of the trench 16. This improves the dielectric strength against an electric field near the end of the gate structure 15.

[0392] The chip 2 may include SiC. This configuration provides the semiconductor device 1 as a SiC semiconductor device having a novel layout. The semiconductor device 1 further improves the breakdown voltage due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the effect of improving the dielectric strength achieved by thickening part of the insulating film 17 at the end of the gate structure 15 is effective.

[0393] The first film portion 20 may cover the sidewalls and bottom wall of the trench 16. The second film portion 21 may cover the sidewalls and bottom wall of the trench 16. This configuration improves the dielectric strength of the sidewalls and bottom wall at the end of the trench 16. The coverage area of ​​the second film portion 21 with respect to the trench 16 may be smaller than the coverage area of ​​the first film portion 20 with respect to the trench 16. This configuration locally improves the dielectric strength of the end of the gate structure 15.

[0394] The buried electrode 18 may be buried in the trench 16 at a distance from the first main surface 3 toward the bottom wall of the trench 16. In this case, the gate structure 15 may include a buried insulator 19 buried above the buried electrode 18 in the trench 16. According to this configuration, the dielectric strength on the opening end side of the trench 16 is improved by the buried insulator 19.

[0395] The buried insulator 19 may be buried in the trench 16 at a distance from the first main surface 3 toward the bottom wall of the trench 16. With this configuration, the area of ​​the first main surface 3 that is hidden by the insulating structure for the gate structure 15 is reduced, and therefore, electrical contact points with the first main surface 3 can be appropriately secured.

[0396] The semiconductor device 1 may include a surface insulating film 50. The surface insulating film 50 may cover the first main surface 3 around the end of the gate structure 15 and be connected to the insulating film 17. According to this configuration, the surface insulating film 50 improves the dielectric strength around the end of the gate structure 15.

[0397] The surface insulating film 50 may include a first surface film portion 51 and a second surface film portion 52. The first surface film portion 51 covers the periphery of the end portion of the gate structure 15 and may have a thickness greater than the thickness of the first film portion 20 of the insulating film 17.

[0398] According to this configuration, the dielectric strength around the end of the gate structure 15 is improved by the first surface film portion 51, which is thicker than the first film portion 20. The second surface film portion 52 covers the periphery of the first surface film portion 51 and may have a thickness greater than the thickness of the second film portion 21 of the insulating film 17. According to this configuration, the dielectric strength around the periphery of the first surface film portion 51 is improved by the second surface film portion 52, which is thicker than the second film portion 21.

[0399] The semiconductor device 1 may include an n-type second semiconductor layer 7 (semiconductor layer), a gate structure 15, and a p-type outer well region 45. The second semiconductor layer 7 may be formed in a surface layer portion of the first main surface 3. The gate structure 15 may be formed on the first main surface 3 so as to be located within the second semiconductor layer 7. The outer well region 45 may be formed in a surface layer portion of the second semiconductor layer 7 around an end portion of the gate structure 15.

[0400] With this configuration, a depletion layer spreads around the end of the gate structure 15, starting from the outer well region 45. This reduces the electric field with respect to the end of the gate structure 15, thereby improving the dielectric strength. In this case, the surface insulating film 50 may cover the outer well region 45. With this configuration, the electric field with respect to the surface insulating film 50 is reduced, thereby improving the dielectric strength.

[0401] The semiconductor device 1 may include an n-type second semiconductor layer 7 (semiconductor layer), a gate structure 15, and a p-type outer well region 45. The second semiconductor layer 7 may be formed in a surface layer portion of the first main surface 3. The gate structure 15 may be formed on the first main surface 3 so as to be located within the second semiconductor layer 7. The outer well region 45 may be formed in a surface layer portion of the second semiconductor layer 7 around an end portion of the gate structure 15.

[0402] With this configuration, a depletion layer spreads around the end of the gate structure 15, starting from the outer well region 45. This reduces the electric field at the end of the gate structure 15, thereby improving the dielectric strength. The outer well region 45 may face the buried electrode 18 with the second film portion 21 interposed therebetween. With this configuration, the electric field at the second film portion 21 is reduced, thereby improving the dielectric strength.

[0403] The semiconductor device 1 may include an n-type second semiconductor layer 7 (semiconductor layer), a gate structure 15, and a p-type well region 30. The second semiconductor layer 7 may be formed in a surface layer portion of the first main surface 3. The gate structure 15 may be formed on the first main surface 3 so as to be located within the second semiconductor layer 7. The well region 30 may be formed below the gate structure 15 within the second semiconductor layer 7.

[0404] With this configuration, a depletion layer spreads starting from the well region 30. This reduces the electric field applied to the gate structure 15, improving the dielectric strength. The well region 30 may have a portion that extends along the second film portion 21 of the insulating film 17. With this configuration, the electric field applied to the bottom wall of the gate structure 15 is reduced, improving the dielectric strength.

[0405] The semiconductor device 1 includes a p-type body region 10, a gate structure 15, and a p-type contact region 42. The body region 10 is formed in a surface layer portion of the first main surface 3. The gate structure 15 is formed on the first main surface 3 so as to penetrate the body region 10. The contact region 42 extends along the sidewall of the gate structure 15 and electrically connects the well region 30 to the body region 10. With this configuration, the electrical response characteristics of the well region 30 can be appropriately improved.

[0406] The semiconductor device 1 may include a p-type outer well region 45. The outer well region 45 may be formed in a surface layer portion of the second semiconductor layer 7 around the end of the gate structure 15. With this configuration, a depletion layer spreads around the end of the gate structure 15, starting from the outer well region 45. This reduces the electric field at the end of the gate structure 15, thereby improving the dielectric strength.

[0407] The semiconductor device 1 may include a gate wiring 60. The gate wiring 60 may be disposed on the first main surface 3 and electrically connected to the buried electrode 18 at an end of the gate structure 15. This configuration improves the dielectric strength caused by the electric field at the end of the gate structure 15 to which the gate wiring 60 is connected.

[0408] The semiconductor device 1 may include an insulating interlayer film 65, a source pad electrode 70, and a gate finger electrode 81. The interlayer film 65 may cover the gate structure 15 and the gate wiring 60. The source pad electrode 70 may be disposed on a portion of the interlayer film 65 that covers the gate structure 15. The gate finger electrode 81 may be disposed on a portion of the interlayer film 65 that covers the gate wiring 60.

[0409] The semiconductor device 1 may include a first slit portion 82. The first slit portion 82 may be defined in a region between the source pad electrode 70 and the gate finger electrode 81, and may overlap the first main surface 3 in the stacking direction. According to this configuration, the first slit portion 82 is formed in a relatively flat portion of the interlayer film 65. As a result, the source pad electrode 70 and the gate finger electrode 81 are appropriately separated by the first slit portion 82.

[0410] From another perspective, the semiconductor device 1 includes a chip 2, a trench electrode type gate structure 15, and a surface insulating film 50. The chip 2 has a first main surface 3. The gate structure 15 is formed on the first main surface 3.

[0411] The surface insulating film 50 includes a first surface film portion 51 and a second surface film portion 52. The first surface film portion 51 covers the periphery of the gate structure 15 on the first main surface 3. The second surface film portion 52 covers the periphery of the first surface film portion 51 on the first main surface 3 and has a thickness greater than that of the first surface film portion 51.

[0412] This configuration provides a semiconductor device 1 having a novel layout. For example, in this semiconductor device 1, the dielectric strength around the end of the gate structure 15 is improved by the first surface film portion 51, and the dielectric strength around the first surface film portion 51 is improved by the second surface film portion 52, which is thicker than the first surface film portion 51. This improves the dielectric strength.

[0413] The chip 2 may include SiC. This configuration provides the semiconductor device 1 as a SiC semiconductor device having a novel layout. The semiconductor device 1 further improves the breakdown voltage due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the effect of improving the dielectric strength provided by the second surface film portion 52 is effective.

[0414] The second surface film portion 52 may have a width greater than the width of the first surface film portion 51. With this configuration, the dielectric strength provided by the second surface film portion 52 is appropriately improved.

[0415] The semiconductor device 1 may include a gate wiring 60. The gate wiring 60 may be disposed on the first surface film portion 51 and electrically connected to an end of the gate structure 15. According to this configuration, the first surface film portion 51 improves the dielectric strength between the chip 2 and the gate wiring 60.

[0416] The gate wiring 60 may be disposed on the second surface film portion 52 and may have a portion facing the first main surface 3 across the second surface film portion 52. According to this configuration, the second surface film portion 52 improves the dielectric strength between the chip 2 and the gate wiring 60.

[0417] The area covered by the gate wiring 60 on the second surface film portion 52 is larger than the area covered by the gate wiring 60 on the first surface film portion 51. According to this configuration, the second surface film portion 52 appropriately improves the dielectric strength between the chip 2 and the gate wiring 60.

[0418] The semiconductor device 1 may include an insulating interlayer film 65 and a gate finger electrode 81. The interlayer film 65 may cover the gate structure 15 and the gate wiring 60. The gate finger electrode 81 may be disposed on a portion of the interlayer film 65 that covers the gate wiring 60.

[0419] The gate finger electrodes 81 may be formed at intervals from the gate structure 15 toward the periphery of the chip 2. The portion of the interlayer film 65 that covers the gate wiring 60 can be formed relatively flat because it is possible to avoid design rule restrictions resulting from the gate structure 15. This improves the film formation properties of the gate finger electrodes 81 on the interlayer film 65.

[0420] In this case, the gate finger electrodes 81 do not have to face the gate structure 15 in the stacking direction. This configuration appropriately improves the film formability of the gate finger electrodes 81. The gate finger electrodes 81 may face the surface insulating film 50 with the gate wiring 60 and the interlayer film 65 sandwiched therebetween. This configuration improves the dielectric strength between the chip 2 and the gate finger electrodes 81 by the surface insulating film 50.

[0421] The gate finger electrodes 81 may face the second surface film portion 52. With this configuration, the dielectric strength between the chip 2 and the gate finger electrodes 81 is improved by the second surface film portion 52. The gate finger electrodes 81 may be formed at a distance from the first surface film portion 51 toward the peripheral edge of the first main surface 3. With this configuration, the dielectric strength between the chip 2 and the gate finger electrodes 81 is appropriately improved by the second surface film portion 52.

[0422] The semiconductor device 1 may include a source pad electrode 70. The source pad electrode 70 may be disposed on a portion of the interlayer film 65 that covers the gate structure 15. In this case, the semiconductor device 1 may include a first slit portion 82. The first slit portion 82 may be defined in a region between the source pad electrode 70 and the gate finger electrode 81, and may overlap the first main surface 3 in the stacking direction.

[0423] According to this configuration, the first slit portion 82 is formed in a relatively flat portion of the interlayer film 65. As a result, the source pad electrode 70 and the gate finger electrode 81 are appropriately separated by the first slit portion 82.

[0424] The semiconductor device 1 may include an n-type second semiconductor layer 7 (semiconductor device 1), a gate structure 15, and a p-type outer well region 45. The second semiconductor layer 7 is formed in a surface layer portion of the first main surface 3. The gate structure 15 is formed on the first main surface 3 so as to be located within the second semiconductor layer 7. The outer well region 45 may be formed in a surface layer portion of the second semiconductor layer 7 around an end portion of the gate structure 15.

[0425] With this configuration, a depletion layer spreads around the end of the gate structure 15, starting from the outer well region 45. This reduces the electric field with respect to the end of the gate structure 15, thereby improving the dielectric strength. In this case, the surface insulating film 50 may cover the outer well region 45. With this configuration, the electric field with respect to the surface insulating film 50 is reduced, thereby improving the dielectric strength.

[0426] The first surface film portion 51 may cover the outer well region 45. With this configuration, the electric field applied to the first surface film portion 51 is alleviated, thereby improving the dielectric strength. The second surface film portion 52 may cover the outer well region 45. With this configuration, the electric field applied to the second surface film portion 52 is alleviated, thereby improving the dielectric strength.

[0427] The semiconductor device 1 may include a p-type well region 30. The well region 30 may be formed in the second semiconductor layer 7 below the gate structure 15. With this configuration, a depletion layer spreads from the well region 30. This reduces the electric field with respect to the gate structure 15, thereby improving the dielectric strength. The well region 30 may have a portion that is aligned with the second film portion 21 of the insulating film 17.

[0428] The semiconductor device 1 may include a p-type body region 10, a gate structure 15, and a p-type contact region 42. The body region 10 may be formed in a surface layer portion of the first main surface 3. The gate structure 15 may be formed on the first main surface 3 so as to penetrate the body region 10. The contact region 42 may extend along a sidewall of the gate structure 15 and electrically connect the well region 30 to the body region 10. With this configuration, the electrical response characteristics of the well region 30 can be appropriately improved.

[0429] The semiconductor device 1 includes a chip 2, a trench electrode type gate structure 15, gate wiring 60, an insulating interlayer film 65, a source pad electrode 70, a gate finger electrode 81, and a first slit portion 82. The chip 2 has a first main surface 3. The gate structure 15 is formed on the first main surface 3. The gate wiring 60 is disposed on the first main surface 3 and is electrically connected to an end of the gate structure 15. The interlayer film 65 covers the gate structure 15 and the gate wiring 60.

[0430] The source pad electrode 70 is disposed on the interlayer film 65 and faces the gate structure 15 and the gate wiring 60 with the interlayer film 65 sandwiched therebetween. The gate finger electrode 81 is disposed on the interlayer film 65 at a distance from the pad electrode and faces the gate wiring 60 with the interlayer film 65 sandwiched therebetween. The first slit portion 82 is defined in a region between the source pad electrode 70 and the gate finger electrode 81 and overlaps the first main surface 3 in the stacking direction.

[0431] This configuration provides a semiconductor device 1 having a novel layout. For example, with this semiconductor device 1, the portion of the interlayer film 65 that covers the gate wiring 60 can be formed relatively flat because it is possible to avoid design rule limitations resulting from the gate structure 15. Therefore, the first slit portion 82 can be formed in the relatively flat portion of the interlayer film 65. As a result, the source pad electrode 70 and the gate finger electrode 81 are appropriately electrically isolated by the first slit portion 82 on the interlayer film 65.

[0432] Chip 2 may include SiC. This configuration provides semiconductor device 1 as a SiC semiconductor device having a novel layout. This semiconductor device 1 further improves the breakdown voltage due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high-voltage environments, a configuration in which source pad electrode 70 and gate finger electrode 81, to which different potentials are applied, are appropriately electrically isolated by first slit portion 82 is effective.

[0433] The first slit portion 82 does not have to overlap the gate structure 15 in the stacking direction. With this configuration, a flat portion of the interlayer film 65 is appropriately exposed from the first slit portion 82. This allows the source pad electrode 70 and the gate finger electrode 81 to be appropriately electrically isolated from each other.

[0434] Modifications applied to the semiconductor device 1 will be described below. Figures 15 to 20 are cross-sectional perspective views showing first to sixth modifications of the semiconductor device 1. Figure 15 is a cross-sectional perspective view showing a first modification of the semiconductor device 1. Figures 16 to 20 are cross-sectional views showing second to sixth modifications of the semiconductor device 1.

[0435] The semiconductor device 1 can include any one of the features of the first to sixth modifications. The first to sixth modifications can be combined as appropriate. Therefore, the semiconductor device 1 can include at least two of the features of the first to sixth modifications simultaneously in the same cross-sectional area or different cross-sectional areas.

[0436] 15 (first modification), semiconductor device 1 may include insulating film 17 having an upper end formed at a distance from the height position of first main surface 3 toward the bottom wall of trench 16. The upper end of insulating film 17 may expose chip 2 from the side wall and opening end of trench 16.

[0437] The electrode surface of the buried electrode 18 may protrude toward the first main surface 3 beyond the upper end of the insulating film 17. The electrode surface of the buried electrode 18 may be located closer to the bottom wall of the trench 16 than the upper end of the insulating film 17. The buried insulator 19 may be buried within the trench 16 above the upper end of the insulating film 17 and the electrode surface of the buried electrode 18.

[0438] The buried insulator 19 may cover the upper end of the insulating film 17 and the electrode surface of the buried electrode 18. The buried insulator 19 may have a portion that directly covers the sidewall of the trench 16. The body region 10, the source region 40, and the contact region 42 may each have a portion that is in direct contact with the buried insulator 19 in a portion along the gate structure 15.

[0439] 16 (second modified example), the semiconductor device 1 does not necessarily have to have the second surface film portion 52. In this case, the surface insulating film 50 may be configured with a laminated structure including a first surface insulating film 53 and a second surface insulating film 54.

[0440] The first surface insulating film 53 directly covers the first main surface 3 around the ends of the plurality of gate structures 15. The first surface insulating film 53 is connected to the second insulating film 23 at the ends of the plurality of gate structures 15, exposing the buried electrodes 18 and the buried insulators 19. The first surface insulating film 53 has portions located in regions between the plurality of gate structures 15. The first surface insulating film 53 is connected to the second insulating film 23 at both the portions of the ends of the plurality of gate structures 15 that extend in the first direction X and the portions that extend in the second direction Y.

[0441] The first surface insulating film 53 is formed in a region between the periphery of the first main surface 3 and the end of the gate structure 15, and directly covers the outer well region 45 and the plurality of field regions 47 in a film form. The first surface insulating film 53 is continuous with the first to fourth side surfaces 5A to 5D. The first surface insulating film 53 may be formed at a distance inward from the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3.

[0442] The second surface insulating film 54 directly covers the first surface insulating film 53 around the ends of the plurality of gate structures 15. The second surface insulating film 54 is connected to the third insulating film 24 of the insulating film 17 at the ends of the plurality of gate structures 15, exposing the buried electrode 18 and the buried insulator 19.

[0443] The second surface insulating film 54 has a portion located in a region between the plurality of gate structures 15. The second surface insulating film 54 is connected to the third insulating film 24 at both the portion extending in the first direction X and the portion extending in the second direction Y of the ends of the plurality of gate structures 15.

[0444] The second surface insulating film 54 is formed in the region between the periphery of the first main surface 3 and the end of the gate structure 15, and covers the outer well region 45 and the plurality of field regions 47 with the first surface insulating film 53 sandwiched therebetween.

[0445] The second surface insulating film 54 covers the outer well region 45 and the plurality of field regions 47 with the first surface film portion 51 in between. The second surface insulating film 54 is continuous with the first to fourth side surfaces 5A to 5D. The second surface insulating film 54 is formed at an interval inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral portion of the first main surface 3 and the first surface insulating film 53.

[0446] 17 (Third Modification), the semiconductor device 1 has a layout obtained by modifying the configuration of the insulating film 17 in the second modification. Specifically, the insulating film 17 has a layered structure including a second insulating film 23 and a third insulating film 24, and does not have the first insulating film 22.

[0447] In this embodiment, the second insulating film 23 covers the sidewalls and bottom wall of the trench 16 in the inner portion and at the end of the gate structure 15. In this embodiment, the third insulating film 24 covers the sidewalls and bottom wall of the trench 16 in the inner portion and at the end of the gate structure 15, with the second insulating film 23 sandwiched therebetween.

[0448] 18 (fourth modified example), semiconductor device 1 does not necessarily have to have first film portion 20 of insulating film 17. In this case, semiconductor device 1 may have insulating film 17 configured with second film portion 21. In other words, insulating film 17 has a layered structure including second insulating film 23 and third insulating film 24, and may not have first insulating film 22.

[0449] In this embodiment, the second insulating film 23 covers the sidewalls and bottom wall of the trench 16 in the inner portion and at the end of the gate structure 15. In this embodiment, the third insulating film 24 covers the sidewalls and bottom wall of the trench 16 in the inner portion and at the end of the gate structure 15, with the second insulating film 23 sandwiched therebetween.

[0450] 19 (fifth modification), semiconductor device 1 does not necessarily have to have second film portion 21 of insulating film 17. In this case, semiconductor device 1 may have insulating film 17 configured with a single-layer structure made of first insulating film 22. In this embodiment, first insulating film 22 covers the sidewalls and bottom wall of trench 16 in the inner portion and end portion of gate structure 15.

[0451] The surface insulating film 50 includes a first surface film portion 51 and a second surface film portion 52. In this embodiment, the first surface insulating film 53 has a single-layer structure made of the first surface insulating film 53. The first surface insulating film 53 covers the periphery of the end portion of the gate structure 15 and is connected to the first insulating film 22. In other words, the first surface insulating film 53 is formed integrally with the first insulating film 22.

[0452] In this embodiment, the second surface film portion 52 is configured with a laminated structure including a third surface insulating film 55 and a fourth surface insulating film 56. The third surface insulating film 55 is formed in the same layout as in the embodiment described above. The fourth surface insulating film 56 directly covers the third surface insulating film 55 and is connected to the first surface insulating film 53. In other words, the fourth surface insulating film 56 is formed integrally with the first insulating film 22 and the first surface insulating film 53.

[0453] 20 (sixth modification), semiconductor device 1 does not have buried insulator 19 in the plurality of gate structures 15. Surface insulating film 50 includes active insulating film 90 that selectively covers first main surface 3 in active region 8.

[0454] The active insulating film 90 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The active insulating film 90 may include an insulator that is the same as or different from the first insulating film 22. The active insulating film 90 may include an insulator that is the same as or different from the second insulating film 23. The active insulating film 90 may include an insulator that is the same as or different from the third insulating film 24.

[0455] The active insulating film 90 may include an insulator that is the same as or different from the first surface insulating film 53. The active insulating film 90 may include an insulator that is the same as or different from the second surface insulating film 54. The active insulating film 90 may include an insulator that is the same as or different from the third surface insulating film 55. The active insulating film 90 may include an insulator that is the same as or different from the fourth surface insulating film 56. The active insulating film 90 may include an insulator that is the same as or different from the fifth surface insulating film 57.

[0456] In this embodiment, the active insulating film 90 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. The active insulating film 90 preferably contains an oxide other than the oxide of the chip 2. In this embodiment, the active insulating film 90 is made of an NSG film.

[0457] The active insulating film 90 directly covers the first main surface 3 (the multiple mesa portions 27) around the inner portions of the multiple gate structures 15 and is connected to the multiple insulating films 17. Specifically, the active insulating film 90 is connected to the multiple first insulating films 22 and exposes the multiple buried electrodes 18. The first surface insulating film 53 directly covers the multiple source regions 40 and the multiple contact regions 42. The first surface film portion 51 is connected to the third insulating film 24 and the second surface insulating film 54 at the ends of the multiple gate structures 15.

[0458] In this embodiment, the active insulating film 90 is made of the same insulating film as the first insulating film 22, the third insulating film 24, the second surface insulating film 54, and the fourth surface insulating film 56. In other words, the active insulating film 90 is formed integrally with the first insulating film 22 and the third insulating film 24, and is formed as an extension portion of the first insulating film 22 and the third insulating film 24 that is extended from the trench 16 onto the first main surface 3.

[0459] The thickness of the active insulating film 90 may be greater or less than the first thickness of the first film portion 20. The thickness of the active insulating film 90 may be greater or less than the second thickness of the second film portion 21. The thickness of the active insulating film 90 may be less than the thickness of the second insulating film 23. The thickness of the active insulating film 90 may be greater or less than the thickness of the third insulating film 24.

[0460] The thickness of the active insulating film 90 may be greater or less than the third thickness of the first surface film portion 51. The thickness of the active insulating film 90 may be greater or less than the fourth thickness of the second surface film portion 52. The thickness of the active insulating film 90 may be greater or less than the thickness of the first surface insulating film 53. The thickness of the active insulating film 90 may be greater or less than the thickness of the second surface insulating film 54.

[0461] The thickness of the active insulating film 90 may be greater or less than the thickness of the third surface insulating film 55. The thickness of the active insulating film 90 may be greater or less than the thickness of the fourth surface insulating film 56. The thickness of the active insulating film 90 may be greater or less than the thickness of the fifth surface insulating film 57.

[0462] The thickness of the active insulating film 90 is substantially equal to the thickness of the first insulating film 22, the thickness of the third insulating film 24, the thickness of the second surface insulating film 54, and the thickness of the fourth surface insulating film 56. The thickness of the active insulating film 90 may be 10 nm to 250 nm. The thickness of the active insulating film 90 may have a value belonging to at least one of the ranges of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, 175 nm to 200 nm, 200 nm to 225 nm, and 225 nm to 250 nm.

[0463] In this embodiment, the interlayer film 65 collectively covers the plurality of gate structures 15 in the active region 8 .

[0464] The interlayer film 65 collectively covers the plurality of gate structures 15 and the active insulating film 90 in the active region 8. The interlayer film 65 extends into the trench 16 from above the active insulating film 90, and covers the buried electrode 18, the first insulating film 22, the second insulating film 23, and the third insulating film 24 within the trench 16. The interlayer film 65 has portions that cover the plurality of source regions 40 and the plurality of contact regions 42 with the active insulating film 90 sandwiched therebetween.

[0465] In this embodiment, the semiconductor device 1 includes a plurality of source openings 68 formed in the interlayer film 65. The plurality of source openings 68 penetrate the interlayer film 65 and the active insulating film 90, and selectively expose a plurality of mesas 27. The plurality of source openings 68 may be formed in a one-to-one correspondence with one mesa 27.

[0466] In this case, the plurality of source openings 68 are formed in strip shapes extending in the second direction Y in accordance with the extension direction of the corresponding mesa portions 27. The plurality of source openings 68 selectively expose the plurality of source regions 40 and the plurality of contact regions 42 from the corresponding mesa portions 27.

[0467] Of course, the plurality of source openings 68 may be formed in a one-to-many correspondence with one mesa portion 27. In this case, the plurality of source openings 68 are formed at intervals along the extension direction of the corresponding mesa portion 27.

[0468] The source openings 68 may be formed in a strip shape, a square shape, a circle shape, or the like extending in the second direction Y. The source openings 68 selectively expose the source regions 40 and the contact regions 42 from the corresponding mesa portions 27.

[0469] The source pad electrode 70 extends from above the interlayer film 65 into the plurality of source openings 68 and is electrically connected to the plurality of source regions 40 and the plurality of contact regions 42 within the plurality of source openings 68 .

[0470] The source pad electrode 70 includes either one or both of a lower electrode film 71 and a main electrode film 72. The lower electrode film 71 has a laminated structure including a first electrode film 73 and a second electrode film 74. Of course, the lower electrode film 71 may have a single-layer structure made of the first electrode film 73.

[0471] The first electrode film 73 collectively covers the region of the interlayer film 65 where the multiple source openings 68 are formed, and extends into the multiple source openings 68 from above the interlayer film 65. The first electrode film 73 has a portion that covers the insulating surface of the interlayer film 65 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 68 in a film-like manner, and a portion that covers the first main surface 3 within the multiple source openings 68 in a film-like manner. The first electrode film 73 is mechanically and electrically connected to the multiple source regions 40 and the multiple contact regions 42.

[0472] The second electrode film 74 directly covers the first electrode film 73. The second electrode film 74 collectively covers the region of the interlayer film 65 where the plurality of source openings 68 are formed, sandwiching the first electrode film 73 therebetween, and extends from above the interlayer film 65 into the plurality of source openings 68.

[0473] The second electrode film 74 has a portion that covers the insulating surface of the interlayer film 65 in a film-like manner with the first electrode film 73 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 68 in a film-like manner with the first electrode film 73 sandwiched therebetween, and a portion that covers the first main surface 3 in a film-like manner with the first electrode film 73 sandwiched therebetween within the plurality of source openings 68. The second electrode film 74 is electrically connected to the plurality of source regions 40 and the plurality of contact regions 42 via the first electrode film 73 within the source openings 68.

[0474] The main electrode film 72 directly covers the lower electrode film 71 (second electrode film 74). The main electrode film 72 collectively covers the region of the interlayer film 65 where the plurality of source openings 68 are formed, and backfills the plurality of source openings 68.

[0475] The main electrode film 72 has a portion that covers the insulating surface of the interlayer film 65 with the lower electrode film 71 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 68 with the lower electrode film 71 sandwiched therebetween, and a portion that covers the first main surface 3 with the lower electrode film 71 sandwiched therebetween. The main electrode film 72 is electrically connected to the plurality of source regions 40 and the plurality of contact regions 42 via the lower electrode film 71 within the plurality of source openings 68.

[0476] The above-described embodiments (including modifications) can be implemented in other forms. For example, the above-described embodiments employ the chip 2 including a SiC single crystal. However, the chip 2 may include a silicon single crystal. The first semiconductor layer 6 may include a silicon single crystal. The second semiconductor layer 7 may include a silicon single crystal.

[0477] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0478] In each of the above-described embodiments, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0479] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," "semiconductor rectifier device," etc., as necessary.

[0480] [A1] A semiconductor device (1) comprising: a chip (2) having a main surface (3); and a trench electrode type gate structure (15) formed on the main surface (3), the gate structure (15) comprising: a trench (16) formed on the main surface (3); an insulating film (17) including a first film portion (20) covering the wall surface of the inner part of the trench (16) and a second film portion (21) covering the wall surface of the end of the trench (16) and having a thickness greater than that of the first film portion (20); and a buried electrode (18) buried in the trench (16) across the insulating film (17).

[0481] [A2] The semiconductor device (1) according to A1, wherein the chip (2) includes SiC.

[0482] [A3] The semiconductor device (1) according to A1 or A2, wherein the second film portion (21) covers the sidewalls and bottom wall of the trench (16).

[0483] [A4] A semiconductor device (1) according to any one of A1 to A3, wherein the coverage area of ​​the second film portion (21) with respect to the trench (16) is smaller than the coverage area of ​​the first film portion (20) with respect to the trench (16).

[0484] [A5] A semiconductor device (1) according to any one of A1 to A4, wherein the buried electrode (18) is buried in the trench (16) at a distance from the main surface (3) toward the bottom wall of the trench (16).

[0485] [A6] The semiconductor device (1) according to A5, wherein the gate structure (15) includes a buried insulator (19) buried in the trench (16) above the buried electrode (18).

[0486] [A7] The semiconductor device (1) according to A6, wherein the buried insulator (19) is buried in the trench (16) at a distance from the main surface (3) toward the bottom wall of the trench (16).

[0487] [A8] The semiconductor device (1) according to any one of A1 to A7, further comprising a surface insulating film (50) covering the main surface (3) around the end of the gate structure (15) and connected to the insulating film (17).

[0488] [A9] The semiconductor device (1) described in A8, wherein the surface insulating film (50) includes a first surface film portion (51) that covers the periphery of the end of the gate structure (15) and has a thickness greater than the thickness of the first film portion (20) of the insulating film (17), and a second surface film portion (52) that covers the periphery of the first surface film portion (51) and has a thickness greater than the thickness of the second film portion (21) of the insulating film (17).

[0489] [A10] The semiconductor device (1) according to A8 or A9, further comprising: a semiconductor layer (7) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); the gate structure (15) formed on the main surface (3) so as to be positioned within the semiconductor layer (7); and an outer well region (45) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor layer (7) around an end portion of the gate structure (15), wherein the surface insulating film (50) covers the outer well region (45).

[0490] [A11] A semiconductor device (1) according to any one of A1 to A7, further comprising: a first conductivity type (n-type) semiconductor layer (7) formed in a surface layer portion of the main surface (3); the gate structure (15) formed on the main surface (3) so as to be positioned within the semiconductor layer (7); and a second conductivity type (p-type) outer well region (45) formed in a surface layer portion of the semiconductor layer (7) around an end portion of the gate structure (15).

[0491] [A12] The semiconductor device (1) according to A11, wherein the outer well region (45) has a portion that extends along the second film portion (21).

[0492] [A13] The semiconductor device (1) according to any one of A1 to A7, further comprising: a semiconductor layer (7) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); the gate structure (15) formed on the main surface (3) so as to be positioned within the semiconductor layer (7); and a well region (30) of a second conductivity type (p-type) formed below the gate structure (15) within the semiconductor layer (7).

[0493] [A14] The semiconductor device (1) according to A13, wherein the well region (30) has a portion that is along the second film portion (21) of the insulating film (17).

[0494] [A15] The semiconductor device (1) according to A13 or A14, further comprising: a body region (10) of a second conductivity type (p-type) formed in a surface layer portion of the main surface (3); the gate structure (15) formed on the main surface (3) so as to penetrate the body region (10); and a contact region (42) of the second conductivity type (p-type) extending along a sidewall of the gate structure (15) and electrically connecting the well region (30) to the body region (10).

[0495] [A16] The semiconductor device (1) according to any one of A13 to A15, further comprising a second conductivity type (p-type) outer well region (45) formed in the surface layer portion of the semiconductor layer (7) around the end of the gate structure (15).

[0496] [A17] The semiconductor device (1) according to any one of A1 to A7, further comprising: a first conductivity type (n-type) semiconductor layer (7) formed in a surface layer portion of the main surface (3); and a first conductivity type (n-type) high concentration region formed in the semiconductor layer (7) on the side of the gate structure (15) and having an impurity concentration higher than the impurity concentration of the semiconductor layer (7).

[0497] [A18] The semiconductor device (1) according to any one of A1 to A17, further comprising a gate wiring (60) arranged around an end of the gate structure (15) on the main surface (3) and electrically connected to the gate structure (15).

[0498] [A19] The semiconductor device (1) according to A18, further comprising: an insulating interlayer film (65) covering the gate structure (15) and the gate wiring (60); a pad electrode (70) arranged on a portion of the interlayer film (65) covering the gate structure (15); and a gate finger electrode (81) arranged on a portion of the interlayer film (65) covering the gate wiring (60).

[0499] [A20] The semiconductor device (1) according to A19, further comprising a slit portion (82) defined in the region between the pad electrode (70) and the gate finger electrode (81) and overlapping the main surface (3) in the stacking direction.

[0500] [B1] A semiconductor device (1) comprising: a chip (2) having a main surface (3); a trench electrode type gate structure (15) formed on the main surface (3); a first surface film portion (51) covering the periphery of the gate structure (15) on the main surface (3); and a surface insulating film (50) including a second surface film portion (52) covering the periphery of the first surface film portion (51) on the main surface (3) and having a thickness greater than the thickness of the first surface film portion (51).

[0501] [B2] The semiconductor device (1) according to B1, wherein the chip (2) includes SiC.

[0502] [B3] The semiconductor device (1) according to B1 or B2, wherein the second surface film portion (52) has a width greater than a width of the first surface film portion (51).

[0503] [B4] The semiconductor device (1) according to any one of B1 to B3, further comprising a gate wiring (60) disposed on the first surface film portion (51) and electrically connected to an end of the gate structure (15).

[0504] [B5] The semiconductor device (1) according to B4, wherein the gate wiring (60) has a portion facing the main surface (3) with the second surface film portion (52) interposed therebetween.

[0505] [B6] The semiconductor device (1) according to B4 or B5, wherein the coverage area of ​​the gate wiring (60) with respect to the second surface film portion (52) is larger than the coverage area of ​​the gate wiring (60) with respect to the first surface film portion (51).

[0506] [B7] The semiconductor device (1) according to any one of B4 to B6, further comprising an insulating interlayer film (65) covering the gate structure (15) and the gate wiring (60), and a gate finger electrode (81) arranged on a portion of the interlayer film (65) covering the gate wiring (60).

[0507] [B8] The semiconductor device (1) according to B7, wherein the gate finger electrode (81) is formed at a distance from the end of the gate structure (15) toward the peripheral edge of the chip (2).

[0508] [B9] The semiconductor device (1) according to B7 or B8, wherein the gate finger electrode (81) does not overlap the gate structure (15) in the stacking direction.

[0509] [B10] The semiconductor device (1) according to any one of B7 to B9, wherein the gate finger electrode (81) faces the surface insulating film (50) with the gate wiring (60) and the interlayer film (65) sandwiched therebetween.

[0510] [B11] The semiconductor device (1) according to any one of B7 to B10, wherein the gate finger electrode (81) faces the second surface film portion (52).

[0511] [B12] The semiconductor device (1) according to any one of B7 to B11, wherein the gate finger electrode (81) is formed at an interval from the first surface film portion (51) toward the peripheral edge of the main surface (3).

[0512] [B13] The semiconductor device (1) according to any one of B7 to B12, further comprising a pad electrode (70) arranged on a portion of the interlayer film (65) that covers the gate structure (15).

[0513] [B14] The semiconductor device (1) according to B13, further comprising a slit portion (82) defined in a region between the pad electrode (70) and the gate finger electrode (81) and overlapping the main surface (3) in the stacking direction.

[0514] [B15] A semiconductor device (1) according to any one of B1 to B14, further comprising: a first conductivity type (n-type) semiconductor layer (7) formed in a surface layer portion of the main surface (3); and a gate structure (15) formed on the main surface (3) so as to be positioned within the semiconductor layer (7).

[0515] [B16] The semiconductor device (1) described in B15 further includes a second conductivity type (p-type) outer well region (45) formed in the surface layer of the semiconductor layer (7) around the end of the gate structure (15), and the surface insulating film (50) covers the outer well region (45).

[0516] [B17] The semiconductor device (1) according to B16, wherein the first surface film portion (51) covers the outer well region (45).

[0517] [B18] The semiconductor device (1) according to B16 or B17, wherein the second surface film portion (52) covers the outer well region (45).

[0518] [B19] A semiconductor device (1) according to any one of B15 to B18, further comprising a second conductivity type (p-type) well region (30) formed in the semiconductor layer (7) below the gate structure (15).

[0519] [B20] The semiconductor device (1) according to B19, further comprising: a body region (10) of a second conductivity type (p-type) formed in a surface layer portion of the main surface (3); the gate structure (15) formed on the main surface (3) so as to penetrate the body region (10); and a contact region (42) of the second conductivity type (p-type) extending along a sidewall of the gate structure (15) and electrically connecting the well region (30) to the body region (10).

[0520] [C1] A semiconductor device (1) comprising: a chip (2) having a main surface (3); a trench electrode-type gate structure (15) formed on the main surface (3); a gate wiring (60) electrically connected to an end of the gate structure (15) on the main surface (3); an insulating interlayer film (65) covering the gate structure (15) and the gate wiring (60); a pad electrode (70) disposed on the interlayer film (65) and facing the gate structure (15) and the gate wiring (60) across the interlayer film (65); a gate finger electrode (81) disposed on the interlayer film (65) at a distance from the pad electrode (70) and facing the gate wiring (60) across the interlayer film (65); and a slit portion (82) defined in a region between the pad electrode (70) and the gate finger electrode (81) and overlapping the main surface (3) in a stacking direction.

[0521] [C2] The semiconductor device (1) according to C1, wherein the chip (2) includes SiC.

[0522] [C3] The semiconductor device (1) according to C1 or C2, wherein the slit portion (82) does not overlap the gate structure (15) in the stacking direction.

[0523] Although specific embodiments have been described in detail above, these are merely examples that clarify the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification, the order of the embodiment examples, the order of the modified examples, etc.

[0524] REFERENCE SIGNS LIST 1 semiconductor device 2 chip 3 first main surface (main surface) 7 second semiconductor layer (semiconductor layer) 10 body region 15 gate structure 16 trench 17 insulating film 18 buried electrode 19 buried insulator 20 first film portion 21 second film portion 30 well region 42 contact region 45 outer well region 50 surface insulating film 51 first surface film portion 52 second surface film portion 60 gate wiring 65 interlayer film 70 source pad electrode (pad electrode) 81 gate finger electrode 82 first slit portion (slit portion)

Claims

1. A semiconductor device including a chip having a main surface and a trench electrode type gate structure formed on the main surface, the gate structure including a trench formed on the main surface, an insulating film including a first film portion covering the inner wall surface of the trench and a second film portion covering the end wall surface of the trench and having a thickness greater than that of the first film portion, and a buried electrode buried in the trench with the insulating film interposed therebetween.

2. The semiconductor device according to claim 1, wherein the chip contains SiC.

3. The semiconductor device according to claim 1 or 2, further including a surface insulating film covering the main surface around the end of the gate structure and connected to the insulating film.

4. The semiconductor device according to claim 3, wherein the surface insulating film includes a first surface film portion covering around the end of the gate structure and having a thickness greater than that of the first film portion of the insulating film, and a second surface film portion covering around the first surface film portion and having a thickness greater than that of the second film portion of the insulating film.

5. The semiconductor device according to any one of claims 1 to 4, further including a first conductivity type semiconductor layer formed in the surface layer portion of the main surface, the gate structure formed on the main surface so as to be located within the semiconductor layer, and a second conductivity type outer well region formed in the surface layer portion of the semiconductor layer around the end of the gate structure.

6. The semiconductor device according to claim 5, wherein the outer well region has a portion along the second film portion.

7. The semiconductor device according to any one of claims 1 to 6, further including a first conductivity type semiconductor layer formed in the surface layer portion of the main surface, the gate structure formed on the main surface so as to be located within the semiconductor layer, and a second conductivity type well region formed below the gate structure within the semiconductor layer.

8. The semiconductor device according to claim 7, wherein the well region has a portion along the second film portion of the insulating film.

9. The semiconductor device according to any one of claims 1 to 8, further including a gate wiring disposed around the end of the gate structure on the main surface and electrically connected to the gate structure.

10. An insulating interlayer film covering the gate structure and the gate wiring, a pad electrode disposed on a portion of the interlayer film covering the gate structure, and a gate finger electrode disposed on a portion of the interlayer film covering the gate wiring. The semiconductor device according to claim 9 further includes these components.

11. The semiconductor device according to claim 10 further includes a slit portion partitioned in a region between the pad electrode and the gate finger electrode and overlapping the main surface in the stacking direction.

12. A semiconductor device including a chip having a main surface, a trench electrode type gate structure formed on the main surface, a first surface film portion covering the periphery of the gate structure on the main surface, and a surface insulating film including a second surface film portion covering the periphery of the first surface film portion on the main surface and having a thickness greater than that of the first surface film portion.

13. The semiconductor device according to claim 12 further includes a gate wiring having a portion facing the main surface with the first surface film portion interposed therebetween and being electrically connected to the gate structure.

14. The semiconductor device according to claim 13, wherein the gate wiring has a portion facing the main surface with the second surface film portion interposed therebetween.

15. An insulating interlayer film covering the gate structure and the gate wiring, and a gate finger electrode disposed on a portion of the interlayer film covering the gate wiring. The semiconductor device according to claim 13 or 14 further includes these components.

16. A pad electrode disposed on a portion of the interlayer film covering the gate structure, and a slit portion partitioned in a region between the pad electrode and the gate finger electrode and overlapping the main surface in the stacking direction. The semiconductor device according to claim 15 further includes these components.

17. A semiconductor layer of a first conductivity type formed in a surface layer portion of the main surface, the gate structure formed on the main surface so as to be located within the semiconductor layer, and an outer well region of a second conductivity type formed in a surface layer portion of the semiconductor layer around an end portion of the gate structure. The surface insulating film covers the outer well region. The semiconductor device according to any one of claims 12 to 16 further includes these components.

18. The semiconductor device according to any one of claims 12 to 17, further comprising: a first conductivity type semiconductor layer formed in a surface layer portion of the main surface; the gate structure formed in the main surface so as to be positioned within the semiconductor layer; and a second conductivity type well region formed below the gate structure within the semiconductor layer.

19. The semiconductor device according to claim 18, further comprising: a second conductivity type body region formed in a surface layer portion of the main surface; the gate structure formed in the main surface so as to penetrate the body region; and a second conductivity type contact region extending along a side wall of the gate structure and electrically connecting the well region to the body region.

20. A semiconductor device including: a chip having a main surface; a trench electrode type gate structure formed in the main surface; a gate wiring electrically connected to an end portion of the gate structure on the main surface; an insulating interlayer film covering the gate structure and the gate wiring; a pad electrode disposed on the interlayer film and facing the gate structure and the gate wiring with the interlayer film therebetween; a gate finger electrode disposed on the interlayer film with a space from the pad electrode and facing the gate wiring with the interlayer film therebetween; and a slit portion partitioned in a region between the pad electrode and the gate finger electrode and overlapping the main surface in a stacking direction.

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