Offset correction apparatus and method

Abstract

An offset correction apparatus according to an embodiment of the present invention is for correcting an offset voltage generated in an output buffer, and may comprise: a DAC-embedded amplifier (AMP) including the output buffer; an offset correction signal generation unit that receives an input of a bit string signal from the outside and generates an offset correction signal on the basis of the bit string signal; and an offset correction current generation unit that includes a differential difference amplifier (DDA) and generates an offset correction current that compensates for the offset voltage on the basis of the offset correction signal.

Description

Offset compensation device and method

[0001] The present invention relates to an offset compensation device and method, and is a technology for compensating for an offset occurring in an output buffer.

[0002] Recently, display technology is advancing towards the highest resolutions possible, such as FHD, 4K, and 8K. High resolution means the inclusion of countless light-emitting elements within the display. Uniformity, which represents the consistency of light output from these individual light-emitting elements, is becoming increasingly important as display development continues.

[0003] Display uniformity can be determined by a variety of factors, but one of the primary causes of display uniformity degradation is the output buffer offset, which is one of the sources of dispersion across each channel. Mismatches within the display's transistors lead to current mismatches, resulting in output buffer offset, which in turn degrades display uniformity.

[0004] Accordingly, various methods for compensating the offset of transistors are being studied, and auto zeroing is a representative example, but there are still areas lacking in optimization, so technology for optimizing offset compensation is still needed.

[0005] In order to solve the above-described problem, the present invention provides an offset compensation device and method that generate an offset compensation signal based on a bit string signal input from an external source and generate an offset compensation current that compensates for an offset voltage based on the offset compensation signal.

[0006] An offset correction device according to one embodiment of the present invention relates to an offset correction device for correcting an offset voltage generated in an output buffer, and may include a DAC embedded amp including an output buffer, an offset correction signal generation unit for receiving a bit string signal from the outside and generating an offset correction signal based on the bit string signal, and a DDA (Differential difference amp), and an offset correction current generation unit for generating an offset correction current that compensates for the offset voltage based on the offset correction signal.

[0007] In addition, according to one embodiment, the DAC built-in amplifier may include an N-bit DAC built-in input stage, a first node and a second node connected to the N-bit DAC built-in input stage, and the DDA may be provided in a form parallel to the N-bit DAC built-in input stage through a first compensation current port connected to the first node and a second compensation current port connected to the second node.

[0008] Additionally, according to one embodiment, the DDA may include a first transistor connected to a first correction current port and a second transistor connected to a second correction current port, wherein the first transistor and the second transistor are connected in parallel.

[0009] Additionally, according to one embodiment, the DDA may be characterized in that the first and second transistors are connected to opposite ends of the first and second compensation current ports to a third node, and further includes a third transistor between the third node and the ground node.

[0010] Additionally, according to one embodiment, the offset compensation current generation unit may be characterized by further including an M-bit R-string DAC.

[0011] In addition, according to one embodiment, the offset correction current generation unit may be characterized by generating an offset correction current in the DDA based on an input voltage and an output voltage output from the M-bit R-string DAC based on an offset correction signal and an externally input input voltage.

[0012] Additionally, according to one embodiment, the M-bit R-string DAC may be characterized by adjusting a minimum value of an offset compensation voltage for generating an offset compensation current based on an input voltage.

[0013] Additionally, according to one embodiment, an offset voltage polarity unification unit may be further included to unify the polarity of the offset voltage generated in the output buffer to positive or negative.

[0014] In addition, according to one embodiment, the offset correction signal generation unit may be characterized in that it receives a bit string signal whose size gradually increases until the polarity of the offset voltage is reversed, stores the bit string signal at the moment when the polarity of the offset voltage is reversed as the size of the bit string signal increases as the offset correction signal, and the offset correction current generation unit continuously generates an offset correction current based on the stored offset correction signal.

[0015] Additionally, according to one embodiment, the DAC built-in amplifier may be characterized in that it includes a switch for reversing an offset polarity, and the offset polarity reversal switch is controlled by an offset voltage polarity unification unit.

[0016] An offset correction method according to another embodiment of the present invention relates to an offset correction method for correcting an offset voltage generated in an output buffer, and may include a step of providing a DAC embedded amplifier including an output buffer, an offset correction signal generation step of receiving a bit string signal from the outside in an offset correction signal generation unit and generating an offset correction signal based on the bit string signal, and an offset correction current generation step of generating an offset correction current that compensates for an offset voltage based on the offset correction signal in an offset correction current generation unit including a DDA (Differential difference amp).

[0017] In addition, according to one embodiment, the DAC built-in amplifier may include an N-bit DAC built-in input stage, a first node and a second node connected to the N-bit DAC built-in input stage, and the DDA may be provided in a form parallel to the N-bit DAC built-in input stage through a first compensation current port connected to the first node and a second compensation current port connected to the second node.

[0018] Additionally, according to one embodiment, the DDA may be characterized by including a first transistor connected to a first correction current port and a second transistor connected to a second correction current port, wherein the first transistor and the second transistor are connected in parallel.

[0019] Additionally, according to one embodiment, the DDA may be characterized in that the first and second transistors are connected to opposite ends of the first and second compensation current ports to a third node, and further includes a third transistor between the third node and the ground node.

[0020] Additionally, according to one embodiment, the offset compensation current generation unit may be characterized by further including an M-bit R-string DAC.

[0021] Additionally, according to one embodiment, the offset correction current generation step may be characterized by generating an offset correction current in the DDA based on an input voltage and an output voltage output from the M-bit R-string DAC based on an offset correction signal and an externally input input voltage.

[0022] Additionally, according to one embodiment, the M-bit R-string DAC may be characterized by adjusting a minimum value of an offset compensation voltage for generating an offset compensation current based on an input voltage.

[0023] Additionally, according to one embodiment, the offset voltage polarity unification unit may further include an offset voltage polarity unification step for unifying the polarity of the offset voltage generated in the output buffer to positive or negative.

[0024] In addition, according to one embodiment, the offset correction signal generation step may be characterized by receiving a bit string signal whose size gradually increases until the polarity of the offset voltage is reversed, storing the bit string signal at the moment when the polarity of the offset voltage is reversed as the size of the bit string signal increases as the offset correction signal, and the offset correction current generation step may be characterized by continuously generating an offset correction current based on the stored offset correction signal.

[0025] Additionally, according to one embodiment, the DAC built-in amplifier may be characterized in that it includes a switch for reversing an offset polarity, and the offset polarity reversal switch is controlled by an offset voltage polarity unification unit.

[0026] According to the offset correction device and method of the present invention, an offset correction signal can be generated based on a bit string signal input from an external source, and an offset compensation current can be generated based on the offset correction signal to compensate for an offset voltage.

[0027] Figure 1 is a schematic diagram showing the structure of a general display driving circuit according to one embodiment.

[0028] Fig. 2 is a diagram showing an offset voltage according to the output of a general display driving circuit according to one embodiment.

[0029] FIG. 3 is a diagram showing an offset voltage according to the output of a display driving circuit when an offset is corrected using an offset correction device and method of the present invention according to one embodiment.

[0030] Fig. 4 is a block diagram of an offset correction device according to one embodiment of the present invention.

[0031] Fig. 5 is a schematic diagram showing the relationship between each component of the offset correction device of the present invention according to one embodiment.

[0032] Fig. 6 is a circuit diagram of a DAC built-in amplifier according to one embodiment of the present invention.

[0033] Fig. 7 is a schematic diagram showing an output value when an output buffer according to one embodiment operates as a comparator.

[0034] Fig. 8 is a schematic diagram of an offset polarity unification unit according to one embodiment.

[0035] Fig. 9 is a timing diagram showing a process of unifying offset polarity according to one embodiment.

[0036] Fig. 10 is a graph showing a single offset polarity according to one embodiment.

[0037] Figures 11 and 12 are schematic diagrams showing how an offset polarity reversal switch is controlled by a switch control signal according to each embodiment.

[0038] Fig. 13 is a schematic diagram of an offset correction signal generation unit according to one embodiment.

[0039] Fig. 14 is a timing diagram for generating a correction signal in an offset correction signal generation unit according to one embodiment.

[0040] Fig. 15 is a schematic diagram of an offset correction current generation unit according to one embodiment.

[0041] Figures 16 and 17 are circuit diagrams showing the connection of an offset correction current generation unit and a DAC built-in amplifier according to an embodiment.

[0042] Fig. 18 is a flowchart of an offset correction method according to one embodiment.

[0043] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0044] The terms used in this specification will be briefly explained, and the present invention will be described in detail.

[0045] The terms used in this invention have been selected from widely used, current terms, taking into account their functions. However, these terms may vary depending on the intentions of those skilled in the art, precedents, the emergence of new technologies, etc. Furthermore, in certain cases, terms may be arbitrarily selected by the applicant, in which case their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should not be defined simply as names, but rather based on their inherent meanings and the overall content of the invention.

[0046] Below, with reference to the attached drawings, embodiments of the present invention are described in detail so that those skilled in the art can easily practice them. Furthermore, in order to clearly explain the present invention, portions irrelevant to the description are omitted in the drawings.

[0047] Terms including ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, the first component could be referred to as the second component, and similarly, the second component could also be referred to as the first component. The term "and / or" includes any combination of multiple related items or any one of multiple related items.

[0048]

[0049] Fig. 1 is a schematic diagram illustrating the structure of a typical display data driver according to one embodiment. Referring to Fig. 1, the typical display data driver may include a shift register, a sampling latch, a holding latch, a digital-to-analog converter (DAC), and an output buffer.

[0050] The shift register can receive a horizontal synchronization signal and a data clock signal (CLK) as input, and sequentially generate sampling pulses while shifting the horizontal synchronization signal based on the data clock signal (CLK).

[0051] A sampling latch can sequentially sample and store data signals (Data) in response to sampling pulses generated from a shift register.

[0052] The holding latch can simultaneously receive and store data stored in the sampling latch according to the data load signal (Load).

[0053] A digital-to-analog converter can convert an input digital signal into an analog signal.

[0054] The output buffer can apply a data voltage to the data line corresponding to each channel for the input analog signal, and can act as a buffer between the data line and the data driver.

[0055] Additionally, Fig. 2 is a diagram illustrating offset voltages according to the output of a typical display data driver. Referring to Fig. 2, it can be seen that the offset of the output buffer causes dispersion in each channel, and that the dispersion degrades the uniformity of the display screen.

[0056]

[0057] Hereinafter, the offset correction device and method of the present invention will be described.

[0058] The offset compensation device and method of the present invention relate to an offset compensation device and method for compensating an offset voltage generated in an output buffer, which receives a bit string signal (CAL) from an external source, generates an offset compensation signal (TRM) based on the bit string signal (CAL), and generates an offset compensation current that compensates for the offset voltage based on the offset compensation signal (TRM) by including a DDA (Differential Difference AMP).

[0059] The offset correction device and method of the present invention can improve the uniformity of a display screen by correcting the offset by adding a separate device that generates a current for compensating the offset to the general display data driver of FIG. 1. FIG. 3 is a diagram showing an offset voltage according to the output of a display data driver when the offset is corrected using the offset correction device and method of the present invention according to one embodiment. When FIG. 2 and FIG. 3 are compared, it can be confirmed that the output voltage has a lower offset than that of a general display data driver and maintains a more uniform value by the offset correction device and method of the present invention.

[0060]

[0061] Hereinafter, the offset correction device of the present invention will be described.

[0062] The offset correction device (1) of the present invention is preferably implemented as a circuit, but is not limited thereto.

[0063] Fig. 4 is a block diagram of an offset correction device (1) of the present invention, and Fig. 5 is a schematic diagram showing the relationship between each component of an offset correction device (1) of the present invention according to one embodiment.

[0064] The offset correction device (1) of the present invention may include a DAC embedded amplifier (20), an offset voltage polarity unification unit (40), an offset correction signal generation unit (60), and an offset correction current generation unit (80). In addition, it may further include an N-bit DAC decoder and a mode selection MUX. The offset correction device (1) of the present invention may include various configurations without limitation in addition to the configurations described above.

[0065]

[0066] The DAC built-in amplifier (20) will be described with reference to FIGS. 6 and 7.

[0067] Fig. 6 is a circuit diagram of a DAC built-in amplifier (20) of the present invention according to one embodiment.

[0068] Referring to FIG. 6, the DAC built-in amplifier (20) may include an amplification stage module and an input stage module. The DAC built-in amplifier (20) may function as a general output buffer by including the amplification stage module and the input stage module. This means that the DAC built-in amplifier includes the same output buffer, and the expressions herein may be used interchangeably.

[0069] In the DAC built-in amplifier (20) that operates as an output buffer, an offset voltage of irregular size may be generated depending on current mismatch, and each offset may have a positive or negative polarity.

[0070] The amplifier stage module may include at least one power voltage node (VDD), a ground node (VSS), capacitors (C1, C2), and a plurality of transistors (M3 to M16). In addition, each transistor may be provided with bias signals (V BP1 , V BP2 , V BN1 , V BN2 ) can be authorized.

[0071] The input stage module may include an N-bit DAC embedded input stage, at least one MUX and transistor that serve as input terminals of the input stage, etc. The N-bit DAC embedded input stage may have a structure in which a plurality of transistors (MN1 to MN8) are connected in parallel, and a separate signal (VN, VP) may be input to each transistor. Here, the N-bit embedded input stage may be a 2-bit DAC embedded input stage, but is not limited thereto.

[0072] According to one embodiment, the DAC built-in amplifier (20) may be provided in such a manner that an amplification stage module and an input stage module are connected in parallel through a plurality of nodes. For example, referring to FIG. 6, a first node (N1) located at an opposite terminal of one transistor (M3) connected to a power supply voltage node (VDD) and a second node (N2) located at an opposite terminal of another transistor (M4) connected to the same power supply voltage node (VDD) may be provided in a form in which they are connected in parallel to an N-bit DAC built-in input stage. In addition, the N-bit DAC built-in input stage may be connected to a ground node (VSS) of the amplification stage module with at least one transistor interposed therebetween at an opposite terminal of a terminal to which the first node (N1) and the second node (N2) are connected.

[0073] In one embodiment, the output buffer can operate as a comparator. The DAC built-in amplifier (20) can operate the output buffer as a comparator during offset removal operation, and this can be switched by an externally input selection signal (SEL). That is, the output buffer can operate as a comparator when the selection signal (SEL) is 1, and can operate as an output buffer when the selection signal (SEL) is 0.

[0074] Fig. 7 is a schematic diagram showing an output value when the output buffer in the DAC built-in amplifier (20) operates as a comparator according to one embodiment. When the output buffer operates as a comparator, the output buffer (comparator) outputs different values ​​(V) depending on the polarity of the offset voltage. out ) can be output. For example, if the offset voltage is positive (positive V os ), output value (V out ) becomes High (1), and when the offset voltage is negative (negative V os ), output value (V out ) can appear as low(0).

[0075] In addition, according to one embodiment, the DAC built-in amplifier (20) includes a switch for reversing the offset polarity, and the offset polarity reversal switch can be controlled by the offset voltage polarity unification unit (40). Specifically, the DAC built-in amplifier (20) can include an offset polarity reversal switch in the amplification stage module, and the offset polarity reversal switch can be controlled by a switch control signal (CH, CHB) output from the offset voltage polarity unification unit (40). Referring again to FIG. 6, it can be confirmed that the DAC built-in amplifier (20) includes an offset polarity reversal switch, and it can be confirmed that each offset polarity reversal switch can be controlled by a switch control signal (CH, CHB). A detailed description thereof will be provided later.

[0076]

[0077] The offset polarity unification unit will be described with reference to FIGS. 8 to 10.

[0078] Fig. 8 is a schematic diagram of an offset polarity unification unit according to one embodiment.

[0079] The offset voltage polarity unification unit (40) can unify the polarity of the offset voltage generated in the output buffer to either positive or negative. Specifically, the offset voltage polarity unification unit (40) can determine the polarity of the offset voltage and convert it to indicate either positive or negative polarity.

[0080] Referring to Fig. 8, the offset voltage polarity unification unit (40) outputs the output value (V) according to the comparator operation of the output buffer. out ) and receives a control signal (RSB) and a polarity signal (SAVE_POL) from the outside, and can generate a switch control signal (CH, CHB) that controls the offset polarity inversion switch as an output. That is, the offset voltage polarity unification unit (40) outputs the output value (V) of the output buffer. out) is input, and through this, it is determined whether the offset voltage is positive or negative, and a switch control signal (CH, CHB) that controls the offset polarity inversion switch based on the control signal (RSB) and the polarity signal (SAVE_POL) is generated, so that the offset voltage generated in the output buffer can be standardized as positive or negative.

[0081] Fig. 9 is a timing diagram showing a process of unifying the polarity of an offset voltage according to one embodiment, and Fig. 10 is a graph showing a state in which the offset voltage polarity is unified. With the example of Fig. 9 as an explanation, if the control signal (RSB) is 0, the offset voltage polarity unification unit (40) can generate a switch control signal CH=1 as an output (initial state). Thereafter, if the control signal (RSB) becomes 1 and the polarity signal (SAVE_POL) becomes 1, the switch control signal (CH) signal can be determined according to the offset voltage polarity. If the offset voltage is negative, the output value (V out ) is 0, the switch control signal (CH) can be 1 (maintain the initial state). On the other hand, if the offset voltage is positive, the output value (V out ) is 1, the switch control signal (CH) can be 0 (polarity inversion). The switch control signal (CH) can control the offset polarity inversion switch inside the DAC built-in amplifier (20) to invert the offset polarity. According to the example described above, as shown in FIG. 10, the offset voltage polarity unification unit (40) can unify the offset voltage generated in the output buffer to a negative number.

[0082] Figures 11 and 12 are schematic diagrams showing how an offset polarity reversal switch is controlled by a switch control signal (CH). Referring to Figures 11 and 12, it can be confirmed that the offset polarity reversal switch is controlled by the switch control signal (CH) being 1 or 0.

[0083]

[0084] The offset correction signal generation unit (60) will be described with reference to FIGS. 13 and 14.

[0085] Fig. 13 is a schematic diagram of an offset correction signal generation unit (60) according to one embodiment.

[0086] The offset correction signal generation unit (60) can receive a bit string signal (CAL) from the outside and generate an offset correction signal (TRM) based on the bit string signal (CAL). Specifically, the offset correction signal generation unit (60) can generate an output value (V) of the output buffer. out ) and an enable signal (EN_CAL) and a bit string signal (CAL) can be input from the outside, and an offset correction signal (TRM) can be generated based on these. Here, the bit string signal (CAL) can be a 5-bit signal, but is not limited thereto.

[0087] In addition, according to one embodiment, the offset correction signal generation unit (60) may receive a bit string signal (CAL) whose size gradually increases until the polarity of the offset voltage is inverted. For example, if the bit string signal (CAL) is a 5-bit signal, the offset correction signal generation unit (60) may receive the smallest 00000 bit string signal (CAL) and sequentially receive bit string signals (CAL) whose sizes gradually increase in the order of 00001, 00010, and 00011. The offset correction signal generation unit (60) may generate an offset correction signal (TRM) based on the input bit string signal (CAL), and offset compensation may be performed based on this in the offset correction current generation unit (80). As the bit string signal (CAL) increases, the offset compensation may also increase, so that the polarity of the offset voltage may be inverted.

[0088] According to one embodiment, the size of the offset correction signal (TRM) generated by the offset correction signal generation unit (60) may be proportional to the size of the bit string signal (CAL) on which it is based. That is, as the size of the input bit string signal (CAL) increases, the size of the offset correction signal (TRM) generated based thereon may increase.

[0089] In addition, according to one embodiment, the offset correction signal generation unit (60) can store the bit string signal (CAL) at the moment when the polarity of the offset voltage is reversed as the size of the bit string signal (CAL) increases, as a fixed offset correction signal (TRM-f). As described in the above example, if the offset correction signal (TRM) is generated based on the bit string signal (CAL) of 00010, and the polarity of the offset voltage is reversed from negative to positive as a result of offset compensation performed based thereon, the offset correction signal generation unit (60) can separately store 00010 as a fixed offset correction signal (TRM-f).

[0090] Referring to Fig. 14, the process of generating an offset correction signal by the offset correction signal generation unit (60) will be described.

[0091] Fig. 14 is a timing diagram for generating a correction signal in an offset correction signal generation unit (60) according to one embodiment. Fig. 14 is an embodiment for a case where the bit string signal (CAL) is a 5-bit string signal.

[0092] Referring to the embodiment of Fig. 14, after the polarity is unified to a negative number in the offset voltage polarity unification unit (40), the offset correction signal generation unit (60) can receive a bit string signal (CAL) according to an enable signal (EN_CAL). The offset correction signal generation unit (60) can sequentially receive bit string signals (CAL) of increasing size one step at a time in the order of the smallest 00000, 00001, and 00010. The offset correction signal generation unit (60) can generate an offset correction signal (TRM) based on the bit string signal (CAL), and based on the bit string signal (CAL), the offset correction current generation unit (80) can generate an offset correction current to compensate for the offset. As the bit string signal (CAL) received by the offset correction signal generation unit (60) increases step by step, the offset correction current generated based on the bit string signal (CAL) can also increase. The offset compensation signal generation unit (60) can store the bit string signal (CAL) at the moment when the offset voltage switches from negative to positive according to the increased offset compensation current as a fixed offset compensation signal (TRM-f). In the example of Fig. 14, when the bit string signal (CAL) is 00100, the offset voltage switches to positive, and 00100 can be stored as the fixed offset compensation signal (TRM-f).

[0093]

[0094] The offset correction current generation unit (80) will be described with reference to FIGS. 15 to 17.

[0095] Fig. 15 is a schematic diagram of an offset compensation current generation unit (80), and Figs. 16 and 17 are circuit diagrams showing the offset compensation current generation unit and the DAC built-in amplifier connected.

[0096] Referring to FIGS. 15 to 17, the offset compensation current generation unit (80) can generate an offset compensation current by including an M-bit R-string DAC and a DDA (Differential difference amp). The offset compensation current generation unit (80) generates an offset compensation signal (TRM) generated by the offset compensation signal generation unit (60) and an input voltage (V) input from the outside. TRMH , V TRML ) can generate an offset compensation current based on which the M-bit R-string DAC may be, but is not limited to, a 5-bit R-string DAC.

[0097] Referring to Figure 15, the M-bit R-string DAC has an offset compensation signal and an input voltage (V TRMH , V TRML ) as input and output voltage (V DP ) can be generated, and the DDA is the output voltage (V) of the M-bit R-string DAC. DP ) and input voltage (V TRML ) can be used as input to generate an offset compensation current. The DDA has two input voltages (V DP , V TRML ) may cause a difference in current, and this can be used as an offset compensation current to compensate for the offset voltage.

[0098] Also, referring to FIGS. 16 and 17, the DDA can be provided in connection with a DAC built-in amplifier (20).

[0099] Referring to FIG. 17, a DDA according to one embodiment may be arranged in parallel with an input stage module through a first correction current port (P1) connected to a first node (N1) and a second correction current port (P3) connected to a second node (N2).

[0100] Additionally, the DDA according to one embodiment may include a first transistor (TR1) connected to a first correction current port (P1) and a second transistor (TR2) connected to a second correction current port (P2). Additionally, the first transistor (TR1) and the second transistor (TR2) may be connected in parallel.

[0101] Also, in the DDA according to one embodiment, the first transistor (TR1) and the second transistor (TR2) each output voltage (V) of the M-bit R-string DAC. DP ) and input voltage (V TRML ) can be used as an input terminal. The first transistor (TR1) and the second transistor (TR2) can be used to input the voltage (V) of the two input nodes. DP , V TRML ) may cause a difference in current, and this can be used as an offset compensation current to compensate for the offset voltage.

[0102] In addition, according to FIGS. 16 and 17, in a DDA according to one embodiment, the first transistor (TR1) and the second transistor (TR2) can be connected to the third node (P3) at opposite ends of the first correction current port (P1) and the second correction current port (P2). That is, the third node (P3) can be located and connected at the opposite ends of the first transistor (TR1) having the first correction current port (P1) at one end and the second transistor (TR2) having the second correction current port (P2) at one end.

[0103] Additionally, the DDA may further include a third transistor (TR3) between the third node (P3) and the ground node (VSS). That is, the third node (P3) and the ground node (VSS) of the amplification stage module may be connected with the third transistor (TR3) therebetween.

[0104] In one embodiment, as the magnitude of the offset compensation signal (TRM) increases, the difference between the voltages of the two input nodes of the DDA may increase. Since the magnitude of the offset compensation signal (TRM) may be proportional to the magnitude of the input bit string signal (CAL), this means that as the magnitude of the input bit string signal (CAL) increases, the difference between the voltages of the two input nodes of the DDA may increase, thereby increasing the magnitude of the generated offset compensation current.

[0105] In addition, according to one embodiment, the offset correction current generation unit (80) can continuously generate the offset correction current based on the stored fixed offset correction signal (TRM-f). Referring again to the example of FIG. 14, the offset voltage can be minimized by generating the offset correction current based on the stored fixed offset correction signal (TRM-f) 00100, and by continuously generating it, the deviation of the offset voltage can be minimized as much as possible.

[0106] Additionally, in one embodiment, the M-bit R-string DAC receives an externally input voltage (V TRMH , V TRML ) can be used to adjust the minimum value of the offset compensation voltage. Here, the offset compensation voltage may mean a voltage for generating an offset compensation current. According to one embodiment, the minimum value of the offset compensation voltage is (V TRMH -V TRML ) / 32 values, but are not limited thereto.

[0107]

[0108] Hereinafter, the offset correction method of the present invention will be described.

[0109] Fig. 18 is a flowchart of an offset correction method according to one embodiment.

[0110] Referring to FIG. 18, the offset correction method of the present invention relates to an offset correction method for correcting an offset voltage generated in an output buffer, and may include a step (S1810) of providing a DAC embedded amplifier (DAC embedded amp) including an output buffer. In addition, the offset correction method may include an offset correction signal generation step (S1820) of, in an offset correction signal generation unit, receiving a bit string signal from the outside and generating an offset correction signal based on the bit string signal. In addition, the offset correction method may include an offset correction current generation step (S1830) of, in an offset correction current generation unit including a DDA (Differential difference amp), generating an offset correction current that compensates for an offset voltage based on the offset correction signal.

[0111] In addition, according to one embodiment, the DAC built-in amplifier may include a 2-bit DAC built-in input stage, a first node and a second node connected to the 2-bit DAC built-in input stage, and the DDA may be provided in a form parallel to the 2-bit DAC built-in input stage through a first compensation current port connected to the first node and a second compensation current port connected to the second node.

[0112] Additionally, according to one embodiment, the DDA may be characterized by including a first transistor connected to a first correction current port and a second transistor connected to a second correction current port, wherein the first transistor and the second transistor are connected in parallel.

[0113] Additionally, according to one embodiment, the DDA may be characterized in that the first and second transistors are connected to opposite ends of the first and second compensation current ports to a third node, and further includes a third transistor between the third node and the ground node.

[0114] Additionally, according to one embodiment, the offset compensation current generation unit may be characterized by further including an M-bit R-string DAC.

[0115] Additionally, according to one embodiment, the offset correction current generation step may be characterized by generating an offset correction current in the DDA based on an input voltage and an output voltage output from the M-bit R-string DAC based on an offset correction signal and an externally input input voltage.

[0116] Additionally, according to one embodiment, the M-bit R-string DAC may be characterized by adjusting a minimum value of an offset compensation voltage for generating an offset compensation current based on an input voltage.

[0117] Additionally, according to one embodiment, the offset voltage polarity unification unit may further include an offset voltage polarity unification step for unifying the polarity of the offset voltage generated in the output buffer to positive or negative.

[0118] In addition, according to one embodiment, the offset correction signal generation step may be characterized by receiving a bit string signal whose size gradually increases until the polarity of the offset voltage is reversed, storing the bit string signal at the moment when the polarity of the offset voltage is reversed as the size of the bit string signal increases as the offset correction signal, and the offset correction current generation step may be characterized by continuously generating an offset correction current based on the stored offset correction signal.

[0119] Additionally, according to one embodiment, the DAC built-in amplifier may be characterized in that it includes a switch for reversing an offset polarity, and the offset polarity reversal switch is controlled by an offset voltage polarity unification unit.

[0120]

[0121] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

[0122] The offset correction device and method of the present invention can generate an offset correction signal based on a bit string signal input from an external source, and generate an offset compensation current based on the offset correction to compensate for an offset voltage, and thus has high industrial applicability.

Claims

1. Regarding an offset compensation device for compensating the offset voltage generated in the output buffer. A DAC embedded amp including the above output buffer; An offset correction signal generation unit that receives a bit string signal from an external source and generates an offset correction signal based on the bit string signal; and An offset compensation current generation unit including a DDA (Differential Difference amp) that generates an offset compensation current that compensates for the offset voltage based on the offset compensation signal; Offset compensation device.

2. In paragraph 1, The above DAC built-in amplifier is, An N-bit DAC embedded input stage, comprising a first node and a second node connected to the N-bit DAC embedded input stage, The above DDA is, It is characterized in that it is arranged in a parallel form with the N-bit DAC built-in input stage through a first compensation current port connected to the first node and a second compensation current port connected to the second node. Offset compensation device.

3. In paragraph 2, The above DDA is, A first transistor connected to the first correction current port and a second transistor connected to the second correction current port, characterized in that the first transistor and the second transistor are connected in parallel. Offset compensation device.

4. In paragraph 3, The above DDA is, The first and second transistors are characterized in that the opposite terminals of the first and second compensation current ports are connected to a third node, and a third transistor is further included between the third node and the ground node. Offset compensation device.

5. In paragraph 3, The above offset compensation current generation unit is, Featuring an M-bit R-string DAC Offset compensation device.

6. In paragraph 5, The above offset compensation current generation unit is, The offset correction signal and the input voltage input from the outside are used as the basis for generating the offset correction current in the DDA based on the output voltage output from the M-bit R-string DAC and the input voltage. Offset compensation device.

7. In paragraph 6, The above M-bit R-string DAC, It is characterized by controlling the minimum value of the offset compensation voltage for generating the offset compensation current based on the input voltage. Offset compensation device.

8. In paragraph 1, An offset voltage polarity unification unit further comprising: a polarity unification unit that unifies the polarity of the offset voltage generated in the output buffer to positive or negative; Offset compensation device.

9. In paragraph 8, The above offset compensation signal generation unit, The bit string signal whose size gradually increases until the polarity of the offset voltage is reversed is received, and the bit string signal at the moment when the polarity of the offset voltage is reversed as the size of the bit string signal increases is stored as the offset correction signal. The above offset compensation current generation unit is, Characterized in that the offset correction current is continuously generated based on the stored offset correction signal. Offset compensation device.

10. In paragraph 8, The above DAC built-in amplifier is, A switch for reversing the offset polarity, characterized in that the offset polarity reversing switch is controlled by the offset voltage polarity unification unit. Offset compensation device.

11. About an offset compensation method for compensating the offset voltage generated in the output buffer. A step of providing a DAC embedded amp including the above output buffer; An offset correction signal generation step for receiving a bit string signal from an external source and generating an offset correction signal based on the bit string signal in an offset correction signal generation unit; and In an offset compensation current generation unit including a DDA (Differential Difference amp), an offset compensation current generation step for generating an offset compensation current that compensates for the offset voltage based on the offset compensation signal; How to compensate for offset.

12. In paragraph 11, The above DAC built-in amplifier is, An N-bit DAC embedded input stage, comprising a first node and a second node connected to the N-bit DAC embedded input stage, The above DDA is, It is characterized in that it is arranged in a parallel form with the N-bit DAC built-in input stage through a first compensation current port connected to the first node and a second compensation current port connected to the second node. How to compensate for offset.

13. In paragraph 12, The above DDA is, A first transistor connected to the first correction current port and a second transistor connected to the second correction current port, characterized in that the first transistor and the second transistor are connected in parallel. How to compensate for offset.

14. In paragraph 13, The above DDA is, The first and second transistors are characterized in that the opposite terminals of the first and second compensation current ports are connected to a third node, and a third transistor is further included between the third node and the ground node. How to compensate for offset.

15. In paragraph 13, The above offset compensation current generation unit is, Featuring an M-bit R-string DAC How to compensate for offset.

16. In paragraph 15, The above offset compensation current generation step is: The offset correction signal and the input voltage input from the outside are used as the basis for generating the offset correction current in the DDA based on the output voltage output from the M-bit R-string DAC and the input voltage. How to compensate for offset.

17. In paragraph 16, The above M-bit R-string DAC, It is characterized by controlling the minimum value of the offset compensation voltage for generating the offset compensation current based on the input voltage. How to compensate for offset.

18. In paragraph 11, In the offset voltage polarity unification unit, an offset voltage polarity unification step for unifying the polarity of the offset voltage generated in the output buffer to positive or negative is further included; How to compensate for offset.

19. In Article 18, The above offset compensation signal generation step is: The bit string signal whose size gradually increases until the polarity of the offset voltage is reversed is received, and the bit string signal at the moment when the polarity of the offset voltage is reversed as the size of the bit string signal increases is stored as the offset correction signal. The above offset compensation current generation step is: Characterized in that the offset correction current is continuously generated based on the stored offset correction signal. How to compensate for offset.

20. In paragraph 18, The above DAC built-in amplifier is, A switch for reversing the offset polarity, characterized in that the offset polarity reversing switch is controlled by the offset voltage polarity unification unit. How to compensate for offset.

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