Superconducting quantum qubit device and manufacturing method therefor

Abstract

The technical subject of the present invention relates to a manufacturing method for a superconducting quantum qubit device and a superconducting quantum qubit device manufactured thereby, the method comprising the steps of: forming a superconducting qubit layer on a first substrate; forming an interconnector layer on a second substrate; forming an oxide film on a silicon substrate and a via pattern; forming a via hole in the silicon substrate, and removing the oxide film, and an insulating film on the interconnector layer, which is exposed through the via hole; forming an interposer layer; and turning the superconducting qubit layer upside down and bonding the superconducting qubit layer to the interposer layer.

Description

Superconducting quantum qubit device and its manufacturing method

[0001] The present invention relates to a quantum qubit device and a method for manufacturing the same, and more particularly, to a superconducting quantum qubit structure, and more particularly, to a three-dimensional superconducting quantum qubit device and a method for manufacturing the same for implementing a quantum computer having a commercial level of integration.

[0002] For a quantum computer to achieve quantum supremacy—the ability to perform calculations impossible for a classical von Neumann computer—at a practical level, it must integrate at least hundreds to thousands of qubits. Indeed, some companies have presented roadmaps to achieve 1,121 qubits by 2023, with long-term plans for a million-qubit Quantum Processing Unit (QPU).

[0003] In the case of the superconducting qubit, which is currently the most technologically advanced, an integration density of more than 100 has been reported, but in the case of the superconducting qubit, the size of the qubit, that is, the footprint, is hundreds of microns x hundreds of microns, which is incomparably larger than that of a typical semiconductor device.

[0004] In addition, when controlling qubits to perform computational tasks through quantum logic gates or reading out the results (readout), microwaves at the level of 3 to 10 GHz are used. The length of the components required, which are single-planar waveguides (CPWs) and resonators, is several millimeters or larger. For example, since the wavelength of a typical 5 GHz frequency is about 60 mm in free space, even if the resonator is designed to be λ / 2 or λ / 4, the size of several millimeters or larger cannot be avoided.

[0005] In addition, the signals input / output to the qubit are transmitted to the qubit through the resonator via the bond pad configured at the perimeter of the chip. However, since the resonator is very large compared to the qubit, as the number of qubits increases, there is also the problem that it becomes difficult to connect the data bus to the qubits placed inside the chip.

[0006] In particular, as the number of qubits increases, not only the lines controlling the qubits but also the interconnections between qubits are required to exploit entanglement, which drastically reduces the structural degrees of freedom that enable this. It goes without saying that superior quantum computer performance requires as many interconnections as possible between qubits.

[0007] In addition, since the signals transmitted to the qubits are microwaves, as the data bus becomes denser and more complex, not only will crosstalk occur between signals, but it will also have a negative impact on the coherence time of the qubits.

[0008] In addition, the dielectric substrate contains electromagnetic waves of the fundamental mode with the frequency of the following equation. However, if the x, y values, or the size of the chip, become too large, the frequency of the fundamental mode overlaps with the frequency band (3-8 GHz) that controls the qubit, which becomes a factor that practically limits the size of the chip.

[0009]

[0010] c: Speed ​​of light in free space

[0011] ε r : Dielectric constant

[0012] x, y: size of the chip

[0013] Due to the problems mentioned above, it is impossible to implement a QPU with hundreds to thousands of qubits or more using a planar architecture in which all components are placed on the same surface, and therefore, the demand for a 3D architecture to overcome this is increasing.

[0014] One approach to achieving this is a superconducting Through Silicon Via (TSV) architecture. This architecture implements a qubit layer, a TSV interposer and resonator layer, and a wiring layer on each substrate, each connected using an indium bumper. Electrical signals between layers are transmitted via the TSV interposer.

[0015] Fig. 1 illustrates a three-dimensional superconducting quantum qubit and circuit element using an interposer layer (30) manufactured using a conventional TSV technology. First, a superconducting qubit layer (10) equipped with a superconducting qubit and a superconducting wiring (connection circuit) (12), an interconnector layer (20) equipped with one or more layers of superconducting wiring and an insulating film for DC and RF routing circuits (22) are connected to each other through a superconducting TSV interposer layer (30) and integrated in three dimensions. The superconducting TSV interposer layer (30) may be equipped with a connection line (circuit) (32) such as a resonator for applying a microwave signal to the qubit to control the qubit, i.e., perform quantum logic operations, and a wiring for readout.

[0016] Here, the connection between the qubit and the resonator uses capacitive coupling, so direct contact is not required, and the mechanical and electrical connection between the qubit plan and the resonator plan is bonded using an indium bumper, which is a superconducting metal. The superconducting TSV interposer layer (30) and the interconnector layer (20) are also mechanically and electrically connected by bonding using the indium bumper (40). In other words, two bondings of the indium bumper (40) are required.

[0017] Meanwhile, in the field of Si CMOS technology, TSV technology is a technology developed for 3D integration, and is usually manufactured in the following steps.

[0018] - Via formation: Reactive ion etching or laser drilling

[0019] - Dielectric Deposition: Forming a SiO2 or Si3N4 liner that acts as a diffusion barrier between Cu and Si by thermal deposition or PECVD.

[0020] - Adhesion & Seed Layer Deposition: Ti / Cu deposition using PVD method

[0021] - Copper electroplating: Filling vias with copper and then heat treatment to relieve stress.

[0022] - Removal of overburden Cu by CMP

[0023] - TSV Exposure (Reveal): Via exposure by grinding / polishing or wet etching

[0024] However, it is difficult to apply the TSV technology commonly used in CMOS for the following reasons.

[0025] - Dielectric liners such as SiO2 and Si3N4 cause dielectric loss in microwaves, which reduces coherence time.

[0026] Superconducting metals must be used instead of copper. Electroplating is difficult when using aluminum, and the PVD process for producing high-quality superconducting aluminum is too slow and stressful for via filling. Furthermore, because the material is used at extremely low temperatures, the difference in thermal expansion coefficient between the metal and silicon is also important.

[0027] - Residues from the CMP process contaminate the insulating Si substrate or act as dopants, reducing the coherence time of the qubit.

[0028] Therefore, in order to apply TSV technology to superconducting quantum QPU structures, development of a new TSV technology compatible with QPU is required.

[0029] In addition, there is a need to develop an interposer process that does not degrade the characteristics of the qubit, and there is a disadvantage in that two indium bumpers are used to mechanically and electrically connect the three layers, but as the density of TSV lines increases, alignment between them becomes difficult and the process becomes complicated.

[0030] The present invention is intended to solve the above problem, and the purpose of the present invention is to provide a superconducting quantum qubit device having a three-dimensional structure in which an interposer having a via pattern is first bonded to a DC and RF routing interconnector layer using wafer bonding, then an interposer layer is formed, and these are connected through indium bumper bonding.

[0031] In order to achieve the above object, the present invention comprises the steps of forming a superconducting qubit layer by implementing a superconducting qubit and a superconducting wiring on a first substrate, forming an interconnector layer including DC and RF routing circuits by alternately and repeatedly implementing superconducting wiring and an insulating film on a second substrate, forming a mask pattern layer on a silicon substrate, using the mask pattern layer as an etching mask to form a via pattern on the silicon substrate, removing the mask pattern layer, and forming an oxide film on the silicon substrate and the via pattern, bonding the silicon substrate upside down on the interconnector layer, polishing the back surface of the silicon substrate to expose the via pattern, forming a via hole in the silicon substrate, and removing the oxide film and the insulating film on the interconnector layer exposed to the via hole, depositing a superconducting metal layer on the silicon substrate and the via hole on a total surface (Total Surface) so that the superconducting metal layer and the DC and RF routing circuit are in contact, and forming an interconnector layer on the back surface of the silicon substrate. The technical gist of the present invention is a method for manufacturing a superconducting quantum qubit device, including the steps of forming an interposer layer by patterning a superconducting metal layer to form resonators and connecting lines, and the step of turning the superconducting qubit layer upside down and bonding it to the interposer layer using an indium bumper.

[0032] In addition, the present invention comprises a first substrate, a superconducting qubit layer including a superconducting qubit and a superconducting wiring formed on the first substrate, a second substrate, an interconnector layer including DC and RF routing circuits by alternately and repeatedly forming superconducting wiring and an insulating film on the second substrate, a silicon substrate having a via pattern formed thereon is flipped over and bonded to the interconnector layer, the via pattern is exposed to form a via hole, a superconducting metal layer is deposited on the via hole and the entire surface of the silicon substrate, and a silicon interposer layer including a resonator and a connection line formed by patterning the superconducting metal layer so as to be in contact with the superconducting metal layer and the DC and RF routing circuit, wherein the superconducting qubit layer and the interposer layer are bonded to the interposer layer using an indium bumper, and the superconducting qubit layer and the interposer layer are characterized in that the superconducting qubit layer and the interposer layer are bonded to the interposer layer using an indium bumper.

[0033] Additionally, it is preferable that the interconnector layer and the interposer layer are bonded with an oxide film to an oxide film.

[0034] In addition, it is preferable that the first substrate and the second substrate are formed of one of high-resistance Si, sapphire, and alumina (Al2O3).

[0035] Additionally, it is preferable that the superconducting metal is at least one of Al, TiN, Nb, Ta, and V.

[0036] In addition, the insulating film included in the interconnector layer is preferably an oxide film or a nitride film, and the top insulating film is preferably formed of a silicon oxide film.

[0037] Additionally, it is preferable that the depth of the above via pattern be 1 to 300 μm or 50 to 200 μm.

[0038] In addition, it is preferable that the qubit is one of a charge qubit, a flux qubit, and a phase qubit including at least one Josephson element.

[0039] Additionally, it is preferable that the resonator formed in the silicon interposer layer has a length of one of 1 / 4, 1 / 2, and an integer multiple thereof of the wavelength corresponding to the microwave frequency used.

[0040] In addition, it is preferable that the superconducting qubit and resonator are capacitively coupled without direct contact of the superconducting metal.

[0041] Additionally, it is preferable that the superconducting qubit layer and the silicon interposer layer are electrically and mechanically connected by one or more indium bumpers.

[0042] In addition, it is preferable that the oxide film formed on the silicon substrate is formed by depositing an oxide film on the silicon substrate or performing heat treatment in an oxygen atmosphere.

[0043] In the present invention, an interposer having a via pattern is first bonded to a DC and RF routing interconnector layer using wafer bonding, a via hole is exposed, and an interposer layer having a resonator and a connection line formed by deposition and patterning of a superconducting metal layer is formed, and a three-dimensional structure of a superconducting quantum qubit device is provided, which connects the interposer layer through indium bumper bonding.

[0044] The typical TSV interposer manufacturing process involves creating a via hole that completely penetrates the substrate, filling it with metal, and then removing a portion of the substrate on the opposite side of the via hole through a CMP process so that the via hole penetrates the substrate. At this time, the substrate is temporarily bonded to another substrate for handling purposes and the process is then performed.

[0045] On the other hand, the technology proposed in the present invention does not require a handling substrate by forming a via hole that does not completely penetrate the substrate, then bonding it to the DC and RF routing interconnector layers using wafer bonding, and then etching the remaining insulating film and depositing the superconducting metal layer. The technology eliminates the use of indium bumpers, and the process is simple and enables precise alignment by electrically connecting directly to the superconducting metal formed on the DC and RF routing interconnector layers.

[0046] Figure 1 - A diagram showing a three-dimensional superconducting quantum qubit and circuit element using an interposer manufactured using conventional TSV technology.

[0047] Figure 2 - Cross-sectional schematic diagram of a superconducting qubit layer according to an embodiment of the present invention.

[0048] FIG. 3 - Cross-sectional schematic diagram of a DC and RF routing interconnect layer according to an embodiment of the present invention.

[0049] Figure 4 - A schematic diagram of a process for forming a via pattern and an oxide film on a silicon substrate to utilize a wafer bonding technique according to an embodiment of the present invention.

[0050] Figure 5 - A schematic diagram of a process for forming a silicon interposer layer by bonding a silicon substrate manufactured using a wafer bonding technique according to an embodiment of the present invention to an interconnector layer and then forming a superconducting resonator and a connecting line.

[0051] FIG. 6 - A schematic diagram of a three-dimensional superconducting quantum qubit device implemented by bonding a silicon interposer layer and a superconducting qubit layer by an indium bumper according to an embodiment of the present invention.

[0052] In the present invention, an interposer having a via pattern is first bonded to a DC and RF routing interconnector layer using wafer bonding, a via hole is exposed, and an interposer layer having a resonator and a connection line formed by deposition and patterning of a superconducting metal layer is formed, and a three-dimensional structure of a superconducting quantum qubit device is provided, which connects the interposer layer through indium bumper bonding.

[0053] The typical TSV interposer manufacturing process involves creating a via hole that completely penetrates the substrate, filling it with metal, and then removing a portion of the substrate on the opposite side of the via hole through a CMP process so that the via hole penetrates the substrate. At this time, the substrate is temporarily bonded to another substrate for handling purposes and the process is then performed.

[0054] On the other hand, the technology proposed in the present invention does not require a handling substrate by forming a via hole that does not completely penetrate the substrate, then bonding it to the DC and RF routing interconnector layers using wafer bonding, and then etching the remaining insulating film and depositing the superconducting metal layer. The technology eliminates the use of indium bumpers, and the process is simple and enables precise alignment by electrically connecting directly to the superconducting metal formed on the DC and RF routing interconnector layers.

[0055] Hereinafter, an embodiment of the present invention will be described with reference to the attached drawings.

[0056] FIG. 2 is a cross-sectional schematic diagram of a superconducting qubit layer according to an embodiment of the present invention, FIG. 3 is a cross-sectional schematic diagram of a DC and RF routing interconnector layer according to an embodiment of the present invention, FIG. 4 is a process schematic diagram of forming a via pattern and an oxide film on a silicon substrate to use a wafer bonding technique according to an embodiment of the present invention, FIG. 5 is a process schematic diagram of forming a silicon interposer layer by bonding a silicon substrate manufactured using a wafer bonding technique according to an embodiment of the present invention to an interconnector layer and then forming a superconducting resonator and a connection line, and FIG. 6 is a schematic diagram of a superconducting quantum qubit device having a three-dimensional structure implemented by bonding a silicon interposer layer and a superconducting qubit layer by an indium bumper according to an embodiment of the present invention.

[0057] A method for manufacturing a superconducting quantum qubit device according to an embodiment of the present invention comprises the steps of forming a superconducting qubit layer (100) by implementing a superconducting qubit and a superconducting wiring (140) on a first substrate (120), forming an interconnector layer (200) including DC and RF routing circuits by alternately and repeatedly implementing a superconducting wiring (240) and an insulating film (260) on a second substrate (220), forming a mask pattern layer (340) on a silicon substrate (300), forming a via pattern (360) on the silicon substrate (300) using the mask pattern layer (340) as an etching mask, and then removing the mask pattern layer (340) and forming an oxide film (380) on the silicon substrate (300) and the via pattern (360), and bonding the silicon substrate (300) upside down on the interconnector layer (200), and bonding the silicon substrate (300) on the silicon substrate (300) The method is characterized by comprising the steps of: polishing the back surface of the substrate (300) to expose the via pattern (360) to form a via hole (420) in the silicon substrate (300), removing the oxide film and the insulating film (260) on the interconnector layer (200) exposed to the via hole (420); depositing a superconducting metal layer (440) on the entire surface (Total Surface) of the silicon substrate (300) and the via hole (420) so that the superconducting metal layer (440) and the DC and RF routing circuits are in contact; patterning the superconducting metal layer (440) formed on the back surface of the silicon substrate (300) to form a resonator and a connection line (460) to form an interposer layer (400); and turning the superconducting qubit layer (100) upside down and bonding it to the interposer layer (400) using an indium bumper (500). Do it.

[0058] First, as shown in Fig. 2, a superconducting qubit and a superconducting wiring (140) are implemented on a first substrate (120) to form a superconducting qubit layer (100).

[0059] That is, a superconducting metal layer (440) for forming a superconducting qubit and a superconducting wiring (140) required therefor is deposited on a first substrate (120), and a superconducting qubit layer (100) is formed by patterning the same.

[0060] In one embodiment of the present invention, the superconducting qubit may include, but is not limited to, one or more Josephson elements and a capacitance, an inductor, or a superconducting loop.

[0061] Additionally, the superconducting qubit may be any one of a charge qubit, a flux qubit, and a phase qubit including at least one Josephson element.

[0062] The above required superconducting wiring may differ depending on the type of superconducting qubit, i.e., the operating method, but since it is unrelated to the spirit of the present invention, a detailed description thereof will not be provided.

[0063] And, as shown in Fig. 3, superconducting wiring (240) and an insulating film (260) are alternately and repeatedly implemented on a second substrate (220) to form an interconnector layer (200) including DC and RF routing circuits.

[0064] A superconducting metal layer is formed on the second substrate (220), a superconducting wiring (240) is formed by patterning the superconducting metal layer, an insulating film (260) is deposited on top of the superconducting metal layer, and then the superconducting wiring (240) is flattened by a CMP process or the like. The process of forming the superconducting metal layer and patterning the superconducting metal layer and depositing the insulating film (260) is repeated as many times as necessary to complete an interconnector layer (200) including a multilayer DC and RF routing circuit.

[0065] Superconducting wiring (240) uses a superconducting metal, and a metal with a superconducting critical temperature higher than the operating temperature of superconducting qubits, which is tens of mK, can be used. Specifically, various metals such as Al, TiN, Nb, Ta, and V can be used. However, when using Al, it should be taken into account that the thermal budget of the subsequent process is limited to approximately 400°C. Considering this, a metal with a melting point higher than Al is preferable.

[0066] In addition, the insulating film (260) may use various oxide-based, nitride-based, etc. materials, and considering that oxide-to-oxide film bonding (SiO2-SiO2) is easy during bonding with the subsequent process, the interconnector layer (200), an oxide film (SiO2) may be used.

[0067] The first substrate (120) and the second substrate (220) used in manufacturing the superconducting qubit layer (100) and the DC and RF routing interconnector layer (200) may be of the same or different types of substrates, and are not particularly limited when composed of a material with a low dielectric loss, but may typically be formed of any one of high-resistance Si, sapphire, and alumina (Al2O3).

[0068] And, as shown in FIG. 4, a mask pattern layer (340) is formed on a silicon substrate (300), and a via pattern (360) is formed on the silicon substrate (300) using this as an etching mask, and then the mask pattern layer (340) is removed, and an oxide film (380) is formed on the silicon substrate (300) and the via pattern (360).

[0069] A mask layer (320) is formed on a silicon substrate (300), and patterning thereof is performed to form a mask pattern layer (340). Using the mask pattern layer (340) as an etching mask, a via pattern (360) is formed on the silicon substrate (300), and then the mask layer (320) is removed, and an oxide film (380) is formed on the silicon substrate (300) and the via pattern (360).

[0070] First, a mask layer (320) is formed on a high-resistance silicon substrate (300), and patterning is performed to form a mask pattern layer (340). Using the mask pattern layer (340) as an etching mask, the silicon substrate (300) is etched to a required depth using a dry etching process. The depth of the via pattern (360) can be set from 1 to 300 μm, but is typically preferably in the range of 50 to 200 μm.

[0071] Furthermore, this process describes a conventional technique and may be performed using different processes. For example, the etched via pattern (360) may be formed using laser drilling.

[0072] Then, the mask pattern layer (340) is removed, and an oxide film (380) is formed on the silicon substrate (300) and the via pattern (360). At this time, the method of forming the oxide film (380) is not limited, but considering the convenience of the process and the quality of the oxide film, a method of Si oxidation by heat treatment is preferable.

[0073] At this time, the method of forming an oxide film may be to form a natural silicon oxide film by performing heat treatment in an oxygen atmosphere, but is not limited thereto. However, considering the convenience of the process and the quality of the oxide film, an oxidation method by heat treatment is preferable.

[0074] And, as shown in FIG. 5, the silicon substrate (300) is bonded upside down on the interconnector layer (200). At this time, the bonding uses a conventional wafer bonding technique in which the surfaces of the two layers are cleaned, brought into contact, and then heat-treated for bonding. In particular, bonding is very easy when the surfaces of the two layers are oxides. Therefore, it is preferable to form an oxide film on the silicon substrate (300), and to form an insulating film (260) formed on the interconnector layer (200), especially, an insulating film of the uppermost layer, as an oxide film. In one embodiment of the present invention, a silicon oxide film (SiO2) is formed.

[0075] Then, the back surface (upper surface in the drawing) of the silicon substrate (300) is polished to expose the via pattern (360) to form a via hole (420) on the silicon substrate (300), and the oxide film and the insulating film (260) on the interconnector layer (200) exposed to the via hole (420) are removed.

[0076] That is, after bonding, the back surface of the silicon substrate (300) is partially removed through a CMP process to expose the via pattern (360) and form a via hole (420). Thereafter, the oxide film is removed, and at this time, not only the oxide film on the wall surface of the via hole (420) but also the oxide film (insulating film (260)) covering the superconducting wiring (240) to be electrically connected to the via hole (420) in the DC and RF routing interconnector layer (200) is removed.

[0077] Then, a superconducting metal layer (440) is deposited on the entire surface of the silicon substrate (300) and via hole (420), so that the superconducting metal layer (440) and the DC and RF routing circuits are in contact, and the superconducting metal layer (440) formed on the back surface of the silicon substrate (300) is patterned to form a resonator and a connecting line (460), thereby forming an interposer layer (400).

[0078] The types of superconducting metals used at this time include, but are not limited to, Al, TiN, Nb, Ta, and V. However, TiN is generally preferred when considering the step coverage of deposition, etc.

[0079] Meanwhile, when fabricating superconducting qubits in three dimensions, the reason for using an interposer instead of directly connecting, for example, the DC and RF routing interconnector layers to the superconducting qubit layer is that the characteristics of the superconducting qubit are seriously degraded when directly connected.

[0080] That is, the interconnector layer manufacturing process is similar to the BEOL process used in conventional CMOS technology as described above, in which a metal wiring is formed, an insulating film, usually an oxide, is deposited to insulate, and then a metal wiring is formed on top of it again, repeating the process to complete a multi-layer wiring. However, if this surface is directly connected to the superconducting qubit layer through an indium bumper and brought into close proximity, dielectric loss occurs, which seriously damages the characteristics of the qubit, and therefore an interposer is used to block this.

[0081] And, by turning the superconducting qubit layer (100) upside down and bonding it to the interposer layer (400) using an indium bumper (500), a superconducting quantum qubit device is completed, as shown in FIG. 6.

[0082] The superconducting qubit layer (100) is electrically and mechanically connected to the silicon interposer layer (400) by one or more indium bumpers (500).

[0083] At this time, since an indium bumper (500) was used, the superconducting qubit (140) and the resonator have a gap of about several ㎛, and the connection between the two components is made through capacitive coupling rather than direct contact of the superconducting metal.

[0084] In addition, it is preferable that the resonator formed in the silicon interposer layer (400) has a length of one of 1 / 4, 1 / 2, and an integer multiple thereof of the wavelength corresponding to the microwave frequency used. The present invention can provide a compact superconducting quantum qubit device even if the resonator is designed to be λ / 4, λ / 2, or an integer multiple thereof.

[0085] Meanwhile, a superconducting quantum qubit device manufactured according to an embodiment of the present invention comprises a first substrate (120), a superconducting qubit layer (100) including a superconducting qubit and a superconducting wiring (140) formed on the first substrate (120), a second substrate (220), and superconducting wiring (240) and an insulating film (260) alternately and repeatedly formed on the second substrate (220), an interconnector layer (200) including DC and RF routing circuits, and a silicon substrate (300) on which a via pattern (360) is formed, and then bonded to the interconnector layer (200) by exposing the via pattern (360) to form a via hole (420), and a superconducting metal layer (440) is deposited on the entire surface of the via hole (420) and the silicon substrate (300), so that the superconducting metal layer (440) and the DC and It is characterized in that it includes a silicon interposer layer (400) that is in contact with an RF routing circuit and includes a resonator and a connection line (460) formed by patterning the superconducting metal layer (440), and the superconducting qubit layer (100) and the interposer layer (400) are bonded to the interposer layer (400) using an indium bumper (500).

[0086] Accordingly, the superconducting quantum qubit device according to the embodiment of the present invention forms a superconducting qubit and a superconducting wiring (140) for controlling the superconducting qubit on a superconducting qubit layer (100) to perform an operation such as a quantum logic gate, and readout is performed through a resonator (460) provided on the upper side of an interposer layer (400), and a DC signal and a microwave signal for controlling the same are transmitted through a DC and RF routing interconnector layer (200). In addition, a resonator bus for entanglement between qubits may be provided on an interposer layer (400) in which a via hole (420) is formed by exposing a via pattern (360) by wafer bonding.

[0087] In addition, the reason why the present invention uses an interposer instead of directly connecting, for example, the DC and RF routing interconnector layer (200) to the superconducting qubit layer (100) when manufacturing a superconducting qubit in three dimensions is that the characteristics of the superconducting qubit are seriously degraded when directly connected. The process of manufacturing the interconnector layer (200) is to alternately and repeatedly implement superconducting wiring (240) and an insulating film (260) on a second substrate (220) to complete a multi-layer wiring. However, if this surface is directly connected to the superconducting qubit layer (100) and the indium bumper (500) and brought into close proximity, dielectric loss occurs, which seriously deteriorates the characteristics of the qubit, and therefore, this is blocked using an interposer.

[0088] In order to overcome the problem of dielectric loss mentioned above, unlike the prior art, in the present invention, a conventional TSV interposer manufacturing process creates a via hole that completely penetrates a substrate, fills it with metal, and then removes a portion of the substrate opposite the via hole through a CMP process so that the via hole penetrates the substrate. At this time, in order to handle the substrate, the process is performed by temporarily bonding it to another substrate.

[0089] According to an embodiment of the present invention, instead of a process that penetrates tens to hundreds of tens of micrometers, a process that penetrates silicon with a thickness of several to several tens of micrometers is used, so that problems in the existing TSV process, such as the problem caused by the difference in thermal expansion coefficient between the superconducting metal penetrating the via and the substrate, and the problem of reduced coherence time of the qubit due to CMP residue, can all be overcome, so there is no need to develop a complex process to bypass the problems of the existing TSV process.

[0090] In addition, according to an embodiment of the present invention, after oxide-to-oxide bonding a silicon substrate on which a via pattern is formed and a DC and RF routing interconnector layer, a superconducting metal layer is deposited by exposing a via hole, and a resonator and a necessary superconducting connection line are provided on the interposer layer, and at this time, alignment with the circuit of the interconnector layer is performed, so that the alignment error problem using an indium bumper as in the prior art is also solved.

[0091] That is, the present invention provides a method for implementing three-dimensional integration of qubits, which is unavoidable for implementing a quantum computer with a commercial level of integration, and minimizes the reduction in the coherence time of qubits while providing ease of process compared to the method of using a conventional TSV interposer.

[0092] In addition, the indium bumper process used twice in existing technology is reduced to one process, and the complex wiring connection between the interposer layer and the interconnector is replaced with a conventional patterning process rather than the indium bumper process, which has the advantage of enabling precise connection.

Claims

1. A step of forming a superconducting qubit layer by implementing a superconducting qubit and superconducting wiring on a first substrate; A step of forming an interconnector layer including DC and RF routing circuits by alternately and repeatedly implementing superconducting wiring and an insulating film on a second substrate; A step of forming a mask pattern layer on a silicon substrate, forming a via pattern on the silicon substrate using the mask pattern layer as an etching mask, removing the mask pattern layer, and forming an oxide film on the silicon substrate and the via pattern; A step of bonding the silicon substrate upside down on the interconnector layer, polishing the back surface of the silicon substrate to expose the via pattern, forming a via hole in the silicon substrate, and removing the oxide film and the insulating film on the interconnector layer exposed to the via hole; A step of depositing a superconducting metal layer on the entire surface (Total Surface) of the silicon substrate and via holes so that the superconducting metal layer and the DC and RF routing circuits come into contact, and patterning the superconducting metal layer formed on the back surface of the silicon substrate to form a resonator and a connecting line, thereby forming an interposer layer; A method for manufacturing a superconducting quantum qubit device, comprising: a step of flipping the superconducting qubit layer upside down and bonding it to the interposer layer using an indium bumper.

2. In the first paragraph, the interconnector layer and the interposer layer, A method for manufacturing a superconducting quantum qubit device characterized by oxide-to-oxide film bonding.

3. In paragraph 1, the first substrate and the second substrate, A method for manufacturing a superconducting quantum qubit device characterized by being formed of one of high-resistance Si, sapphire, and alumina (Al2O3).

4. In paragraph 1, the superconducting metal is, A method for manufacturing a superconducting quantum qubit device characterized by at least one of Al, TiN, Nb, Ta, and V.

5. In the first paragraph, the insulating film included in the interconnector layer, An oxide film or a nitride film is used, A method for manufacturing a superconducting quantum qubit device, characterized in that the top insulating film is formed of a silicon oxide film.

6. A method for manufacturing a superconducting quantum qubit device, characterized in that in claim 1, the depth of the via pattern is 1 to 300 ㎛, or 50 to 200 ㎛.

7. In the first paragraph, the superconducting qubit, A three-dimensional superconducting quantum qubit device characterized by being any one of a charge qubit, a flux qubit, and a phase qubit, each of which includes at least one Josephson element.

8. In the first paragraph, the resonator formed in the silicon interposer layer is A method for manufacturing a superconducting quantum qubit device, characterized in that the device has a length of one quarter, one half, or an integer multiple thereof of a wavelength corresponding to the microwave frequency used.

9. In the first paragraph, the superconducting qubit and the resonator, A method for manufacturing a superconducting quantum qubit device characterized in that the superconducting metals do not come into direct contact and are capacitively coupled.

10. In paragraph 1, The above superconducting qubit layer and the silicon interposer layer, A method for manufacturing a superconducting quantum qubit device characterized by being electrically and mechanically connected by one or more indium bumpers.

11. In the first paragraph, the oxide film formed on the silicon substrate is A method for manufacturing a superconducting quantum qubit device, characterized in that the device is formed by depositing an oxide film on the silicon substrate or performing heat treatment in an oxygen atmosphere.

12. A superconducting qubit layer including a first substrate and a superconducting qubit and a superconducting wiring formed on the first substrate; A second substrate, and an interconnector layer including DC and RF routing circuits by alternately and repeatedly forming superconducting wiring and an insulating film on the second substrate; A silicon interposer layer comprising: a silicon substrate having a via pattern formed thereon is flipped over and bonded to an interconnector layer; the via pattern is exposed to form a via hole; a superconducting metal layer is deposited on the entire surface of the silicon substrate and the via hole; and a resonator and a connection line formed by patterning the superconducting metal layer are formed so as to be in contact with the superconducting metal layer and the DC and RF routing circuits. A superconducting quantum qubit device, characterized in that the superconducting qubit layer and the interposer layer are bonded to the interposer layer using an indium bumper.

13. In the 12th paragraph, the interconnector layer and the interposer layer, A superconducting quantum qubit device characterized by oxide-to-oxide film bonding.

14. In the 12th paragraph, the first substrate and the second substrate, A superconducting quantum qubit device characterized by being formed from one of high-resistivity Si, sapphire, and alumina (Al2O3).

15. In paragraph 12, the superconducting metal is, A superconducting quantum qubit device characterized by at least one of Al, TiN, Nb, Ta, and V.

16. In the 12th paragraph, the insulating film included in the interconnector layer is An oxide film or a nitride film is used, A superconducting quantum qubit device characterized in that the top insulating film is formed of a silicon oxide film.

17. A superconducting quantum qubit device according to claim 12, characterized in that the depth of the via pattern is 1 to 300 μm, or 50 to 200 μm.

18. In the 12th paragraph, a three-dimensional superconducting quantum qubit element characterized in that the superconducting qubit is any one of a charge qubit, a flux qubit, and a phase qubit including at least one Josephson element.

19. In the 12th paragraph, the resonator formed in the silicon interposer layer, A superconducting quantum qubit device characterized by having a length equal to one quarter, one half, or an integer multiple thereof of a wavelength corresponding to the microwave frequency used.

20. In the 12th paragraph, the superconducting qubit and the resonator, A superconducting quantum qubit device characterized by capacitive coupling without direct contact between superconducting metals.

21. In paragraph 12, The above superconducting qubit layer and the silicon interposer layer, A superconducting quantum qubit device characterized by being electrically and mechanically connected by one or more indium bumpers.

22. In the 12th paragraph, the oxide film formed on the silicon substrate is A superconducting quantum qubit device characterized by being formed by depositing an oxide film on the silicon substrate or performing heat treatment in an oxygen atmosphere.

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