Display device

Abstract

This display device includes a display panel including a pixel, a data driver which provides a data voltage to the pixel, a gate driver which provides a gate signal to the pixel, and a controller which controls the data driver and the gate driver. The pixel includes a first sub-pixel including a first light-emitting element and a second sub-pixel including a plurality of second light-emitting elements.

Description

display device

[0001] The present invention relates to a display device.

[0002] As information technology advances, the importance of display devices, which serve as a link between users and information, is growing. In response, the use of display devices such as liquid crystal displays (LCDs), organic light-emitting displays (OLEDs), and inorganic light-emitting displays (ILDs), is increasing.

[0003] One object of the present invention is to provide a display device that displays high brightness.

[0004] In order to achieve one object of the present invention, a display device according to embodiments of the present invention includes a display panel including a pixel, a data driver providing a data voltage to the pixel, a gate driver providing a gate signal to the pixel, and a controller controlling the data driver and the gate driver, wherein the pixel may include a first sub-pixel including a first light-emitting element, and a second sub-pixel including a plurality of second light-emitting elements.

[0005] In one embodiment, each of the plurality of second light-emitting elements may be smaller than the first light-emitting element.

[0006] In one embodiment, the plurality of second light-emitting elements may be electrically connected in parallel.

[0007] In one embodiment, each of the plurality of second light-emitting elements can display the same color as the first light-emitting element.

[0008] In one embodiment, any one of the plurality of second light-emitting elements can display a different color.

[0009] In one embodiment, the first sub-pixel may include a 1-1 sub-pixel displaying a first color, a 1-2 sub-pixel displaying a second color, and a 1-3 sub-pixel displaying a third color, and the plurality of second light-emitting elements may include a 2-1 light-emitting element displaying the first color, a 2-2 light-emitting element displaying the second color, and a 2-3 light-emitting element displaying the third color.

[0010] In one embodiment, the first light-emitting element can be turned on in a first mode, and the plurality of second light-emitting elements can be turned off in the first mode.

[0011] In one embodiment, the first light-emitting element can be turned on in a second mode, and the plurality of second light-emitting elements can be turned on in the second mode.

[0012] In one embodiment, the peak luminance in the second mode may be greater than the peak luminance in the first mode.

[0013] In one embodiment, the display panel is driven in one of a 1-1 mode, a 1-2 mode, and a 2nd mode, and in the 1-1 mode, the light-emitting time of the first light-emitting element is controlled according to the gradation, in the 1-2 mode, the magnitude of the driving current applied to the first light-emitting element is controlled according to the gradation, in the 2nd mode, the light-emitting time of the first light-emitting element and the magnitude of the driving current applied to the first light-emitting element are controlled according to the gradation, and in the 2nd mode, the light-emitting times of the plurality of second light-emitting elements and the magnitude of the driving current applied to the second light-emitting elements can be controlled according to the gradation.

[0014] In one embodiment, the display panel may include sub-pixels including the first sub-pixel and the second sub-pixel, and each of the sub-pixels may include a first sub-pixel circuit that controls the light-emitting time of each light-emitting element of the sub-pixels according to the grayscale, and a second sub-pixel circuit that controls the amount of driving current applied to the light-emitting element according to the grayscale.

[0015] In one embodiment, the first light-emitting element is controlled by the first sub-pixel circuit in the 1-1 mode, is controlled by the second sub-pixel circuit in the 1-2 mode, is controlled by the first sub-pixel circuit and the second sub-pixel circuit in the second mode, and the plurality of second light-emitting elements can be controlled by the first sub-pixel circuit and the second sub-pixel circuit in the second mode.

[0016] In one embodiment, the second sub-pixel can display a white color.

[0017] In one embodiment, the first sub-pixel may include a 1-1 sub-pixel displaying a first color, a 1-2 sub-pixel displaying a second color, and a 1-3 sub-pixel displaying a third color, wherein the 1-1 sub-pixel may include a first photo-conversion pattern, the 1-2 sub-pixel may include a second photo-conversion pattern, the 1-3 sub-pixel may include a third photo-conversion pattern, and the second sub-pixel may include the first to third photo-conversion patterns.

[0018] In one embodiment, the first to third light conversion patterns in the second sub-pixel may overlap.

[0019] In one embodiment, the first sub-pixel may include a 1-1 sub-pixel displaying a first color, a 1-2 sub-pixel displaying a second color, and a 1-3 sub-pixel displaying a third color, wherein the 1-1 sub-pixel includes a first color filter, the 1-2 sub-pixel includes a second color filter, the 1-3 sub-pixel includes a third color filter, and the second sub-pixel may not include the first to third color filters.

[0020] In order to achieve one object of the present invention, a display device according to embodiments of the present invention includes a display panel including a pixel, a data driver providing a data voltage to the pixel, a gate driver providing a gate signal to the pixel, and a controller controlling the data driver and the gate driver, wherein the pixel may include a 1-1 sub-pixel including a plurality of 1-1 light-emitting elements, a 1-2 sub-pixel including a plurality of 1-2 light-emitting elements, a 1-3 sub-pixel including a plurality of 1-3 light-emitting elements, and a 2nd sub-pixel including a 2nd light-emitting element.

[0021] In one embodiment, the plurality of first-first light-emitting elements display a first color, the plurality of first-second light-emitting elements display a second color, the plurality of first-third light-emitting elements display a third color, and the second light-emitting element can display any one of the first to third colors.

[0022] In order to achieve one object of the present invention, a display device according to embodiments of the present invention includes a display panel including a pixel, a data driver providing a data voltage to the pixel, a gate driver providing a gate signal to the pixel, and a controller controlling the data driver and the gate driver, wherein the pixel may include a first sub-pixel including a first light-emitting element including an inorganic light-emitting diode, and a second sub-pixel including a second light-emitting element including an organic light-emitting diode.

[0023] In one embodiment, the second light-emitting element can display a white color.

[0024] A display device according to embodiments of the present invention can display higher brightness by including a second sub-pixel in addition to the existing first sub-pixels.

[0025] However, the effects of the present invention are not limited to the above-described effects, and may be expanded in various ways without departing from the spirit and scope of the present invention.

[0026] Figure 1 is a block diagram showing an embodiment of a display device.

[0027] FIG. 2 is a block diagram showing an example of a first sub-pixel among the sub-pixels of FIG. 1.

[0028] FIG. 3 is a block diagram showing an example of a second sub-pixel among the sub-pixels of FIG. 1.

[0029] Fig. 4 is a plan view showing an embodiment of the display panel of Fig. 1.

[0030] Fig. 5 is a cross-sectional view showing an embodiment of the display panel of Fig. 4.

[0031] FIG. 6 is a cross-sectional view showing another embodiment of the display panel of FIG. 4.

[0032] FIG. 7 is a plan view showing an embodiment of one of the pixels of FIG. 4.

[0033] Fig. 8 is a cross-sectional view taken along line II' of Fig. 7.

[0034] Fig. 9 is a cross-sectional view taken along line II-II' of Fig. 7.

[0035] Fig. 10 is a graph showing an example in which the display panel of the display device of Fig. 1 operates in mode 1-1.

[0036] Fig. 11 is a graph showing an example in which the display panel of the display device of Fig. 1 operates in mode 1-2.

[0037] FIG. 12 is a graph showing an example in which the sub-pixels of the display device of FIG. 1 operate in the first mode.

[0038] Fig. 13 is a graph showing an example in which the display panel of the display device of Fig. 1 operates in the second mode.

[0039] FIG. 14 is a graph showing an example in which the sub-pixels of the display device of FIG. 1 operate in the second mode.

[0040] FIG. 15 is a plan view showing an example of one of the pixels according to embodiments of the present invention.

[0041] FIG. 16 is a plan view showing an example of one of the pixels according to embodiments of the present invention.

[0042] FIG. 17 is a plan view showing an example of one of the pixels according to embodiments of the present invention.

[0043] Figure 18 is a block diagram showing an embodiment of a display system.

[0044] Figures 19 to 22 are perspective views showing application examples of the display system of Figure 18.

[0045] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the portions necessary for understanding the operation of the present invention will be described, and the description of other portions will be omitted so as not to obscure the gist of the present invention. Furthermore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to explain the technical idea of ​​the present invention in sufficient detail to enable those of ordinary skill in the art to easily practice it.

[0046] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected" but also the case where it is "indirectly connected" with another element in between. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the present invention. Throughout the specification, when a part is said to "comprise" a certain element, this does not exclude other elements unless specifically stated to the contrary, but rather means that it can include other elements. "At least one of X, Y, and Z", and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Herein, "and / or" includes any combination of one or more of the configurations.

[0047] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0048] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features are now positioned "above" the other elements or features. Thus, in one embodiment, the term "below" may encompass both above and below. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are to be interpreted accordingly.

[0049] Various embodiments are described with reference to drawings schematically illustrating ideal embodiments. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the present embodiments are not limited thereto.

[0050] Figure 1 is a block diagram showing an embodiment of a display device.

[0051] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0052] The display panel (DP) includes sub-pixels (SP). The sub-pixels (SP) can be connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) can be electrically connected to a data driver (130) via first to n-th data lines (DL1 to DLn).

[0053] The sub-pixels (SP) can generate light of two or more colors. For example, each of the sub-pixels (SP) can generate light of red, green, blue, cyan, magenta, yellow, white, etc.

[0054] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). For example, the pixel (PXL) can include four sub-pixels as illustrated in FIG. 1. In this way, the pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels included therein.

[0055] The gate driver (120) is electrically connected to the sub-pixels (SP) arranged in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) can output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) can include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0056] The gate driver (120) may be arranged on one side of the display panel (DP). However, embodiments are not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be arranged on one side of the display panel (DP) and the other side of the display panel (DP) opposite to the one side. In this way, the gate driver (120) may be arranged around the display panel (DP) in various forms according to embodiments.

[0057] The data driver (130) is electrically connected to the sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) receives image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) operates in response to the data control signal (DCS). In embodiments, the data control signal (DCS) may include a source start signal, a source shift clock, a source output enable signal, etc.

[0058] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can use the received voltages to apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn). When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLm). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0059] In embodiments, the gate driver (120) and data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0060] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) is configured to generate a plurality of voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate a plurality of voltages by receiving an input voltage from the outside of the display device (DD) and regulating the received voltage.

[0061] A voltage generator (140) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In other embodiments, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0062] In addition, the voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a reference voltage (e.g., a predetermined or selectable reference voltage) can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In embodiments, the voltage generator (140) may provide pixel control signals to the sub-pixels (SP) via pixel control lines (PXCL). Although FIG. 1 illustrates that the pixel control lines (PXCL) are electrically connected between the voltage generator (140) and the display panel (DP), embodiments are not limited thereto. For example, the pixel control lines (PXCL) may be electrically connected between the gate driver (120) and the display panel (DP). In this case, the pixel control signals may be transmitted from the gate driver (120) to the sub-pixels (SP) via the pixel control lines (PXCL).

[0063] The controller (150) controls all operations of the display device (DD). The controller (150) receives input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0064] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (DATA). In embodiments, the controller (150) can output image data (DATA) by aligning the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit.

[0065] Two or more components of the data driver (130), the voltage generator (140), and the controller (150) may be mounted on a single integrated circuit. As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0066] Fig. 2 is a block diagram showing an embodiment of a first sub-pixel among the sub-pixels of Fig. 1, and Fig. 3 is a block diagram showing an embodiment of a second sub-pixel among the sub-pixels of Fig. 1. In Figs. 2 and 3, sub-pixels arranged in the ith row (i is an integer greater than or equal to 1 and less than or equal to m) and the jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 are exemplarily shown.

[0067] Referring to FIGS. 2 and 3, each of the sub-pixels (SP1, SP2) may include a sub-pixel circuit (SPC) and a light-emitting element (LD1, LD2). The sub-pixel circuit (SPC) may include a first sub-pixel circuit (SPC1) that controls the light-emitting time of the light-emitting element (LD1, LD2) according to the grayscale, and a second sub-pixel circuit (SPC2) that controls the amount of driving current applied to the light-emitting element (LD1, LD2) according to the grayscale.

[0068] The light emitting elements (LD1, LD2) are electrically connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) is electrically connected to one of the power supply lines (PL) of FIG. 1 and receives a first power supply voltage. The second power supply voltage node (VSSN) is electrically connected to another of the power supply lines (PL) of FIG. 1 and receives a second power supply voltage. The first power supply voltage may have a higher voltage level than the second power supply voltage.

[0069] In this embodiment, it is exemplified that the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) are electrically connected to the same first power voltage node (VDDN), but the present invention is not limited thereto. For example, the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) may be electrically connected to different power voltage nodes, and first power voltages of different magnitudes may be applied to the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2).

[0070] The light-emitting elements (LD1, LD2) are electrically connected between the anode electrode (AE) and the cathode electrode (CE). The anode electrode (AE) may be electrically connected to a first power voltage node (VDDN) through a sub-pixel circuit (SPC1, SPC2). For example, the anode electrode (AE) may be electrically connected to the first power voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC1, SPC2). The cathode electrode (CE) may be electrically connected to a second power voltage node (VSSN). The light-emitting elements (LD1, LD2) are configured to emit light according to a current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0071] The first sub-pixel (SP1) may include a first light-emitting element (LD1). For example, the first sub-pixel (SP1) may include one first light-emitting element (LD1).

[0072] The second sub-pixel (SP2) may include a plurality of second light-emitting elements (LD2). For example, the second sub-pixel (SP2) may include a plurality of second light-emitting elements (LD2) that are electrically connected in parallel. Since the second sub-pixel (SP2) includes a plurality of second light-emitting elements (LD2) that are electrically connected in parallel, high brightness can be realized.

[0073] A detailed description of the light emitting elements (LD1, LD2) will be provided later.

[0074] The sub-pixel circuit (SPC) may be electrically connected to an ith gate line (GLi) among the first to mth gate lines (GL1 to GLm) of FIG. 1 and a jth data line (DLj) among the first to nth data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the ith gate line (GLi), the sub-pixel circuit (SPC) controls the light-emitting elements (LD1, LD2) to emit light according to a data signal received through the jth data line (DLj). In embodiments, the sub-pixel circuits (SPC1, SPC2) may be further electrically connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the light-emitting elements (LD1, LD2) in response to pixel control signals received through the pixel control lines (PXCL).

[0075] For these operations, a sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0076] In this embodiment, it is exemplified that the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) are electrically connected to the same gate line (e.g., GLi), but the present invention is not limited thereto. For example, the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) may receive different gate signals through different gate lines.

[0077] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Silicon Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0078] Fig. 4 is a plan view showing an embodiment of the display panel of Fig. 1.

[0079] Referring to FIG. 4, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) displays an image through the display area (DA). The non-display area (NDA) is arranged around the display area (DA).

[0080] A display panel (DP) includes sub-pixels (SP) in a display area (DA). The sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). For example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on the embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0081] Among a plurality of sub-pixels (SP), two or more sub-pixels can constitute one pixel (PXL). In FIG. 3, the pixel (PXL) is illustrated as including four sub-pixels (SP1-1 to SP1-3, SP2), but embodiments are not limited thereto. For example, the pixel (PXL) may include two sub-pixels. Hereinafter, for convenience of explanation, it is assumed that the pixel (PXL) includes first sub-pixels (SP1) and second sub-pixels (SP2).

[0082] Each of the first to third sub-pixels (SP1 to SP3) can generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. Hereinafter, for the sake of clarity and concise explanation, it is assumed that the first to third sub-pixel (SP1-1) is configured to generate red color light, the first to second sub-pixel (SP1-2) is configured to generate green color light, and the first to third sub-pixel (SP1-3) is configured to generate blue color light.

[0083] The second sub-pixel (SP2) can generate white color light. By displaying white color from the second sub-pixel (SP2), the pixel (PXL) can realize higher brightness.

[0084] As a display panel (DP), a self-luminous display panel such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements, can be used.

[0085] Components for controlling sub-pixels (SP) may be arranged in the non-display area (NDA). Wires electrically connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1, may be arranged in the non-display area (NDA).

[0086] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) may be disposed in the non-display area (NDA). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be electrically connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120) may be implemented as a single integrated circuit that is separate from the display panel (DP) together with the data driver (130), the voltage generator (140), and the controller (150).

[0087] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have the shape of a closed loop including straight and / or curved edges. For example, the display area (DA) may have shapes such as a polygon, a circle, a semicircle, or an ellipse.

[0088] In some embodiments, the display panel (DP) may have a substantially flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface. In some embodiments, the display panel (DP) may be bendable, foldable, or rollable. In such cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0089] Fig. 5 is a cross-sectional view showing an embodiment of the display panel of Fig. 4.

[0090] Referring to FIG. 5, the display panel (DP) may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), and a light conversion layer (LCL) that are sequentially laminated in a third direction (DR3) intersecting the first and second directions (DR1, DR2) on the substrate (SUB).

[0091] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. As another example, the substrate (SUB) may include a polyimide (PI) substrate. As yet another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0092] In embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0093] A pixel circuit layer (PCL) is arranged on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns arranged between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, etc.

[0094] The circuit elements of the pixel circuit layer (PCL) may include the sub-pixel circuits (SPCs, see FIGS. 2 and 3) of FIGS. 2 and 3. In other words, the circuit elements of the pixel circuit layer (PCL) may be provided by transistors of the sub-pixel circuit (SPCs, see FIGS. 2 and 3) and one or more capacitors.

[0095] The wiring of the pixel circuit layer (PCL) may include wiring electrically connected to each of the sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines necessary to drive the display element layer (DPL).

[0096] A display element layer (DPL) is arranged on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0097] A light conversion layer (LCL) may be disposed on the display element layer (DPL). The light conversion layer (LCL) may include light conversion patterns having color conversion particles and / or scattering particles. For example, the color conversion particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). In embodiments, the light conversion patterns may be omitted.

[0098] The light conversion layer (LCL) may further include a color filter layer including color filters. The color filter may selectively transmit light of a specific wavelength (or, a specific color). In embodiments, the color filter layer may be omitted.

[0099] A window may be provided on a light conversion layer (LCL) to protect an exposed surface (or upper surface) of a display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded to the light conversion layer (LCL) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0100] FIG. 6 is a cross-sectional view showing another embodiment of the display panel of FIG. 4.

[0101] Referring to FIG. 6, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light conversion layer (LCL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light conversion layer (LCL) are configured similarly to the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light conversion layer (LCL) described with reference to FIG. 4, respectively. Hereinafter, redundant descriptions are omitted.

[0102] An input sensing layer (ISL) can detect user input on the upper surface (or display surface) of a display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting external objects, such as a user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0103] FIG. 7 is a plan view showing an embodiment of one of the pixels of FIG. 4.

[0104] Referring to FIG. 7, a pixel (PXL) may include first sub-pixels (SP1) and second sub-pixels (SP2). The first sub-pixels (SP1) and the second sub-pixels (SP2) may be arranged in a first direction (DR1). However, the arrangement of the pixels (PXL) is not limited thereto and may vary depending on embodiments. For example, the first sub-pixels (SP1) and the second sub-pixels (SP2) may be arranged in a zigzag pattern.

[0105] The first sub-pixels (SP1) may include 1-1 to 1-3 sub-pixels (SP1-1 to SP1-3). Each of the 1-1 to 1-3 sub-pixels (SP1-1 to SP1-3) may include a first light-emitting element (LD1).

[0106] The second sub-pixel (SP2) may include a plurality of second light-emitting elements (LD2). The second light-emitting elements (LD2) may be arranged in the second direction (DR2). However, the arrangement of the second light-emitting elements (LD2) is not limited thereto and may vary depending on embodiments.

[0107] The second light-emitting element (LD2) may be smaller than the first light-emitting element (LD1). The second sub-pixel (SP2) may include a plurality of second light-emitting elements (LD2) smaller than the first light-emitting element (LD1), thereby realizing higher brightness in the same area.

[0108] In one embodiment, the second light-emitting elements (LD2) can display the same color as the first light-emitting element (LD1). For example, the first light-emitting elements (LD1) and the second light-emitting elements (LD2) can display a blue color.

[0109] The first light-emitting element (LD1) and the second light-emitting element (LD2) may be inorganic light-emitting diodes containing inorganic light-emitting materials. However, embodiments are not limited thereto, and for example, organic light-emitting diodes may be used.

[0110] Fig. 8 is a cross-sectional view taken along line II' of Fig. 7.

[0111] Referring to FIG. 8, a pixel circuit layer (PCL), a display element layer (DPL), and a light conversion layer (LCL) can be sequentially arranged on a substrate (SUB).

[0112] A pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns stacked on a substrate (SUB). The insulating layers may include a buffer layer (BFL), one or more interlayer insulating layers (ILD), and one or more passivation layers (PSV1, PSV2). The semiconductor patterns and conductive patterns may be positioned between the insulating layers. The conductive patterns may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0113] As described above, each of the first and second sub-pixels (SP1, SP2, see FIGS. 2 and 3) may include a sub-pixel circuit (SPC, see FIGS. 2 and 3) including transistors and one or more capacitors. The semiconductor patterns and conductive patterns of the pixel circuit layer (PCL) may function as transistors and capacitors of the sub-pixel circuit (SPC, see FIGS. 2 and 3). In addition, the conductive patterns of the pixel circuit layer (PCL) may further function as wirings, for example, the first to m-th gate lines (GL1 to GLm, see FIG. 1), the first to n-th data lines (DL1 to DLn, see FIG. 1), power lines (PL, see FIG. 1), and pixel control lines (PXCL, see FIG. 1).

[0114] A buffer layer (BFL) may be disposed on one surface of a substrate (SUB). The buffer layer (BFL) may prevent impurities from diffusing into circuit elements and wirings included in a pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer including an inorganic material. In embodiments, the buffer layer (BFL) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The buffer layer (BFL) may be provided as a single layer or multiple layers. When the buffer layer (BFL) is provided as multiple layers, each layer may be formed of the same material or different materials.

[0115] In embodiments, one or more barrier layers may be disposed between the substrate (SUB) and the buffer layer (BFL). Each of the barrier layers may comprise polyimide.

[0116] A transistor (T_SP1) may be placed on the buffer layer (BFL). The transistor (T_SP1) may be any one of the transistors of the sub-pixel circuit (SPC) included in the first sub-pixel (SP1). For example, the transistor (T_SP1) may be understood as a transistor connected to the anode electrode (AE) among the transistors of the sub-pixel circuit (SPC).

[0117] The transistor (T_SP1) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (ET1), and a second terminal (ET2). The first terminal (ET1) may be either a source electrode or a drain electrode, and the second terminal (ET2) may be the other of the source electrode and the drain electrode. For example, the first terminal (ET1) may be a source electrode, and the second terminal (ET2) may be a drain electrode.

[0118] A semiconductor pattern (SCP) may be disposed on a buffer layer (BFL). The semiconductor pattern (SCP) may include a first contact region contacting a first terminal (ET1) and a second contact region contacting a second terminal (ET2). A region between the first contact region and the second contact region may be a channel region. The channel region may overlap with a gate electrode (GE) of the transistor (T_SP1). The channel region may be a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. For example, a p-type impurity may be used as the impurity, but embodiments are not limited thereto.

[0119] The semiconductor pattern (SCP) may include any one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a polysilicon semiconductor, a low temperature polysilicon semiconductor, and an oxide semiconductor.

[0120] Interlayer insulating layers (ILDs) may be sequentially stacked on a semiconductor pattern (SCP). The interlayer insulating layers (ILDs) may be inorganic insulating layers including an inorganic material. For example, each of the interlayer insulating layers (ILDs) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the interlayer insulating layers (ILDs) are not limited thereto. For example, any one of the interlayer insulating layers (ILDs) may include an organic insulating layer including an organic material.

[0121] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers (ILDs). For example, the interlayer insulating layers (ILDs) can include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) can be disposed between the semiconductor pattern (SCP) and the gate electrode (GE) such that the gate electrode (GE) is spaced apart from the semiconductor pattern (SCP). In embodiments, the gate insulating layer (GI) can be provided over the entire surface of the semiconductor pattern (SCP) and the buffer layer (BFL) to cover the semiconductor pattern (SCP) and the buffer layer (BFL). As the number of layers required for the conductive patterns and / or semiconductor patterns increases, the number of interlayer insulating layers (ILDs) can increase.

[0122] A gate electrode (GE) is disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap a channel region of a semiconductor pattern (SCP). In embodiments, the gate electrode (GE) may be provided as a single layer including at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In embodiments, the gate electrode (GE) may be provided as a multilayer including at least one material selected from the group consisting of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag), which are low-resistance materials.

[0123] The first and second terminals (ET1, ET2) are disposed on interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) can contact a semiconductor pattern (SCP) through contact holes penetrating the interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) can contact first and second contact areas of the semiconductor pattern (SCP), respectively. Each of the first and second terminals (ET1, ET2) can include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag).

[0124] Although the first and second terminals (ET1, ET2) are illustrated as separate electrodes electrically connected to the semiconductor pattern (SCP), embodiments are not limited thereto. In embodiments, the first terminal (ET1) may be a first contact region adjacent to one side of a channel region of the semiconductor pattern (SCP), and the second terminal (ET2) may be a second contact region adjacent to the other side of the channel region. In this case, the first terminal (ET1) may be electrically connected to the first light-emitting element (LD1) via a connecting means, such as a bridge electrode, disposed on at least one of the interlayer insulating layers (ILD).

[0125] In embodiments, the transistor (T_SP1) may be formed of a low-temperature polysilicon transistor. However, embodiments are not limited thereto. For example, the transistor (T_SP1) may also be formed of an oxide semiconductor transistor. In embodiments, the sub-pixel circuit of the first sub-pixel (SP1) may include transistors of different types. For example, the transistor (T_SP1) may be formed of a low-temperature polysilicon transistor, and the other transistors of the first sub-pixel (SP1) may be formed of oxide semiconductor transistors. In this case, the oxide semiconductor of the oxide semiconductor transistor may be formed on any one of the interlayer insulating layers (ILD) other than the insulating layer on which the semiconductor pattern (SCP) of the transistor (T_SP1) is formed.

[0126] In the embodiments, the transistor (T_SP1) is described as a transistor having a top gate structure, but the embodiments are not limited thereto. For example, the transistor (T_SP1) may be a transistor having a bottom gate structure. In addition, the structure of the transistor (T_SP1) may be changed in various ways.

[0127] At least some of the various wirings of the display panel (DP) and / or display device (DD) may be further arranged on the interlayer insulating layers (ILD).

[0128] A first passivation layer (PSV1) may be disposed on the first to third transistors (T_SP1 to T_SP3). The passivation layer may also be referred to as a protective layer or a via layer. The first passivation layer (PSV1) protects components disposed thereunder and may provide a flat upper surface.

[0129] A connection pattern (CP) may be arranged on the first passivation layer (PSV1). The connection pattern (CP) may penetrate the first passivation layer (PSV1) and be electrically connected to the first terminal (ET1) of the transistor (T_SP1). The connection pattern (CP) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag).

[0130] At least some of the various wires of the display panel (DP) and / or the display device (DD) may be further arranged on the first passivation layer (PSV1).

[0131] A second passivation layer (PSV2) is disposed on the connection pattern (CP) and the first passivation layer (PSV1). The second passivation layer (PSV2) protects components disposed thereunder and can provide a flat upper surface.

[0132] Each of the first and second passivation layers (PSV1, PSV2) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The organic insulating layer may include, for example, at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0133] The first and second passivation layers (PSV1, PSV2) may comprise the same material as one of the interlayer insulating layers (ILD), but embodiments are not limited thereto. Each of the first and second passivation layers (PSV1, PSV2) may be provided as a single layer, but may also be provided as multiple layers.

[0134] A display element layer (DPL) may be disposed on the second passivation layer (PSV2). The display element layer (DPL) may include an anode electrode (AE), a cathode electrode (CE), a first bank (BNK1), first and second reflective electrodes (RFE1, RFE2), a first light-emitting element (LD1), an overcoat layer (OCL), a third passivation layer (PSV3), and a capping layer (CPL).

[0135] An anode electrode (AE) and a cathode electrode (CE) are arranged on the pixel circuit layer (PCL).

[0136] The anode electrode (AE) can be electrically connected to the connection pattern (CP) through a contact hole penetrating the second passivation layer (PSV2). In this way, the anode electrode (AE) can be electrically connected to the first transistor (T_SP1).

[0137] The cathode electrode (CE) may be spaced apart from the anode electrode (AE) in a second direction (DR2). The cathode electrode (CE) may be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) may be transmitted to the cathode electrode (CE).

[0138] A first bank (BNK1) may be disposed on the anode electrode (AE) and the cathode electrode (CE). The first bank (BNK1) may have a first opening (OP1) exposing portions of the anode electrode (AE) and the cathode electrode (CE). A first light-emitting element (LD1) may be disposed in the first opening (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel defining film that defines an area where the first light-emitting element (LD1) is positioned.

[0139] The first bank (BNK1) is configured to include a light-shielding material to prevent light mixing between adjacent sub-pixels. In embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0140] A first reflective electrode (RFE1) may be disposed on an exposed portion of the anode electrode (AE) and a side surface of the first bank (BNK1) adjacent thereto. A second reflective electrode (RFE2) may be disposed on an exposed portion of the cathode electrode (CE) and a side surface of the first bank (BNK1) adjacent thereto. The first and second reflective electrodes (RFE1, RFE2) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1) may be improved. In embodiments, the first and second reflective electrodes (RFE1, RFE2) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0141] The first light-emitting element (LD1) is electrically connected to the anode electrode (AE) through the first reflective electrode (RFE1). The first light-emitting element (LD1) is electrically connected to the cathode electrode (CE) through the second reflective electrode (RFE2). The first light-emitting element (LD1) can be bonded to the first and second reflective electrodes (RFE1, RFE2).

[0142] The first light-emitting element (LD1) may include a first semiconductor layer (11), an active layer (12), a second semiconductor layer (13), and an auxiliary layer (15). The first light-emitting element (LD1) includes a light-emitting laminate in which the auxiliary layer (15), the first semiconductor layer (11), the active layer (12), and the second semiconductor layer (13) are sequentially laminated.

[0143] The first light-emitting element (LD1) includes first and second bonding electrodes (BDE1, BDE2) facing the same direction (e.g., opposite to the third direction (DR3)). The first bonding electrode (BDE1) may be electrically connected to the second semiconductor layer (13). The second bonding electrode (BDE2) may be connected to the first semiconductor layer (11) exposed by etching the second semiconductor layer (13) and the active layer (12). The first light-emitting element (LD1) may be a flip chip type light-emitting element.

[0144] The first semiconductor layer (11) is configured to provide electrons to the active layer (12). The first semiconductor layer (11) may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer (11) may include any one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first semiconductor layer (11) is not limited thereto, and various other materials may also constitute the first semiconductor layer (11). In one embodiment of the present invention, the first semiconductor layer (11) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). According to an embodiment, the first semiconductor layer (11) may form an n-type semiconductor layer together with the auxiliary layer (15).

[0145] The active layer (12) is disposed on the first semiconductor layer (11) and may be a region where electrons and holes recombine. As electrons and holes recombine in the active layer (12), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The active layer (12) may be formed in a single or multiple quantum well structure. When the active layer (12) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcing layer, and a well layer may be repeatedly stacked to form the active layer (12). However, embodiments of the active layer (12) are not limited thereto.

[0146] The second semiconductor layer (13) is disposed on the active layer (12) and provides holes to the active layer (12). The second semiconductor layer (13) may include a semiconductor layer of a different type from the first semiconductor layer (11). For example, the second semiconductor layer (13) may include at least one p-type semiconductor layer. For example, the second semiconductor layer (13) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc. However, the material constituting the second semiconductor layer (13) is not limited thereto, and various other materials may constituting the second semiconductor layer (13). In one embodiment of the present invention, the second semiconductor layer (13) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant).

[0147] The auxiliary layer (15) may include a gallium nitride (GaN) semiconductor material that is not doped with impurities, and may form an n-type semiconductor layer together with the first semiconductor layer (11).

[0148] The first bonding electrode (BDE1) may be electrically connected to the second semiconductor layer (13). The second bonding electrode (BDE2) may be electrically connected to the first semiconductor layer (11). The first and second bonding electrodes (BDE1, BDE2) may include a eutectic metal.

[0149] The first light-emitting element (LD1) may further include an insulating film (16) covering an outer surface of the light-emitting stack. The insulating film (16) may prevent an electrical short circuit that may occur when the active layer (12) comes into contact with a conductive material other than the first and second semiconductor layers (11, 13). The insulating film (16) may include a transparent insulating material. The insulating film (16) is configured to expose the lower surfaces of the first and second bonding electrodes (BDE1, BDE2).

[0150] The lower surface of the first bonding electrode (BDE1) contacts the first reflective electrode (RFE1). Accordingly, the first bonding electrode (BDE1) is electrically connected to the anode electrode (AE) via the first reflective electrode (RFE1). The lower surface of the second bonding electrode (BDE2) contacts the second reflective electrode (RFE2). Accordingly, the second bonding electrode (BDE2) is electrically connected to the cathode electrode (CE) via the second reflective electrode (RFE2).

[0151] An overcoat layer (OCL) may be disposed within a first opening (OP1) in which first and second reflective electrodes (RFE1, RFE2) and a first light-emitting element (LD1) are disposed. The overcoat layer (OCL) may fix the first light-emitting element (LD1) bonded to the first and second reflective electrodes (RFE1, RFE2) so as not to move. In addition, the overcoat layer (OCL) may protect components disposed thereunder from foreign substances such as dust and moisture. For example, the overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include epoxy, but embodiments are not limited thereto.

[0152] A third passivation layer (PSV3) is disposed on the first bank (BNK1) and the overcoat layer (OCL). The third passivation layer (PSV3) protects components disposed thereunder and can provide a substantially flat upper surface. The third passivation layer (PSV3) may include the same material as either of the first and second passivation layers (PSV1, PSV2), but embodiments are not limited thereto.

[0153] In embodiments, the third passivation layer (PSV3) may not be disposed on the upper surface (LTS) of the first light-emitting element (LD1). The first light-emitting element (LD1) may protrude into the light conversion layer (LCL). The first light-emitting element (LD1) may be at least partially positioned within the second opening (OP2) of the second bank (BNK2). For example, the height of the upper surface (LTS) of the first light-emitting element (LD1) from the substrate (SUB) may be higher than the lowermost end (RBE) of the reflective layer (RFL). Accordingly, light emitted from the first light-emitting element (LD1) may be provided to the light conversion layer (LCL) at a relatively high rate.

[0154] The capping layer (CPL) is disposed on the third passivation layer (PSV3). The capping layer (CPL) can protect components under the capping layer (CPL), such as the first light-emitting element (LD1), from external moisture and humidity. In embodiments, the capping layer (CPL) may not be disposed on the upper surface of the first light-emitting element (LD1). In other embodiments, the capping layer (CPL) may entirely cover the first light-emitting element (LD1) and the third passivation layer (PSV3). The capping layer (CPL) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the material of the capping layer (CPL) is not limited thereto.

[0155] The pixel circuit layer (PCL) and the display element layer (DPL) of the first-first sub-pixel (SP1-1) have been described above. Each of the first-second and first-third sub-pixels (SP1-2, SP1-3) of FIG. 7 may also be configured similarly to the first-first sub-pixel (SP1-1), unless otherwise described herein. Similarly, the second sub-pixel (SP2) may also be configured similarly to the first-first sub-pixel (SP1-1), unless otherwise described herein.

[0156] A light conversion layer (LCL) is disposed on a capping layer (CPL). The light conversion layer (LCL) may include a second bank (BNK2), a reflective layer (RFL), a fourth passivation layer (PSV4), a first light conversion pattern (CCP1), a low-refractive-index layer (LRL), and a color filter layer (CFL).

[0157] A second bank (BNK2) is disposed on the capping layer (CPL). The second bank (BNK2) may overlap the first bank (BNK1). The second bank (BNK2) may have a second opening (OP2) that overlaps the first opening (OP1).

[0158] The second bank (BNK2) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In embodiments, the second bank (BNK2) may include an organic material. For example, the second bank (BNK2) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0159] A reflective layer (RFL) may be disposed on the side surfaces of the second bank (BNK2) adjacent to the second opening (OP2). The reflective layer (RFL) is configured to reflect incident light, thereby improving light emission efficiency. The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0160] On the capping layer (CPL), a fourth passivation layer (PSV4) is disposed within the second opening (OP2). The fourth passivation layer (PSV4) protects components disposed thereunder and can provide a substantially flat upper surface. The fourth passivation layer (PSV4) may include the same material as any one of the first to third passivation layers (PSV1 to PSV3), but embodiments are not limited thereto.

[0161] On the fourth passivation layer (PSV4), a first light conversion pattern (CCP1) can be arranged within a second opening (OP2).

[0162] The first light conversion pattern (CCP1) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. Additionally, the color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0163] The first sub-pixel (SP1-1) may be a red sub-pixel. When the first light-emitting element (LD1) emits blue light, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. When the first light-emitting element (LD1) emits red light, the first light conversion pattern (CCP1) may include scattering particles. In this way, the particles included in the first light conversion pattern (CCP1) may be varied depending on the first light-emitting element (LD1).

[0164] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), and the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) may have a lower refractive index than the first light conversion pattern (CCP1) and the first color filter (CF1). The low-refractive-index layer (LRL) is configured to refract or totally reflect light depending on the incident angle of the light. For example, the low-refractive-index layer (LRL) may provide light that has passed through the first light conversion pattern (CCP1) back to the first light conversion pattern (CCP1). Accordingly, the light conversion efficiency of the first light conversion pattern (CCP1) may be improved.

[0165] A color filter layer (CFL) may be disposed on a low refractive index layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and light blocking patterns (LBP). The first color filter (CF1) overlaps the first light conversion pattern (CCP1). The first color filter (CF1) may selectively transmit light of a desired wavelength range. When the 1-1 sub-pixel (SP1-1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0166] Fig. 9 is a cross-sectional view taken along line II-II' of Fig. 7.

[0167] Referring to FIGS. 7 and 9, a pixel circuit layer (PCL), a display element layer (DPL), and a light conversion layer (LCL) can be sequentially provided on a substrate (SUB).

[0168] The pixel circuit layer (PCL) and the display element layer (DPL) are described in the same manner as described with reference to FIG. 8. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first sub-pixels (SP1) and the second sub-pixels (SP2) are provided, respectively. In the display element layer (DPL), first light-emitting elements (LD1) corresponding to the first to third sub-pixels (SP1-1 to SP1-3) are provided, respectively. In the display element layer (DPL), second light-emitting elements (LD2) corresponding to the second sub-pixel (SP2) are provided. The first and second light-emitting elements (LD1, LD2) may overlap the first openings (OP1) of the first bank (BNK1). The first light-emitting element (LD1) is electrically connected between a cathode electrode (CE, see FIG. 8) and a transistor included in a sub-pixel circuit (SPC, FIG. 2) of one of the first to third sub-pixels (SP1-1 to SP1-3). The second light-emitting element (LD2) is electrically connected between a cathode electrode (CE) and a transistor included in a sub-pixel circuit (SPC, FIG. 3) of the second sub-pixel (SP2). Hereinafter, redundant descriptions are omitted.

[0169] A light conversion layer (LCL) is provided on the display element layer (DPL). The light conversion layer (LCL) is described in the same manner as described with reference to Fig. 8. Hereinafter, redundant descriptions are omitted.

[0170] The second bank (BNK2) has second openings (OP2). It can be understood that the light-emitting area (EMA) and the non-light-emitting area (NEMA) for the first and second sub-pixels (SP1, SP2) are defined by the second bank (BNK2). The overlapping area of ​​the second bank (BNK2) may correspond to the non-light-emitting area (NEMA). The overlapping area of ​​the second openings (OP2) of the second bank (BNK2) may correspond to the light-emitting area (EMA) of the first and second sub-pixels (SP1, SP2).

[0171] On the capping layer (CPL), a fourth passivation layer (PSV4) may be disposed within the second openings (OP2). On the fourth passivation layer (PSV4), first to third photo-conversion patterns (CCP1 to CCP3) may be disposed within the second openings (OP2).

[0172] In embodiments, the first light-emitting elements (LD1) may be configured to emit blue light. In this case, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. The second light conversion pattern (CCP2) may include second color conversion particles (QD2) configured to convert blue light into green light. The third light conversion pattern (CCP3) may include scattering particles (SCT) that scatter blue light to improve light emission efficiency. Accordingly, the 1-1 to 1-3 sub-pixels (SP1-1 to SP1-3) may be provided as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.

[0173] In embodiments, the second light emitting element (LD2) may be configured to emit blue light. In this case, the light conversion pattern disposed in the second sub-pixel (SP2) may convert the blue light into white light. For example, the first to third light conversion patterns (CCP1 to CCP3) may be disposed in the second sub-pixel (SP2). For example, in the second sub-pixel (SP2), the first to third light conversion patterns (CCP1 to CCP3) may overlap in the third direction (DR3). Accordingly, the light conversion pattern of the second sub-pixel (SP2) may convert the blue light into white light.

[0174] Depending on the first and second light-emitting elements (LD1, LD2), the particles included in the first to third light-conversion patterns (CCP1 to CCP3) can be varied.

[0175] In embodiments, the first to third optical conversion patterns (CCP1 to CCP3) may be omitted.

[0176] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), and the first to third light conversion patterns (CCP1 to CCP3). The low-refractive-index layer (LRL) may have a lower refractive index than the first to third light conversion patterns (CCP1 to CCP3) and the first to third color filters (CF1 to CF3). In embodiments, the low-refractive-index layer (LRL) may be omitted in an area corresponding to the third sub-pixel (SP3).

[0177] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1 to CF3) and light blocking patterns (LBP).

[0178] Each of the first to third color filters (CF1 to CF3) can selectively transmit light of a desired wavelength range. When the 1-1 sub-pixel (SP1-1) is a red sub-pixel, the first color filter (CF1) can include a red color filter. When the 1-2 sub-pixel (SP1-2) is a green sub-pixel, the second color filter (CF2) can include a green color filter. When the 1-3 sub-pixel (SP3) is a blue sub-pixel, the third color filter (CF3) can include a blue color filter.

[0179] Light blocking patterns (LBP) may be arranged between the color filters (CF1 to CF3). It may be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first and second sub-pixels (SP1, SP2) are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0180] In one embodiment, the first to third color filters (CF1 to CF3) may not be arranged in the second sub-pixel (SP2). Since the second sub-pixel (SP2) displays a white color, a color filter may not be required.

[0181] In embodiments, the light-blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light-blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1 to CF3) overlap. For example, each of the light-blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1 to CF3). As another example, the light-blocking pattern between the first and second color filters (CF1, CF2) among the light-blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, and the light-blocking pattern between the second and third color filters (CF2, CF3) among the light-blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap. The light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of the neighboring pixel can be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1 to CF3) can extend into the non-emitting area (NEMA) to form light blocking patterns (LBP).

[0182] FIG. 10 is a graph showing an example in which the display panel of the display device of FIG. 1 operates in the 1-1 mode, FIG. 11 is a graph showing an example in which the display panel of the display device of FIG. 1 operates in the 1-2 mode, FIG. 12 is a graph showing an example in which the sub-pixels of the display device of FIG. 1 operate in the 1st mode, FIG. 13 is a graph showing an example in which the display panel of the display device of FIG. 1 operates in the 2nd mode, and FIG. 14 is a graph showing an example in which the sub-pixels of the display device of FIG. 1 operate in the 2nd mode.

[0183] Referring to FIGS. 10 to 14, the display panel can be driven in the first, second, and second modes (M1-1, M1-2, M2), respectively. The peak luminance of the first, second, and third modes (M1-2) can be greater than the peak luminance of the first, first, and second modes (M1-1, M1-2, M2). The peak luminance of the second mode (M2) can be greater than the peak luminance of the first, second, and third modes (M1-2).

[0184] Here, peak luminance represents the maximum luminance that can be displayed, and as the peak luminance increases, the luminance of all gray levels can increase overall.

[0185] As shown in Fig. 12, the first light-emitting element (LD1) can be turned on in the first mode (M1-1, M1-2), and the second light-emitting elements (LD2) can be turned off in the first mode (M1-1, M1-2). As shown in Fig. 14, the first light-emitting element (LD1) can be turned on in the second mode (M2), and the second light-emitting elements (LD2) can be turned on in the second mode (M2). That is, since the peak luminance of the second mode (M2) is higher than the peak luminance of the first mode (M1-1, M1-2), it is necessary to display a higher luminance in the second mode (M2). In addition, by using the second sub-pixel (SP2) in the second mode (M2), a higher luminance can be implemented.

[0186] In one embodiment, the peak luminance may be determined based on the user's settings. In this case, once the peak luminance is determined, the operating mode of the display panel may be determined by the controller (150, see FIG. 1).

[0187] In one embodiment, the peak luminance may be determined based on the ambient brightness of the display panel, and the operating mode of the display panel may be determined based on the peak luminance. For example, in a dark indoor environment, the display panel may operate in mode 1-1 (M1-1), in a bright indoor environment, the display panel may operate in mode 1-2 (M1-2), and outdoors, the display panel may operate in mode 2 (M2).

[0188] However, the operating mode is not necessarily determined based on peak brightness, and the operating mode may be determined directly based on the user's settings or ambient brightness.

[0189] Referring to FIG. 2 and FIG. 10, in the 1-1 mode (M1-1), the light emission time of the first light-emitting element (LD1) can be controlled according to the grayscale. For example, as the light emission time increases, the displayed brightness can increase. For example, in the 1-1 mode (M1-1), the first light-emitting element (LD1) can be controlled by the first sub-pixel circuit (SPC1). For example, in the 1-1 mode (M1-1), the first light-emitting element (LD1) can receive current generated by the driving transistor of the first sub-pixel circuit (SPC1) and emit light.

[0190] In one embodiment, in the 1-1 mode (M1-1), the number of times the first light-emitting element (LD1) emits light during one frame may increase as the grayscale increases. For example, in the first grayscale (GV1), the first light-emitting element (LD1) emits light once during one frame, in the second grayscale (GV2) greater than the first grayscale (GV1), the first light-emitting element (LD1) emits light twice during one frame, and in the third grayscale (GV3) greater than the second grayscale (GV2), the first light-emitting element (LD1) may emit light four times during one frame.

[0191] However, the method of controlling the light emission time is not limited to increasing the number of light emission times. For example, the light emission time can be controlled by adjusting the time for which one light emission is maintained.

[0192] In one embodiment, the anode voltage (V_AE) of the anode electrode (AE) of the first light-emitting element (LD1) in the 1-1 mode (M1-1) may be constant regardless of the grayscale. The anode voltage (V_AE) in the 1-1 mode (M1-1) may be greater than the anode voltage (V_AE) in the 1-2 mode (M1-2, FIG. 13).

[0193] Referring to FIG. 2 and FIG. 11, in the 1-2 mode (M1-2), the magnitude of the driving current applied to the first light-emitting element (LD1) can be controlled according to the grayscale. For example, as the magnitude of the driving current increases, the displayed brightness can increase. For example, in the 1-2 mode (M1-2), the first light-emitting element (LD1) can be controlled by the second sub-pixel circuit (SPC2). For example, in the 1-2 mode (M1-2), the first light-emitting element (LD1) can receive the current generated by the driving transistor of the second sub-pixel circuit (SPC2) and emit light.

[0194] For example, the anode voltage (V_AE) at the first grayscale (GV1) may be less than the anode voltage (V_AE) at the second grayscale (GV2) which is greater than the first grayscale (GV1), and the anode voltage (V-AE) at the second grayscale (GV) may be less than the anode voltage (V-AE) at the third grayscale (GV3) which is greater than the second grayscale (GV).

[0195] Referring to FIG. 13, in the second mode (M2), the light emission time of the first light-emitting element (LD1) and the magnitude of the driving current applied to the first light-emitting element (LD1) can be controlled according to the grayscale. In the second mode (M2), the light emission time of the second light-emitting element (LD2) and the magnitude of the driving current applied to the second light-emitting element (LD2) can be controlled according to the grayscale. In order to implement higher luminance than in the first mode (M1-1, M1-2), the second mode (M2) can control both the light emission time and the magnitude of the driving current. For example, in the second mode (M2), the first and second light-emitting elements (LD1, LD2) can be controlled by the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2). For example, in the second mode (M2), the second sub-pixel circuit (SPC2) can receive current generated by the driving transistor of the first sub-pixel circuit (SPC1), and the first and second light-emitting elements (LD1, LD2) can receive current generated by the driving transistor of the second sub-pixel circuit (SPC2) and emit light.

[0196] In one embodiment, in the second mode (M2), the number of times the first and second light-emitting elements (LD1, LD2) emit light during one frame may increase as the grayscale increases. For example, in the first grayscale (GV1), the first and second light-emitting elements (LD1, LD2) emit light once during one frame, in the second grayscale (GV2) greater than the first grayscale (GV1), the first and second light-emitting elements (LD1, LD2) emit light twice during one frame, and in the third grayscale (GV3) greater than the second grayscale (GV2), the first and second light-emitting elements (LD1, LD2) emit light four times during one frame.

[0197] In one embodiment, in the second mode (M2), the anode voltage (V_AE) may increase within one frame. For example, when the first and second light-emitting elements (LD1, LD2) emit light multiple times, the anode voltage (V_AE) at the Nth emission may be less than the anode voltage (V_AE) at the Mth emission. Here, N is a positive integer, and M is a positive integer greater than N.

[0198] FIG. 15 is a plan view showing an example of one of the pixels according to embodiments of the present invention.

[0199] Since the pixel according to the present embodiments is substantially the same as the configuration of the pixel of FIG. 7, except for the second light-emitting element (LD2), the same reference numbers and reference symbols are used for the same or similar components, and redundant descriptions are omitted.

[0200] Referring to Fig. 15, the second light-emitting elements (LD2) can display different colors. For example, the second-first light-emitting element (LD2-1) can display a red color, the second-second light-emitting element (LD2-2) can display a green color, and the second-third light-emitting element (LD2-3) can display a blue color. Accordingly, the second sub-pixel (SP2) can display a white color.

[0201] In one embodiment, the light conversion patterns of the light conversion layer (LCL, see FIG. 9) of the second sub-pixel (SP2) may include scattering particles (SCT, see FIG. 9). In one embodiment, the light conversion patterns of the light conversion layer (LCL, see FIG. 9) of the second sub-pixel (SP2) may be omitted.

[0202] FIG. 16 is a plan view showing an example of one of the pixels according to embodiments of the present invention.

[0203] Since the pixel according to the present embodiments is substantially the same as the configuration of the pixel of FIG. 7, except for the first light-emitting element (LD1), the same reference numbers and reference symbols are used for the same or similar components, and redundant descriptions are omitted.

[0204] Referring to FIG. 16, the 1-1 sub-pixel (SP1-1) may include 1-1 light-emitting elements (LD1-1), the 1-2 sub-pixel (SP1-2) may include 1-2 light-emitting elements (LD1-1), and the 1-3 sub-pixel (SP1-3) may include 1-3 light-emitting elements (LD1-3). For example, the 1-1 sub-pixel (SP1-1) may include 1-1 light-emitting elements (LD1-1) that are electrically connected in parallel, the 1-2 sub-pixel (SP1-2) may include 1-2 light-emitting elements (LD1-1) that are electrically connected in parallel, and the 1-3 sub-pixel (SP1-3) may include 1-3 light-emitting elements (LD1-3) that are electrically connected in parallel.

[0205] The second light-emitting element (LD2) may be larger than the first to third light-emitting elements (LD1-1 to LD1-3).

[0206] The first-first light-emitting elements (LD1-1) can display a first color, the first-second light-emitting elements (LD1-2) can display a second color, and the first-third light-emitting elements (LD1-3) can display a third color. The second light-emitting element (LD2) can display any one of the first to third colors.

[0207] For example, the first-first light-emitting elements (LD1-1) can display a red color, the first-second light-emitting elements (LD1-2) can display a green color, the first-third light-emitting elements (LD1-3) can display a blue color, and the second light-emitting element (LD2) can display a green color.

[0208] In one embodiment, each of the first to third light conversion patterns (CCP1 to CCP3, see FIG. 9) of the first to third sub-pixels (SP1-1 to SP1-3) may include scattering particles (SCT, see FIG. 9). When the second light-emitting element (LD2) displays a second color, the first light conversion pattern (CCP1, see FIG. 9) of the second sub-pixel (SP2) may include first color conversion particles (QD1, see FIG. 9), the second light conversion pattern (CCP2) of the second sub-pixel (SP2) may include scattering particles (SCT, see FIG. 9), and the third light conversion pattern (CCP3) of the second sub-pixel (SP2) may include third color conversion particles configured to convert light of the second color into light of the third color.

[0209] FIG. 17 is a plan view showing an example of one of the pixels according to embodiments of the present invention.

[0210] The pixel according to the present embodiments is substantially identical to the configuration of the pixel of FIG. 7, except for the first and second light-emitting elements (LD1, LD2), and therefore the same reference numbers and reference symbols are used for identical or similar components, and redundant descriptions are omitted.

[0211] Referring to FIG. 17, the 1-1 sub-pixel (SP1-1) may include the 1-1 light-emitting element (LD1-1), the 1-2 sub-pixel (SP1-2) may include the 1-2 light-emitting element (LD1-1), and the 1-3 sub-pixel (SP1-3) may include the 1-3 light-emitting element (LD1-3).

[0212] The first light-emitting element (LD1) may include an inorganic light-emitting diode, and the second light-emitting element (LD2) may include an organic light-emitting diode. For example, the 1-1 light-emitting element (LD1-1) may include an inorganic light-emitting diode that displays a red color, the 1-2 light-emitting element (LD1-2) may include an inorganic light-emitting diode that displays a green color, the 1-3 light-emitting element (LD1-3) may include an inorganic light-emitting diode that displays a blue color, and the 2nd light-emitting element (LD2) may include an organic light-emitting diode that displays a white color.

[0213] In one embodiment, each of the first to third light conversion patterns (CCP1 to CCP3, see FIG. 9) of the first to third sub-pixels (SP1-1 to SP1-3) may include scattering particles (SCT, see FIG. 9).

[0214] In one embodiment, each of the first to third light conversion patterns (CCP1 to CCP3, see FIG. 9) of the second sub-pixel (SP2) may include scattering particles (SCT, see FIG. 9). In one embodiment, the second sub-pixel (SP2) may include one light conversion pattern including scattering particles (SCT, see FIG. 9).

[0215] Figure 18 is a block diagram showing an embodiment of a display system.

[0216] Referring to FIG. 18, the display system (1000) may include a processor (1100) and a display device (1200).

[0217] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor (1100) can be electrically connected to other components of the display system (1000) via a bus system and control them.

[0218] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0219] The display system (1000) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. In addition, the display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0220] Figures 19 to 22 are perspective views showing application examples of the display system of Figure 18.

[0221] Referring to FIG. 19, the display system (1000) of FIG. 18 can be applied to a smart watch (2000) including a display unit (2100) and a strap unit (2200).

[0222] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0223] Referring to FIG. 20, the display system (1000) of FIG. 18 may be applied to an automotive display system (3000). Here, the automotive display system (3000) may include a computing system provided inside and / or outside a vehicle to provide image data.

[0224] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear seat display provided in a vehicle.

[0225] Referring to FIG. 21, the display system (1000) of FIG. 18 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0226] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0227] The frame (4100) may be equipped with a battery, a touch pad, a microphone, a camera, etc. In addition, the frame (4100) may be equipped with a projector that outputs light, a processor that controls light signals, etc.

[0228] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or the like.

[0229] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). At this time, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0230] Referring to FIG. 22, the display system (1000) of FIG. 18 can be applied to a head-mounted display device (500).

[0231] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0232] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be electrically connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in the form of eyeglass frames, helmets, etc.

[0233] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0234] Although specific embodiments and applications have been described herein, other embodiments and variations may be derived from the above description. Accordingly, the scope of the present invention is not limited to these embodiments, but extends to the claims set forth below, various obvious modifications, and equivalents.

[0235] The present invention can be applied to display devices and electronic devices including the same. For example, the present invention can be applied to digital TVs, 3D TVs, mobile phones, smart phones, tablet computers, VR devices, PCs, home electronic devices, laptop computers, PDAs, PMPs, digital cameras, music players, portable game consoles, navigation systems, and the like.

[0236] Although the present invention has been described with reference to the above embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims

1. A display panel containing pixels; A data driver providing data voltage to the above pixels; a gate driver providing a gate signal to the above pixel; and A controller comprising: a data driver and a gate driver; The above pixel is a first sub-pixel comprising a first light-emitting element; and A display device characterized by comprising a second sub-pixel including a plurality of second light-emitting elements.

2. A display device according to claim 1, characterized in that each of the plurality of second light-emitting elements is smaller than the first light-emitting element.

3. A display device according to claim 1, characterized in that the plurality of second light-emitting elements are electrically connected in parallel.

4. A display device according to claim 1, characterized in that each of the plurality of second light-emitting elements displays the same color as the first light-emitting element.

5. A display device according to claim 1, characterized in that any one of the plurality of second light-emitting elements displays a different color.

6. In the fifth paragraph, the first sub-pixel The 1-1 sub-pixel displaying the first color; 1-2 sub-pixels displaying the second color; and Contains 1-3 sub-pixels displaying a third color, The above plurality of second light-emitting elements A second-first light-emitting element displaying the first color; A second-2 light-emitting element displaying the second color; and A display device characterized by including a 2nd-3rd light-emitting element displaying the third color.

7. In the first paragraph, the first light-emitting element is turned on in the first mode, A display device, characterized in that the plurality of second light-emitting elements are turned off in the first mode.

8. In the 7th paragraph, the first light-emitting element is turned on in the second mode, A display device, characterized in that the plurality of second light-emitting elements are turned on in the second mode.

9. A display device according to claim 8, characterized in that the peak brightness in the second mode is greater than the peak brightness in the first mode.

10. In the first paragraph, the display panel is driven in one of the 1-1 mode, the 1-2 mode, and the 2nd mode, In the above 1-1 mode, the light-emitting time of the first light-emitting element is controlled according to the gradation, In the above 1-2 mode, the size of the driving current applied to the first light-emitting element is controlled according to the grayscale. In the second mode, the light-emitting time of the first light-emitting element and the magnitude of the driving current applied to the first light-emitting element are controlled according to the grayscale. A display device characterized in that the light-emitting time of the plurality of second light-emitting elements and the size of the driving current applied to the plurality of second light-emitting elements are controlled according to the gradation in the second mode.

11. In the 10th paragraph, the display panel includes sub-pixels including the first sub-pixel and the second sub-pixel, Each of the above sub-pixels A first sub-pixel circuit that controls the light-emitting time of each light-emitting element of the sub-pixels according to the above-mentioned gradation; and A display device characterized by including a second sub-pixel circuit that controls the size of the driving current applied to the light-emitting element according to the gradation.

12. In the 11th paragraph, the first light-emitting element is controlled by the first sub-pixel circuit in the 1-1 mode, is controlled by the second sub-pixel circuit in the 1-2 mode, and is controlled by the first sub-pixel circuit and the second sub-pixel circuit in the 2nd mode. A display device, characterized in that the plurality of second light-emitting elements are controlled by the first sub-pixel circuit and the second sub-pixel circuit in the second mode.

13. A display device according to claim 1, characterized in that the second sub-pixel displays a white color.

14. In the first paragraph, the first sub-pixel The 1-1 sub-pixel displaying the first color; 1-2 sub-pixels displaying the second color; and Contains 1-3 sub-pixels displaying a third color, The above 1-1 sub-pixel includes a first light conversion pattern, The above first and second sub-pixels include a second light conversion pattern, The above 1-3 sub-pixels include a third optical conversion pattern, A display device, characterized in that the second sub-pixel includes the first to third light conversion patterns.

15. A display device according to claim 14, characterized in that the first to third light conversion patterns in the second sub-pixel overlap each other.

16. In the first paragraph, the first sub-pixel The 1-1 sub-pixel displaying the first color; 1-2 sub-pixels displaying the second color; and Contains 1-3 sub-pixels displaying a third color, The above 1-1 sub-pixel includes a first color filter, The above first and second sub-pixels include a second color filter, The above 1-3 sub-pixels include a 3rd color filter, A display device, characterized in that the second sub-pixel does not include the first to third color filters.

17. A display panel containing pixels; A data driver providing data voltage to the above pixels; a gate driver providing a gate signal to the above pixel; and A controller comprising: a data driver and a gate driver; The above pixel is A first sub-pixel comprising a plurality of first-first light-emitting elements; A first-second sub-pixel comprising a plurality of first-second light-emitting elements; a first-third sub-pixel comprising a plurality of first-third light-emitting elements; and A display device characterized by comprising a second sub-pixel including a second light-emitting element.

18. In the 17th paragraph, the plurality of first-first light-emitting elements display a first color, The above plurality of first and second light-emitting elements display a second color, The above plurality of first-third light-emitting elements display a third color, A display device, characterized in that the second light-emitting element displays any one of the first to third colors.

19. A display panel containing pixels; A data driver providing data voltage to the above pixels; a gate driver providing a gate signal to the above pixel; and A controller comprising: a data driver and a gate driver; The above pixel is a first sub-pixel comprising a first light-emitting element comprising a weapon light-emitting diode; and A display device characterized by including a second sub-pixel including a second light-emitting element including an organic light-emitting diode.

20. A display device according to claim 19, characterized in that the second light-emitting element displays a white color.

Images