Semiconductor transistor using monolithic oxidized metal schottky gate and manufacturing method thereof

Abstract

A semiconductor transistor according to an embodiment of the present invention includes: a substrate; a gate layer formed on the substrate; a channel layer formed on the substrate; an insertion layer formed at an interface between the gate layer and the channel layer; and a first electrode and a second electrode coupled to respective ends of the channel layer, wherein the insertion layer is formed on a surface of the gate layer via a monolithic oxidation process.

Description

Semiconductor transistor using a monolithic oxidized metal Schottky gate and its manufacturing method

[0001] The present invention relates to a semiconductor transistor using a monolithic oxidized metal Schottky gate and a method for manufacturing the same.

[0002] Because the surface of a two-dimensional semiconductor has almost no unsaturated bonds, it is difficult to form a uniform thin film using atomic layer deposition equipment used in conventional transistor processes.

[0003] Additionally, defects that occur during the gate dielectric deposition process can cause problems such as hysteresis and subthreshold swing in the transistor.

[0004] Therefore, the MES-PET structure using the Schottky junction can solve the problem of high capacitance and gate dielectric, but it has the problem of difficulty in implementation due to the Fermi level pinning phenomenon in the two-dimensional semiconductor-metal junction.

[0005] Therefore, the present invention aims to provide an n-type transistor approaching the Boltzmann switching limit by forming a Schottky gate with a Fermi level de-pinned at a metal-semiconductor junction through a monolithic oxidation process of a three-dimensional metal gate.

[0006] In this regard, as a prior art document, Korean Patent No. 10-1056221 (Title of invention: Integrated low-leakage Schottky diode) is disclosed.

[0007] The present invention aims to provide a semiconductor transistor using a Schottky gate in which the Fermi level is de-pinned at a metal-semiconductor junction through a monolithic oxidation process of a three-dimensional metal gate, and a method for manufacturing the same, in order to solve the above-mentioned problems.

[0008] However, the technical tasks that this embodiment seeks to accomplish are not limited to the technical tasks described above, and other technical tasks may exist.

[0009] According to a first aspect of the present invention for achieving the above technical task, a semiconductor transistor comprises: a substrate; a gate layer formed on the substrate; a channel layer formed on top of the gate layer; an insertion layer formed at an interface between the gate layer and the channel layer; and a first electrode and a second electrode respectively bonded to both ends of the channel layer, wherein the insertion layer is formed on the surface of the gate layer by a monolithic oxidation process.

[0010] A semiconductor transistor according to a second aspect of the present invention comprises: a substrate; a channel layer formed on the substrate; a gate layer formed on top of the channel layer; an insertion layer formed at an interface between the gate layer and the channel layer; and a first electrode and a second electrode respectively bonded to both ends of the channel layer, wherein the insertion layer is a gate metal layer oxidized by an oxidation process.

[0011] A method for manufacturing a semiconductor transistor according to a third aspect of the present invention includes the steps of: providing a channel layer; forming a gate layer on a substrate; forming an insertion layer by oxidizing a surface of the gate layer using a monolithic oxidation process; arranging a channel layer on top of the insertion layer; and forming a first electrode and a second electrode respectively bonded to both ends of the channel layer.

[0012] A method for manufacturing a semiconductor transistor according to a fourth aspect of the present invention comprises the steps of forming a channel layer on a substrate; forming a first electrode and a second electrode respectively bonded to both ends of the channel layer; forming a gate metal layer on top of the channel layer; forming an insertion layer by oxidizing the gate metal layer using an oxidation process; and forming a gate layer on top of the insertion layer.

[0013] One embodiment of the present invention utilizes a three-dimensional metal gate structure to form an insertion layer, thereby suppressing an induced gap state and forming a Schottky junction. This enables switching at low voltages, and by controlling the threshold voltage based on the work function of the gate electrode, the depletion mode and enhancement mode of the transistor can be controlled.

[0014] Additionally, unlike conventional MESPETS, it uses a monolithic surface-oxidized gate rather than a direct metal-semiconductor bond, providing an insertion layer that reduces gate leakage current.

[0015] In addition, since one embodiment of the present invention can operate as a Schottky diode in addition to a transistor that is switched by a van der Waals Schottky gate, various functions can be implemented in one device.

[0016] FIG. 1 is a diagram illustrating a semiconductor transistor according to one embodiment of the present invention.

[0017] FIG. 2 is a cross-sectional view of a semiconductor transistor according to another embodiment of the present invention.

[0018] FIG. 3 is an exemplary diagram of a band alignment structure of a semiconductor transistor according to one embodiment of the present invention.

[0019] FIG. 4 is a flowchart illustrating a method for manufacturing a semiconductor transistor according to one embodiment of the present invention.

[0020] FIG. 5 is a drawing illustrating one embodiment of a method for manufacturing a semiconductor transistor of FIG. 4.

[0021] FIG. 6 is a flowchart illustrating a method for manufacturing a semiconductor transistor according to another embodiment of the present invention.

[0022] FIG. 7 is a drawing illustrating one embodiment of a method for manufacturing a semiconductor transistor of FIG. 6.

[0023] FIGS. 8 to 12 are drawings for explaining the characteristics of a semiconductor transistor manufactured according to one embodiment of the present invention.

[0024] Below, with reference to the attached drawings, embodiments of the present invention are described in detail so that those skilled in the art can easily implement them. However, the present invention may be implemented in various different forms and is not limited to the embodiments described herein. In the drawings, irrelevant parts have been omitted for clarity of description, and similar reference numerals have been used throughout the specification to indicate similar elements.

[0025] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected" but also the case where it is "electrically connected" with another element in between. Furthermore, when a part is said to "include" a component, this should be understood to mean that, unless specifically stated to the contrary, it may include other components rather than excluding them, and does not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0026] FIG. 1 is a drawing illustrating a semiconductor transistor according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor transistor according to another embodiment of the present invention.

[0027] Referring to FIG. 1, a semiconductor transistor includes a substrate (100), a gate layer (150) formed on the substrate (100), a channel layer (110) formed on top of the gate layer (150), an insertion layer (120) formed at an interface between the gate layer (150) and the channel layer (110), and a first electrode (130) and a second electrode (140) respectively bonded to both ends of the channel layer (110). Here, a method of forming the insertion layer (120) on the surface of the gate layer (150) by a monolithic oxidation process will be described in detail later with reference to FIG. 5.

[0028] Referring to FIG. 2, a semiconductor transistor includes a substrate (100), a channel layer (110) formed on the substrate (100), a gate layer (150) formed on top of the channel layer (110), an insertion layer (120) formed at an interface between the gate layer (150) and the channel layer (110), and a first electrode (130) and a second electrode (140) respectively bonded to both ends of the channel layer (110). At this time, the insertion layer (120) is formed on one side of the gate layer (150) by a monolithic oxidation process.

[0029] For example, the gate layer (150) may be formed on the lower side of the channel layer (110) or on the upper side of the channel layer (110). For example, the gate layer (150) may be made of a metal such as Ni or Cu, but is not limited thereto.

[0030] For example, as illustrated in FIG. 1, a semiconductor transistor may be formed in a bottom gate structure in which a gate layer (150), an insertion layer (120), and a channel layer (110) are sequentially stacked on a substrate (100). A method for manufacturing such a bottom gate structure will be described later with reference to FIG. 4.

[0031] As another example, as illustrated in FIG. 2, a semiconductor transistor may be formed with a top gate structure in which a channel layer (110), an insertion layer (120), and a gate layer (150) are sequentially stacked on a substrate (100). A method for manufacturing such a top gate structure will be described later with reference to FIGS. 6 and 7.

[0032] For example, the channel layer (110) may include at least one material selected from the group of transition metal chalcogenides consisting of MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, Bi2O2Se, InSe, In2Se3, PdS2, PdSe2, HfS2, HfSe2, ZrS2, and ZrSe2.

[0033] In addition, the first electrode (130) and the second electrode (140) may be respectively connected to both ends of the channel layer (110) to function as a source electrode and a drain electrode. Meanwhile, a separate gate electrode may be connected to one side of the gate layer (150). For example, each electrode may be made of a metal such as Sb, Au, Ti, Cr, Bi, Al, etc., but is not limited thereto.

[0034] FIG. 3 is an exemplary diagram of a band alignment structure of a semiconductor transistor according to one embodiment of the present invention.

[0035] Referring to FIG. 3, the insertion layer (120) is an oxide film formed on the surface of the gate layer (150) by a monolithic oxidation process, and can play a role in suppressing the electron wave function from transmitting from the gate layer (150) to the channel layer (110).

[0036] For example, since the insertion layer (120) is formed between the gate layer (150) and the channel layer (110), it can prevent the electron wave function from penetrating into the semiconductor band gap. That is, since the electron wave function is blocked by the insertion layer (120), metal-induced gap states (MIGS) can be suppressed and the Fermi level pinning phenomenon can be alleviated. Accordingly, the original electrical characteristics of the semiconductor can be maintained, and the performance of the device can be improved.

[0037] FIG. 4 is a flowchart for explaining a method for manufacturing a semiconductor transistor according to one embodiment of the present invention, and FIG. 5 is a drawing illustrating one embodiment of a method for manufacturing the semiconductor transistor of FIG. 4.

[0038] Referring to FIG. 4, a method for manufacturing a semiconductor transistor according to an embodiment of the present invention includes a step of providing a channel layer (110) (S110), a step of forming a gate layer (150) on a substrate (100) (S120), a step of forming an insertion layer (120) by oxidizing the surface of the gate layer (150) using a monolithic oxidation process, a step of arranging the channel layer (110) on top of the insertion layer (120) (S140), and a step of forming a first electrode (130) and a second electrode (140) respectively coupled to both ends of the channel layer (110) (S150). Here, the insertion layer (120) may be an oxide film that suppresses an electron wave function from transmitting from the gate layer (150) to the channel layer (110).

[0039] For example, a method for manufacturing a semiconductor transistor with a bottom gate structure can provide a channel layer (110) made of MoS2 with reference to FIG. 5(a). In addition, with reference to FIG. 5(b), a substrate (100) equipped with an existing patterned electrode can be used to form a gate layer (150). At this time, the structure of the patterned electrode is only one example and is not limited thereto. Thereafter, with reference to FIG. 5(c), a gate layer (150) can be formed on the substrate (100) by performing a lithography and deposition process. Subsequently, with reference to FIG. 5(d), an insertion layer (120) can be formed by oxidizing the surface of the gate layer (150) through an ozone treatment at 150 degrees for 30 minutes on the entire gate layer (150). That is, the insertion layer (120) can be an oxide film formed by monolithically oxidizing a portion of the surface of the gate layer (150) before the oxidation process. After the oxidation process illustrated in FIG. 5(d), the channel layer (110) can be transferred on top of the insertion layer (120) using a PPC (polyprophylene carbonate) / PDMS (polydemethylsiloxane) stamp. At this time, the gate layer (150) illustrated in FIG. 5(c) can be formed in a form in which the insertion layer (120) is laminated on top of the gate layer (150), as illustrated in FIG. 5(e). Thereafter, referring to FIG. 5(f), the first electrode (130) and the second electrode (140), which serve as source / drain electrodes, can be formed on both ends of the channel layer (110) through lithography and deposition processes. Accordingly, the semiconductor transistor of the bottom gate structure can be formed in a form in which the gate layer (150), the insertion layer (120), and the channel layer (110) are sequentially laminated on the substrate (100), as illustrated in FIG. 1.

[0040] FIG. 6 is a flowchart for explaining a method for manufacturing a semiconductor transistor according to another embodiment of the present invention, and FIG. 7 is a drawing illustrating one embodiment of a method for manufacturing the semiconductor transistor of FIG. 6.

[0041] Referring to FIG. 6, a method for manufacturing a semiconductor transistor according to another embodiment of the present invention includes a step of forming a channel layer (110) on a substrate (100) (S210), a step of forming a first electrode (130) and a second electrode (140) respectively bonded to both ends of the channel layer (110) (S220), a step of forming a gate metal layer (150-1) on top of the channel layer (110) (S230), a step of forming an insertion layer (120) by oxidizing the gate metal layer (150-1) using an oxidation process (S240), and a step of forming a gate layer (150) on top of the insertion layer (120) (S250). Here, the insertion layer (120) may be an oxide film that suppresses an electron wave function from transmitting from the gate layer (150) to the channel layer (110).

[0042] For example, a method for manufacturing a semiconductor transistor with a top gate structure can form a channel layer (110) on a substrate (100) with reference to FIG. 7(a). Then, with reference to FIG. 7(b), a first electrode (130) and a second electrode (140), which serve as source / drain electrodes, can be formed at both ends of the channel layer (110) through a lithography and deposition process. Thereafter, with reference to FIG. 7(c), a gate metal layer (150-1) can be formed on top of the channel layer (110) by performing a lithography and deposition process. Subsequently, with reference to FIG. 7(d), an oxidation process can be used to oxidize the gate metal layer (150-1) to form an insertion layer (120). At this time, the oxidation process includes, but is not limited to, an oxygen plasma process or an ozone treatment process. That is, the insertion layer (120) may be an oxide film formed by oxidizing the gate metal layer (150-1) prior to the oxidation process through the oxidation process. Next, as illustrated in FIG. 7(e), a gate layer (150) may be formed on top of the insertion layer (120) by performing lithography and deposition processes. Accordingly, a semiconductor transistor having a top gate structure may be formed in a form in which a channel layer (110), an insertion layer (120), and a gate layer (150) are sequentially stacked on a substrate (100), as illustrated in FIG. 2.

[0043] FIGS. 8 to 12 are drawings for explaining the characteristics of a semiconductor transistor manufactured according to one embodiment of the present invention.

[0044] FIG. 8(a) shows the transfer characteristics (Id-Vg characteristics) of a MESFET (Metal-Semiconductor Field-Effect Transistor) of a bottom gate structure according to one embodiment of the present invention, and FIG. 8(b) shows the transfer characteristics (Id-Vg characteristics) of a MESFET of a top gate structure according to another embodiment of the present invention.

[0045] As illustrated in Fig. 8(a), the semiconductor transistor of the present invention exhibits on / off switching at a gate voltage of less than 0.5 V, and in particular, the subthreshold swing (SS) close to the Boltzmann limit (60 mV / dec) at room temperature exhibits a subthreshold slope. In addition, when a Cu electrode (illustrated in Fig. 8(b)) having a lower work function than a Ni electrode (illustrated in Fig. 8(a)) is used, the size of the Schottky barrier formed at the channel layer and the gate metal interface decreases, thereby shifting the threshold voltage in the negative direction, indicating that the same operation is possible with a Cu electrode.

[0046] Referring to Fig. 9, the voltage transfer characteristics of an inverter composed of two-dimensional semiconductor transistors based on Schottky gates are shown. That is, an n-type transistor-based inverter fabricated by connecting semiconductor transistors in series exhibits a characteristic in which the output voltage changes as the VDD value increases, and the voltage gain shows a value of 40 V / V at VDD=2 V.

[0047] Referring to FIG. 10, the semiconductor transistor according to the present invention can perform functions as both a transistor and a diode. That is, since the semiconductor transistor has a device structure that can not only use a Schottky electrode as a gate but also operate as a Schottky diode, diode characteristics exhibiting rectifying characteristics were also confirmed.

[0048] Referring to FIG. 11, it is shown how the threshold voltage of a semiconductor transistor according to the present invention varies depending on the type of gate metal. A transistor using a Cu gate exhibits a threshold voltage at a low gate voltage, and the voltage range where the current begins to increase rapidly is lower than that of Ni. This means that Cu forms a lower Schottky barrier than Ni, resulting in a low threshold voltage. A transistor using a Ni gate begins to increase the current at a slightly higher gate voltage. This means that Ni forms a higher Schottky barrier than Cu, resulting in a high threshold voltage. In other words, the depletion mode and enhancement mode of the transistor can control the threshold voltage by utilizing a metal-semiconductor junction with a de-pinned Fermi level.

[0049] Fig. 12(a) shows the output characteristics of a large-area MoS2MESFET array according to the present invention, and Fig. 12(b) shows the transfer characteristics of a single MoS2MESFET according to the present invention. That is, in order to confirm uniform device characteristics even over a large area, an array device was manufactured using a MoS2 film synthesized by a CVD (chemical vapor deposition) method, and when the characteristics were evaluated, it was confirmed that it showed similar performance to a unit device.

[0050] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will readily appreciate that the present invention can be readily modified into other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single entity may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined manner.

[0051] The scope of the present invention is indicated by the claims described below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

Claims

1. In semiconductor transistors, substrate; A gate layer formed on the above substrate; A channel layer formed on top of the gate layer; An insertion layer formed at the interface between the gate layer and the channel layer; and Including a first electrode and a second electrode respectively coupled to both ends of the channel layer, A semiconductor transistor, wherein the above-mentioned insertion layer is formed on one side of the gate layer by a monolithic oxidation process.

2. In semiconductor transistors, substrate; A channel layer formed on the above substrate; A gate layer formed on top of the channel layer; An insertion layer formed at the interface between the gate layer and the channel layer; and Including a first electrode and a second electrode respectively coupled to both ends of the channel layer, A semiconductor transistor, wherein the above-mentioned insert layer is a gate metal layer oxidized by an oxidation process.

3. In paragraph 1 or 2, A semiconductor transistor, wherein the above-mentioned insertion layer is an oxide film that suppresses the electron wave function from transmitting from the gate layer to the channel layer.

4. In paragraph 1 or 2, A semiconductor transistor, wherein the channel layer comprises at least one material selected from the group of transition metal chalcogenides consisting of MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, Bi2O2Se, InSe, In2Se3, PdS2, PdSe2, HfS2, HfSe2, ZrS2, and ZrSe2.

5. In a method for manufacturing a semiconductor transistor, Step of preparing the channel layer; A step of forming a gate layer on a substrate; A step of forming an insertion layer by oxidizing the surface of the gate layer using a monolithic oxidation process; A step of arranging a channel layer on top of the above insertion layer; and A method for manufacturing a semiconductor transistor, comprising the step of forming a first electrode and a second electrode respectively coupled to both ends of the channel layer.

6. In a method for manufacturing a semiconductor transistor, A step of forming a channel layer on a substrate; A step of forming a first electrode and a second electrode respectively coupled to both ends of the channel layer; A step of forming a gate metal layer on top of the above channel layer; A step of forming an insertion layer by oxidizing the gate metal layer using an oxidation process; and A method for manufacturing a semiconductor transistor, comprising the step of forming a gate layer on top of the above-mentioned insertion layer.

7. In paragraph 5 or 6, A method for manufacturing a semiconductor transistor, wherein the above-mentioned insertion layer is an oxide film that suppresses the electron wave function from transmitting from the gate layer to the channel layer.

8. In paragraph 5 or 6, A method for manufacturing a semiconductor transistor, wherein the channel layer comprises at least one material selected from the group of transition metal chalcogenides consisting of MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, Bi2O2Se, InSe, In2Se3, PdS2, PdSe2, HfS2, HfSe2, ZrS2, and ZrSe2.

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