A GaN-based CMOS device and a method for fabricating the same

Abstract

The application discloses a GaN-based CMOS device and a preparation method thereof. The GaN-based CMOS device comprises a substrate, a buffer layer, an epitaxial layer and electrodes. The lower surface of the buffer layer is in contact with the substrate. The epitaxial layer is composed of a PMOS region and an NMOS region on the upper surface of the buffer layer. The electrodes comprise an NMOS Schottky gate electrode, an NMOS ohmic electrode arranged in the NMOS region, a PMOS ohmic electrode and a PMOS Schottky gate electrode arranged in the PMOS region. The NMOS Schottky gate electrode and the PMOS Schottky gate electrode are both in a fin structure. The GaN-based CMOS device has a greatly improved carrier mobility, a stronger gate control ability, a smaller gate leakage and a wider practical range.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronics, and particularly relates to a GaN-based CMOS device and a preparation method thereof. BACKGROUND

[0002] Complementary metal-oxide-semiconductor transistor (CMOS) has many advantages such as low power consumption, low power supply voltage, high speed, strong anti-interference ability and high integration, and therefore develops rapidly and becomes the mainstream technology of current large-scale integrated circuits. The technology is developed on the basis of previous PMOS and NMOS technologies, and combines the two processes to manufacture the devices on the same silicon substrate. However, the development of silicon devices has reached the limit of the material, and it is difficult to further develop. Therefore, other alternative materials are considered as the substrate of CMOS devices to promote the development of semiconductor devices.

[0003] Wide-bandgap semiconductor materials represented by gallium nitride (GaN) have a high critical breakdown field, and can realize lower capacitance and on-resistance under the same breakdown voltage, and are considered as the ideal next-generation power device material. GaN power switch devices have advantages such as low energy consumption, fast switching speed and large power, and can miniaturize and lighten the power electronic switching device, improve the efficiency of electric energy conversion, and effectively reduce the system manufacturing cost. Using GaN power switch devices to replace traditional Si-based devices can effectively improve the utilization rate of electric energy, alleviate the energy crisis, and has a very broad market application prospect.

[0004] At present, the CMOS process production line is generally built on the basis of silicon material, and therefore the silicon substrate GaN-based power device becomes the first choice to reduce the manufacturing cost. In the existing GaN CMOS scheme, a P channel is generally formed by using a secondary epitaxy technology on the basis of an AlGaN / GaN epitaxial structure, and the process is relatively complex and the price is relatively high. In the traditional transistor structure, the gate that controls the current flow can only control the turn-on and turn-off of the circuit on one side of the gate, and belongs to a planar structure. The existing technology cannot solve the problem of regulating the threshold voltage of NMOS and PMOS. SUMMARY

[0005] This section is intended to summarize some aspects of the embodiments of the present application and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the abstract and title of the specification to avoid obscuring the purpose of this section, the abstract and the title, and such simplifications or omissions cannot be used to limit the scope of the present application.

[0006] In view of the above and / or problems existing in the prior art, the present application is proposed.

[0007] One of the purposes of the present application is to provide a GaN-based CMOS device, which is directly grown with an AlN layer and a second GaN layer from bottom to top in a PMOS region, forms a hole channel between the two layers, and is enhanced by depleting channel electrons or holes under the gate and preserving electron or hole channels under the source-drain region by using a Fin structure.

[0008] To solve the above technical problems, the present application provides the following technical solutions: a GaN-based CMOS device, comprising,

[0009] a substrate;

[0010] a buffer layer, a lower surface of the buffer layer being in contact with the substrate;

[0011] an epitaxial layer, composed of a PMOS region and an NMOS region on an upper surface of the buffer layer; and

[0012] an electrode, comprising an NMOS Schottky gate electrode, an NMOS ohmic electrode arranged in the NMOS region, and a PMOS ohmic electrode and a PMOS Schottky gate electrode arranged in the PMOS region;

[0013] wherein the NMOS Schottky gate electrode and the PMOS Schottky gate electrode are both in a fin structure.

[0014] As a preferred scheme of the GaN-based CMOS device of the present application, the substrate comprises one of silicon, sapphire, silicon carbide, or gallium nitride.

[0015] As a preferred scheme of the GaN-based CMOS device of the present application, the PMOS region is sequentially provided with a GaN layer, an AlGaN layer, a buffer layer, an AlN layer, and a second GaN layer from bottom to top.

[0016] The GaN layer is in contact with the buffer layer, a hole channel is formed between the AlN layer and the second GaN layer, the PMOS ohmic electrode is arranged on both sides of the second GaN layer, and the second GaN layer is in contact with the PMOS Schottky gate electrode.

[0017] As a preferred scheme of the GaN-based CMOS device of the present application, the NMOS region is sequentially provided with a GaN layer and an AlGaN layer from bottom to top, an electron channel is formed between the GaN layer and the AlGaN layer, the NMOS ohmic electrode is arranged on both sides of the AlGaN layer, and the AlGaN layer is in contact with the NMOS Schottky gate electrode.

[0018] As a preferred scheme of the GaN-based CMOS device, the GaN layer and the AlGaN layer are both non-doped semiconductors, the thickness of the GaN layer is 50-5000 nm, and the thickness of the AlGaN layer is 5-100 nm.

[0019] As a preferred scheme of the GaN-based CMOS device, the second GaN layer and the AlN layer are both non-doped semiconductors, the thickness of the second GaN layer is 5-100 nm, and the thickness of the AlN layer is 50-5000 nm.

[0020] As a preferred scheme of the GaN-based CMOS device, the width of the fin-shaped structure of the NMOS Schottky gate electrode and the PMOS Schottky gate electrode is less than 100 nm.

[0021] As a preferred scheme of the GaN-based CMOS device, the buffer layer comprises one of graded AlGaN, AlGaN / AlN superlattice, and high-low temperature AlN, and the thickness of the buffer layer is 10-3000 nm.

[0022] Another object of the present application is to provide a preparation method of the GaN-based CMOS device as described above, comprising,

[0023] The buffer layer and the epitaxial layer are sequentially formed on the surface of the substrate by metal organic chemical vapor deposition;

[0024] The epitaxial layer is etched by using photoetching technology and dry etching technology to realize electrical isolation of the PMOS region and the NMOS region;

[0025] The NMOS ohmic electrode is formed on both sides of the NMOS region by electron beam evaporation or magnetron sputtering;

[0026] The PMOS ohmic electrode is formed on both sides of the PMOS region by electron beam evaporation or magnetron sputtering;

[0027] The PMOS Schottky gate electrode is formed on the surface of the PMOS region by electron beam evaporation or magnetron sputtering.

[0028] The NMOS Schottky gate electrode is formed on the surface of the NMOS region by photoetching technology, electron beam evaporation or magnetron sputtering;

[0029] As a preferred scheme of the preparation method of the GaN-based CMOS device, the NMOS ohmic electrode is a Ti / Al / Ni / Au stack.

[0030] The PMOS ohmic electrode is a nickel layer.

[0031] As a preferred scheme of the preparation method of the GaN-based CMOS device, in the method, the NMOS Schottky gate electrode is formed by using Ni, Pt or TiN as the Schottky metal to deplete the electron channel under the gate.

[0032] The PMOS Schottky gate electrode is formed by using Ti, W or Mo as the Schottky metal to deplete the hole channel under the gate.

[0033] Compared with the prior art, the GaN-based CMOS device has the following beneficial effects:

[0034] The GaN-based CMOS device provided by the application is different from the PMOS part of the conventional p-GaN channel device in that the device is directly grown with an AlN layer and a second GaN layer from bottom to top in the PMOS region, and a hole channel is formed between the two layers, and the device is enhanced by using the Fin structure to deplete the channel electrons or holes under the gate and reserve the electron or hole channel under the source-drain region, so that the device has a greatly improved carrier mobility, a stronger gate control ability, a smaller gate leakage and a wider practical range.

[0035] The application further provides a preparation method of the GaN-based CMOS device, which uses an electron beam evaporation method or a magnetron sputtering method to prepare the Fin gate structure, so as to improve the carrier mobility and reduce the gate leakage current. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative labor. Among them:

[0037] Figure 1 Fig. 1 is a structural schematic diagram of the device of the embodiment 1 of the application;

[0038] Figure 2 Fig. 2 is a structural schematic diagram of the device of the comparative example 1;

[0039] Figure 3 Fig. 3 is a comparison diagram of the threshold voltage of the NMOS tube of the embodiment 1 and the comparative example 1 of the application;

[0040] Figure 4 Fig. 4 is a comparison diagram of the threshold voltage of the PMOS tube of the embodiment 1 and the comparative example 1 of the application;

[0041] Figure 5 Fig. 5 is a diagram of the threshold voltage movement of the NMOS tube of the GaN-based CMOS device in the embodiment 2 of the application when different Al components are selected;

[0042] Figure 6 Threshold voltage shift of PMOS for GaN-based CMOS device with different Al composition in embodiment 2 of the present application;

[0043] Figure 7 Threshold voltage shift of NMOS for GaN-based CMOS device with different gate metal in embodiment 3 of the present application;

[0044] Figure 8 Threshold voltage shift of PMOS for GaN-based CMOS device with different gate metal in embodiment 3 of the present application. DETAILED DESCRIPTION

[0045] In order to make the above objectives, features and advantages of the present application more apparent, the specific embodiments of the present application will be described in detail below with the embodiments of the specification.

[0046] In the following description, a lot of specific details are set forth in order to provide a thorough understanding of the present application, however, the present application can be practiced in other manners different from those described herein, and those skilled in the art can make similar generalization without departing from the spirit of the present application, therefore, the present application is not limited to the specific embodiments disclosed below.

[0047] Secondly, the "one embodiment" or "embodiment" referred to herein means that the specific features, structures or characteristics can be included in at least one implementation of the present application. The "in one embodiment" appearing in different places in the specification does not mean the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments.

[0048] Embodiment 1

[0049] As shown in Figure 1 A GaN-based CMOS device provided by the first embodiment of the present application includes a substrate 100, a buffer layer 200, and an epitaxial layer. The substrate 100 is a silicon, sapphire, silicon carbide or gallium nitride substrate. The lower surface of the buffer layer 200 is in contact with the substrate 100. If the silicon or sapphire is selected as the substrate 100, the buffer layer 200 is an AlGaN buffer layer; if the gallium nitride substrate is selected, the buffer layer 200 is a GaN buffer layer, and the thickness of the buffer layer 200 is generally 50-1000 nm.

[0050] The epitaxial layer is composed of a PMOS region 301 and an NMOS region 302 located on the upper surface of the buffer layer 200;

[0051] The PMOS region 300 is sequentially provided with a GaN layer 301a, an AlGaN layer 301b, a buffer layer 301c, an AlN layer 301d and a second GaN layer 301e from bottom to top, the GaN layer 301a is in contact with the buffer layer 200, and a positive-charged hole is induced at the second GaN / AlN interface by using the strong spontaneous polarization effect of the second GaN / AlN and the piezoelectric polarization effect caused by the large lattice mismatch between the second GaN / AlN, so as to form a hole channel; the PMOS Schottky gate electrode 404 is arranged in the middle of the second GaN layer 301e, the PMOS Schottky gate electrode 404 is made into a fin structure, the fin width is less than 100 nm, the hole channel below is depleted, and the bottom of the PMOS Schottky gate electrode 404 is in contact with the buffer layer 301c; the PMOS ohmic electrode 403 is arranged on the second GaN layer 301e on both sides of the PMOS Schottky gate electrode 404; the second GaN layer 301e and the AlN layer 301d are non-doped semiconductors, and the thicknesses are 20 nm and 500 nm respectively; and the buffer layer 301c is an AlGaN buffer layer, and the thickness is 500 nm.

[0052] The NMOS region is sequentially provided with a GaN layer 302a and an AlGaN layer 302b from bottom to top, and an electron channel is formed between the GaN layer 302a and the AlGaN layer 302b (the thickness of the GaN is much greater than that of the AlGaN, the GaN is completely relaxed, only the spontaneous polarization exists, the piezoelectric polarization and the spontaneous polarization exist in the AlGaN, the negative-charged electron is generated at the heterojunction interface, and the electron channel is formed); the NMOS Schottky gate electrode 401 is arranged in the middle of the AlGaN layer 302b, the NMOS Schottky gate electrode 401 is made into a fin structure, the fin width is less than 100 nm, the electron channel below is depleted, and the bottom of the NMOS Schottky gate electrode 401 is in contact with the buffer layer 200; the NMOS ohmic electrode 402 is arranged on the AlGaN layer 302b on both sides of the NMOS Schottky gate electrode 401, and the GaN layer 302a and the AlGaN layer 302b are non-doped semiconductors, and the thicknesses are 500 nm and 20 nm respectively.

[0053] The specific manufacturing process of the GaN-based CMOS device is as follows:

[0054] (1) A metal organic chemical vapor deposition method is adopted to sequentially form a buffer layer and epitaxial layers including a GaN layer, an AlGaN layer, a buffer layer, an AlN layer and a second GaN layer on the surface of a substrate;

[0055] (2) Photolithography and dry etching techniques are used to etch the epitaxial layer including GaN layer, AlGaN layer, buffer layer, AlN layer and second GaN layer to achieve electrical isolation between PMOS region and NMOS region;

[0056] (3) NMOS ohmic electrodes are formed on both sides of the AlGaN layer in the NMOS region by magnetron sputtering. The sputtering targets used in the magnetron sputtering method are titanium targets, aluminum targets, nickel targets, and gold targets. The magnetron sputtering method is carried out in an argon atmosphere, followed by annealing in a nitrogen atmosphere to achieve ohmic contact. The annealing temperature is 400-900℃ and the annealing time is 0.5-6min.

[0057] (4) PMOS ohmic electrodes are formed on both sides of the second GaN layer in the PMOS region by magnetron sputtering. The sputtering target used in the magnetron sputtering method is a nickel target, and the magnetron sputtering method is carried out in an argon atmosphere filled with oxygen.

[0058] (5) A PMOS Schottky Fin gate electrode is formed on the surface of the second GaN layer in the PMOS region by magnetron sputtering. The Fin structure is made of TiN and depletes the hole channel below the gate.

[0059] (6) Using photolithography and magnetron sputtering, an NMOS Schottky Fin gate electrode is formed on the surface of the AlGaN layer in the NMOS region of the device. The Fin structure is made of TiN to deplete the electron channel below the gate.

[0060] Comparative Example 1

[0061] The structural schematic diagram of the Finless structure device in Comparative Example 1 is shown below. Figure 2 As shown.

[0062] The electrodes in steps (3) and (6) of Example 1 are made into ordinary electrodes without Fin structure, and the rest are the same as in Example 1.

[0063] The I of the device measured by the semiconductor parameter analyzer ds -V gs Characteristics. A comparison of the threshold voltages of the n-MOSFETs in Example 1 and Comparative Example 1 is shown in the figure below. Figure 3 As shown in the figure. A comparison of the threshold voltages of the p-MOSFETs in Example 1 and Comparative Example 1 is shown in the figure. Figure 4 As shown.

[0064] Depend on Figure 3 It can be seen that the threshold voltage of an NMOS transistor with a fin structure is positively shifted compared to an NMOS transistor without a fin structure. This is due to... Figure 4 It can be seen that the threshold voltage of a PMOS transistor with a fin structure is negatively shifted compared to a PMOS transistor without a fin structure.

[0065] Example 2

[0066] In this Example 2, based on Comparative Example 1, the AlGaN composition is adjusted to Al 0.3 Ga 0.7 N, Al 0.6 Ga 0.4 N, AlN.

[0067] The I of the device measured by the semiconductor parameter analyzer ds -V gs Characteristics. Threshold voltage shift graph of n-MOS transistor with different Al components is shown below. Figure 5 As shown in the figure. The threshold voltage shift of the p-MOS transistor with different Al components is shown in the figure. Figure 6 As shown.

[0068] Depend on Figure 5 As can be seen, for NMOS transistors, the higher the Al content, the greater the concentration of two-dimensional electron gas, the greater the saturation current, and the more negative the threshold voltage. Correspondingly, with an Al content of 0.3, the threshold voltage is -2V and the saturation current is 1mA; with an Al content of 0.6, the threshold voltage is -3V and the saturation current is 5mA; and with an Al content of 1, the threshold voltage is -4V and the saturation current is 10mA.

[0069] Depend on Figure 6 It can be seen that for PMOS transistors, the higher the Al content, the higher the two-dimensional hole concentration, the larger the saturation current, and the more positive the threshold voltage. The corresponding Al content is 0.3, with a threshold voltage of 2V and a saturation current of 1mA; Al content is 0.6, with a threshold voltage of 3V and a saturation current of 5mA; and Al content is 1, with a threshold voltage of 4V and a saturation current of 10mA.

[0070] Al with low Al content 0.3 Ga 0.7 N / GaN heterojunction materials exhibit good 2DEG confinement and can effectively suppress current collapse effects. GaN / high-Al content Al 0.6 Ga 0.4 In N / GaN or GaN / AlN heterojunction materials, two-dimensional hole gas is generated at the channel, which can effectively improve the hole carrier concentration and mobility.

[0071] Example 3

[0072] Based on Example 1, Example 3 selects different gate electrode materials, namely W, Mo, and TiN, for NMOS and PMOS.

[0073] The threshold voltage variation of NMOS transistors with different gate metals is shown in the figure below. Figure 7 As shown, using TiN as the Schottky gate for the n-channel can shift the threshold voltage of the NMOS positively, resulting in a larger threshold voltage.

[0074] The threshold voltage variation diagram of different metals of PMOS is shown in Fig. Figure 8 As can be seen, the adoption of TiN as the Schottky gate of p-channel can make the threshold voltage of PMOS negatively shift, and obtain greater negative threshold voltage (the threshold voltage is farther away from 0V), which is beneficial to the realization of CMOS logic device.

[0075] The application provides a fin-shaped (Fin) gate structure GaN-based CMOS device, which comprises a substrate, a buffer layer, an epitaxial layer and an electrode, and the epitaxial layer comprises a GaN layer, an AlGaN layer, a Buffer layer, an AlN layer and a GaN layer arranged in sequence, and the epitaxial layer is provided with an ohmic electrode on a source-drain region and a Schottky electrode on a gate region. The PMOS part of the CMOS device is different from a conventional p-GaN channel device, and the AlN layer and the GaN layer are directly grown from bottom to top in the PMOS region, and a hole channel is formed between the two layers. The device is enhanced by utilizing the Fin structure to deplete the channel electrons or holes under the gate and reserve the electron or hole channel under the source-drain region. The width of the Fin is less than 100nm, which is beneficial to the transportation of electrons between the metal and the semiconductor, and the transconductance is greater. The GaN-based CMOS device of the application has greater carrier mobility, stronger gate control ability, smaller gate leakage and wider practical range.

[0076] The application further provides a preparation method of the GaN-based CMOS device, and the Fin gate structure is prepared by using an electron beam evaporation method or a magnetron sputtering method, which is beneficial to improving the carrier mobility and reducing the gate leakage current.

[0077] It should be noted that the above examples are only used to illustrate the technical solutions of the application and not to limit the application. Although the application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the application, and all should be covered in the scope of the claims of the application.

Claims

1. A GaN-based CMOS device, characterized in that: include, Substrate (100); A buffer layer (200) has a lower surface that contacts the substrate (100). The epitaxial layer (300) is composed of a PMOS region (301) and an NMOS region (302) located on the upper surface of the buffer layer (200); and, Electrode (400) includes an NMOS Schottky gate electrode (401) and an NMOS ohmic electrode (402) disposed in the NMOS region (302), and a PMOS ohmic electrode (403) and a PMOS Schottky gate electrode (404) disposed in the PMOS region (301); Both the NMOS Schottky gate electrode (401) and the PMOS Schottky gate electrode (404) are fin-shaped structures. The PMOS region (301) is provided with GaN layer (301a), AlGaN layer (301b), buffer layer (301c), AlN layer (301d), and second GaN layer (301e) from bottom to top; The GaN layer (301a) is in contact with the buffer layer (200), a hole channel is formed between the AlN layer (301d) and the second GaN layer (301e), the PMOS ohmic electrode (403) is provided on both sides of the second GaN layer (301e), and the second GaN layer (301e) is in contact with the PMOS Schottky gate electrode (404).

2. The GaN-based CMOS device as described in claim 1, characterized in that: The substrate (100) includes one of silicon, sapphire, silicon carbide or gallium nitride substrates.

3. The GaN-based CMOS device as described in claim 1, characterized in that: The second GaN layer (301e) and the AlN layer (301d) are both undoped semiconductors. The thickness of the second GaN layer (301e) is 5-100 nm, and the thickness of the AlN layer (301d) is 50-5000 nm.

4. The GaN-based CMOS device as described in claim 3, characterized in that: The NMOS region (302) is provided with a GaN layer (302a) and an AlGaN layer (302b) from bottom to top. An electron channel is formed between the GaN layer (302a) and the AlGaN layer (302b). The NMOS ohmic electrode (402) is provided on both sides of the AlGaN layer (302b). The AlGaN layer (302b) is in contact with the NMOS Schottky gate electrode (401).

5. The GaN-based CMOS device as described in claim 4, characterized in that: The GaN layers (301a, 302a) and the AlGaN layers (301b, 302b) are both undoped semiconductors. The GaN layers (301a, 302a) have a thickness of 50–5000 nm, and the AlGaN layers (301b, 302b) have a thickness of 5–100 nm.

6. The GaN-based CMOS device according to any one of claims 1 to 5, characterized in that: The width of the fin structure of both the NMOS Schottky gate electrode (401) and the PMOS Schottky gate electrode (404) is less than 100 nm.

7. The GaN-based CMOS device as described in claim 6, characterized in that: The NMOS ohmic electrode is a Ti / Al / Ni / Au stack; The PMOS ohmic electrode is a nickel layer.

8. The method for fabricating a GaN-based CMOS device according to any one of claims 1 to 7, characterized in that: include, A buffer layer and an epitaxial layer are sequentially formed on the substrate surface using metal-organic chemical vapor deposition. Photolithography and dry etching techniques are used to etch the epitaxial layer to achieve electrical isolation between the PMOS and NMOS regions; NMOS ohmic electrodes are formed on both sides of the NMOS region using electron beam evaporation or magnetron sputtering. PMOS ohmic electrodes are formed on both sides of the PMOS region using electron beam evaporation or magnetron sputtering. PMOS Schottky gate electrodes are formed on the surface of the PMOS region using electron beam evaporation or magnetron sputtering. An NMOS Schottky gate electrode is formed on the surface of the NMOS region using photolithography, electron beam evaporation, or magnetron sputtering.

9. The method for fabricating a GaN-based CMOS device as described in claim 8, characterized in that: The formation of the NMOS Schottky gate electrode uses Ni, Pt, or TiN as the Schottky metal to deplete the electron channel below the gate. The formation of the PMOS Schottky gate electrode uses Ti, W, or Mo as the Schottky metal to deplete the hole channel beneath the gate.

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