Light-emitting device-thin film transistor integration structure and manufacturing method therefor

Abstract

The present invention relates to a light-emitting device-thin film transistor integration structure and a manufacturing method therefor. The integration structure according to an embodiment includes: a substrate; a channel layer of a thin film transistor, which is formed on the substrate; an intermediate insulating layer formed on a first region of the channel layer; a light-emitting device formed on the intermediate insulating layer and including a lower electrode layer protruding by a preset length; a wiring layer formed on the protruding region of the lower electrode layer; and a gate insulator, a gate electrode, a first electrode, and a second electrode of the thin film transistor, which are formed on a second region of the channel layer, wherein the wiring layer, the gate electrode, the first electrode, and the second electrode may be simultaneously formed through a single wiring process and patterning process.

Description

Light-emitting device - Thin-film transistor integration structure and manufacturing method thereof

[0001] The present invention relates to an integration structure of a light-emitting element and a thin film transistor, and more specifically, to a technical idea for implementing an integration structure through a simplified manufacturing process.

[0002] The existing integrated structure of a light-emitting element and a thin film transistor applies an additional process of forming a light shielding wall to prevent light output from the light-emitting element from entering the thin film transistor.

[0003] That is, many processes are currently being applied to implement integration structures, and efforts are being made to simplify the manufacturing process of integration structures to improve productivity and margins.

[0004] The present invention aims to provide an integration structure capable of depositing a light-emitting element structure on a lower electrode layer with high quality, and a method for manufacturing the same.

[0005] In addition, the present invention seeks to provide an integration structure and a manufacturing method thereof capable of simultaneously forming a wiring layer and a plurality of electrodes through a single process and a patterning process.

[0006] In addition, the present invention seeks to provide an integration structure and a manufacturing method thereof that can more easily form a light-emitting element by depositing and etching multiple layers at once in a single chamber.

[0007] In addition, the present invention seeks to provide an integration structure and a manufacturing method thereof capable of forming a high-quality semiconductor thin film at a low temperature by supplying additional energy during the process of depositing a semiconductor thin film of a light-emitting element.

[0008] In addition, the present invention seeks to provide an integration structure and a manufacturing method thereof that can improve productivity by simplifying the manufacturing process.

[0009] An integration structure according to one embodiment of the present invention includes a substrate, a channel layer of a thin film transistor formed on an upper portion of the substrate, an intermediate insulating layer formed on an upper portion of a first region of the channel layer, a light emitting element having a lower electrode layer formed on an upper portion of the intermediate insulating layer and protruding by a predetermined length, a wiring layer formed on a protruding region of the lower electrode layer, and a gate insulator, a gate electrode, a first electrode, and a second electrode of the thin film transistor formed on an upper portion of a second region of the channel layer, wherein the wiring layer, the gate electrode, the first electrode, and the second electrode can be formed simultaneously through a single wiring process and a patterning process.

[0010] According to one side, the lower electrode layer may be a reflective layer containing a highly reflective metal material.

[0011] According to one side, the semiconductor thin film of the light-emitting element can be formed by supplying additional energy based on at least one of an ion beam, an electron beam, plasma, ultraviolet rays, a laser, and LED light during a deposition process based on at least one of a physical deposition method and a chemical deposition method.

[0012] According to one side, the integration structure may further include a first barrier rib formed on a first side of the light-emitting element over the lower electrode layer and a second barrier rib formed on a second side of the light-emitting element over the channel layer.

[0013] According to one side, the first electrode is formed adjacent to the second barrier rib on the upper side of the channel layer and can be electrically connected to the upper electrode layer provided in the light-emitting element.

[0014] According to one side, the light-emitting element may include a lower electrode layer, an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and an upper electrode layer.

[0015] According to one side, the substrate may include at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate.

[0016] A method for manufacturing an integration structure according to an embodiment of the present invention may include the steps of sequentially forming a light-emitting element layer having a channel layer, an intermediate insulating layer, and a lower electrode layer of a thin film transistor on a substrate, the step of etching layers of the light-emitting element layer except for the lower electrode layer to form a light-emitting element, the step of etching the lower electrode layer formed in a second region of the channel layer, the step of forming a plurality of partition walls on a side surface of the light-emitting element, and the step of etching the intermediate insulating layer formed on an upper portion of the second region of the channel layer to form a gate insulator, the step of forming a wiring layer on an upper portion of a region protruding from the light-emitting element by a predetermined length in the lower electrode layer formed on a first region of the channel layer, and forming a gate electrode of the thin film transistor on an upper portion of the gate insulator formed on the second region of the channel layer, and forming a first electrode and a second electrode of the thin film transistor in an exposed region of the channel layer, wherein the wiring layer, the gate electrode, the first electrode, and the second electrode are formed simultaneously through a single wiring process and a patterning process.

[0017] According to one side, the step of forming a plurality of partition walls and a gate insulator may include forming a first partition wall formed on a first side of the light-emitting element over a lower electrode layer and a second partition wall formed on a second side of the light-emitting element over a channel layer.

[0018] According to one side, the step of simultaneously forming may include a step of depositing a metal material on the top of the structure on which the gate insulator is formed, and a step of patterning the deposited metal material to simultaneously form a wiring layer, a gate electrode, a first electrode, and a second electrode.

[0019] According to one side, the gate electrode is formed on the upper side of the gate insulator, the first electrode is formed adjacent to the second barrier rib on the upper side of the channel layer, and can be electrically connected to the upper electrode layer provided in the light-emitting element.

[0020] According to one side, the step of sequentially forming may include supplying additional energy based on at least one of an ion beam, an electron beam, plasma, ultraviolet rays, a laser, and LED light during a process of depositing a semiconductor thin film of a light-emitting element layer based on at least one of a physical deposition method and a chemical deposition method.

[0021] According to one side, the sequential forming step may include a step of forming an n-type semiconductor layer on top of a lower electrode layer, a step of forming an active layer on top of the n-type semiconductor layer, a step of forming a p-type semiconductor layer on top of the active layer, and a step of forming an upper electrode layer on top of the p-type semiconductor layer.

[0022] According to one side, the lower electrode layer is a reflective layer including a highly reflective metal material, and the substrate may include at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate.

[0023] According to one embodiment, the present invention can deposit a light-emitting element structure on a lower electrode layer with high quality.

[0024] In addition, the present invention can simultaneously form a wiring layer and a plurality of electrodes through a single process and a patterning process.

[0025] In addition, the present invention can more easily form a light-emitting element by depositing and etching multiple layers at once in a single chamber.

[0026] In addition, the present invention can form a high-quality semiconductor thin film at a low temperature by supplying additional energy during the process of depositing the semiconductor thin film of the light-emitting element.

[0027] In addition, the present invention can improve productivity by simplifying the manufacturing process.

[0028] FIG. 1 is a drawing for explaining an integration structure according to one embodiment.

[0029] FIG. 2 is a drawing for explaining a method for manufacturing an integration structure according to one embodiment.

[0030] FIGS. 3A to 3H are drawings for more specifically explaining a method for manufacturing an integration structure according to one embodiment.

[0031] Below, various embodiments of this document are described with reference to the attached drawings.

[0032] The examples and terms used herein are not intended to limit the technology described in this document to a particular embodiment, but should be understood to encompass various modifications, equivalents, and / or alternatives of the embodiments.

[0033] In the following description of various embodiments, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the invention, the detailed description will be omitted.

[0034] The terms described below are defined based on their functions in various embodiments, and may vary depending on the intent or custom of the user or operator. Therefore, their definitions should be based on the contents of this specification.

[0035] In connection with the description of the drawings, similar reference numerals may be used for similar components.

[0036] A singular expression may include a plural expression unless the context clearly indicates otherwise.

[0037] In this document, expressions such as "A or B" or "at least one of A and / or B" may include all possible combinations of the items listed together.

[0038] Expressions such as "first," "second," "first," or "second," may modify the components without regard to order or importance, and are used only to distinguish one component from another, but do not limit the components.

[0039] When it is said that a component (e.g., a first component) is “(functionally or communicatively) connected” or “connected” to another component (e.g., a second component), that component may be directly connected to the other component, or may be connected through another component (e.g., a third component).

[0040] In this specification, “configured to” may be used interchangeably with “suitable for,” “capable of,” “modified to,” “made to,” “capable of,” or “designed to,” depending on the context, for example, in terms of hardware or software.

[0041] In some contexts, the expression "a device configured to" may mean that the device is "capable of" doing something in conjunction with other devices or components.

[0042] For example, the phrase "a processor configured (or set) to perform A, B, and C" may mean a dedicated processor (e.g., an embedded processor) for performing those operations, or a general-purpose processor (e.g., a CPU or application processor) that can perform those operations by executing one or more software programs stored in a memory device.

[0043] Also, the term 'or' means 'inclusive or' rather than 'exclusive or'.

[0044] That is, unless otherwise stated or clear from context, the expression 'x utilizes a or b' means any one of the natural inclusive permutations.

[0045]

[0046] In the specific embodiments described above, the components included in the invention are expressed singularly or plurally depending on the specific embodiment presented.

[0047] However, the singular or plural expressions are selected to suit the situation presented for convenience of explanation, and the above-described embodiments are not limited to singular or plural components, and even components expressed in plural may be composed of singular elements, or even components expressed in singular elements may be composed of plural elements.

[0048] Meanwhile, although the description of the invention has described specific embodiments, it is clear that various modifications are possible within the scope that does not depart from the scope of the technical ideas contained in the various embodiments.

[0049] Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the claims described below but also by equivalents of the claims.

[0050]

[0051] FIG. 1 is a drawing for explaining an integration structure according to one embodiment.

[0052] Referring to FIG. 1, an integration structure (100) according to one embodiment can simultaneously form a wiring layer and a plurality of electrodes through a single process and a patterning process.

[0053] In addition, the integration structure (100) can more easily form a light-emitting element by depositing multiple layers at once in a single chamber and then etching them.

[0054] In addition, the integration structure (100) can form a high-quality semiconductor thin film at a low temperature by supplying additional energy during the process of depositing the semiconductor thin film of the light-emitting element.

[0055] In addition, the integration structure (100) can improve productivity by simplifying the manufacturing process.

[0056] Specifically, the integration structure (100) may include a light-emitting element having a channel layer (120) of a thin film transistor formed on an upper portion of a substrate (110), an intermediate insulating layer (130) formed on an upper portion of a first region of the channel layer (120), and a lower electrode layer (140-1) formed on an upper portion of the intermediate insulating layer (130) and protruding by a preset length.

[0057] In addition, the integration structure (100) may further include a wiring layer (160-1) formed in a protruding area of ​​the lower electrode layer (140-1), and a gate insulator (130-1), a gate electrode (160-3), a first electrode (160-2), and a second electrode (160-4) of a thin film transistor formed on an upper portion of a second area of ​​the channel layer (120), wherein the wiring layer (160-1), the gate electrode (160-3), the first electrode (160-2), and the second electrode (160-4) may be formed simultaneously through a single wiring process and a patterning process.

[0058] For example, the substrate (110) may include at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate, and a lower insulating layer may be further provided between the substrate (110) and the channel layer (120). Preferably, the substrate may be a glass substrate.

[0059] In addition, one of the first electrode (160-2) and the second electrode (160-4) may be a source electrode of the thin film transistor and the other may be a drain electrode of the thin film transistor, and the gate electrode (160-3) of the thin film transistor may be formed on the gate insulator (130-1), wherein the gate insulator (130-1) may be formed of the same material as the intermediate insulating layer (130), but is not limited thereto.

[0060] For example, each of the wiring layer (160-1), the gate electrode (160-3), the first electrode (160-2), and the second electrode (160-4) may include at least one of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), or silver (Ag), and a metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO).

[0061] In addition, the channel layer (120) of the thin film transistor may include at least one of amorphous silicon, nanocrystalline silicon, microcrystalline silicon, polycrystalline silicon, InGaZnO, a-IGZO (amorphous-Indium Gallium Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), IZO (Indium Zinc Oxide), IGO (Indium Gallium Oxide), ITZO (Indium Tin Zinc Oxide), GTO (Gallium Tin Oxide), ZTO (Zinc Tin Oxide), IAZO (Indium Antimony Zinc Oxide), AZO (Antimony Zinc Oxide), ITO (Indium Tin Oxide), ATO (Antimony Tin Oxide), and GZO (Gallium Zinc Oxide).

[0062] According to one side, the light-emitting element may include a lower electrode layer (140-1), an n-type semiconductor layer (140-2), an active layer (140-3), a p-type semiconductor layer (140-4), and an upper electrode layer (140-5).

[0063] The lower electrode layer (140-1) can serve as a metal reflective film by including a metal material with high reflectivity, and through this, the lower electrode layer (140-1) can improve the light extraction efficiency of the light-emitting element by reflecting light generated from the light-emitting element.

[0064] For example, the lower electrode layer (140-1) may include at least one metal material among silver (Ag) and aluminum (Al).

[0065] Preferably, the lower electrode layer (140-1) is implemented as an aluminum (Al) electrode layer, and can simultaneously serve as a buffer layer that induces easier c-axis growth of a semiconductor thin film (i.e., at least one layer among the n-type semiconductor layer (140-2), the active layer (140-3), and the p-type semiconductor layer (140-4)) of a light-emitting element formed on the lower electrode layer (140-1).

[0066] The n-type semiconductor layer (140-2) may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). Preferably, the n-type semiconductor layer (130-2) may be an n-GaN layer.

[0067] The active layer (140-3) may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN).

[0068] In addition, the active layer (140-3) may have a structure in which a quantum well using a material having a small energy band gap and a quantum barrier using a material having a large energy band gap are alternately stacked at least once, and the quantum well may have a single quantum well structure or a multi-quantum well (MQW) structure. Preferably, the active layer (140-3) may include an MQW structure.

[0069] According to one side, the active layer (140-3) may include an InGaN-based red MQW structure, wherein the InGaN-based red MQW structure may be implemented as a stacked structure of a first GaN layer, a first InAlN-based capping layer, an InGaN layer, a second InAlN-based capping layer, and a second GaN layer.

[0070] Specifically, the high indium content InGaN MQW structure applied to nitride-based red light-emitting devices causes the QCSE effect and phase separation due to stress generated by the difference in lattice parameters with the GaN layer, which may cause a decrease in internal quantum efficiency (IQE).

[0071] Accordingly, the active layer (130-3) according to one embodiment can minimize stress due to a difference in lattice constant between the GaN layer and the InGaN layer by applying an InAlN capping layer having a thickness of 1 nm to 2 nm between the GaN layer and the InGaN layer provided in the MQW structure. At this time, doping may be additionally applied to the InAlN capping layer to control conduction band and valence band characteristics.

[0072] The p-type semiconductor layer (140-4) may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). Preferably, the p-type semiconductor layer (140-4) may be a p-GaN layer.

[0073] The upper electrode layer 140-5 includes amorphous-Indium Gallium Zinc Oxide (a-IGZO), Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Indium Gallium Oxide (IGO), Indium Tin Zinc Oxide (ITZO), Gallium Tin Oxide (GTO), Zinc Tin Oxide (ZTO), and Indium Tin Oxide (IAZO). It may be a transparent electrode containing at least one of antimony zinc oxide (AZO), antimony zinc oxide (AZO), indium tin oxide (ITO), antimony tin oxide (ATO), and gallium zinc oxide (GZO).

[0074] According to one side, the light-emitting element can be formed by depositing a light-emitting element structure with high quality on the lower electrode layer (140-1).

[0075] Specifically, the semiconductor thin film of the light-emitting element (i.e., at least one layer among the n-type semiconductor layer (140-2), the active layer (140-3), and the p-type semiconductor layer (140-4)) can be formed by supplying additional energy based on at least one of an ion beam, an electron beam, plasma, ultraviolet rays, a laser, and LED light during a deposition process based on at least one of a physical deposition method and a chemical deposition method. Preferably, additional energy based on an ion beam can be supplied during the deposition process of the semiconductor thin film of the light-emitting element.

[0076] More specifically, when a glass substrate is used as the substrate (110), in order to grow a thin film directly on the glass substrate without a transfer process, it is necessary to lower the growth temperature of the thin film to a low temperature.

[0077] Accordingly, the integration structure according to one embodiment lowers the temperature for growing a semiconductor thin film of a light-emitting element to a low temperature (for example, a temperature of 700°C or lower) and, in this process, supplies additional energy to the semiconductor thin film being deposited to supplement the energy required for thin film growth, thereby enabling the realization of a high-quality semiconductor thin film at a low temperature.

[0078] According to one side, the integration structure (100) may further include a first partition wall (150-1) formed on the first side of the light-emitting element above the lower electrode layer (140-1) and a second partition wall (150-2) formed on the second side of the light-emitting element above the channel layer (120).

[0079] In addition, the first electrode (160-2) is formed adjacent to the second partition wall (150-2) on the upper side of the channel layer (120) and can be electrically connected to the upper electrode layer (140-5) provided in the light-emitting element.

[0080]

[0081] FIG. 2 is a drawing for explaining a method for manufacturing an integration structure according to one embodiment.

[0082] Referring to FIG. 2, in step 210, the manufacturing method can sequentially form a light-emitting element layer having a channel layer, an intermediate insulating layer, and a lower electrode layer of a thin film transistor on a substrate.

[0083] For example, the substrate may include at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate. Preferably, the substrate may be a glass substrate.

[0084] According to one side, in step 210, the manufacturing method may sequentially form a lower insulating layer on top of the substrate, and then a channel layer, an intermediate insulating layer, and a light-emitting element layer on top of the lower insulating layer.

[0085] According to one side, the light-emitting element layer may include a lower electrode layer, an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and an upper electrode layer, and the lower electrode layer may be a reflective layer including a metal material with high reflectivity.

[0086] In addition, in step 210, the manufacturing method may supply additional energy based on at least one of an ion beam, an electron beam, a plasma, ultraviolet rays, a laser, and LED light during the process of depositing a semiconductor thin film of the light-emitting element layer based on at least one of a physical deposition method and a chemical deposition method.

[0087] In step 220, the manufacturing method can form a light-emitting element by etching the remaining layers except the lower electrode layer among the light-emitting element layers.

[0088] Specifically, after depositing multiple layers at once within a single chamber through 210 steps, in step 220, the manufacturing method etching the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the upper electrode layer of the light-emitting device in a preset area and a preset size can more easily form the light-emitting device.

[0089] That is, the manufacturing method according to one embodiment can form a light-emitting element by depositing a light-emitting element structure on a lower electrode layer with high quality through the process described through steps 210 and 220.

[0090] At step 230, the manufacturing method can etch the lower electrode layer formed in the second region of the channel layer.

[0091] In step 240, the manufacturing method can form a plurality of partitions on the side of the light-emitting element and form a gate insulator by etching the intermediate insulating layer formed on the upper part of the second region of the channel layer.

[0092] According to one side, in step 240, the manufacturing method can form a first barrier rib formed on the first side of the light-emitting element on top of the lower electrode layer and a second barrier rib formed on the second side of the light-emitting element on top of the channel layer.

[0093] In step 250, the manufacturing method may include forming a wiring layer on top of an area protruding from a light-emitting element by a predetermined length in a lower electrode layer formed in a first area of ​​the channel layer, forming a gate electrode of a thin film transistor on top of a gate insulator formed in a second area of ​​the channel layer, and forming a first electrode and a second electrode of the thin film transistor in an exposed area of ​​the channel layer.

[0094] Specifically, in step 250, the manufacturing method can simultaneously form a wiring layer, a gate electrode, a first electrode, and a second electrode through a single wiring process and a patterning process.

[0095] For example, the gate electrode may be formed on top of a gate insulator formed in the second region of the channel layer.

[0096] Additionally, the first electrode is formed adjacent to the second barrier rib on the upper portion of the channel layer and can be electrically connected to the upper electrode layer provided in the light-emitting element.

[0097] A method for manufacturing an integration structure according to one embodiment will be described in more detail later with reference to Examples 3a to 3h.

[0098]

[0099] FIGS. 3A to 3H are drawings for more specifically explaining a method for manufacturing an integration structure according to one embodiment.

[0100] Referring to FIGS. 3a to 3h, in step 310, the manufacturing method can sequentially form a light-emitting element layer having a channel layer (302), an intermediate insulating layer (303), and a lower electrode layer (304-1) of a thin film transistor on a substrate (301).

[0101] According to one side, in step 310, the manufacturing method may sequentially form a lower insulating layer on top of the substrate (301), and then a channel layer (302), an intermediate insulating layer (303), and a light-emitting element layer on top of the lower insulating layer.

[0102] For example, the substrate (301) may include at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate.

[0103] In addition, the channel layer (302) may include at least one of amorphous silicon, nanocrystalline silicon, microcrystalline silicon, polycrystalline silicon, InGaZnO, amorphous-indium gallium zinc oxide (a-IGZO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium zinc oxide (IGO), indium tin zinc oxide (ITZO), gallium tin oxide (GTO), zinc tin oxide (ZTO), indium antimony zinc oxide (IAZO), antimony zinc oxide (AZO), indium tin oxide (ITO), antimony tin oxide (ATO), and gallium zinc oxide (GZO).

[0104] According to one side, the light emitting element layer may include a lower electrode layer (304-1), an n-type semiconductor layer (304-2), an active layer (304-3), a p-type semiconductor layer (304-4), and an upper electrode layer (304-5).

[0105] Specifically, in step 310, the manufacturing method can form an n-type semiconductor layer (304-2) on top of the lower electrode layer (304-1).

[0106] For example, the lower electrode layer (304-1) can include a metal material with high reflectivity and serve as a metal reflective film, thereby improving the light extraction efficiency of the light-emitting element by reflecting light generated from the light-emitting element.

[0107] For a more specific example, the lower electrode layer (304-1) may include at least one metal material among silver (Ag) and aluminum (Al).

[0108] For example, the n-type semiconductor layer (304-2) may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). Preferably, the n-type semiconductor layer (130-2) may be an n-GaN layer.

[0109] Next, in step 310, the manufacturing method can form an active layer (304-3) on top of the n-type semiconductor layer (304-2).

[0110] For example, the active layer (304-3) may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN).

[0111] In addition, the active layer (304-3) may have a structure in which a quantum well using a material having a small energy band gap and a quantum barrier using a material having a large energy band gap are alternately stacked at least once, and the quantum well may have a single quantum well structure or a multi-quantum well (MQW) structure. Preferably, the active layer (140-3) may include an MQW structure.

[0112] According to one side, the active layer (304-3) may include an InGaN-based red MQW structure, wherein the InGaN-based red MQW structure may be implemented as a stacked structure of a first GaN layer, a first InAlN-based capping layer, an InGaN layer, a second InAlN-based capping layer, and a second GaN layer.

[0113] Next, in step 310, the manufacturing method can form a p-type semiconductor layer (304-4) on top of the active layer (304-3).

[0114] For example, the p-type semiconductor layer (304-4) may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). Preferably, the p-type semiconductor layer (304-4) may be a p-GaN layer.

[0115] Next, in step 310, the manufacturing method can form an upper electrode layer (304-5) on top of the p-type semiconductor layer (304-4).

[0116] For example, the upper electrode layer (304-5) may be a transparent electrode including at least one of a-IGZO (amorphous-Indium Gallium Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), IZO (Indium Zinc Oxide), IGO (Indium Gallium Oxide), ITZO (Indium Tin Zinc Oxide), GTO (Gallium Tin Oxide), ZTO (Zinc Tin Oxide), IAZO (Indium Antimony Zinc Oxide), AZO (Antimony Zinc Oxide), ITO (Indium Tin Oxide), ATO (Antimony Tin Oxide), and GZO (Gallium Zinc Oxide).

[0117] According to one side, in step 310, the manufacturing method may supply additional energy based on at least one of an ion beam, an electron beam, plasma, ultraviolet rays, a laser, and LED light during the process of depositing a semiconductor thin film of the light-emitting element layer based on at least one of a physical vapor deposition method and a chemical vapor deposition method.

[0118] In step 320, the manufacturing method can form a light-emitting element by etching the remaining layers (304-2 to 304-5) excluding the lower electrode layer (304-1) among the light-emitting element layers to a preset size.

[0119] In step 330, the manufacturing method can etch the lower electrode layer (304-1) formed in the second region of the channel layer (302).

[0120] In steps 340 to 360, the manufacturing method may form a plurality of partition walls (305-1, 305-2) on the side of the light-emitting element and form a gate insulator (303-1) on the upper part of the second region of the channel layer (302).

[0121] Specifically, in step 340, the manufacturing method can form an insulating material (305) on the upper portion of the structure in which the light-emitting element is formed. For example, the insulating material (305) can be formed of the same material as the gate insulating layer (303), but is not limited thereto.

[0122] In step 350, the manufacturing method can etch the insulating material (305) formed on the first region and the upper electrode layer (304-5) to form a first partition wall (305-1) formed on the first side of the light-emitting element on the lower electrode layer (304-1) and a second partition wall (305-2) formed on the second side of the light-emitting element on the channel layer (302).

[0123] In step 360, the manufacturing method can form a gate insulator (303-1) on the upper part of the second region of the channel layer (302) by etching the insulating material (305) and the gate insulating layer (303) formed on the upper part of the second region of the channel layer (302).

[0124] In the manufacturing method according to one embodiment, steps 350 and 360 are described separately for convenience of explanation, but steps 350 and 360 may be performed simultaneously through a single etching process.

[0125] In steps 370 and 380, the manufacturing method may form a wiring layer (306-1) on the upper portion of an area protruding from the light-emitting element by a predetermined length in the lower electrode layer (304-1) formed in the first area of ​​the gate insulating layer (303), form a gate electrode (306-3) of a thin film transistor on the upper portion of the gate insulator (303-1) formed in the second area of ​​the channel layer (302), and form a first electrode (306-2) and a second electrode (306-4) in the exposed area of ​​the channel layer (302).

[0126] For example, one of the first electrode (306-2) and the second electrode (306-4) may be a source electrode of the thin film transistor and the other electrode may be a drain electrode of the thin film transistor.

[0127] Additionally, each of the wiring layer (306-1), the gate electrode (160-3), the first electrode (160-2), and the second electrode (160-4) may include at least one of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), or silver (Ag), and a metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO).

[0128] According to one side, in steps 370 and 380, the manufacturing method can simultaneously form a wiring layer (306-1), a gate electrode (306-3), a first electrode (306-2), and a second electrode (306-4) through a single wiring process and patterning process.

[0129] Specifically, in step 370, the manufacturing method can deposit a metal material (306) on top of the structure on which the gate insulator (303-1) is formed.

[0130] In step 380, the manufacturing method can simultaneously form a wiring layer (306-1), a gate electrode (306-3), a first electrode (306-2), and a second electrode (306-4) by patterning the deposited metal material (306).

[0131] For example, the gate electrode (306-3) may be formed on top of the gate insulator (303-1).

[0132] Additionally, the first electrode (306-2) is formed adjacent to the second partition wall (305-2) on the upper portion of the channel layer (302), and can be electrically connected to the upper electrode layer (304-5) provided in the light-emitting element.

[0133]

[0134] Ultimately, using the present invention, a light-emitting element structure can be deposited on a lower electrode layer with high quality.

[0135] In addition, using the present invention, a wiring layer and a plurality of electrodes can be formed simultaneously through a single process and a patterning process.

[0136] In addition, by using the present invention, a light-emitting element can be formed more easily by depositing and etching multiple layers at once in a single chamber.

[0137] In addition, by using the present invention, it is possible to form a high-quality semiconductor thin film at a low temperature by supplying additional energy during the process of depositing the semiconductor thin film of the light-emitting element.

[0138] In addition, by using the present invention, productivity can be improved by simplifying the manufacturing process.

[0139]

[0140] Although the embodiments described above have been described with limited drawings, those skilled in the art will recognize that various modifications and variations can be made based on the above description. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0141] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

[0142] The present invention can be applied to the medical, mobile phone, display industries, etc.

Claims

1. Substrate; A channel layer of a thin film transistor formed on the upper part of the substrate; An intermediate insulating layer formed on the upper part of the first region of the channel layer; A light emitting element having a lower electrode layer formed on top of the intermediate insulating layer and protruding by a preset length; A wiring layer formed in the protruding area of ​​the lower electrode layer and The gate insulator, gate electrode, first electrode and second electrode of the thin film transistor formed on the upper part of the second region of the channel layer Including, The above wiring layer, the gate electrode, the first electrode and the second electrode are formed simultaneously through a single wiring process and a patterning process. Integration structure.

2. In paragraph 1, The above lower electrode layer, A reflective layer containing a highly reflective metal material. Integration structure.

3. In paragraph 1, The semiconductor thin film of the above light-emitting element is, In a deposition process based on at least one of a physical deposition method and a chemical deposition method, additional energy based on at least one of an ion beam, an electron beam, a plasma, ultraviolet light, a laser, and an LED light is supplied to form Integration structure.

4. In paragraph 1, A first barrier formed on the first side of the light-emitting element above the lower electrode layer, and A second barrier formed on the second side of the light-emitting element above the channel layer An integration structure that further includes:

5. In paragraph 4, The above first electrode, It is formed adjacent to the second barrier on the upper part of the channel layer and is electrically connected to the upper electrode layer provided in the light-emitting element. Integration structure.

6. In paragraph 1, The above light emitting element, Comprising the lower electrode layer, the n-type semiconductor layer, the active layer, the p-type semiconductor layer and the upper electrode layer Integration structure.

7. In paragraph 1, The above substrate is, Comprising at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate. Integration structure.

8. A step of sequentially forming a light-emitting element layer having a channel layer, an intermediate insulating layer, and a lower electrode layer of a thin film transistor on a substrate; A step of forming a light-emitting element by etching the remaining layers of the light-emitting element layer except for the lower electrode layer; A step of etching the lower electrode layer formed in the second region of the above channel layer; A step of forming a plurality of partitions on the side of the light-emitting element and etching the intermediate insulating layer formed on the upper part of the second region of the channel layer to form a gate insulator; and A step of forming a wiring layer on the upper part of a region protruding from the light-emitting element by a preset length in the lower electrode layer formed in the first region of the channel layer, forming a gate electrode of the thin film transistor on the upper part of the gate insulator formed in the second region of the channel layer, and forming a first electrode and a second electrode of the thin film transistor in the exposed region of the channel layer, wherein the wiring layer, the gate electrode, the first electrode, and the second electrode are formed simultaneously through a single wiring process and a patterning process. A method for manufacturing an integration structure including:

9. In paragraph 8, The step of forming the plurality of partition walls and gate insulators is: A first barrier wall formed on the first side of the light-emitting element above the lower electrode layer and a second barrier wall formed on the second side of the light-emitting element above the channel layer are formed. A method for manufacturing an integration structure.

10. In paragraph 8, The steps of forming the above simultaneously are: A step of depositing a metal material on the upper part of the structure on which the gate insulator is formed; and A step of patterning the deposited metal material to simultaneously form the wiring layer, the gate electrode, the first electrode, and the second electrode. A method for manufacturing an integration structure including:

11. In paragraph 10, The above gate electrode is, is formed on the upper part of the gate insulator, The above first electrode, It is formed adjacent to the second barrier on the upper part of the channel layer and is electrically connected to the upper electrode layer provided in the light-emitting element. A method for manufacturing an integration structure.

12. In paragraph 8, The above sequentially forming steps are: In the process of depositing the semiconductor thin film of the light-emitting element layer based on at least one of a physical deposition method and a chemical deposition method, additional energy based on at least one of an ion beam, an electron beam, a plasma, ultraviolet rays, a laser, and an LED light is supplied. A method for manufacturing an integration structure.

13. In paragraph 8, The above sequentially forming steps are: A step of forming an n-type semiconductor layer on top of the lower electrode layer; A step of forming an active layer on top of the n-type semiconductor layer; A step of forming a p-type semiconductor layer on top of the above active layer, and A step of forming an upper electrode layer on top of the above p-type semiconductor layer A method for manufacturing an integration structure including:

14. In paragraph 8, The above lower electrode layer, A reflective layer containing a metal material having high reflectivity, The above substrate is, Comprising at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate. A method for manufacturing an integration structure.

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